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| september 2013 doc id 15177 rev 8 1/1740 RM0029 reference manual spc564a74xx, spc564a80xx 32-bit mcu family built on the embedded power architecture ? introduction the primary objective of this document is to define the functionality of the spc564a74xx, spc564a80xx family of microcontrollers for use by software and hardware developers. the spc564a74xx, spc564a80xx family is built on power architecture ? technology and integrates technologies that are important for today?s lower-end applications. www.st.com
contents RM0029 2/1740 doc id 15177 rev 8 contents preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 chapter organization and device-specific information . . . . . . . . . . . . . . . . . . . . . 66 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.1 the spc564a74xx, spc564a80xx microcontroller family . . . . . . . . . . . 67 1.2 spc564a80 and spc564a70 device comparison . . . . . . . . . . . . . . . . . 68 1.3 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 1.4 feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.4.1 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.4.2 e200z4 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.4.3 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.4.4 edma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.4.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.4.6 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.4.7 fmpll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.4.8 siu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 1.4.9 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 1.4.10 bam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 1.4.11 emios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 1.4.12 etpu2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 1.4.13 reaction module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 1.4.14 eqadc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 1.4.15 dspi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 1.4.16 esci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1.4.17 flexcan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1.4.18 flexray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 1.4.19 system timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 1.4.20 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 1.4.21 cyclic redundancy check ( crc) module . . . . . . . . . . . . . . . . . . . . . . . . 89 1.4.22 error correction status module (ecsm) . . . . . . . . . . . . . . . . . . . . . . . . . 89 RM0029 contents doc id 15177 rev 8 3/1740 1.4.23 external bus interface (ebi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 1.4.24 calibration ebi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 1.4.25 power management controller (pmc) . . . . . . . . . . . . . . . . . . . . . . . . . . 91 1.4.26 nexus port controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 1.4.27 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 1.4.28 development trigger semaphore (dts) . . . . . . . . . . . . . . . . . . . . . . . . 91 2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 2.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.2 signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.1 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.2 reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.3 reset pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.3.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.3.2 rstout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.4 fmpll lock gating signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.5 reset source descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.5.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 4.5.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 4.5.3 loss of lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 4.5.4 loss of clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.5.5 core watchdog timer/debug reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.5.6 jtag reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.5.7 software system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.5.8 software external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.6 reset registers in the siu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.7 reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.7.1 reset configuration half word (rchw) . . . . . . . . . . . . . . . . . . . . . . . . 144 4.7.2 reset configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 4.7.3 reset weak pull up/down configuration . . . . . . . . . . . . . . . . . . . . . . . . 147 contents RM0029 4/1740 doc id 15177 rev 8 5 operating modes and clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.2.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.2.2 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.2.3 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.3 clock architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 5.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 5.3.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 5.3.3 system clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 5.3.4 fmpll modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 6 device performance optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.3 configuring hardware features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 6.3.1 branch target buffer (btb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 6.3.2 frequency-modulated pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6.3.3 flash bus interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.3.4 crossbar switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.3.5 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.3.6 memory management unit (mmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.4 application software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.4.1 compiler optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.4.2 signal processing extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.4.3 hardware single precision floating point . . . . . . . . . . . . . . . . . . . . . . . 169 6.4.4 variable length encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.5 peripherals and general application guidelines . . . . . . . . . . . . . . . . . . . 170 6.6 performance optimization checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 7 e200z4 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 7.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 7.3 microarchitecture summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 7.3.1 instruction unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 7.3.2 integer unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 RM0029 contents doc id 15177 rev 8 5/1740 7.3.3 load/store unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 7.3.4 cache features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 7.3.5 mmu features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 7.3.6 e200z4 system bus features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7.3.7 nexus 3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 8 enhanced direct memory access controller (edma). . . . . . . . . . . . . 179 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 8.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 8.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 8.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 8.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 8.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 8.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 8.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 8.4.1 edma basic data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 8.5 initialization / application information . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 8.5.1 edma initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 8.5.2 dma programming errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 8.5.3 dma request assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 8.5.4 dma arbitration mode considerations . . . . . . . . . . . . . . . . . . . . . . . . . 224 8.5.5 dma transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 8.5.6 tcd status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 8.5.7 channel linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 8.5.8 dynamic programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 9 multi-layer ahb crossbar switch (xbar) . . . . . . . . . . . . . . . . . . . . . 233 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 9.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 9.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 9.1.3 limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 9.1.4 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 9.2 xbar registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 9.2.1 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 9.2.2 xbar register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 contents RM0029 6/1740 doc id 15177 rev 8 9.2.3 coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 9.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 9.3.1 arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 9.3.2 priority assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 10 peripheral bridge (pbridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 10.1 pbridge features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 10.2 pbridge modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 10.3 pbridge block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 10.4 pbridge signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 10.5 pbridge functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 10.5.1 read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 10.5.2 write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 10.6 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . 246 10.6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 10.6.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 11 general-purpose static ram (sram). . . . . . . . . . . . . . . . . . . . . . . . . . 251 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 11.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 11.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 11.3.1 normal (functional) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 11.3.2 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 11.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 11.5 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 11.6 register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 11.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 11.8 sram ecc mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 11.8.1 access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 11.8.2 reset effects on sram accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 11.9 initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . 254 11.9.1 example code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 12 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 RM0029 contents doc id 15177 rev 8 7/1740 12.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 12.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 12.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 12.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 12.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 12.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 12.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 12.4.1 flash user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 12.4.2 flash read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 12.4.3 read while write (rww) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 12.4.4 utest mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 12.4.5 flash programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 12.4.6 flash erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 12.4.7 flash shadow block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 12.4.8 flash reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 12.4.9 dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 12.4.10 interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 13 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 13.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 13.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 13.2 mpu-to-xbar slave port mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 13.3 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 13.4 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 13.4.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 13.4.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 13.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 13.5.1 access evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 13.5.2 xbar error terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 13.6 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 13.7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 14 external bus interface (ebi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 14.1 information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 contents RM0029 8/1740 doc id 15177 rev 8 14.1.1 device-specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 14.1.2 unsupported features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 14.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 14.2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 14.2.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 14.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 14.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 14.3.2 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 14.3.3 signal output buffer enable logic by mode . . . . . . . . . . . . . . . . . . . . . . 321 14.4 memory map/register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 14.4.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 14.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 14.5.1 external bus interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 14.5.2 external bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 14.6 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 14.6.1 booting from external memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 14.6.2 running with sdr (single data rate) burst memories . . . . . . . . . . . . 371 14.6.3 running with asynchronous memories . . . . . . . . . . . . . . . . . . . . . . . . 371 14.6.4 connecting an mcu to multiple memories . . . . . . . . . . . . . . . . . . . . . . 374 14.6.5 ebi operation with reduced pinout mcus . . . . . . . . . . . . . . . . . . . . . . 375 15 interrupt controller (intc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 15.1 information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 15.1.1 device-specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 15.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 15.2.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 15.2.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 15.2.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 15.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 15.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 15.4.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 15.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 15.5.1 interrupt request sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 15.5.2 priority management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 RM0029 contents doc id 15177 rev 8 9/1740 15.5.3 details on handshaking with processor . . . . . . . . . . . . . . . . . . . . . . . . 405 15.6 initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . 407 15.6.1 initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 15.6.2 interrupt exception handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 15.6.3 isr, rtos, and task hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 15.6.4 order of execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 15.6.5 priority ceiling protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 15.6.6 selecting priorities according to request rates and deadlines 412 15.6.7 software configurable interrupt requests . . . . . . . . . . . . . . . . . . . . . . . 412 15.6.8 lowering priority within an isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 15.6.9 negating an interrupt request outside of its isr . . . . . . . . . . . . . . . . . 413 15.6.10 examining lifo contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 16 system integration unit (siu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 16.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 16.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 16.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 16.3.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 16.3.2 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 16.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 16.5 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 16.6 memory map and register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 418 16.6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 16.6.2 mcu id register 2 (siu_midr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 16.6.3 mcu id register (siu_midr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 16.6.4 reset status register (siu_rsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 16.6.5 system reset control register (siu_srcr) . . . . . . . . . . . . . . . . . . . 425 16.6.6 external interrupt status register (siu_eisr) . . . . . . . . . . . . . . . . . . 426 16.6.7 dma/interrupt request enable register (siu_direr) . . . . . . . . . . . . 427 16.6.8 dma/interrupt request select register (siu_dirsr) . . . . . . . . . . . . 428 16.6.9 overrun status register (siu_osr) . . . . . . . . . . . . . . . . . . . . . . . . . . 429 16.6.10 overrun request enable register (siu_orer) . . . . . . . . . . . . . . . . . 430 16.6.11 irq rising-edge event enable register (siu_ireer) . . . . . . . . . . . . 430 16.6.12 external irq falling-edge event enable register (siu_ifeer) . . . . 431 16.6.13 external irq digital filter register (siu_idfr) . . . . . . . . . . . . . . . . . 432 16.6.14 irq filtered input register (siu_ifir) . . . . . . . . . . . . . . . . . . . . . . . . 433 contents RM0029 10/1740 doc id 15177 rev 8 16.6.15 pad configuration registers (siu_pcr) . . . . . . . . . . . . . . . . . . . . . . . 434 16.6.16 gpio pin data output registers (siu_gpdo0_3 ? siu_gpdo412_413) 551 16.6.17 gpio pin data input registers (siu_gpdi0_3 ? siu_gpdi_232) . . . 552 16.6.18 eqadc trigger input select register (siu_etisr) . . . . . . . . . . . . . . 553 16.6.19 external irq input select register (siu_eiisr) . . . . . . . . . . . . . . . . . 555 16.6.20 dspi input select register (siu_disr) . . . . . . . . . . . . . . . . . . . . . . . 558 16.6.21 imux select register 3 (siu_isel3) . . . . . . . . . . . . . . . . . . . . . . . . . 560 16.6.22 imux select register 8 (siu_isel8) . . . . . . . . . . . . . . . . . . . . . . . . . 566 16.6.23 imux select register 9 (siu_isel9) . . . . . . . . . . . . . . . . . . . . . . . . . 568 16.6.24 imux select register 10 (siu_isel10) . . . . . . . . . . . . . . . . . . . . . . . 569 16.6.25 chip configuration register (siu_ccr) . . . . . . . . . . . . . . . . . . . . . . . 571 16.6.26 external clock control register (siu_eccr) . . . . . . . . . . . . . . . . . . . 572 16.6.27 compare a high register (siu_carh) . . . . . . . . . . . . . . . . . . . . . . . 573 16.6.28 compare a low register (siu_carl) . . . . . . . . . . . . . . . . . . . . . . . . 573 16.6.29 compare b high register (siu_cbrh) . . . . . . . . . . . . . . . . . . . . . . . 574 16.6.30 compare b low register (siu_cbrl) . . . . . . . . . . . . . . . . . . . . . . . . 574 16.6.31 system clock register (siu_sysdiv) . . . . . . . . . . . . . . . . . . . . . . . . 575 16.6.32 halt register (siu_hlt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 16.6.33 halt acknowledge register (siu_hltack) . . . . . . . . . . . . . . . . . . . . . 579 16.6.34 core mmu pid control register (siu_empcr0) . . . . . . . . . . . . . . . . 581 16.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 16.7.1 system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 16.7.2 reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 16.7.3 external interrupt request input (irq) . . . . . . . . . . . . . . . . . . . . . . . . . 583 16.7.4 gpio operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 16.7.5 internal multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 17 frequency-modulated phase locked loop (fmpll) . . . . . . . . . . . . . . 588 17.1 information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 17.1.1 device-specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 17.1.2 device-specific parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 17.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 17.2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 17.2.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 17.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 RM0029 contents doc id 15177 rev 8 11/1740 17.3.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 17.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 17.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 17.4.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 17.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 17.5.1 input clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 17.5.2 clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 17.5.3 lock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 17.5.4 loss-of-clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 17.5.5 frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 18 error correction status module (ecsm) . . . . . . . . . . . . . . . . . . . . . . . 611 18.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611 18.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611 18.3 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611 18.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 18.4.1 miscellaneous reset status register (ecsm_mrsr) . . . . . . . . . . . . 612 18.4.2 miscellaneous wakeup control register (ecsm_mwcr) . . . . . . . . . 613 18.4.3 miscellaneous user-defined control register (ecsm_mudcr) . . . . 614 18.4.4 ecc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 19 system timer module (stm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 19.1 information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 19.1.1 device-specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 19.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 19.2.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 19.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 19.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 19.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 19.4.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 19.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 20 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 20.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 contents RM0029 12/1740 doc id 15177 rev 8 20.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 20.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 20.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 20.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 20.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 20.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 20.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 21 boot assist module (bam) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 21.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 21.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 21.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 21.3.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 21.3.2 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 21.3.3 internal boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 21.3.4 serial boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 21.3.5 calibration bus boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 21.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 21.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 21.5.1 bam program flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 21.5.2 bam program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 21.5.3 reset configuration half word (rchw) . . . . . . . . . . . . . . . . . . . . . . . . 654 21.5.4 internal boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 21.5.5 serial boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 21.5.6 booting from the external bus interface (ebi) . . . . . . . . . . . . . . . . . . . 664 22 configurable enhanced modular io subsystem (emios200) . . . . . . 666 22.1 device-specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 22.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 22.2.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 22.2.3 channel configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 22.3 external signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 22.4 memory map/register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 22.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 22.4.2 global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 RM0029 contents doc id 15177 rev 8 13/1740 22.4.3 channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 22.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 22.5.1 unified channel (uc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 22.5.2 ip bus interface unit (biu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 22.5.3 stac client submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 22.5.4 global clock prescaler submodule (gcp) . . . . . . . . . . . . . . . . . . . . . . 716 22.6 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 22.6.1 considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 22.6.2 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 23 reaction module (reacm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 23.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 23.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 23.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 23.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 23.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 23.2.1 reacm_rchn ? reacm channel (n) output pin a, b and c . . . . . . 725 23.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 23.3.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 23.3.2 reacm module configuration register (reacm_mcr) . . . . . . . . . . . 726 23.3.3 reacm timer configuration register (reacm_tcr) . . . . . . . . . . . . 728 23.3.4 reacm threshold router register (reacm_thrr) . . . . . . . . . . . . 729 23.3.5 reacm adc sensor input register (reacm_sinr) . . . . . . . . . . . . 730 23.3.6 reacm global error flag register (reacm_gefr) . . . . . . . . . . . . . 731 23.3.7 reacm channel n configuration register (reacm_chcrn) . . . . . . 732 23.3.8 reacm channel n status register (reacm_chsrn) . . . . . . . . . . . 734 23.3.9 reacm channel n router register (reacm_chrrn) . . . . . . . . . . . 737 23.3.10 reacm shared timer bank registers (reacm_stbk) . . . . . . . . . . 739 23.3.11 reacm hold-off timer bank registers (reacm_hotbk) . . . . . . . . 739 23.3.12 reacm threshold bank register (reacm_thbk) . . . . . . . . . . . . . . 740 23.3.13 reacm adc result maximum limit check register (reacm_adcmax) . 741 23.3.14 reacm modulation range pulse width register (reacm_rangepwd) 741 23.3.15 reacm modulation minimum pulse width register (reacm_minpwd) 742 23.3.16 reacm modulation control word bank registers (reacm_mwbk) 743 contents RM0029 14/1740 doc id 15177 rev 8 23.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 23.4.1 reaction channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 23.4.2 modulation control words bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 23.4.3 shared timer bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 23.4.4 hold-off timer bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 23.4.5 threshold bank and comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 23.4.6 adc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 23.4.7 prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 23.4.8 banked mode support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 23.5 modulation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 23.5.1 threshold/threshold mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 23.5.2 threshold/hold-off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 23.5.3 limitations on the modulation process . . . . . . . . . . . . . . . . . . . . . . . . 757 23.6 monitored modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 23.7 dma support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 23.8 reset overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 23.9 reaction module interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 23.9.1 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 23.10 use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 23.10.1 advancing modulation phase on a threshold level . . . . . . . . . . . . . . . 770 23.10.2 controlling the loop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 23.10.3 banked mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 24 enhanced time processing unit (etpu2) . . . . . . . . . . . . . . . . . . . . . . 773 24.1 information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 24.1.1 device-specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 24.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 24.2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780 24.2.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 24.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786 24.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786 24.3.2 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 24.4 memory map/register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 24.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 24.4.2 system configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 RM0029 contents doc id 15177 rev 8 15/1740 24.4.3 time base registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 24.4.4 engine related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 24.4.5 channel registers layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 24.4.6 global channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 24.4.7 channel configuration and control registers . . . . . . . . . . . . . . . . . . . . 830 24.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 24.5.1 functions and threads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 24.5.2 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 24.5.3 scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 24.5.4 parameter sharing and coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 24.5.5 enhanced channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 24.5.6 time bases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912 24.5.7 eac ? etpu angle counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919 24.5.8 microengine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938 24.5.9 microinstruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953 24.5.10 test and development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984 24.6 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990 24.6.1 configuration sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990 24.6.2 reset options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992 24.6.3 multiple parameter coherency methods . . . . . . . . . . . . . . . . . . . . . . . . 992 24.6.4 programming hints and caveats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993 24.6.5 estimating worst-case latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994 24.6.6 endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009 24.7 appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009 24.7.1 microcycle and i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009 24.7.2 initialization code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 24.7.3 predefined channel mode summary . . . . . . . . . . . . . . . . . . . . . . . . . 1017 24.7.4 misc algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 25 enhanced queued analog-to-digital converter (eqadc) . . . . . . . . 1023 25.1 information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 25.1.1 device-specific pin configuration features . . . . . . . . . . . . . . . . . . . 1023 25.1.2 availability of analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024 25.2.1 module overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024 25.2.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 25.2.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027 contents RM0029 16/1740 doc id 15177 rev 8 25.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028 25.3.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028 25.3.2 streaming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028 25.3.3 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029 25.3.4 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030 25.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031 25.4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031 25.4.2 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033 25.5 memory map/register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036 25.5.1 eqadc memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036 25.5.2 eqadc register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039 25.5.3 on-chip adc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 25.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092 25.6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092 25.6.2 data flow in eqadc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093 25.6.3 command/result queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 25.6.4 eqadc command fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 25.6.5 eqadc result fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138 25.6.6 on-chip adc configuration and control . . . . . . . . . . . . . . . . . . . . . . 1142 25.6.7 internal/external multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154 25.6.8 eqadc dma/interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161 25.6.9 eqadc synchronous serial interface (ssi) sub-block . . . . . . . . . . 1163 25.6.10 eqadc parallel side interface (psi) sub-block . . . . . . . . . . . . . . . . 1168 25.6.11 analog sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171 25.7 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . .1174 25.7.1 multiple queues control setup example . . . . . . . . . . . . . . . . . . . . . . . 1174 25.7.2 eqadc/dmac interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179 25.7.3 sending immediate command setup example . . . . . . . . . . . . . . . . . . 1181 25.7.4 modifying queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182 25.7.5 cqueue and rqueues usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182 25.7.6 adc result calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184 25.7.7 eqadc versus qadc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186 26 decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191 26.1 information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1191 26.1.1 device-specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191 RM0029 contents doc id 15177 rev 8 17/1740 26.1.2 device-specific parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191 26.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1191 26.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191 26.2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193 26.2.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193 26.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1194 26.3.1 decimation trigger signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194 26.3.2 integrator enable signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195 26.3.3 integrator halt signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195 26.3.4 integrator reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195 26.3.5 integrator output request signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195 26.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . .1195 26.4.1 decimation filter device memory map . . . . . . . . . . . . . . . . . . . . . . . . 1195 26.4.2 decimation filter register descriptions . . . . . . . . . . . . . . . . . . . . . . . . 1197 26.4.3 decimation filter memory map for parallel side interface . . . . . . . . 1218 26.4.4 psi register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218 26.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220 26.5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220 26.5.2 parallel side interface (psi) description . . . . . . . . . . . . . . . . . . . . . . 1220 26.5.3 input buffer description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221 26.5.4 output buffer description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222 26.5.5 bypass configuration description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223 26.5.6 iir and fir filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224 26.5.7 filter prefill control description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227 26.5.8 timestamp data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228 26.5.9 flush command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228 26.5.10 soft-reset command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229 26.5.11 interrupts requests description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229 26.5.12 dma requests description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231 26.5.13 freeze mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232 26.5.14 enhanced debug monitor description . . . . . . . . . . . . . . . . . . . . . . . . 1232 26.5.15 integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232 26.5.16 cascade mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236 26.6 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241 26.6.1 initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241 26.7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241 contents RM0029 18/1740 doc id 15177 rev 8 26.7.1 eqadc ip as the psi master block . . . . . . . . . . . . . . . . . . . . . . . . . . 1241 26.8 filter example simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242 26.8.1 coefficients calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242 26.8.2 input data calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243 26.8.3 filter results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244 27 temperature sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245 27.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245 27.2 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245 27.3 temperature formula . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246 27.3.1 t low and t high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247 27.3.2 t tsens_code (t low ) and t tsens_code (t high ) . . . . . . . . . . . . . . . . 1247 27.3.3 v bg_code (t low ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248 27.3.4 temperature sensor voltage (v tens (t)) . . . . . . . . . . . . . . . . . . . . . . 1248 27.3.5 bandgap reference voltage (v bg_code (t)) . . . . . . . . . . . . . . . . . . . . 1248 27.3.6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248 28 system information module and trim (sim) . . . . . . . . . . . . . . . . . . . 1251 28.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251 28.2 user trim values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251 29 cyclic redundancy checker (crc) unit . . . . . . . . . . . . . . . . . . . . . . 1252 29.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252 29.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252 29.2.1 access and performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252 29.3 calculating a crc checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253 29.3.1 configuring the context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254 29.3.2 initializing the context seed value . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255 29.3.3 writing the data stream to the context input . . . . . . . . . . . . . . . . . . . 1255 29.3.4 reading the checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255 29.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256 29.4.1 crc configuration register (crc_cfg) . . . . . . . . . . . . . . . . . . . . . 1257 29.4.2 crc input register (crc_inp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258 29.4.3 crc current status register (crc_cstat) . . . . . . . . . . . . . . . . . . 1259 29.4.4 crc output register (crc_outp) . . . . . . . . . . . . . . . . . . . . . . . . . 1260 29.5 use cases and limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261 RM0029 contents doc id 15177 rev 8 19/1740 29.5.1 checksums for configuration registers . . . . . . . . . . . . . . . . . . . . . . . 1261 29.5.2 calculations on incoming/outgoing protocol frames . . . . . . . . . . . . . 1261 30 deserial serial peripheral interface (dspi) . . . . . . . . . . . . . . . . . . . . 1265 30.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265 30.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265 30.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267 30.4 dspi configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268 30.4.1 spi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268 30.4.2 dsi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269 30.4.3 csi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270 30.5 dspi frequency support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270 30.6 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271 30.6.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271 30.6.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271 30.6.3 module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271 30.6.4 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271 30.7 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271 30.7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271 30.7.2 detailed signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272 30.8 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273 30.8.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273 30.8.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275 30.9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307 30.9.1 start and stop of dspi transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308 30.9.2 serial peripheral interface (spi) configuration . . . . . . . . . . . . . . . . . . 1308 30.9.3 deserial serial interface (dsi) configuration . . . . . . . . . . . . . . . . . . . 1311 30.9.4 combined serial interface (csi) configuration . . . . . . . . . . . . . . . . . . 1317 30.9.5 dspi baud rate and clock delay generation . . . . . . . . . . . . . . . . . . . 1318 30.9.6 transfer formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1321 30.9.7 continuous serial communications clock . . . . . . . . . . . . . . . . . . . . . . 1329 30.9.8 timed serial bus (tsb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1331 30.9.9 parity generation and check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333 30.9.10 interrupts/dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1334 30.9.11 buffered spi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336 30.9.12 continuous peripheral chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336 contents RM0029 20/1740 doc id 15177 rev 8 30.9.13 peripheral chip select expansion and deglitching . . . . . . . . . . . . . . . 1336 30.9.14 dma and interrupt conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1337 30.9.15 modified spi transfer format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338 30.9.16 lvds pad usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338 30.9.17 dspi connections to etpu_a, emios and siu . . . . . . . . . . . . . . . . 1338 30.9.18 power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347 30.10 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347 30.10.1 how to manage dspi queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347 30.10.2 switching master and slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348 30.10.3 baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348 30.10.4 delay settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349 30.10.5 calculation of fifo pointer addresses . . . . . . . . . . . . . . . . . . . . . . . 1350 31 enhanced serial communication interface (esci) . . . . . . . . . . . . . . 1353 31.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353 31.1.1 bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353 31.1.2 acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353 31.1.3 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353 31.1.4 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354 31.1.5 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355 31.1.6 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355 31.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356 31.2.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356 31.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356 31.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357 31.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357 31.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373 31.4.1 module control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373 31.4.2 frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373 31.4.3 baud rate and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377 31.4.4 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378 31.4.5 sci mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381 31.4.6 lin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395 31.4.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404 31.5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405 31.5.1 sci data frames separated by preamble . . . . . . . . . . . . . . . . . . . . . . 1405 RM0029 contents doc id 15177 rev 8 21/1740 32 flexcan module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407 32.1 information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407 32.1.1 device-specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407 32.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407 32.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1409 32.2.2 flexcan module features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410 32.2.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411 32.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1411 32.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411 32.3.2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412 32.4 memory map/register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412 32.4.1 flexcan memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412 32.4.2 message buffer architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414 32.4.3 message buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414 32.4.4 rx fifo structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417 32.4.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420 32.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439 32.5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439 32.5.2 transmit process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440 32.5.3 arbitration process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440 32.5.4 receive process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1441 32.5.5 matching process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1443 32.5.6 data coherence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444 32.5.7 rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447 32.5.8 can protocol related features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448 32.5.9 modes of operation details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452 32.5.10 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454 32.5.11 bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455 32.6 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455 32.6.1 flexcan initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455 32.6.2 flexcan addressing and ram size configurations . . . . . . . . . . . . . . 1456 33 flexray communication controller (flexray) . . . . . . . . . . . . . . . . . 1457 33.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457 33.1.1 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457 33.1.2 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457 contents RM0029 22/1740 doc id 15177 rev 8 33.1.3 color coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458 33.1.4 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458 33.1.5 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1460 33.1.6 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461 33.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462 33.2.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462 33.3 controller host interface clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463 33.4 protocol engine clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463 33.4.1 oscillator clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463 33.4.2 pll clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463 33.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . 1463 33.5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463 33.5.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469 33.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547 33.6.1 message buffer concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547 33.6.2 physical message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547 33.6.3 message buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1549 33.6.4 flexray memory area layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554 33.6.5 physical message buffer description . . . . . . . . . . . . . . . . . . . . . . . . . 1557 33.6.6 individual message buffer functional description . . . . . . . . . . . . . . . . 1567 33.6.7 individual message buffer search . . . . . . . . . . . . . . . . . . . . . . . . . . . 1594 33.6.8 individual message buffer reconfiguration . . . . . . . . . . . . . . . . . . . . . 1597 33.6.9 receive fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1598 33.6.10 channel device modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604 33.6.11 external clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606 33.6.12 sync frame id and sync frame deviation tables . . . . . . . . . . . . . . . . 1607 33.6.13 mts generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610 33.6.14 key slot transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611 33.6.15 sync frame filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612 33.6.16 strobe signal support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612 33.6.17 timer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613 33.6.18 slot status monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614 33.6.19 system bus access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1618 33.6.20 interrupt support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619 33.6.21 lower bit rate support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1623 33.6.22 pe data memory (pe dram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624 RM0029 contents doc id 15177 rev 8 23/1740 33.6.23 chi lookup-table memory (chi lram) . . . . . . . . . . . . . . . . . . . . . . . 1625 33.6.24 memory content error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1625 33.6.25 memory error injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630 33.7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631 33.7.1 module configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631 33.7.2 initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632 33.7.3 chi lram error injection out of poc:default config . . . . . . . . . . . . . 1634 33.7.4 pe dram error injection out of poc:default config . . . . . . . . . . . . . 1634 33.7.5 shut down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634 33.7.6 number of usable message buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 1634 33.7.7 protocol control command execution . . . . . . . . . . . . . . . . . . . . . . . . . 1635 33.7.8 message buffer search on simple message buffer configuration . . . . 1636 34 periodic interrupt timer (pit_rti) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640 34.1 information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640 34.1.1 device-specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640 34.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640 34.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641 34.2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641 34.3 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642 34.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . 1642 34.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642 34.4.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642 34.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646 34.5.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646 34.5.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648 34.6 initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . 1648 34.6.1 example configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648 35 power management controller (pmc) . . . . . . . . . . . . . . . . . . . . . . . . 1650 35.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650 35.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651 35.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652 35.2.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652 35.3 memory map/register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653 35.3.1 module configuration register (mcr) . . . . . . . . . . . . . . . . . . . . . . . . 1654 contents RM0029 24/1740 doc id 15177 rev 8 35.3.2 trimming register (trimr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656 35.3.3 status register (sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659 35.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662 35.4.1 bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662 35.4.2 5 v lvi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663 35.4.3 3.3 v internal voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663 35.4.4 3.3 v lvi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665 35.4.5 1.2 v voltage regulator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666 35.4.6 1.2 v lvi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666 35.4.7 resets and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666 35.4.8 soft-start (for 1.2 v and 3.3 v regulators) . . . . . . . . . . . . . . . . . . . . . 1670 35.4.9 adc test mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670 35.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671 36 jtag controller (jtagc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672 36.1 information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672 36.1.1 device-specific parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672 36.1.2 device identification register parameters . . . . . . . . . . . . . . . . . . . . . . 1672 36.1.3 auxiliary tap controller instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 1672 36.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673 36.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673 36.2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673 36.2.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673 36.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674 36.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674 36.3.2 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674 36.4 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675 36.4.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675 36.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1678 36.5.1 jtagc reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1678 36.5.2 ieee 1149.1-2001 (jtag) test access port . . . . . . . . . . . . . . . . . . . . 1678 36.5.3 tap controller state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1678 36.5.4 jtagc block instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1680 36.5.5 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1682 36.6 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . 1682 RM0029 contents doc id 15177 rev 8 25/1740 37 nexus port controller (n pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684 37.1 information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684 37.1.1 device-specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684 37.1.2 parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1685 37.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1686 37.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1687 37.2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688 37.2.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688 37.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689 37.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689 37.3.2 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689 37.4 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1690 37.4.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1691 37.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695 37.5.1 npc reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695 37.5.2 auxiliary output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695 37.5.3 ieee 1149.1-2001 (jtag) tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698 37.5.4 nexus jtag port sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703 37.5.5 mcko and ipg_sync_mcko . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703 37.5.6 evto sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703 37.5.7 nexus reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703 37.5.8 system clock locked indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704 37.6 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704 37.6.1 accessing npc tool-mapped registers . . . . . . . . . . . . . . . . . . . . . . . 1704 38 development trigger semaphore (dts) . . . . . . . . . . . . . . . . . . . . . . 1705 38.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705 38.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705 38.3 dts device connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707 38.3.1 dts register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707 38.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708 38.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708 38.5.1 dts output enable register (dts_enable) . . . . . . . . . . . . . . . . . 1708 38.5.2 dts startup register (dts_startup) . . . . . . . . . . . . . . . . . . . . . . 1709 38.5.3 dts semaphore register (dts_semaphore) . . . . . . . . . . . . . . . 1710 38.6 example application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1711 contents RM0029 26/1740 doc id 15177 rev 8 39 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713 RM0029 list of tables doc id 15177 rev 8 27/1740 list of tables table 1. spc564a80 and spc564a70 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 2. spc564a74xx, spc564a80xx memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 3. spc564a74xx, spc564a80xx signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 4. pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 5. signal details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 6. power/ground segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 7. bootcfg options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 8. pllref options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 9. timing for reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 10. rchw location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 11. reset configuration half word (rchw) field descriptions. . . . . . . . . . . . . . . . . . . . . . . . 145 table 12. watchdog timeout periods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 13. clock mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 14. mdis support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 15. bucsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 16. l1csr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 17. mas2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 18. msr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 19. performance optimization checklist?part 1. hardware configuration . . . . . . . . . . . . . . . 171 table 20. performance optimization checklist?part 2. software configuration . . . . . . . . . . . . . . . . 171 table 21. performance optimization checklist?part 3. peripherals and general application guidelines 172 table 22. edma memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 23. edma 32-bit memory map?graphical view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 24. edma_cr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 25. edma_esr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 26. edma_erqrl field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 27. edma_eeirl field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 96 table 28. edma_serqr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 29. edma_cerqr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 30. edma_seeir field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 98 table 31. edma_ceeir field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 99 table 32. edma_cirqr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 table 33. edma_cer field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 34. edma_ssbr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 00 table 35. edma_cdsbr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 36. edma_irqrl field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 02 table 37. edma_erl field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 38. edma_hrsl field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 04 table 39. edma_cprn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 05 table 40. tcd n 32-bit memory structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 41. tcdn field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 42. tcd primary control and status fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 19 table 43. dma request summary for edma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 44. modulo feature example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 45. channel linking parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 table 46. coherency model for a dynamic channel link request . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 table 47. coherency model for method 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 32 list of tables RM0029 28/1740 doc id 15177 rev 8 table 48. coherency model for method 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 32 table 49. master/slave mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 table 50. xbar register configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 table 51. xbar master priority register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 table 52. xbar slave general purpose control register field descriptions . . . . . . . . . . . . . . . . . 240 table 53. pbridge registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 table 54. pbridge memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 table 55. mpcr n field structure descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 table 56. mpcr register fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 table 57. pacr n field structure descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 table 58. peripheral access control register (pacr) fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 table 59. off-platform peripheral access control register (opacr) fields . . . . . . . . . . . . . . . . . . 250 table 60. sram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 table 61. number of wait states required for ram operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 table 62. flash memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 table 63. flash shadow block mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 table 64. flash configuration register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 table 65. mcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 table 66. mcr bit set/clear priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 table 67. lmlr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 table 68. hlr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 table 69. slmlr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 table 70. lmsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 table 71. hsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 table 72. ar field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 table 73. biucr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 table 74. biuapr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 table 75. biucr2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 table 76. ut0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 table 77. ut1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 table 78. ut2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 table 79. umisr n field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 table 80. mpu-to-xbar slave port mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 table 81. mpu memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 table 82. mpu_cesr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 table 83. mpu_ear n field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 table 84. mpu_edr n field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 table 85. mpu_rgd n word 0 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 table 86. mpu_rgd n word 1 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 table 87. mpu_rgd n word 2 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 table 88. mpu_rgd n word 3 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 table 89. mpu_rgdaac n field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 table 90. overlapping region descriptor example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 table 91. typical pin usage across supported ebi modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 table 92. signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 table 93. signal output buffer enable logic by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 table 94. ebi address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 table 95. ebi module configuration register (ebi_mcr) field descriptions . . . . . . . . . . . . . . . . . 323 table 96. ebi transfer error status register (ebi_tesr) field descriptions. . . . . . . . . . . . . . . . . 325 table 97. ebi bus monitor control register (ebi_bmcr) field descriptions . . . . . . . . . . . . . . . . . 326 table 98. ebi base registers (ebi_br0-ebi_br3, ebi_cal_br0-3) field descriptions327 RM0029 list of tables doc id 15177 rev 8 29/1740 table 99. ebi option registers (ebi_or0-ebi_or3, ebi_cal_or0-3) field descriptions330 table 100. default attributes for non-chip-select transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 table 101. write/byte enable signals function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 35 table 102. wrap bursts order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 table 103. small access cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 table 104. examples of 4-word burst addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 table 105. transaction sizes supported by ebi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 table 106. data bus requirements for read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 table 107. data bus contents for write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 60 table 108. termination signals protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 table 109. misalignment cases supported by a 64 bit amba ebi (internal bus) . . . . . . . . . . . . . . . 366 table 110. misalignment cases supported by a 64 bit amba ebi (external bus) . . . . . . . . . . . . . . . 367 table 111. interrupt sources available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 table 112. intc memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 table 113. intc_mcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 table 114. intc_cpr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 table 115. intc_iackr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 table 116. intc_sscir n field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 table 117. intc_psr n field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 table 118. interrupt request sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 table 119. order of isr execution example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 table 120. siu signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 table 121. siu address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 table 122. siu_midr2 field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 table 123. flash memory size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 table 124. flash memory size detailed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 table 125. siu_midr field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 table 126. siu_rsr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 table 127. siu_srcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 table 128. siu_eisr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 table 129. siu_direr field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 table 130. siu_dirsr field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 table 131. siu_osr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 table 132. siu_orer field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 table 133. siu_ireer field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 table 134. siu_ifeer field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 table 135. siu_idfr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 table 136. siu_pcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 table 137. siu_pcr0 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 table 138. siu_pcr1 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 table 139. siu_pcr2 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 table 140. siu_pcr3 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 table 141. siu_pcr8 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 table 142. siu_pcr9 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 table 143. siu_pcr10 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 table 144. siu_pcr11 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 table 145. siu_pcr12 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 table 146. siu_pcr13 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 table 147. siu_pcr14 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 table 148. siu_pcr15 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 table 149. siu_pcr16 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 list of tables RM0029 30/1740 doc id 15177 rev 8 table 150. siu_pcr17 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 table 151. siu_pcr18 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 table 152. siu_pcr19 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 table 153. siu_pcr20 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 table 154. siu_pcr21 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 table 155. siu_pcr22 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 table 156. siu_pcr23 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 table 157. siu_pcr24 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 table 158. siu_pcr25 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 table 159. siu_pcr26 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 table 160. siu_pcr27 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 table 161. siu_pcr28 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 table 162. siu_pcr29 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 table 163. siu_pcr30 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 table 164. siu_pcr31 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 table 165. siu_pcr32 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 table 166. siu_pcr33 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 table 167. siu_pcr34 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 table 168. siu_pcr35 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 table 169. siu_pcr36 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 table 170. siu_pcr37 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 table 171. siu_pcr38 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 table 172. siu_pcr39 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 table 173. siu_pcr40 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 table 174. siu_pcr41 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 table 175. siu_pcr42 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 table 176. siu_pcr43 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 table 177. siu_pcr62 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 table 178. siu_pcr63pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 table 179. siu_pcr64 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 table 180. siu_pcr65 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 table 181. siu_pcr68 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 table 182. siu_pcr69 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 table 183. siu_pcr70 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 table 184. siu_pcr75 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 table 185. siu_pcr76 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 table 186. siu_pcr77 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 table 187. siu_pcr78 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 table 188. siu_pcr79 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 table 189. siu_pcr80 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 table 190. siu_pcr81 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 table 191. siu_pcr82 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 table 192. siu_pcr83 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 table 193. siu_pcr84 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 table 194. siu_pcr85 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 table 195. siu_pcr86 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 table 196. siu_pcr87 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 table 197. siu_pcr88 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 table 198. siu_pcr89 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 table 199. siu_pcr90 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 table 200. siu_pcr91 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 table 201. siu_pcr92 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 RM0029 list of tables doc id 15177 rev 8 31/1740 table 202. siu_pcr93 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 table 203. siu_pcr94 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 table 204. siu_pcr95 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 table 205. siu_pcr96 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 table 206. siu_pcr97 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 table 207. siu_pcr98 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 table 208. siu_pcr99 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 table 209. siu_pcr100 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 table 210. siu_pcr101 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 table 211. siu_pcr102 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 table 212. siu_pcr103 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 table 213. siu_pcr104 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 table 214. siu_pcr105 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 table 215. siu_pcr106 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 table 216. siu_pcr107 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 table 217. siu_pcr108 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 table 218. siu_pcr109 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 table 219. siu_pcr110 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 table 220. siu_pcr113 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 table 221. siu_pcr114 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 table 222. siu_pcr115 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 table 223. siu_pcr116 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 table 224. siu_pcr117 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 table 225. siu_pcr118 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 table 226. siu_pcr119 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 table 227. siu_pcr120 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 table 228. siu_pcr121 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 table 229. siu_pcr122 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 table 230. siu_pcr123 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 table 231. siu_pcr124 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 table 232. siu_pcr125 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 table 233. siu_pcr126 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 table 234. siu_pcr127 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 table 235. siu_pcr128 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 table 236. siu_pcr129 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 table 237. siu_pcr130 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 table 238. siu_pcr131 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 table 239. siu_pcr132 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 table 240. siu_pcr133 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 table 241. siu_pcr134 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 table 242. siu_pcr135 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 table 243. siu_pcr136 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 table 244. siu_pcr137 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 table 245. siu_pcr138 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 table 246. siu_pcr139 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 table 247. siu_pcr140 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 table 248. siu_pcr141 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 table 249. siu_pcr142 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 table 250. siu_pcr143 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 table 251. siu_pcr144 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 table 252. siu_pcr145 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 table 253. siu_pcr179 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 list of tables RM0029 32/1740 doc id 15177 rev 8 table 254. siu_pcr180 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 table 255. siu_pcr181 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 table 256. siu_pcr182 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 table 257. siu_pcr183 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 table 258. siu_pcr184 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 table 259. siu_pcr185 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 table 260. siu_pcr186 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 table 261. siu_pcr187 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 table 262. siu_pcr188 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 table 263. siu_pcr189 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 table 264. siu_pcr190 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 table 265. siu_pcr191 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 table 266. siu_pcr192 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 table 267. siu_pcr193 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 table 268. siu_pcr194 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 table 269. siu_pcr195 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 table 270. siu_pcr196 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 table 271. siu_pcr197 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 table 272. siu_pcr198 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 table 273. siu_pcr199 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 table 274. siu_pcr200 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 table 275. siu_pcr201 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 table 276. siu_pcr202 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 table 277. siu_pcr203 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 table 278. siu_pcr204 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 table 279. siu_pcr206 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 table 280. siu_pcr207 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 table 281. siu_pcr208 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 table 282. siu_pcr209 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 table 283. siu_pcr210 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 table 284. siu_pcr211 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 table 285. siu_pcr212 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 table 286. siu_pcr213 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 table 287. siu_pcr214 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 table 288. siu_pcr215 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 table 289. siu_pcr216 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 table 290. siu_pcr217 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 table 291. siu_pcr218 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 table 292. siu_pcr219 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 table 293. siu_pcr220 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 table 294. siu_pcr221 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 table 295. siu_pcr222 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 table 296. siu_pcr223 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 table 297. siu_pcr224 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 table 298. siu_pcr225 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 table 299. siu_pcr226 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 table 300. siu_pcr227 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 table 301. siu_pcr228 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 table 302. siu_pcr229 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 table 303. siu_pcr230 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 table 304. siu_pcr231 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 table 305. siu_pcr232 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 RM0029 list of tables doc id 15177 rev 8 33/1740 table 306. siu_pcr244 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 table 307. siu_pcr245 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 table 308. siu_pcr336 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 table 309. siu_pcr338 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 table 310. siu_pcr339 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 table 311. siu_pcr340 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 table 312. siu_pcr341pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 table 313. siu_pcr342 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 table 314. siu_pcr343 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 table 315. siu_pcr345 pa values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 table 316. siu_pcr350 ? siu_pcr381 dspi muxing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 table 317. siu_pcr382 ? siu_pcr389 dspi muxing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 table 318. siu_pcr390 ? siu_pcr413 dspi muxing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 table 319. siu_gpdox_x field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 table 320. siu_gpdix_x field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 table 321. siu_etisr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 table 322. siu_eiisr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 table 323. siu_disr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 table 324. eqadc queue0 enhanced trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 table 325. eqadc queue1 enhanced trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 table 326. eqadc queue2 enhanced trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 table 327. eqadc queue3 enhanced trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 table 328. eqadc queue4 enhanced trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 table 329. eqadc queue5 enhanced trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 table 330. siu_isel8 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 table 331. eqadc advance trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 68 table 332. decimation filter control source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 70 table 333. siu_ccr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 table 334. siu_eccr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 table 335. siu_sysdiv field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 table 336. siu_hlt field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 table 337. siu_hltack field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 table 338. siu_empcr0 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 table 339. register field reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 table 340. clock mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 table 341. signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 table 342. fmpll detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 table 343. fmpll memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 table 344. syncr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 table 345. synsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 table 346. esyncr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 table 347. esyncr2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 table 348. synfmmr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 table 349. input clock frequency at the predivider input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 table 350. loss-of-clock monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 table 351. loss-of-clock reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 table 352. loss-of-clock interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 table 353. ecsm 32-bit memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 table 354. ecsm_mrsr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 table 355. ecsm_mwcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 14 table 356. ecsm_mudcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5 table 357. ahb response and ecc reporting for even and odd ecc . . . . . . . . . . . . . . . . . . . . . . 616 list of tables RM0029 34/1740 doc id 15177 rev 8 table 358. ecsm_ecr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 table 359. ecsm_esr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 table 360. ecsm_eegr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 table 361. ecsm_fear field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 table 362. ecsm_femr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 table 363. ecsm_feat field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 table 364. ecsm_fedr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 table 365. ecsm_rear field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 table 366. ecsm_presr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 29 table 367. ram syndrome mapping for single-bit correctable errors. . . . . . . . . . . . . . . . . . . . . . . . . 629 table 368. ecsm_remr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 table 369. ecsm_reat field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 table 370. ecsm_redr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 table 371. stm memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 table 372. stm_cr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 table 373. stm_cnt field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 table 374. stm_ccrn field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 table 375. stm_cirn field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 table 376. stm_cmpn register field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 table 377. swt memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 table 378. swt_mcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 table 379. swt_ir field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 table 380. swt_to register field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 45 table 381. swt_wn register field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5 table 382. swt_sr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 table 383. swt_co register field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 46 table 384. swt_sk field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 table 385. bam memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 table 386. mmu configuration for internal flash boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2 table 387. boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 table 388. rchw field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 table 389. watchdog timeouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 table 390. possible rchw locations in the internal flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 table 391. can/esci pins configuration for can/esci fixed baud rate boot modes. . . . . . . . . . . . . 659 table 392. serial boot mode ? baud rate & watchdog summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 table 393. can bit timing lookup table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 table 394. maximum and minimum detectable baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 table 395. mmu configuration for ebi boot and serial boot modes . . . . . . . . . . . . . . . . . . . . . . . . . 665 table 396. ebi register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 table 397. all available spc564a74xx, spc564a80xx emios channel configurations . . . . . . . . . . 668 table 398. spc564a74xx, spc564a80xx emios memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 table 399. emios_mcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 table 400. emios_gfr field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 table 401. emios_oudr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 table 402. emios_ucdis field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 table 403. emios_cadr[ n ], emios_cbdr[ n ], and emios_alta[ n ] values assignment . . . . . . . 684 table 404. emios_ccr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 table 405. mode values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 table 406. emios_csr[ n ] field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 table 407. stac client submodule server slot assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 table 408. reaction module outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 table 409. signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 RM0029 list of tables doc id 15177 rev 8 35/1740 table 410. reaction module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 25 table 411. reacm_mcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 27 table 412. reacm_tcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 table 413. reacm_thrr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 0 table 414. reacm_sinr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 31 table 415. reacm_gefr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 1 table 416. reacm_chcrn field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 table 417. output assignment through doff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4 table 418. reacm_chsrn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 table 419. reacm_chrrn field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 table 420. reacm_chrrn[chir] values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 table 421. reacm_stbk field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 39 table 422. reacm_hotbk field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 table 423. reacm_thbk field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1 table 424. reacm_adcmax field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 table 425. reacm_rangepwd field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 table 426. reacm_minpwd field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 table 427. reacm_mwbk field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 table 428. mm[2:0] configuration: modulation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 table 429. sm[1:0] configuration: sequencer modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 table 430. etpu signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786 table 431. output disable channel groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 table 432. high level memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 table 433. detailed memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 table 434. etpu_mcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 table 435. etpu_cdcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 table 436. etpu_misccmpr field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802 table 437. etpu_scmoffdatar field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 table 438. etpu_ecr field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 table 439. filter prescaler clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806 table 440. channel digital filter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 table 441. entry table base address options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 table 443. tcr2 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 table 442. etpu_tbcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 table 444. tcrclk filter clock/mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 table 445. am - angle mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 table 446. tcr1 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812 table 447. etpu_tb1r field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 table 448. etpu_tb2r field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815 table 449. etpu_redcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 16 table 450. etpu_wdtr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 table 451. etpu_idle field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 table 452. etpu_cisr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822 table 453. etpu_cdtrsr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3 table 454. etpu_ciosr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 table 455. etpu_cdtrosr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 table 456. etpu_cier field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 table 457. etpu_cdtrer field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7 table 458. etpu_cpssr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 table 459. etpu_cssr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 table 460. channel registers structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 table 461. channel registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 list of tables RM0029 36/1740 doc id 15177 rev 8 table 462. etpu_cxcr field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 table 463. etpu_cxscr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 table 464. etpu_cxhsrr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 38 table 465. standard channel condition encoding scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843 table 466. alternate channel condition encoding scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 table 467. scm clocks and misc activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 table 468. priority passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 table 469. priority passing disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 table 470. event registers microcode accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875 table 471. tbsa/b programming states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876 table 472. pin control registers microcode accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876 table 473. ipaca/b and opaca/b encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878 table 474. psc and pscs encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878 table 475. tbsa output buffer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879 table 476. general channel registers microcode access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 table 477. chan-selected features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 table 478. pdcm encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 table 479. msr[1:0] signals ? match service requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889 table 480. tcap and tsr signals ? transition captures and service requests . . . . . . . . . . . . . . . 890 table 481. mcap signal ? match capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890 table 482. tbm2 signal ? transition blocks match b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890 table 483. m1et, m1em2, m1bm2, m2bm1, m2bt signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890 table 484. predefined channel mode control signals decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891 table 485. simultaneous match pin action priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 07 table 486. link engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909 table 487. pulse widths and delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911 table 488. stac bus and host read sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917 table 489. negative (n) flag behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943 table 490. overflow flag on addition ? v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943 table 491. zero flag ? z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943 table 492. types of add operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944 table 493. carry flag update on add operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 45 table 494. types of adc operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945 table 495. types of bitwise operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946 table 496. number of shifted/rotated bits for each bs[1:0] value . . . . . . . . . . . . . . . . . . . . . . . . . . . 947 table 497. carry flag value on multibit shift/rotate operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947 table 498. alu flags in absolute value operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948 table 499. cin and binv with mdu operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949 table 500. channel flags as branch condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 table 501. spram source/destination register selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955 table 502. spram p access size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955 table 503. spram access direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955 table 504. zero spram operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956 table 505. diob post-increment / pre-decrement ? stc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956 table 506. semaphore operations fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957 table 507. register set selection by abse or abde . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957 table 508. register set selection by t4bbs w/o abse, abde . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 table 509. b source selection ? t4bbs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 table 510. a source selection ? t4abs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959 table 511. destination selection ? t2abd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959 table 512. operation size determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961 table 513. flag sampling using ccsv field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961 RM0029 list of tables doc id 15177 rev 8 37/1740 table 514. flag sampling using ccs field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962 table 515. b-source inversion ? binv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962 table 516. alu carry-in control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962 table 517. shift register control ? src . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963 table 518. post-alu shift operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963 table 519. alu/mdu conditional execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964 table 520. a-source size override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964 table 521. as/ce field a source size override funcionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 table 522. a source sign extension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 table 523. alu operation selection ? aluop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966 table 524. 24-bit immediate destination ? t2d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 67 table 525. alu operation selection with immediate data ? aluopi. . . . . . . . . . . . . . . . . . . . . . . . 967 table 526. p flags operation ? flc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 table 527. time base selection 1 ? tbsa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 table 528. time base selection 2 ? tbsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970 table 529. input and output pin action control ? ipaca/b and opaca/b . . . . . . . . . . . . . . . . . . . . 970 table 530. immediate pin state control ? psc and pscs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 table 531. write matcha/b ? erwa/b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 table 532. clear transition/match event registers ? mrla/b, tdl . . . . . . . . . . . . . . . . . . . . . . . . . 972 table 533. independent tdla/b clear ? two-bit tdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972 table 534. disable matches ? mrle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972 table 535. two-bit mrle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973 table 536. disable match and transition service request ? mtd . . . . . . . . . . . . . . . . . . . . . . . . . . 973 table 537. predefined channel modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973 table 538. channel and data transfer requests ? circ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 table 539. link service request negation control ? lsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 table 540. jump / call selection ? j/c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 table 541. branch condition inversion ? bcf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 76 table 542. branch condition selection ? bcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 76 table 543. return and dispatch ? r/d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977 table 544. return from sub-routine ? rtn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977 table 545. flush pipeline ? fls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978 table 546. diob load from spram and alu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980 table 547. microinstruction formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982 table 548. breakpoint, stop and service requests resolution from idle . . . . . . . . . . . . . . . . . . . . . . . 986 table 549. longest threads and ram accesses for old tpu functions . . . . . . . . . . . . . . . . . . . . . . 1000 table 550. system configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001 table 551. worst-case latency for channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 003 table 552. worst-case latency for channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 004 table 553. worst-case latency for channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 005 table 554. first-try system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006 table 555. second-try system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 08 table 556. second-try system with channel 0 and 1 reconfigured . . . . . . . . . . . . . . . . . . . . . . . . . . 1009 table 557. parameter addresses and endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009 table 558. predefined channel mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 table 559. external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031 table 560. eqadc memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036 table 561. eqadc module configuration register (eqadc_mcr) field description . . . . . . . . . . . 1040 table 562. eqadc ssi enable field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 table 563. debug enable field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 table 564. eqadc null message send format register (eqadc_nmsfr) field description . . . 1042 table 565. eqadc external trigger digital filter register (eqadc_etdfr) field description . . . 1043 list of tables RM0029 38/1740 doc id 15177 rev 8 table 566. minimum required time to valid etrig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043 table 567. eqadc cfifo push register x (eqadc_cfprx) field description . . . . . . . . . . . . . . . 1044 table 568. eqadc rfifo pop register x (eqadc_rfprx) field description . . . . . . . . . . . . . . . . 1045 table 569. eqadc cfifo control register x (eqadc_cfcrx) field description . . . . . . . . . . . . . 1047 table 570. cfifo operation mode table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 48 table 571. cfifo0 advance trigger operation mode table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049 table 572. eqadc interrupt and dma control register x (eqadc_idcrx) field description . . . . 1051 table 573. eqadc fifo and interrupt status register x (eqadc_fisrx) field description . . . . . 1055 table 574. eqadc cfifo transfer counter register x (eqadc_cftcrx) field description . . . . 1061 table 575. eqadc cfifo status snapshot register x (eqadc_cfssrx) field description. . . . . 1063 table 576. lcftcbn description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063 table 577. lcftssi description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064 table 578. field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065 table 579. current cfifo status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065 table 580. eqadc ssi control register (eqadc_ssicr) field description . . . . . . . . . . . . . . . . . 1066 table 581. minimum delay after transmission (tmdt) time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066 table 582. system clock divide factor for baud clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067 table 583. eqadc ssi receive data register (eqadc_ssirdr) field description . . . . . . . . . . . 1068 table 584. eqadc stac client configuration register (eqadc_redlccr) field description . . 1069 table 585. stac bus timebase bits selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 table 586. srvm valid values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 table 587. eqadc cfifox registers (eqadc_cfxrw) (w=0, .., 3) field description . . . . . . . . . . 1073 table 588. field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 table 589. eqadc rfifox registers (eqadc_rfxrw) (w=0, .., 3) field description . . . . . . . . . . 1078 table 590. on-chip adc memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 78 table 591. adc0/1 control registers (adc0/1_cr) field description . . . . . . . . . . . . . . . . . . . . . . . 1081 table 592. timebase selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082 table 593. system clock divide factor for adc clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082 table 594. adc time stamp control register (adc_tscr) field description . . . . . . . . . . . . . . . . 1084 table 595. clock divide factor for time stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4 table 596. adc time base counter register (adc_tbcr) field description . . . . . . . . . . . . . . . . . 1085 table 597. adc0/1 gain calibration constant registers (adc0/1_gccr) field description . . . . . 1086 table 598. adc0/1 offset calibration constant registers (adc0/1_occr) field description . . . . 1087 table 599. alternate configuration 1-8 control registers (adc_acr1-8) field description . . . . . . 1088 table 600. conversion destination selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 089 table 601. resolution selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089 table 602. timebase selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089 table 603. adc pre-gain control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090 table 604. adc0/1 alternate x offset registers (adc0/1_aorx, x=1-2) field description . . . . . . . 1091 table 605. adc pull up/down control register x (a dc_pudcrx, x=0-7) field description . . . . . . 1092 table 606. channel x pull up/down field definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092 table 607. pull up/down strength field definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 2 table 608. conversion command format for the standard configuration field description. . . . . . . 1098 table 609. message_tag description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9 table 610. sampling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100 table 611. conversion command format for alternate configurations field description . . . . . . . . . 1101 table 612. alternate configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101 table 613. write configuration command format for on-chip adc operation field description . . 1102 table 614. read configuration command format for on-chip adc operation field description . . 1103 table 615. adc result format (right justified signed) field description. . . . . . . . . . . . . . . . . . . . . 1105 table 616. correspondence between analog voltages and digital values, . . . . . . . . . . . . . . . . . . . 1105 table 617. command message format for external device operation field description . . . . . . . . . 1107 RM0029 list of tables doc id 15177 rev 8 39/1740 table 618. result message format for external device operation field description . . . . . . . . . . . . 1108 table 619. command bufferx busy status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109 table 620. field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110 table 621. cfifo scan trigger mode - command transfer start/stop summary . . . . . . . . . . . . . 1128 table 622. command fifo status switching condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129 table 623. adc clock configuration example (system clock frequency=120 mhz) . . . . . . . . . . . 1144 table 624. stac client submodule server slot assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 table 625. binary and decimal representations of the gain constant . . . . . . . . . . . . . . . . . . . . . . 1151 table 626. adc0/1_emux bits combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155 table 627. non-multiplexed channel assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155 table 628. multiplexed channel assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7 table 629. encoding of ma pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159 table 630. eqadc fifo interrupt summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161 table 631. eqadc fifo dma summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161 table 632. ctrl[0:1] field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169 table 633. application of each cqueue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174 table 634. example of cqueue commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178 table 635. calibration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185 table 636. terminology comparison between qadc and eqadc . . . . . . . . . . . . . . . . . . . . . . . . . 1189 table 637. usage comparison between qadc and eqadc system . . . . . . . . . . . . . . . . . . . . . . . 1189 table 638. decimation filter parameters for spc564a74xx, spc564a80xx . . . . . . . . . . . . . . . . . 1191 table 639. operation mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193 table 640. decimation filter device memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195 table 641. decfilter_mcr register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198 table 642. cascd[1:0] ? filter cascade mode configuration selection . . . . . . . . . . . . . . . . . . . . . 1198 table 643. ftype[1:0] ? filter type selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199 table 644. scal[1:0] ? filter scaling factor definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 99 table 645. isel/mixm definition ? read/write from/to input/output buffers . . . . . . . . . . . . . . . . . 1201 table 646. dec_rate[3:0] definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202 table 647. tmode[1:0] definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203 table 648. decfilter_msr register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204 table 649. decfilter_mxcr register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207 table 650. szrosel ? integrator zero mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 table 651. shltsel ? integrator halt control selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 table 652. srqsel ? integrator output request mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209 table 653. sensel ? integrator enable control selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209 table 654. decfilter_mxsr register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210 table 655. decfilter_ib register field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212 table 656. decfilter_ob register field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213 table 657. decfilter_coefn register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214 table 658. decfilter_tapn register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214 table 659. decfilter_edid register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215 table 660. decfilter_fintval register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216 table 661. decfilter_fintcnt register field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216 table 662. decfilter_cintval register field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217 table 663. decfilter_cintcnt register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218 table 664. parallel side interface memory map for decfilter data exchange . . . . . . . . . . . . . . . . . . 1218 table 665. decfilter_iob register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219 table 666. m_ctrl[1:0] ? decimation filter control functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219 table 667. decimation filter cascade mode data bus field description . . . . . . . . . . . . . . . . . . . . . . . 1240 table 668. features in cascade mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241 table 669. coefficient values given by spw digital filter design tool . . . . . . . . . . . . . . . . . . . . . . . . 1243 list of tables RM0029 40/1740 doc id 15177 rev 8 table 670. coefficient values for decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243 table 671. temperature calculati on constants register 0 (tsens_tccr0) field descriptions. . . 1249 table 672. temperature calculati on constants register 1 (tsens_tccr1) field descriptions. . . 1250 table 673. user trim values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251 table 674. crc register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256 table 675. crc_cfg field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257 table 676. crc_inp field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258 table 677. crc_cstat field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 59 table 678. crc_outp field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 260 table 679. dspi channel frequency support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 70 table 680. signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271 table 681. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273 table 682. dspi_mcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275 table 683. dspi_hcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278 table 684. dspi_tcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279 table 685. dspi_ctar n field description in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281 table 686. dspi sck duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283 table 687. delay scaler encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284 table 688. dspi baud rate scaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284 table 689. dspi_ctar 0 field description in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285 table 690. dspi_sr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286 table 691. dspi_rser field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288 table 692. dspi_pushr field description in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291 table 693. dspi_pushr field description in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292 table 694. dspi_popr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293 table 695. dspi_txfr n field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293 table 696. dspi_rxfr n field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294 table 697. dspi_dsicr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295 table 698. dspi_sdr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1297 table 699. dspi_asdr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1298 table 700. dspi_compr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 98 table 701. dspi_ddr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299 table 702. dspi_dsicr1 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 300 table 703. dspi_ssr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 301 table 704. dspi_pisr0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 02 table 705. dspi_pisr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 03 table 706. dspi_pisr2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 04 table 707. dspi_pisr3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 05 table 708. dspi_dimr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 306 table 709. dspi_dipr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 307 table 710. dsi data transfer initiation control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314 table 711. baud rate computation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 18 table 712. pcs to sck delay computation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1319 table 713. after sck delay computation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1319 table 714. delay after transfer computation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1319 table 715. peripheral chip select strobe assert computation example. . . . . . . . . . . . . . . . . . . . . . . 1320 table 716. peripheral chip select strobe negate computation example . . . . . . . . . . . . . . . . . . . . . . 1320 table 717. interrupt and dma request conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1334 table 718. dspi interrupt and dma request conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1337 table 719. lvds pads voltage swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338 table 720. dspi_b connectivity table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339 table 721. dspi_c connectivity table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343 RM0029 list of tables doc id 15177 rev 8 41/1740 table 722. dspi_d connectivity table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346 table 723. baud rate values (bit/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349 table 724. delay values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1350 table 725. acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353 table 726. glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353 table 727. esci 32-bit memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357 table 728. register conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357 table 729. esci_brr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358 table 730. esci_cr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359 table 731. receive source mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 360 table 732. esci_cr2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361 table 733. esci_dr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363 table 734. esci_ifsr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364 table 735. esci_ifsr2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 366 table 736. esci_lcr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 367 table 737. esci_lcr2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368 table 738. esci_ltr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370 table 739. esci_lrr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371 table 740. esci_lpr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371 table 741. esci_cr3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1372 table 742. supported data frame formats for rx and tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373 table 743. supported data frame formats for rx only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374 table 744. supported break character formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375 table 745. supported idle character formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6 table 746. baud rates error example (mclk = 10.2 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377 table 747. faster receiver maximum tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1380 table 748. slower receiver maximum tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381 table 749. transmitter states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382 table 750. transmitter application transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 382 table 751. transmitter module transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383 table 752. transmit source priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383 table 753. receiver states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386 table 754. receiver application transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386 table 755. receiver module transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387 table 756. start bit verification result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392 table 757. start bit noise detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392 table 758. data bit sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1393 table 759. stop bit verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1393 table 760. esci interrupt flags and interrupt enable bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405 table 761. flexcan signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412 table 762. module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413 table 763. message buffer mb0 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413 table 764. message buffer structure (word 0?0x0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415 table 765. message buffer code for rx buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416 table 766. message buffer code for tx buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7 table 767. rx fifo structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419 table 768. module configuration register (mcr) field descriptions . . . . . . . . . . . . . . . . . . . . . . . . 1420 table 769. idam coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425 table 770. cr register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426 table 771. rxgmask register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1430 table 772. esr register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1432 table 773. imrh register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436 list of tables RM0029 42/1740 doc id 15177 rev 8 table 774. imrl register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436 table 775. ifrh register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1437 table 776. ifrl register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438 table 777. rximr0 ? rximr63 register field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439 table 778. recommended fen and bcc settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448 table 779. time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1451 table 780. can standard compliant bit time segment settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1451 table 781. minimum ratio between peripheral clock frequency and can bit rate . . . . . . . . . . . 1452 table 782. wake-up from stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454 table 783. list of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457 table 784. external signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462 table 785. flexray memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1464 table 786. register access conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1470 table 787. additional register reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1470 table 788. register write access restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1471 table 789. fr_mvr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472 table 790. fr_mcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1473 table 791. flexray channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474 table 792. fr_symbadr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5 table 793. fr_stbscr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 476 table 794. strobe signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476 table 795. fr_mbdsr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477 table 796. fr_mbssutr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8 table 797. fr_pedrar field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 479 table 798. fr_pocr field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480 table 799. fr_gifer field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481 table 800. fr_pifr0 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483 table 801. fr_pifr1 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486 table 802. fr_pier0 field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487 table 803. fr_pier1 field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488 table 804. fr_chierfr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 489 table 805. fr_mbivec field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492 table 806. fr_casercr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 2 table 807. fr_cbsercr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 3 table 808. fr_psr0 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493 table 809. fr_psr1 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495 table 810. fr_psr2 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496 table 811. fr_psr3 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498 table 812. fr_mtctr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1499 table 813. fr_cyctr field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 table 814. fr_sltctar field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 500 table 815. fr_sltctbr field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 500 table 816. fr_rtcorvr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 1 table 817. fr_ofcorvr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 2 table 818. fr_cifr field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502 table 819. fr_symator field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 3 table 820. fr_sfcntr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 504 table 821. fr_sftor field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 505 table 822. fr_sftccsr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 05 table 823. fr_sfidrfr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 506 table 824. fr_sfidafvr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 07 table 825. fr_sfidafmr field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 07 RM0029 list of tables doc id 15177 rev 8 43/1740 table 826. nmvr[0:5] field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508 table 827. mapping of nmvrn to the received payload bytes nmvn . . . . . . . . . . . . . . . . . . . . . . . 1508 table 828. fr_nmvlr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508 table 829. fr_ticcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509 table 830. fr_ti1cysr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510 table 831. fr_ti1mtor field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 510 table 832. fr_ti2cr0 field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511 table 833. fr_ti2cr1 field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512 table 834. fr_sssr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512 table 835. mapping between fr_sssrn and fr_ssrn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513 table 836. fr_ssccr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513 table 837. mapping between internal fr_ssccrn and fr_sscrn . . . . . . . . . . . . . . . . . . . . . . . 1514 table 838. fr_ssr0?fr_ssr7 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1515 table 839. fr_sscr0?fr_sscr3 field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517 table 840. fr_mtsacfr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 17 table 841. mtsbcfr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518 table 842. fr_rsbir field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518 table 843. fr_rfsymbadr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519 table 844. fr_rfptr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519 table 845. sel controlled receiver fifo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520 table 846. fr_rfwmsr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 20 table 847. fr_rfsir field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521 table 848. rfdsr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521 table 849. fr_rfarir field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522 table 850. fr_rfbrir field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522 table 851. fr_rfflpcr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 23 table 852. fr_rfmidafvr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523 table 853. fr_rfmidafmr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523 table 854. fr_rffidrfvr field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4 table 855. fr_rffidrfmr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524 table 856. fr_rfrfcfr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 25 table 857. fr_rfrfctr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 25 table 858. fr_ldtxslar field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 6 table 859. fr_ldtxslbr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 7 table 860. protocol configuration register fields (sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1527 table 861. wakeup channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529 table 862. fr_eeifer field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537 table 863. fr_eericr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539 table 864. fr_eerar field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540 table 865. fr_eerdr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540 table 866. valid bits in fr_eerdr[data] / fr_eeidr[data] field . . . . . . . . . . . . . . . . . . . . . . . 1541 table 867. fr_eersr field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541 table 868. fr_eeiar field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542 table 869. fr_eeidr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542 table 870. fr_eeicr field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1543 table 871. fr_mbccsrn field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4 table 872. fr_mbccfrn field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 46 table 873. channel assignment description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 546 table 874. fr_mbfidrn field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 547 table 875. fr_mbidxrn field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 547 table 876. frame header write access constraints (transmit message buffer) . . . . . . . . . . . . . . . . 1559 table 877. frame header field description (receive message buffer and receive ffo). . . . . . . . . . 1560 list of tables RM0029 44/1740 doc id 15177 rev 8 table 878. frame header field description (transmit message buffer) . . . . . . . . . . . . . . . . . . . . . . . 1560 table 879. receive message buffer slot status content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561 table 880. receive message buffer slot status field description ) . . . . . . . . . . . . . . . . . . . . . . . . . 1562 table 881. transmit message buffer slot status content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563 table 882. transmit message buffer slot status structure field description . . . . . . . . . . . . . . . . . . 1564 table 883. message buffer data field minimum length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566 table 884. frame data write access constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 7 table 885. frame data field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567 table 886. individual message buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1568 table 887. single transmit message buffer access regions description . . . . . . . . . . . . . . . . . . . . . . 1570 table 888. single transmit message buffer state description (sheet 1 of 2) . . . . . . . . . . . . . . . . . . 1571 table 889. single transmit message buffer application transitions. . . . . . . . . . . . . . . . . . . . . . . . . . 1572 table 890. single transmit message buffer module transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1573 table 891. single transmit message buffer transition priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1574 table 892. receive message buffer access region description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1579 table 893. receive message buffer states and access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1580 table 894. receive message buffer application transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581 table 895. receive message buffer module transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581 table 896. receive message buffer transition priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1582 table 897. receive message buffer update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 83 table 898. double transmit message buffer access regions description . . . . . . . . . . . . . . . . . . . . . 1586 table 899. double transmit message buffer state description (commit side) . . . . . . . . . . . . . . . . . . 1587 table 900. double transmit message buffer state description (transmit side) (sheet 2 of 2) . . . . . . 1588 table 901. double transmit message buffer host transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590 table 902. double transmit message buffer module transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590 table 903. double transmit message buffer transition priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591 table 904. message buffer search priority (static segment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595 table 905. message buffer search priority (dynamic segment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595 table 906. sync frame table generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609 table 907. key slot frame type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611 table 908. slot status content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616 table 909. flexray channel bit rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624 table 910. pe dram layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624 table 911. chi lram layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1625 table 912. detected memory error types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1626 table 913. pe dram checkbits coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627 table 914. fr_eercr[code] pe dram syndrome coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628 table 915. chi lram checkbits coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628 table 916. fr_eercr[code] chi lram syndr ome coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629 table 917. maximum symator[timeout] examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632 table 918. minimum f chi [mhz] examples (128 message buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . 1635 table 919. protocol control command priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 36 table 920. transmit buffer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637 table 921. receive buffer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637 table 922. pit_rti memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642 table 923. timer channel n / rti channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642 table 924. pitmcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643 table 925. ldval field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644 table 926. cval field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645 table 927. tctrl field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646 table 928. tflg field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646 table 929. power management controller external signals (maximum ratings) . . . . . . . . . . . . . . . . 1652 RM0029 list of tables doc id 15177 rev 8 45/1740 table 930. power management controller memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653 table 931. mcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654 table 932. trimr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656 table 933. sr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1660 table 934. non-volatile user options register (nvusro) field description . . . . . . . . . . . . . . . . . . 1665 table 935. eqadc test mux channel for internal pmc signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670 table 936. device-specific parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672 table 937. device identification register parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 2 table 938. device-specific auxiliary tap controller instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672 table 939. jtag signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674 table 940. device identification register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676 table 941. censor_ctrl register field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1677 table 942. jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1680 table 943. nexus trace port routing and speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 85 table 944. parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1685 table 945. npc signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1689 table 946. npc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1690 table 947. did field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692 table 948. pcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693 table 949. mcko_div values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1694 table 950. npc reset configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695 table 951. npc output messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697 table 952. implemented instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698 table 953. loading nexus-enable instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701 table 954. write to a 32-bit nexus client register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702 table 955. dts register access effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708 table 956. dts module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708 table 957. dts_enable field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 09 table 958. dts_startup field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710 table 959. dts_semaphore field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711 table 960. documenr revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713 list of figures RM0029 46/1740 doc id 15177 rev 8 list of figures figure 1. spc564a74xx, spc564a80xx block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 2. external reset flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 3. internal reset flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 4. reset configuration half word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 5. reset configuration timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 6. system clock diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 7. fmpll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 8. bypass mode with crystal reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 figure 9. bypass mode with external reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 10. normal mode with crystal reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 11. normal mode with external reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 12. mdis and halt clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 13. branch unit control and status register (bucsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 14. l1 cache control and status register 1 (l1csr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 15. mmu assist register 2 (mas2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 16. influence of compiler settings on application performance and code size . . . . . . . . . . . . 168 figure 17. machine state register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 18. e200z4 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 19. edma block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 figure 20. edma control register (edma_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 figure 21. edma error status register (edma_esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 22. edma enable request high register (edma_erqrh) . . . . . . . . . . . . . . . . . . . . . . . . . 194 figure 23. edma enable request register (edma_erqrl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 24. edma enable error interrupt high register (edma_eeirh). . . . . . . . . . . . . . . . . . . . . . 196 figure 25. edma enable error interrupt low register (edma_eeirl) . . . . . . . . . . . . . . . . . . . . . . 196 figure 26. edma set enable request register (edma_serqr) . . . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 27. edma clear enable request register (edma_cerqr). . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 28. edma set enable error interrupt register (edma_seeir) . . . . . . . . . . . . . . . . . . . . . . . 198 figure 29. edma clear enable error interrupt register (edma_ceeir) . . . . . . . . . . . . . . . . . . . . . 198 figure 30. edma clear interrupt request (edma_cirqr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 figure 31. edma clear error register (edma_cer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 figure 32. edma set start bit register (edma_ssbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 figure 33. edma clear done status bit register (edma_cdsbr) . . . . . . . . . . . . . . . . . . . . . . . . 201 figure 34. edma interrupt request high register (edma_irqrh) . . . . . . . . . . . . . . . . . . . . . . . . . 202 figure 35. edma interrupt request register (edma_irqrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 figure 36. edma error high register (edma_erh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 37. edma error register (edma_erl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 38. edma hardware request status register high (edma_hrsh). . . . . . . . . . . . . . . . . . . 204 figure 39. edma hardware request status register low (edma_hrsl) . . . . . . . . . . . . . . . . . . . 204 figure 40. edma channel n priority register (edma_cprn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 41. tcd structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 figure 42. edma operation, part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 figure 43. edma operation, part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 figure 44. edma operation, part 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 45. example of multiple loop iterations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 46. memory array terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 47. xbar device-specific block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 figure 48. key to register fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 RM0029 list of figures doc id 15177 rev 8 47/1740 figure 49. master priority register (xbar_mprn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 figure 50. slave general purpose control register (xbar_sgpcrn) . . . . . . . . . . . . . . . . . . . . . . 240 figure 51. pbridge interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 figure 52. mpcr n field structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 figure 53. pacr n field structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 figure 54. sram block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 figure 55. flash segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 figure 56. flash system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 figure 57. module configuration register (mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 figure 58. low/mid-address space block lock register (lmlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 figure 59. high-address space block lock register (hlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 figure 60. secondary low/mid-address space block lock register (slmlr). . . . . . . . . . . . . . . . . 269 figure 61. low/mid-address space block select register (lmsr) . . . . . . . . . . . . . . . . . . . . . . . . . 270 figure 62. high-address space block select register (hsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 figure 63. address register (ar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 figure 64. bus interface unit configuration register (biucr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 figure 65. bus interface unit access protection register (biuapr) . . . . . . . . . . . . . . . . . . . . . . . . 275 figure 66. bus interface unit configurat ion register 2 (biucr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 figure 67. user test 0 (ut0) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 figure 68. user test 1 (ut1) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 figure 69. user test 2 (ut2) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 figure 70. user multiple input signature register 0 (umisr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 figure 71. user multiple input signature register 1 (umisr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 figure 72. user multiple input signature register 2 (umisr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 figure 73. user multiple input signature register 3 (umisr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 figure 74. user multiple input signature register 4 (umisr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 figure 75. program sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 figure 76. erase sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 figure 77. mpu control/error status register (mpu_cesr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 figure 78. mpu error address register, slave port n (mpu_ear n ) . . . . . . . . . . . . . . . . . . . . . . . . 299 figure 79. mpu error detail register, slave port n (mpu_edr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . 300 figure 80. mpu region descriptor n , word 0 register (mpu_rgd n .word0) . . . . . . . . . . . . . . . . . 302 figure 81. mpu region descriptor n , word 1 register (mpu_rgd n .word1) . . . . . . . . . . . . . . . . . 302 figure 82. mpu region descriptor n , word 2 register (mpu_rgd n .word2) . . . . . . . . . . . . . . . . . 304 figure 83. mpu region descriptor n , word 3 register (mpu_rgd n .word3) . . . . . . . . . . . . . . . . . 306 figure 84. mpu rgd alternate access control n (mpu_rgdaac n ). . . . . . . . . . . . . . . . . . . . . . . . 307 figure 85. external bus interface with calibration bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 figure 86. ebi module configuration register (ebi_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 figure 87. ebi transfer error status register (ebi_tesr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 figure 88. ebi bus monitor control register (ebi_bmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 figure 89. ebi base registers (ebi_br0-ebi_br3, ebi_cal_br0-3) . . . . . . . . . . . . . . . . . . . . . . 327 figure 90. ebi option registers (ebi_or0-ebi_or3, ebi_cal_or0-3) . . . . . . . . . . . . . . . . . . . . 330 figure 91. bank base address & match structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 figure 92. basic transfer protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 figure 93. basic flow diagram of a single beat read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 figure 94. single beat 32-bit read cycle, cs access, zero wait states . . . . . . . . . . . . . . . . . . . . . 339 figure 95. single beat 32-bit read cycle, cs access, one wait state . . . . . . . . . . . . . . . . . . . . . . 339 figure 96. single beat 32-bit read cycle, non-cs access, zero wait states . . . . . . . . . . . . . . . . . 340 figure 97. basic flow diagram of a single beat write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 figure 98. single beat 32-bit write cycle, cs access, zero wait states . . . . . . . . . . . . . . . . . . . . . 342 figure 99. single beat 32-bit write cycle, cs access, one wait state . . . . . . . . . . . . . . . . . . . . . . 342 figure 100. single beat 32-bit write cycle, non-cs access, zero wait states . . . . . . . . . . . . . . . . . 343 list of figures RM0029 48/1740 doc id 15177 rev 8 figure 101. back-to-back 32-bit reads to the same cs bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 figure 102. back-to-back 32-bit reads to different cs banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 figure 103. write after read to the same cs bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 figure 104. back-to-back 32-bit writes to the same cs bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 figure 105. read after write to the same cs bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 figure 106. basic flow diagram of a burst read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 figure 107. burst 32-bit read cycle, zero wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 figure 108. burst 32-bit read cycle, one initial wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 figure 109. burst 32-bit read cycle, one wait state between beats, tbdip=0 . . . . . . . . . . . . . . . . 352 figure 110. burst 32-bit read cycle, one wait state between beats, tbdip=1 . . . . . . . . . . . . . . . . 353 figure 111. single beat 32-bit write cycle, 16-bit port size, basic timing . . . . . . . . . . . . . . . . . . . . . 354 figure 112. 32-byte write cycle with external ta, basic timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 figure 113. 32-byte read with b-t-b 16-byte bursts to 32-bit port, zero wait states . . . . . . . . . . . . 356 figure 114. single beat 64-bit read cycle, 16-bit port size, basic timing. . . . . . . . . . . . . . . . . . . . . 357 figure 115. internal operand representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 figure 116. interface to different port size devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 figure 117. termination signals protocol timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 figure 118. 32-bit read from mcu with dbm=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 figure 119. 32-bit write to mcu with dbm=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 figure 120. back-to-back 32-bit reads to cs, cal_cs banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 figure 121. small access (32-bit read to 16-bit port) on address/data multiplexed bus . . . . . . . . . . . 370 figure 122. mcu connected to sdr burst memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 figure 123. mcu connected to asynchronous memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 figure 124. read operation to asynchronous memory, three initial wait states. . . . . . . . . . . . . . . . 373 figure 125. write operation to asynchronous memory, three initial wait states. . . . . . . . . . . . . . . . 374 figure 126. mcu connected to multiple memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 figure 127. intc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 figure 128. intc software vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 figure 129. program flow?software vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 figure 130. program flow?hardware vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 figure 131. software vector mode: interrupt exception handler address calculation . . . . . . . . . . . . 382 figure 132. hardware vector mode: interrupt exception handler address calculation . . . . . . . . . . . 383 figure 133. intc module configuration register (intc_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 figure 134. intc current priority register (intc_cpr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 figure 135. intc interrupt acknowledge register (intc_iackr)?intc_mcr[vtes] = 0 . . . . . . . 387 figure 136. intc interrupt acknowledge register (intc_iackr)?intc_mcr[vtes] = 1 . . . . . . . 387 figure 137. intc end-of-interrupt register (intc_eoir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 figure 138. intc software set/clear interrupt register (intc_sscir n ). . . . . . . . . . . . . . . . . . . . . . 389 figure 139. intc priority select register 0?3 (intc_psr0_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 figure 140. intc priority select register 482?485 (intc_psr482_485) . . . . . . . . . . . . . . . . . . . . . 390 figure 141. software vector mode handshaking timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 figure 142. hardware vector mode handshaking timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 407 figure 143. siu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 figure 144. mcu id register 2 (siu_midr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 21 figure 145. mcu id register (siu_midr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 figure 146. reset status register (siu_rsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 figure 147. system reset control register (siu_srcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 figure 148. external irq status register (siu_eisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 figure 149. dma/interrupt request enable register (siu_direr) . . . . . . . . . . . . . . . . . . . . . . . . . . 428 figure 150. dma/interrupt request select register (siu_dirsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 figure 151. overrun status register (siu_osr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9 figure 152. overrun request enable register (siu_orer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 RM0029 list of figures doc id 15177 rev 8 49/1740 figure 153. irq rising-edge event enable register (siu_ireer) . . . . . . . . . . . . . . . . . . . . . . . . . . 431 figure 154. external irq falling-edge event enable register (siu_ifeer) . . . . . . . . . . . . . . . . . . . 432 figure 155. irq digital filter register (siu_idfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 figure 156. irq filtered input register (siu_ifir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 figure 157. sample pcr map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 figure 158. pad configuration register (siu_pcr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 figure 159. pad configuration register (siu_pcr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 figure 160. pad configuration register (siu_pcr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 figure 161. pad configuration register (siu_pcr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 figure 162. pad configuration register (siu_pcr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 figure 163. pad configuration register (siu_pcr9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 figure 164. pad configuration register (siu_pcr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 figure 165. pad configuration register (siu_pcr11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 figure 166. pad configuration register (siu_pcr12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 figure 167. pad configuration register (siu_pcr13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 figure 168. pad configuration register (siu_pcr14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 figure 169. pad configuration register (siu_pcr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 figure 170. pad configuration register (siu_pcr16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 figure 171. pad configuration register (siu_pcr17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 figure 172. pad configuration register (siu_pcr18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 figure 173. pad configuration register (siu_pcr19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 figure 174. pad configuration register (siu_pcr20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 figure 175. pad configuration register (siu_pcr21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 figure 176. pad configuration register (siu_pcr22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 figure 177. pad configuration register (siu_pcr23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 figure 178. pad configuration register (siu_pcr24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 figure 179. pad configuration register (siu_pcr25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 figure 180. pad configuration register (siu_pcr26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 figure 181. pad configuration register (siu_pcr27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 figure 182. pad configuration register (siu_pcr28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 figure 183. pad configuration register (siu_pcr29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 figure 184. pad configuration register (siu_pcr30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 figure 185. pad configuration register (siu_pcr31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 figure 186. pad configuration register (siu_pcr32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 figure 187. pad configuration register (siu_pcr33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 figure 188. pad configuration register (siu_pcr34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 figure 189. pad configuration register (siu_pcr35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 figure 190. pad configuration register (siu_pcr36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 figure 191. pad configuration register (siu_pcr37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 figure 192. pad configuration register (siu_pcr38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 figure 193. pad configuration register (siu_pcr39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 figure 194. pad configuration register (siu_pcr40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 figure 195. pad configuration register (siu_pcr41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 figure 196. pad configuration register (siu_pcr42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 figure 197. pad configuration register (siu_pcr43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 figure 198. pad configuration register (siu_pcr62) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 figure 199. pad configuration register (siu_pcr63) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 figure 200. pad configuration register (siu_pcr64) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 figure 201. pad configuration register (siu_pcr65) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 figure 202. pad configuration register (siu_pcr68) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 figure 203. pad configuration register (siu_pcr69) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 figure 204. pad configuration register (siu_pcr70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 list of figures RM0029 50/1740 doc id 15177 rev 8 figure 205. pad configuration register (siu_pcr75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 figure 206. pad configuration register (siu_pcr76) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 figure 207. pad configuration register (siu_pcr77) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 figure 208. pad configuration register (siu_pcr78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 figure 209. pad configuration register (siu_pcr79) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 figure 210. pad configuration register (siu_pcr80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 figure 211. pad configuration register (siu_pcr81) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 figure 212. pad configuration register (siu_pcr82) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 figure 213. pad configuration register (siu_pcr83) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 figure 214. pad configuration register (siu_pcr84) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 figure 215. pad configuration register (siu_pcr85) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 figure 216. pad configuration register (siu_pcr86) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 figure 217. pad configuration register (siu_pcr87) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 figure 218. pad configuration register (siu_pcr88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 figure 219. pad configuration register (siu_pcr89) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 figure 220. pad configuration register (siu_pcr90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 figure 221. pad configuration register (siu_pcr91) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 figure 222. pad configuration register (siu_pcr92) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 figure 223. pad configuration register (siu_pcr93) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 figure 224. pad configuration register (siu_pcr94) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 figure 225. pad configuration register (siu_pcr95) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 figure 226. pad configuration register (siu_pcr96) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 figure 227. pad configuration register (siu_pcr97) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 figure 228. pad configuration register (siu_pcr98) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 figure 229. pad configuration register (siu_pcr99) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 figure 230. pad configuration register (siu_pcr100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 figure 231. pad configuration register (siu_pcr101) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 figure 232. pad configuration register (siu_pcr102) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 figure 233. pad configuration register (siu_pcr103) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 figure 234. pad configuration register (siu_pcr104) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 figure 235. pad configuration register (siu_pcr105) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 figure 236. pad configuration register (siu_pcr106) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 figure 237. pad configuration register (siu_pcr107) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 figure 238. pad configuration register (siu_pcr108) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 figure 239. pad configuration register (siu_pcr109) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 figure 240. pad configuration register (siu_pcr110) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 figure 241. pad configuration register (siu_pcr113) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 figure 242. pad configuration register (siu_pcr114) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 figure 243. pad configuration register (siu_pcr115) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 figure 244. pad configuration register (siu_pcr116) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 figure 245. pad configuration register (siu_pcr117) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 figure 246. pad configuration register (siu_pcr118) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 figure 247. pad configuration register (siu_pcr119) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 figure 248. pad configuration register (siu_pcr120) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 figure 249. pad configuration register (siu_pcr121) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 figure 250. pad configuration register (siu_pcr122) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 figure 251. pad configuration register (siu_pcr123) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 figure 252. pad configuration register (siu_pcr124) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 figure 253. pad configuration register (siu_pcr125) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 figure 254. pad configuration register (siu_pcr126) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 figure 255. pad configuration register (siu_pcr127) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 figure 256. pad configuration register (siu_pcr128) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 RM0029 list of figures doc id 15177 rev 8 51/1740 figure 257. pad configuration register (siu_pcr129) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 figure 258. pad configuration register (siu_pcr130) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 figure 259. pad configuration register (siu_pcr131) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 figure 260. pad configuration register (siu_pcr132) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 figure 261. pad configuration register (siu_pcr133) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 figure 262. pad configuration register (siu_pcr134) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 figure 263. pad configuration register (siu_pcr135) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 figure 264. pad configuration register (siu_pcr136) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 figure 265. pad configuration register (siu_pcr137) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 figure 266. pad configuration register (siu_pcr138) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 figure 267. pad configuration register (siu_pcr139) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 figure 268. pad configuration register (siu_pcr140) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 figure 269. pad configuration register (siu_pcr141) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 figure 270. pad configuration register (siu_pcr142) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 figure 271. pad configuration register (siu_pcr143) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 figure 272. pad configuration register (siu_pcr144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 figure 273. pad configuration register (siu_pcr145) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 figure 274. pad configuration register (siu_pcr179) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 figure 275. pad configuration register (siu_pcr180) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 figure 276. pad configuration register (siu_pcr181) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 figure 277. pad configuration register (siu_pcr182) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 figure 278. pad configuration register (siu_pcr183) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 figure 279. pad configuration register (siu_pcr184) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 figure 280. pad configuration register (siu_pcr185) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 figure 281. pad configuration register (siu_pcr186) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 figure 282. pad configuration register (siu_pcr187) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 figure 283. pad configuration register (siu_pcr188) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 figure 284. pad configuration register (siu_pcr189) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 figure 285. pad configuration register (siu_pcr190) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 figure 286. pad configuration register (siu_pcr191) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 figure 287. pad configuration register (siu_pcr192) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 figure 288. pad configuration register (siu_pcr193) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 figure 289. pad configuration register (siu_pcr194) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 figure 290. pad configuration register (siu_pcr195) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 figure 291. pad configuration register (siu_pcr196) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 figure 292. pad configuration register (siu_pcr197) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 figure 293. pad configuration register (siu_pcr198) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 figure 294. pad configuration register (siu_pcr199) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 figure 295. pad configuration register (siu_pcr200) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 figure 296. pad configuration register (siu_pcr201) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 figure 297. pad configuration register (siu_pcr202) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 figure 298. pad configuration register (siu_pcr203) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 figure 299. pad configuration register (siu_pcr204) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 figure 300. pad configuration register (siu_pcr206) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 figure 301. pad configuration register (siu_pcr207) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 figure 302. pad configuration register (siu_pcr208) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 figure 303. pad configuration register (siu_pcr209) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 figure 304. pad configuration register (siu_pcr210) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 figure 305. pad configuration register (siu_pcr211) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 figure 306. pad configuration register (siu_pcr212) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 figure 307. pad configuration register (siu_pcr213) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 figure 308. pad configuration register (siu_pcr214) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 list of figures RM0029 52/1740 doc id 15177 rev 8 figure 309. pad configuration register (siu_pcr215) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 figure 310. pad configuration register (siu_pcr216) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 figure 311. pad configuration register (siu_pcr217) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 figure 312. pad configuration register (siu_pcr218) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 figure 313. pad configuration register (siu_pcr219) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 figure 314. pad configuration register (siu_pcr220) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 figure 315. pad configuration register (siu_pcr221) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 figure 316. pad configuration register (siu_pcr222) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 figure 317. pad configuration register (siu_pcr223) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 figure 318. pad configuration register (siu_pcr224) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 figure 319. pad configuration register (siu_pcr225) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 figure 320. pad configuration register (siu_pcr226) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 figure 321. pad configuration register (siu_pcr227) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 figure 322. pad configuration register (siu_pcr228) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 figure 323. pad configuration register (siu_pcr229) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 figure 324. pad configuration register (siu_pcr230) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 figure 325. pad configuration register (siu_pcr231) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 figure 326. pad configuration register (siu_pcr232) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 figure 327. pad configuration register (siu_pcr244) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 figure 328. pad configuration register (siu_pcr245) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 figure 329. pad configuration register (siu_pcr336) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 figure 330. pad configuration register (siu_pcr338) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 figure 331. pad configuration register (siu_pcr339) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 figure 332. pad configuration register (siu_pcr340) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 figure 333. pad configuration register (siu_pcr341) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 figure 334. pad configuration register (siu_pcr342) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 figure 335. pad configuration register (siu_pcr343) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 figure 336. pad configuration register (siu_pcr345) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 figure 337. pad configuration register 350 ? 381 (siu_pcr350 ? siu_pcr381) . . . . . . . . . . . . . . 548 figure 338. pad configuration register 382 ? 389 (siu_pcr382 ? siu_pcr389) . . . . . . . . . . . . . . 549 figure 339. pad configuration register 390 ? 413 (siu_pcr390 ? siu_pcr413) . . . . . . . . . . . . . . 550 figure 340. gpio pin data out register 0 ? 3 (siu_gpdo0 ? siu_gpdo3) . . . . . . . . . . . . . . . . . . 552 figure 341. gpio pin data out register 412 ? 413 (siu_gpdo410 ? siu_gpdo413) . . . . . . . . . . 552 figure 342. gpio pin data in register 0 ? 3 (siu_gpdi0 ? siu_gpdi3) . . . . . . . . . . . . . . . . . . . . . 553 figure 343. gpio pin data in register 230 ? 232 (siu_gpdi230 ? siu_gpdi232) . . . . . . . . . . . . . 553 figure 344. trigger selection for eqadc cfifo queue 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 figure 345. eqadc trigger input select register (siu_etisr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 figure 346. external irq input select register (siu_eiisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 figure 347. dspi input select register (siu_disr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 figure 348. imux select register 3 (siu_isel3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 0 figure 349. imux select register 8 (siu_isel8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7 figure 350. imux select register 9 (siu_isel9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8 figure 351. imux select register 10 (siu_isel10 or siu_decfil1) . . . . . . . . . . . . . . . . . . . . . . . . 570 figure 352. chip configuration register (siu_ccr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 figure 353. external clock control register (siu_eccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 figure 354. compare a high register (siu_carh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 figure 355. compare a low register (siu_carl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 figure 356. compare b high register (siu_cbrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 figure 357. compare b low register (siu_cbrl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 figure 358. system clock register (siu_sysdiv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 figure 359. halt register (siu_hlt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 figure 360. halt acknowledge register (siu_hltack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 RM0029 list of figures doc id 15177 rev 8 53/1740 figure 361. core mmu pid control register (siu_empcr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 figure 362. siu dma/interrupt request diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 85 figure 363. eqadc trigger input multiplexing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 figure 364. siu external interrupt input multiplexing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 figure 365. fmpll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 figure 366. synthesizer control register (syncr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 figure 367. synthesizer status register (synsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6 figure 368. enhanced synthesizer control register 1 (esyncr1) . . . . . . . . . . . . . . . . . . . . . . . . . . 598 figure 369. enhanced synthesizer control register 2 (esyncr2) . . . . . . . . . . . . . . . . . . . . . . . . . . 600 figure 370. synthesizer fm modulation register (synfmmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 figure 371. clock quality monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 figure 372. triangular frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 figure 373. miscellaneous reset status register (ecsm_mrsr). . . . . . . . . . . . . . . . . . . . . . . . . . . 613 figure 374. miscellaneous wakeup control register (ecsm_mwcr). . . . . . . . . . . . . . . . . . . . . . . . 614 figure 375. miscellaneous user-defined control register (ecsm_mudcr). . . . . . . . . . . . . . . . . . . 615 figure 376. ecc configuration register (ecsm_ecr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 figure 377. ecc status register (ecsm_esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 figure 378. ecc error generation register (ecsm_eegr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 figure 379. flash ecc address register (ecsm_fear). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 figure 380. flash ecc master number register (ecsm_femr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 figure 381. flash ecc attributes (ecsm_feat) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 figure 382. flash ecc data register (ecsm_fedrh, ecsm_fedrl) . . . . . . . . . . . . . . . . . . . . . . 627 figure 383. ram ecc address register (ecsm_rear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 figure 384. ram ecc syndrome register (ecsm_presr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 figure 385. ram ecc master number register (ecsm_remr). . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 figure 386. ram ecc attributes (ecsm_reat) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 figure 387. ram ecc data register (ecsm_redr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 figure 388. stm control register (stm_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 37 figure 389. stm count register (stm_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8 figure 390. stm channel control register (stm_ccrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 figure 391. stm channel interrupt register (stm_cirn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 figure 392. stm channel compare register (stm_cmpn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 figure 393. swt module control register (swt_mcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 figure 394. swt interrupt register (swt_ir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 figure 395. swt time-out register (swt_to) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 figure 396. swt window register (swt_wn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 figure 397. swt service register (swt_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6 figure 398. swt counter output register (swt_co) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 figure 399. swt service register (swt_sk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7 figure 400. bam program flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 figure 401. censorship word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 figure 402. serial boot flash password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 figure 403. reset configuration half word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 figure 404. reset boot vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 figure 405. enabling jtag/nexus port access on a censored device . . . . . . . . . . . . . . . . . . . . . . . . 657 figure 406. can bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 figure 407. start address, vle bit and download size in bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 figure 408. emios200 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 figure 409. emios200 module configuration register (emios_mcr) . . . . . . . . . . . . . . . . . . . . . . . 678 figure 410. emios200 global flag register (emios_gfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 figure 411. emios200 output update disable register (emios_oudr) . . . . . . . . . . . . . . . . . . . . . 681 figure 412. emios200 channel disable register (emios_ucdis). . . . . . . . . . . . . . . . . . . . . . . . . . 682 list of figures RM0029 54/1740 doc id 15177 rev 8 figure 413. emios200 channel a data register (emios_cadr[ n ]). . . . . . . . . . . . . . . . . . . . . . . . . 682 figure 414. emios200 channel b data register (emios_cbdr[ n ]). . . . . . . . . . . . . . . . . . . . . . . . . 683 figure 415. emios200 channel counter register (emios_ccntr[ n ]). . . . . . . . . . . . . . . . . . . . . . . 684 figure 416. emios200 channel control register (emios_ccr[ n ]). . . . . . . . . . . . . . . . . . . . . . . . . . 685 figure 417. emios200 channel status register (emios_csr[ n ]) . . . . . . . . . . . . . . . . . . . . . . . . . . 689 figure 418. emios200 uc alternate a register (emios_alta[ n ]) . . . . . . . . . . . . . . . . . . . . . . . . . . 690 figure 419. unified channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 figure 420. unified channel control and datapath block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 693 figure 421. single action input capture with rising edge triggering example . . . . . . . . . . . . . . . . . . . 695 figure 422. single action input capture with both edges triggering example . . . . . . . . . . . . . . . . . . . 695 figure 423. saoc example with edpol value being transferred to the output flip-flop . . . . . . . . . . . 696 figure 424. saoc example toggling the output flip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 figure 425. saoc example with flag behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 figure 426. input pulse width measurement example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 figure 427. b1 and a1 updates at emios_cadr[n] and emios_cbdr[n] reads. . . . . . . . . . . . . . . 698 figure 428. input period measurement example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9 figure 429. a1 and b1 updates at emios_cadr[n] and emios_cbdr[n] reads. . . . . . . . . . . . . . . 699 figure 430. double action output compare with flag set on the second match . . . . . . . . . . . . . . . 700 figure 431. double action output compare with flag set on both matches. . . . . . . . . . . . . . . . . . . 701 figure 432. daoc with transfer disabling example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 1 figure 433. modulus counter buffered (mcb) up count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 figure 434. modulus counter buffered (mcb) up/down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 figure 435. mcb mode a1 register update in up counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 figure 436. mcb mode a1 register update in up/down counter mode . . . . . . . . . . . . . . . . . . . . . . 704 figure 437. opwfmb a1 and b1 match to output register delay. . . . . . . . . . . . . . . . . . . . . . . . . . . 705 figure 438. opwfmb mode with a1 = 0 (0% duty cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 figure 439. opwfmb a1 and b1 registers update and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 figure 440. opwfmb mode with active output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 figure 441. opwfmb mode from 100% to 0% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 figure 442. opwmb mode matches and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710 figure 443. opwmb mode with 0% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 figure 444. opwmb mode with active output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 figure 445. opwmb mode from 100% to 0% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 figure 446. lnput programmable filter submodule diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 figure 447. input programmable filter example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 figure 448. stac client submodule block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 figure 449. timing diagram for stac bus and stac client submodule output . . . . . . . . . . . . . . . . . 715 figure 450. reaction module system interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 figure 451. channel interaction with internal submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 figure 452. reaction module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 figure 453. reacm module configuration register (reacm_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . 727 figure 454. reacm timer configuration register (reacm_tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . 728 figure 455. reacm threshold router register (reacm_thrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 figure 456. reacm adc sensor input register (reacm_sinr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 figure 457. reacm global error flag register (reacm_gefr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 figure 458. reacm channel n configuration register (reacm_chcrn) . . . . . . . . . . . . . . . . . . . . 732 figure 459. reacm channel n status register (reacm_chsrn) . . . . . . . . . . . . . . . . . . . . . . . . . . 735 figure 460. reacm channel n router register (reacm_chrrn). . . . . . . . . . . . . . . . . . . . . . . . . . 738 figure 461. reacm shared timer bank registers (reacm_stbk) . . . . . . . . . . . . . . . . . . . . . . . . . 739 figure 462. reacm hold-off timer bank registers (reacm_hotbk) . . . . . . . . . . . . . . . . . . . . . . . 740 figure 463. reacm threshold bank register (reacm_thbk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 figure 464. reacm adc result maximum limit check register (reacm_adcmax) . . . . . . . . . . . . . 741 RM0029 list of figures doc id 15177 rev 8 55/1740 figure 465. reacm modulation range pulse width register (reacm_rangepwd). . . . . . . . . . . 742 figure 466. reacm modulation minimum pulse width register (reacm_minpwd). . . . . . . . . . . . 743 figure 467. reacm modulation control word bank registers (reacm_mwbk) . . . . . . . . . . . . . . . 743 figure 468. reaction channel architecture simplified diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 figure 469. modulation control word bank interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8 figure 470. shared timer bank block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 figure 471. hold-off timer bank block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 figure 472. threshold bank and comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 figure 473. adc interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 figure 474. adc interface and threshold bank interconnections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 figure 475. banked mode showing stacking of channels [0] and [1] . . . . . . . . . . . . . . . . . . . . . . . . . . 755 figure 476. threshold/threshold modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 figure 477. threshold/hold-off modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 56 figure 478. limitation on the off modulation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7 figure 479. early end of timer control pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 figure 480. fails detected by the modulation monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 figure 481. open circuit detection using hold-off timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 61 figure 482. short circuit detection using hold-off timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 figure 483. dma req/done protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 figure 484. boosted banked direct injection with passive recirculation . . . . . . . . . . . . . . . . . . . . . . 765 figure 485. etpu ch10/1 controlling reaction ch0/1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 figure 486. system level connection in a banked configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 figure 487. modulation phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 figure 488. modulation words for injector application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 figure 489. advancing modulation phase on a threshold level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 figure 490. loop function used within a modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 figure 491. four channels controlling two injector banks in banked mode . . . . . . . . . . . . . . . . . . . . . 772 figure 492. etpu block diagram (single-engine) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 75 figure 493. etpu engine block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 figure 494. etpu_mcr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 figure 495. etpu_cdcr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 figure 496. etpu_misccmpr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 02 figure 492. etpu_scmoffdatar register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 figure 492. etpu_ecr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 figure 497. etpu_tbcr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 figure 498. etpu_tb1r register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 figure 499. etpu_tb2r register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815 figure 500. etpu_redcr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 figure 501. etpu_wdtr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 figure 502. etpu_idle register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 figure 503. channel registers area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 figure 504. etpu_cisr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822 figure 505. etpu_cdtrsr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823 figure 506. etpu_ciosr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 figure 507. etpu_cdtrosr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 figure 508. etpu_cier register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 figure 509. etpu_cdtrer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 figure 510. etpu_cpssr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 figure 511. etpu_cssr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 figure 512. etpu_cxcr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 figure 513. etpu_cxscr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 figure 514. etpu_cxhsrr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 list of figures RM0029 56/1740 doc id 15177 rev 8 figure 515. entry table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 figure 516. entry point address (host address offset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 1 figure 517. entry point format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 figure 518. tst timing ? no wait-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849 figure 519. tst timing ? 1 wait-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 figure 520. tst timing ? 2 wait-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 figure 521. spram organization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856 figure 522. time slot priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 figure 523. priority passing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 figure 524. priority passing disabling example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863 figure 525. time-slot variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 figure 526. greater-equal comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871 figure 527. channel logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872 figure 528. pin state input/output logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880 figure 529. udcm register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 figure 530. channel mode logic and event flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892 figure 531. either match, blocking modes (em_b_st, em_b_dt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894 figure 532. either match, non blocking modes (em_nb_st, em_nb_dt) . . . . . . . . . . . . . . . . . . . . . . . 895 figure 533. match b request modes (m2_st, m2_dt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896 figure 534. both match request modes (bm_st, bm_dt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897 figure 535. ordered modes with match b request (m2_o_st, m2_o_dt) . . . . . . . . . . . . . . . . . . . . . . 898 figure 536. single match modes (sm_st, sm_dt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9 figure 537. single match enhanced mode (sm_st_e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 figure 538. input/output combination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908 figure 539. microengine link register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909 figure 540. tcr1 clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 figure 541. tcr2 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915 figure 542. time base synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919 figure 543. tpr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921 figure 544. tcr2 in angle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 figure 545. trr register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 figure 546. eac ?pll?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924 figure 547. etpu angle counter system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 figure 548. angle ticks generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928 figure 549. normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930 figure 550. halt mode ? deceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931 figure 551. high rate mode ? acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933 figure 552. missing teeth and last tooth combination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935 figure 553. microengine block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 figure 554. flush pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978 figure 555. worst-case latency for pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994 figure 556. function threads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995 figure 557. time-slot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997 figure 558. multiple time-slot sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997 figure 559. first-pass worst-case latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 figure 560. next servicing for channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002 figure 561. next servicing for channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 figure 562. next servicing for channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004 figure 563. worst-case latency for channel 0 (first try) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 07 figure 564. worst-case latency for channel 0 (second try) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008 figure 565. worst-case latency for channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008 figure 566. execution, timebase and channel t2 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010 RM0029 list of figures doc id 15177 rev 8 57/1740 figure 567. execution, timebase and channel t2/t4 timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011 figure 568. t2 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012 figure 569. t4 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012 figure 570. eqadc block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 figure 571. eqadc module configuration register (eqadc_mcr) . . . . . . . . . . . . . . . . . . . . . . . . 1039 figure 572. eqadc test register (eqadc_tst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 figure 573. eqadc null message send format register (eqadc_nmsfr) . . . . . . . . . . . . . . . . . . . 1041 figure 574. eqadc external trigger digital filter register (eqadc_etdfr) . . . . . . . . . . . . . . . . 1042 figure 575. eqadc cfifo push register x (eqadc_cfprx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044 figure 576. eqadc rfifo pop register x (eqadc_rfprx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045 figure 577. eqadc cfifo control register 0 (eqadc_cfcr0) . . . . . . . . . . . . . . . . . . . . . . . . . . 1046 figure 578. eqadc cfifo control register 1 (eqadc_cfcr1) . . . . . . . . . . . . . . . . . . . . . . . . . . 1046 figure 579. eqadc cfifo control register 2 (eqadc_cfcr2) . . . . . . . . . . . . . . . . . . . . . . . . . . 1047 figure 580. eqadc interrupt and dma control register 0 (eqadc_idcr0) . . . . . . . . . . . . . . . . . 1049 figure 581. eqadc interrupt and dma control register 1 (eqadc_idcr1) . . . . . . . . . . . . . . . . . 1050 figure 582. eqadc interrupt and dma control register 2 (eqadc_idcr2) . . . . . . . . . . . . . . . . . 1050 figure 583. eqadc fifo and interrupt status register x (eqadc_fisrx) . . . . . . . . . . . . . . . . . . 1054 figure 584. eqadc cfifo transfer counter register 0 (eqadc_cftcr0) . . . . . . . . . . . . . . . . . 1059 figure 585. eqadc cfifo transfer counter register 1 (eqadc_cftcr1) . . . . . . . . . . . . . . . . . 1060 figure 586. eqadc cfifo transfer counter register 2 (eqadc_cftcr2) . . . . . . . . . . . . . . . . . 1060 figure 587. eqadc cfifo status snapshot register 0 (eqadc_cfssr0) . . . . . . . . . . . . . . . . . 1061 figure 588. eqadc cfifo status snapshot register 1 (eqadc_cfssr1) . . . . . . . . . . . . . . . . . 1062 figure 589. eqadc cfifo status snapshot register 2 (eqadc_cfssr2) . . . . . . . . . . . . . . . . . 1062 figure 590. eqadc cfifo status register (eqadc_cfsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064 figure 591. eqadc ssi control register (eqadc_ssicr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066 figure 592. eqadc ssi receive data register (eqadc_ssirdr) . . . . . . . . . . . . . . . . . . . . . . . . 1068 figure 593. eqadc stac client configuration register (eqadc_redlccr) . . . . . . . . . . . . . . . 1069 figure 594. eqadc cfifo0 registers (eqadc_cf0rw) (w=0, .., 3). . . . . . . . . . . . . . . . . . . . . . . 1070 figure 595. eqadc cfifo1 registers (eqadc_cf1rw) (w=0, .., 3). . . . . . . . . . . . . . . . . . . . . . . 1071 figure 596. eqadc cfifo2 registers (eqadc_cf2rw) (w=0, .., 3). . . . . . . . . . . . . . . . . . . . . . . 1071 figure 597. eqadc cfifo3 registers (eqadc_cf3rw) (w=0, .., 3). . . . . . . . . . . . . . . . . . . . . . . 1072 figure 598. eqadc cfifo4 registers (eqadc_cf4rw) (w=0, .., 3). . . . . . . . . . . . . . . . . . . . . . . 1072 figure 599. eqadc cfifo5 registers (eqadc_cf5rw) (w=0, .., 3). . . . . . . . . . . . . . . . . . . . . . . 1073 figure 600. eqadc cfifo0 extension registers (eqadc_cf0erw) (w=0, .., 3) . . . . . . . . . . . . . 1074 figure 601. eqadc rfifo0 registers (eqadc_rf0rw) (w=0, .., 3). . . . . . . . . . . . . . . . . . . . . . . 1075 figure 602. eqadc rfifo1 registers (eqadc_rf1rw) (w=0, .., 3). . . . . . . . . . . . . . . . . . . . . . . 1075 figure 603. eqadc rfifo2 registers (eqadc_rf2rw) (w=0, .., 3). . . . . . . . . . . . . . . . . . . . . . . 1076 figure 604. eqadc rfifo3 registers (eqadc_rf3rw) (w=0, .., 3). . . . . . . . . . . . . . . . . . . . . . . 1076 figure 605. eqadc rfifo4 registers (eqadc_rf4rw) (w=0, .., 3). . . . . . . . . . . . . . . . . . . . . . . 1077 figure 606. eqadc rfifo5 registers (eqadc_rf5rw) (w=0, .., 3). . . . . . . . . . . . . . . . . . . . . . . 1077 figure 607. adc0/1 control registers (adc0/1_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080 figure 608. adc time stamp control register (adc_tscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084 figure 609. adc time base counter register (adc_tbcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 figure 610. adc0/1 gain calibration constant registers (adc0/1_gccr) . . . . . . . . . . . . . . . . . . 1086 figure 611. adc0/1 offset calibration constant registers (adc0/1_occr) . . . . . . . . . . . . . . . . . 1087 figure 612. alternate configuration 1-8 control registers (adc_acr1-8) . . . . . . . . . . . . . . . . . . . 1088 figure 613. adc0/1 alternate x gain register (adc0/1_agrx, x=1-2) . . . . . . . . . . . . . . . . . . . . . . 1090 figure 614. adc0/1 alternate x gain register (adc0/1_agrx, x=1-2) field description . . . . . . . . . 1090 figure 615. adc0/1 alternate x offset registers (adc0/1_aorx, x=1-2) . . . . . . . . . . . . . . . . . . . . 1091 figure 616. adc pull up/down control register x (adc_pudcrx, x=0-7) . . . . . . . . . . . . . . . . . . . 1091 figure 617. command flow during eqadc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094 figure 618. result flow during eqadc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095 list of figures RM0029 58/1740 doc id 15177 rev 8 figure 619. conversion command format for the standard configuration. . . . . . . . . . . . . . . . . . . . 1097 figure 620. conversion command format for alternate configurations . . . . . . . . . . . . . . . . . . . . . . 1100 figure 621. write configuration command format for on-chip adc operation . . . . . . . . . . . . . . . 1102 figure 622. read configuration command format for on-chip adc operation . . . . . . . . . . . . . . . 1103 figure 623. adc result format when fmt=1 (right justified signed) . . . . . . . . . . . . . . . . . . . . . . 1104 figure 624. adc result format when fmt=0 (right justified unsigned) . . . . . . . . . . . . . . . . . . . . 1104 figure 625. command message format for external device operation . . . . . . . . . . . . . . . . . . . . . . 1107 figure 626. result message format for external device operation . . . . . . . . . . . . . . . . . . . . . . . . . 1108 figure 627. null message send format for external device operation . . . . . . . . . . . . . . . . . . . . . . 1110 figure 628. null message receive format for external device operation . . . . . . . . . . . . . . . . . . . . 1110 figure 629. cfifo diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113 figure 630. cfifo entry pointer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114 figure 631. cfifo0 in streaming mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117 figure 632. cfifo0 in streaming mode entry pointer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118 figure 633. cfifo0 in streaming mode entry pointer example (cont.) . . . . . . . . . . . . . . . . . . . . . . 1119 figure 634. cfifo prioritization logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122 figure 635. etrig event propagation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123 figure 636. state machine of cfifo status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129 figure 637. trigger overrun on level-trigger mode cfifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132 figure 638. command sequence examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133 figure 639. external cbuffer status detection at command sequence transfer start . . . . . . . . . . 1135 figure 640. non-coherency event when different cfifos use the same cbuffer . . . . . . . . . . . . . . 1136 figure 641. non-coherency event when different cfifos are using different external cbuffers . . 1137 figure 642. non-coherency detection when transfers from a command sequence are interrupted 1138 figure 643. rfifo diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140 figure 644. rfifo entry pointer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141 figure 645. adc0/1 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143 figure 646. redlc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 figure 647. timing diagram for the stac bus and stac client submodule output. . . . . . . . . . . . 1148 figure 648. mac unit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 figure 649. gain calibration constant format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 150 figure 650. on-chip adc control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 53 figure 651. overlapping consecutive conversion commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154 figure 652. example of external multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160 figure 653. eqadc dma and interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162 figure 654. eqadc synchronous serial interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 1163 figure 655. full duplex pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164 figure 656. synchronous serial interface protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166 figure 657. slave driving the msb and consecutive bits in a data transmission . . . . . . . . . . . . . . 1167 figure 658. eqadc parallel side interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168 figure 659. psi input and output data buses content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169 figure 660. rsd adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171 figure 661. rsd stage block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172 figure 662. rsd stage transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173 figure 663. rsd adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174 figure 664. example of a cqueue configuring the on-chip adcs/external device . . . . . . . . . . . . 1176 figure 665. cqueue/cfifo interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180 figure 666. rqueue/rfifo interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181 figure 667. eqadc command and result queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183 figure 668. quantization error reduction during calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186 figure 669. qadc overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187 figure 670. eqadc system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188 RM0029 list of figures doc id 15177 rev 8 59/1740 figure 671. decimation filter block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 figure 672. decimation filter module configuration register (decfilter_mcr) . . . . . . . . . . . . . 1197 figure 673. decimation filter status register (decfilter_msr) . . . . . . . . . . . . . . . . . . . . . . . . . 1203 figure 674. decimation filter extended configuration register (decfilter_mxcr) . . . . . . . . . . 1206 figure 675. decimation filter extended status register (decfilter_mxsr) . . . . . . . . . . . . . . . . 1210 figure 676. decimation filter interface input buffer register (decfilter_ib) . . . . . . . . . . . . . . . . 1212 figure 677. decimation filter interface output buffer register (decfilter_ob). . . . . . . . . . . . . . 1213 figure 678. decimation filter coefficient n register (decfilter_coefn) . . . . . . . . . . . . . . . . . . 1214 figure 679. decimation filter tapn register (decfilter_tapn) . . . . . . . . . . . . . . . . . . . . . . . . . 1214 figure 680. decimation filter interface input buffer register (decfilter_edid) . . . . . . . . . . . . . 1215 figure 681. decimation filter final integration value register (decfilter_fintval) . . . . . . . . . 1215 figure 682. decimation filter final integration count value register (decfilter_fintcnt) . . . 1216 figure 683. decimation filter current integration value register (decfilter_cintval). . . . . . . 1217 figure 684. decimation filter current integration count value register (decfilter_cintcnt) . 1217 figure 685. decimation filter interface input/output buffers register (decfilter_iob). . . . . . . . 1218 figure 686. 1 x 4 poles iir filter functional diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224 figure 687. fourth order iir filter implementation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225 figure 688. filter configuration paths (fir or 1x4 poles iir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226 figure 689. convergent rounding methodology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7 figure 690. cascade mode chain structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237 figure 691. multiple cascade mode chain structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238 figure 692. examples of mixed cascaded and single blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239 figure 693. decimation filter cascade mode data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240 figure 694. decimation filter/eqadc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242 figure 695. calibration points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246 figure 696. temperature formula . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247 figure 697. temperature calculation constants register 0 (tsens_tccr0). . . . . . . . . . . . . . . . . 1248 figure 698. temperature calculation constants register 1 (tsens_tccr1). . . . . . . . . . . . . . . . . 1250 figure 699. crc checksum processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 54 figure 700. crc configuration register (crc_cfg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257 figure 701. crc input register (crc_inp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 58 figure 702. crc current status register (crc_cstat). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259 figure 703. crc output register (crc_outp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260 figure 704. transmission sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262 figure 705. reception sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264 figure 706. dspi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265 figure 707. dspi with queues and dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269 figure 708. dspi connections for spi and dsi transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269 figure 709. dspi connections for csi transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 70 figure 710. dspi module configuration register (dspi_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275 figure 711. dspi hardware configuration register (dspi_hcr). . . . . . . . . . . . . . . . . . . . . . . . . . . 1278 figure 712. dspi transfer count register (dspi_tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279 figure 713. dspi clock and transfer attributes register 0?7 (dspi_ctar0?dspi_ctar7) in the master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 0 figure 714. dspi clock and transfer attributes register 0 (dspi_ctar0) in the slave mode . . . . 1280 figure 715. dspi status register (dspi_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 86 figure 716. dspi dma/interrupt request select and enable register (dspi_rser) . . . . . . . . . . . 1288 figure 717. dspi push tx fifo register (dspi_pushr) in master mode . . . . . . . . . . . . . . . . . . 1290 figure 718. dspi push tx fifo register (dspi_pushr) in slave mode . . . . . . . . . . . . . . . . . . . 1292 figure 719. dspi pop rx fifo register (dspi_popr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292 figure 720. dspi transmit fifo register 0?15 (dspi_txfr0?dspi_txfr15) . . . . . . . . . . . . . . . 1293 figure 721. dspi receive fifo registers 0?15 (dspi_rxfr0?dspi_rxfr15) . . . . . . . . . . . . . . 1294 list of figures RM0029 60/1740 doc id 15177 rev 8 figure 722. dspi dsi configuration register (dspi_dsicr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294 figure 723. dspi dsi serialization data register (dspi_sdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1297 figure 724. dspi dsi alternate serialization data register (dspi_asdr) . . . . . . . . . . . . . . . . . . . 1297 figure 725. dspi dsi transmit comparison register (dspi_compr) . . . . . . . . . . . . . . . . . . . . . . 1298 figure 726. dspi deserialization data register (dspi_ddr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299 figure 727. dspi dsi configuration register 1 (dspi_dsicr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299 figure 728. dspi dsi serialization source select register (dspi_ssr) . . . . . . . . . . . . . . . . . . . . . 1301 figure 729. dspi dsi parallel input select register 0 (dspi_pisr0) . . . . . . . . . . . . . . . . . . . . . . . 1302 figure 730. dspi dsi parallel input select register 1 (dspi_pisr1) . . . . . . . . . . . . . . . . . . . . . . . 1303 figure 731. dspi dsi parallel input select register 2 (dspi_pisr2) . . . . . . . . . . . . . . . . . . . . . . . 1304 figure 732. dspi dsi parallel input select register 3 (dspi_pisr3) . . . . . . . . . . . . . . . . . . . . . . . 1305 figure 733. dspi dsi deserialized data interrupt mask register (dspi_dimr) . . . . . . . . . . . . . . . 1306 figure 734. dspi dsi deserialized data polarity interrupt register (dspi_dipr) . . . . . . . . . . . . . . 1306 figure 735. spi and dsi serial protocol overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7 figure 736. dsi serialization diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313 figure 737. dsi deserialization diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313 figure 738. dspi parallel chaining example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1315 figure 739. dspi serial chaining example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1316 figure 740. example of system using dspi in csi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317 figure 741. communications clock prescalers and scalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1318 figure 742. peripheral chip select strobe timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1320 figure 743. dspi transfer timing diagram (mtfe = 0, cpha = 0, fmsz = 8) . . . . . . . . . . . . . . . . . 1322 figure 744. dspi transfer timing diagram (mtfe = 0, cpha = 1, fmsz = 8) . . . . . . . . . . . . . . . . 1323 figure 745. dspi modified transfer format (mtfe = 1, cpha = 0, f sck = f sys /4) . . . . . . . . . . . . . . . 1325 figure 746. dspi modified transfer format (mtfe = 1, cpha = 0, f sck = f sys /2) . . . . . . . . . . . . . . . 1325 figure 747. dspi modified transfer format (mtfe = 1, cpha = 0, f sck = f sys /3) . . . . . . . . . . . . . . . . 1326 figure 748. dspi modified transfer format (mtfe = 1, cpha = 1, f sck = f sys /2) . . . . . . . . . . . . . . . . 1326 figure 749. dspi modified transfer format (mtfe = 1, cpha = 1, f sck = f sys /3) . . . . . . . . . . . . . . . . 1327 figure 750. dspi modified transfer format (mtfe = 1, cpha = 1, f sck = f sys /4) . . . . . . . . . . . . . . . . 1327 figure 751. example of non-continuous format (cpha = 1, cont = 0) . . . . . . . . . . . . . . . . . . . . . . 1328 figure 752. example of continuous transfer (cpha = 1, cont = 1). . . . . . . . . . . . . . . . . . . . . . . . . 1328 figure 753. continuous sck timing diagram (cont = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330 figure 754. continuous sck timing diagram (cont = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330 figure 755. dspi usage in the tsb configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 1 figure 756. tsb downstream frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332 figure 757. tsb data frame format for msc dual receiver operation . . . . . . . . . . . . . . . . . . . . . . . . 1333 figure 758. dspi queue transfer control in the spc564a74xx, spc564a80xx . . . . . . . . . . . . . . . . 1336 figure 759. dspi pcs expansion and deglitching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1337 figure 760. lvds transmitter pad block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8 figure 761. dspi_b connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339 figure 762. dspi_c connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342 figure 763. dspi_d connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346 figure 764. tx fifo pointers and counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351 figure 765. esci block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354 figure 766. baud rate register (esci_brr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8 figure 767. control register 1 (esci_cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359 figure 768. control register 2 (esci_cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361 figure 769. sci data register (esci_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362 figure 770. interrupt flag and status register 1 (esci_ifsr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364 figure 771. interrupt flag and status register 2 (esci_ifsr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365 figure 772. lin control register 1 (esci_lcr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6 figure 773. lin control register 2 (esci_lcr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8 RM0029 list of figures doc id 15177 rev 8 61/1740 figure 774. lin transmit register (esci_ltr) - lin tx frame generation. . . . . . . . . . . . . . . . . . . . . 1369 figure 775. lin transmit register (esci_ltr) - lin rx frame generation . . . . . . . . . . . . . . . . . . . . 1369 figure 776. lin receive register (esci_lrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370 figure 777. lin crc polynomial register (esci_lpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371 figure 778. control register 3 (esci_cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371 figure 779. lin byte field format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374 figure 780. sci frame formats (8 payload bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 74 figure 781. sci frame formats (9 payload bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 74 figure 782. sci frame formats (2 stop bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375 figure 783. inverted sci frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375 figure 784. lin break symbol format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376 figure 785. sci break character formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376 figure 786. idle character formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377 figure 787. faster receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379 figure 788. slower receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1380 figure 789. transmitter state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382 figure 790. dma controlled sci data frame generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384 figure 791. receiver state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386 figure 792. dual wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388 figure 793. single wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388 figure 794. loop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388 figure 795. dma controlled sci data frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390 figure 796. start bit sampling and strobing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1391 figure 797. data and stop bit sampling and strobing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1393 figure 798. idle-line wake up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395 figure 799. address-mark wake up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395 figure 800. standard lin frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397 figure 801. crc enhanced lin frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 7 figure 802. dma controlled lin tx frame generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399 figure 803. dma controlled lin rx frame generation and reception . . . . . . . . . . . . . . . . . . . . . . . 1401 figure 804. fast bit error detection on a lin bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 402 figure 805. timing diagram fast bit error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402 figure 806. lin wake-up signal frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404 figure 807. flexcan block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408 figure 808. typical can system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1409 figure 809. flexcan message buffer architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414 figure 810. message buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415 figure 811. rx fifo structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418 figure 812. id table 0 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418 figure 813. module configuration register (mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420 figure 814. control register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425 figure 815. free running timer (timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1429 figure 816. rx global mask register (rxgmask). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1429 figure 817. error counter register (ecr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1431 figure 818. error and status register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1432 figure 819. interrupt masks 2 register (imrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 435 figure 820. interrupt masks 1 register (imrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436 figure 821. interrupt flags 2 register (ifrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1437 figure 822. interrupt flags 1 register (ifrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438 figure 823. rx individual mask registers (rximr0 ? rximr63) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439 figure 824. can engine clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1449 figure 825. segments within the bit time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450 list of figures RM0029 62/1740 doc id 15177 rev 8 figure 826. arbitration, match and move time windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1451 figure 827. flexray block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1459 figure 828. module version register (fr_mvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472 figure 829. module configuration register (fr_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472 figure 830. system memory base address high register (fr_symbadhr) . . . . . . . . . . . . . . . . . 1475 figure 831. system memory base address low register (fr_symbadlr). . . . . . . . . . . . . . . . . . 1475 figure 832. strobe signal control register (fr_stbscr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475 figure 833. message buffer data size register (fr_mbdsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477 figure 834. message buffer segment size and utilization register (fr_mbssutr) . . . . . . . . . . . 1477 figure 835. pe dram access register (fr_pedrar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1478 figure 836. pe dram data register (fr_pedrdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479 figure 837. protocol operation control register (fr_pocr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479 figure 838. global interrupt flag and enable register (fr_gifer) . . . . . . . . . . . . . . . . . . . . . . . . 1481 figure 839. protocol interrupt flag register 0 (fr_pifr0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483 figure 840. protocol interrupt flag register 1 (fr_pifr1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1485 figure 841. protocol interrupt enable register 0 (fr_pier0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486 figure 842. protocol interrupt enable register 1 (fr_pier1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488 figure 843. chi error flag register (fr_chierfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489 figure 844. message buffer interrupt vector register (fr_mbivec). . . . . . . . . . . . . . . . . . . . . . . . 1491 figure 845. channel a status error counter register (fr_casercr) . . . . . . . . . . . . . . . . . . . . . . 1492 figure 846. channel b status error counter register (fr_cbsercr) . . . . . . . . . . . . . . . . . . . . . . 1492 figure 847. protocol status register 0 (fr_psr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493 figure 848. protocol status register 1 (fr_psr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494 figure 849. protocol status register 2 (fr_psr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495 figure 850. protocol status register 3 (fr_psr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497 figure 851. macrotick counter register (fr_mtctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1499 figure 852. cycle counter register (fr_cyctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1499 figure 853. slot counter channel a register (fr_sltctar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 figure 854. slot counter channel b register (fr_sltctbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 figure 855. rate correction value register (fr_rtcorvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501 figure 856. offset correction value register (fr_ofcorvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501 figure 857. combined interrupt flag register (fr_cifr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502 figure 858. system memory access time-out register (fr_symator) . . . . . . . . . . . . . . . . . . . . 1503 figure 859. sync frame counter register (fr_sfcntr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504 figure 860. sync frame table offset register (fr_sftor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504 figure 861. sync frame table configuration, control, status register (fr_sftccsr). . . . . . . . . 1505 figure 862. sync frame id rejection filter register (fr_sfidrfr). . . . . . . . . . . . . . . . . . . . . . . . 1506 figure 863. sync frame id acceptance filter value register (fr_sfidafvr). . . . . . . . . . . . . . . . 1507 figure 864. sync frame id acceptance filter mask register (fr_sfidafmr). . . . . . . . . . . . . . . . 1507 figure 865. network management vector registers (fr_nmvr0?fr_nmvr5) . . . . . . . . . . . . . . . 1507 figure 866. network management vector length register (fr_nmvlr) . . . . . . . . . . . . . . . . . . . . 1508 figure 867. timer configuration and control register (fr_ticcr) . . . . . . . . . . . . . . . . . . . . . . . . . 1509 figure 868. timer 1 cycle set register (fr_ti1cysr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510 figure 869. timer 1 macrotick offset register (fr_ti1mtor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510 figure 870. timer 2 configuration register 0 (fr_ti2cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511 figure 871. timer 2 configuration register 1 (fr_ti2cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511 figure 872. slot status selection register (fr_sssr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512 figure 873. slot status counter condition register (fr_ssccr) . . . . . . . . . . . . . . . . . . . . . . . . . . 1513 figure 874. slot status registers (fr_ssr0?fr_ssr7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1515 figure 875. slot status counter registers (fr_sscr0?fr_sscr3) . . . . . . . . . . . . . . . . . . . . . . . 1516 figure 876. mts a configuration register (fr_mtsacfr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517 figure 877. mts b configuration register (mtsbcfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517 RM0029 list of figures doc id 15177 rev 8 63/1740 figure 878. receive shadow buffer index register (fr_rsbir) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518 figure 879. receive fifo system memory base address high register (fr_rfsymbadhr) . . . 1519 figure 880. receive fifo system memory base address low register (fr_rfsymbadlr). . . . 1519 figure 881. receive fifo periodic timer register (fr_rfptr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519 figure 882. receive fifo watermark and selection register (fr_rfwmsr) . . . . . . . . . . . . . . . . 1520 figure 883. receive fifo start index register (fr_rfsir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520 figure 884. receive fifo depth and size register (rfdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521 figure 885. receive fifo a read index register (fr_rfarir) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521 figure 886. receive fifo b read index register (fr_rfbrir) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522 figure 887. receive fifo fill level and pop count register (fr_rfflpcr) . . . . . . . . . . . . . . . . 1522 figure 888. receive fifo message id acceptance filter value register (fr_rfmidafvr) . . . . . 1523 figure 889. receive fifo message id acceptance filter mask register (fr_rfmidafmr) . . . . . 1523 figure 890. receive fifo frame id rejection filter value register (fr_rffidrfvr) . . . . . . . . . 1524 figure 891. receive fifo frame id rejection filter mask register (fr_rffidrfmr) . . . . . . . . . 1524 figure 892. receive fifo range filter configuration register (fr_rfrfcfr) . . . . . . . . . . . . . . . 1524 figure 893. receive fifo range filter control register (fr_rfrfctr) . . . . . . . . . . . . . . . . . . . . 1525 figure 894. last dynamic transmit slot channel a register (fr_ldtxslar) . . . . . . . . . . . . . . . . 1526 figure 895. last dynamic transmit slot channel b register (fr_ldtxslbr) . . . . . . . . . . . . . . . . 1526 figure 896. protocol configuration register 0 (fr_pcr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529 figure 897. protocol configuration register 1 (fr_pcr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529 figure 898. protocol configuration register 2 (fr_pcr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529 figure 899. protocol configuration register 3 (fr_pcr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530 figure 900. protocol configuration register 4 (fr_pcr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530 figure 901. protocol configuration register 5 (fr_pcr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530 figure 902. protocol configuration register 6 (fr_pcr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530 figure 903. protocol configuration register 7 (fr_pcr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530 figure 904. protocol configuration register 8 (fr_pcr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531 figure 905. protocol configuration register 9 (fr_pcr9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531 figure 906. protocol configuration register 10 (fr_pcr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531 figure 907. protocol configuration register 11 (fr_pcr11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531 figure 908. protocol configuration register 12 (fr_pcr12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532 figure 909. protocol configuration register 13 (fr_pcr13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532 figure 910. protocol configuration register 14 (fr_pcr14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532 figure 911. protocol configuration register 15 (fr_pcr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532 figure 912. protocol configuration register 16 (fr_pcr16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532 figure 913. protocol configuration register 17 (fr_pcr17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533 figure 914. protocol configuration register 18 (fr_pcr18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533 figure 915. protocol configuration register 19 (fr_pcr19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533 figure 916. protocol configuration register 20 (fr_pcr20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533 figure 917. protocol configuration register 21 (fr_pcr21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533 figure 918. protocol configuration register 22 (fr_pcr22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1534 figure 919. protocol configuration register 23 (fr_pcr23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1534 figure 920. protocol configuration register 24 (fr_pcr24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1534 figure 921. protocol configuration register 25 (fr_pcr25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1534 figure 922. protocol configuration register 26 (fr_pcr26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535 figure 923. protocol configuration register 27 (fr_pcr27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535 figure 924. protocol configuration register 28 (fr_pcr28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535 figure 925. protocol configuration register 29 (fr_pcr29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535 figure 926. protocol configuration register 30 (fr_pcr30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1536 figure 927. ecc error interrupt flag and enable register (fr_eeifer) . . . . . . . . . . . . . . . . . . . . 1536 figure 928. ecc error report and injection control register (fr_eericr) . . . . . . . . . . . . . . . . . . 1539 figure 929. ecc error report address register (fr_eerar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539 list of figures RM0029 64/1740 doc id 15177 rev 8 figure 930. ecc error report data register (fr_eerdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540 figure 931. ecc error report code register (fr_eercr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541 figure 932. ecc error injection address register (fr_eeiar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541 figure 933. ecc error injection data register (fr_eeidr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542 figure 934. ecc error injection code register (fr_eeicr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542 figure 935. message buffer configuration, control, status registers (fr_mbccsrn). . . . . . . . . . 1543 figure 936. message buffer cycle counter filter registers (fr_mbccfrn) . . . . . . . . . . . . . . . . . 1545 figure 937. message buffer frame id registers (fr_mbfidrn). . . . . . . . . . . . . . . . . . . . . . . . . . . 1546 figure 938. message buffer index registers (fr_mbidxrn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547 figure 939. physical message buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548 figure 940. individual message buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1550 figure 941. receive shadow buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551 figure 942. receive fifo structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552 figure 943. example of flexray memory area layout (fr_mcr[fam] = 0). . . . . . . . . . . . . . . . . . . 1555 figure 944. example of flexray memory area layout (fr_mcr[fam] = 1). . . . . . . . . . . . . . . . . . . 1556 figure 945. frame header structure (receive message buffer and receive fifo). . . . . . . . . . . . . . . 1558 figure 946. frame header structure (transmit message buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558 figure 947. frame header structure (transmit message buffer for key slot) . . . . . . . . . . . . . . . . . . . 1559 figure 948. receive message buffer slot status structure (chab) . . . . . . . . . . . . . . . . . . . . . . . . . . 1562 figure 949. receive message buffer slot status structure (cha). . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562 figure 950. receive message buffer slot status structure (chb). . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562 figure 951. transmit message buffer slot status structure (chab) . . . . . . . . . . . . . . . . . . . . . . . . . . 1564 figure 952. transmit message buffer slot status structure (cha) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564 figure 953. transmit message buffer slot status structure (chb) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564 figure 954. message buffer data field structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566 figure 955. single transmit message buffer access regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1569 figure 956. single transmit message buffer states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 71 figure 957. message transmission timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575 figure 958. message transmission from hlck state with unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575 figure 959. null frame transmission from idle state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 576 figure 960. null frame transmission from hlck state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576 figure 961. null frame transmission from hlck state with unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576 figure 962. null frame transmission from idle state with locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577 figure 963. receive message buffer access regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578 figure 964. receive message buffer states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1579 figure 965. message reception timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1583 figure 966. double transmit buffer structure and data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585 figure 967. double transmit message buffer access regions layout . . . . . . . . . . . . . . . . . . . . . . . . . 1586 figure 968. double transmit message buffer state diagram (commit side) . . . . . . . . . . . . . . . . . . . . 1587 figure 969. double transmit message buffer state diagram (transmit side) . . . . . . . . . . . . . . . . . . . 1588 figure 970. internal message transfer in streaming commit mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1593 figure 971. internal message transfer in immediate commit mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1593 figure 972. inconsistent channel assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1596 figure 973. message buffer reconfiguration scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597 figure 974. received frame fifo filter path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602 figure 975. dual channel device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605 figure 976. single channel device mode (channel a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606 figure 977. single channel device mode (channel b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606 figure 978. external offset correction write and application timing . . . . . . . . . . . . . . . . . . . . . . . . . . 1607 figure 979. external rate correction write and application timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607 figure 980. sync table memory layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608 figure 981. sync frame table trigger and generation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610 RM0029 list of figures doc id 15177 rev 8 65/1740 figure 982. strobe signal timing (type = pulse, clk_offset = -2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613 figure 983. strobe signal timing (type = pulse, clk_offset = +4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613 figure 984. slot status vector update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615 figure 985. slot status counting and fr_sscrn update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617 figure 986. scheme of fr_gifer interrupt signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621 figure 987. scheme of fr_eeifer interrupt signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622 figure 988. scheme of fr_cifr flags generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1623 figure 989. transmit data not available. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638 figure 990. transmit data not available. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639 figure 991. block diagram of pit_rti. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641 figure 992. pit module control register (pitmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643 figure 993. timer load value register (ldval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644 figure 994. current timer value register (cval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645 figure 995. timer control register (tctrl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645 figure 996. timer flag register (tflg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646 figure 997. stopping and starting a timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647 figure 998. modifying running timer period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647 figure 999. dynamically setting a new load value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 47 figure 1000.power management controller diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651 figure 1001.bandgap reference block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 652 figure 1002.module configuration register (mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4 figure 1003.trimming register (trimr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656 figure 1004.status register (sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659 figure 1005.vreg 3.3 v power connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664 figure 1006.non-volatile user options register (nvusro) - array0 . . . . . . . . . . . . . . . . . . . . . . . . 1665 figure 1007.por rising and falling edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667 figure 1008.por - lvi relative rising and falling edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 67 figure 1009.jtag stl (ieee 1149.1) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673 figure 1010.5-bit instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1675 figure 1011.device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676 figure 1012.censor_ctrl register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1677 figure 1013.shifting data through a register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1678 figure 1014.ieee 1149.1-2001 tap controller finite state machine. . . . . . . . . . . . . . . . . . . . . . . . . . 1679 figure 1015.nexus port controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 687 figure 1016.4-bit instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1691 figure 1017.nexus device id register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692 figure 1018.port configuration register (pcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692 figure 1019.mseo transfers (for 2-bit mseo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1696 figure 1020.message field sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697 figure 1021.transmission sequence of messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698 figure 1022.shifting data into register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1698 figure 1023.ieee 1149.1-2001 tap controller state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700 figure 1024.nexus controller state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701 figure 1025.ieee 1149.1 controller command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702 figure 1026.dts block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706 figure 1027.dto event sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706 figure 1028.dts device connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707 figure 1029.dts_enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709 figure 1030.dts_startup register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710 figure 1031.dts_semaphore register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 711 figure 1032.dts startup sequence example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 712 preface RM0029 66/1740 doc id 15177 rev 8 preface overview the primary objective of this document is to define the functionality of the spc564a74xx, spc564a80xx family of microcontrollers for use by software and hardware developers. the spc564a74xx, spc564a80xx family is built on power architecture ? technology and integrates technologies that are important for today?s lower-end applications. as with any technical documentation, it is the reader?s responsibility to be sure he or she is using the most recent version of the documentation. to locate any published errata or updates for this document, visit the st web site at www.st.com. audience this manual is intended for system software and hardware developers and applications programmers who want to develop products with the spc564a74xx, spc564a80xx device. it is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the power architecture. chapter organization and device-specific information this document includes chapters that describe: the device as a whole the functionality of the individual modules on the device in the latter, any device-specific information is presented in the section ?information specific to this device? at the beginning of the chapter. references in addition to this reference manual, the following documents provide additional information on the operation of the spc564a74xx, spc564a80xx: ieee-isto 5001? - 2003 and 2010, the nexus 5001? forum standard for a global embedded processor debug interface ieee 1149.1-2001 standard - ieee standard test access port and boundary-scan architecture RM0029 introduction doc id 15177 rev 8 67/1740 1 introduction 1.1 the spc564a74xx, spc564a80xx microcontroller family the spc564a74xx, spc564a80xx is part of a family of microcontrollers that serves two main application areas: mid-range engine management automotive transmission control the spc564a74xx, spc564a80xx contains features of st?s spc563m family and many new features coupled with high performance 90 nm cmos technology to provide substantial reduction of cost per feature and significant performance improvement. the e200z4 host processor core of the spc564a74xx, spc564a80xx complies with the power architecture ? embedded category architecture. it is 100% user mode compatible (with floating point library) with the classic powerpc instruction set. in addition to the power architecture instruction set, this core also has additional instruction support for digital signal processing (dsp). the spc564a74xx, spc564a80xx has two levels of memory hierarchy consisting of 8 kb of instruction cache, backed by up to 192 kb on-chip sram and up to 4 mb of internal flash memory. the spc564a74xx, spc564a80xx includes an external bus interface and a ?calibration bus? that is only accessible when using calibration tools. on-chip modules include: dual issue, 32-bit power architecture embedded category compliant e200z4 cpu core complex memory protection unit (mpu) interrupt controller (intc) frequency-modulated phase-locked loop (fmpll) system integration unit (siu) boot assist module (bam) 32-channel second generation enhanced time processor unit (etpu2) 24-channel enhanced modular input output system (emios) enhanced queued analog-to-digital converter (eqadc) 3 deserial serial peripheral interface (dspi) modules 3 enhanced serial communication interface (esci) modules 3 controller-area network (flexcan) modules cyclic redundancy check (crc) module system timers nexus development interface (ndi) per ieee-isto 5001-2003 and 2010 standards on-chip voltage regulator for regulating 5 v down to 3.3 v for internal functions and nexus interface on-chip voltage regulator controller for regulating 5 v down to 1.2 v for core logic introduction RM0029 68/1740 doc id 15177 rev 8 1.2 spc564a80 and spc564a70 device comparison ta ble 1 summarizes the features spc564a80 and spc564a70 microcontrollers. table 1. spc564a80 and spc564a70 comparison feature spc564a80 spc564a70 process 90 nm core e200z4 e200z4 simd yes vle yes cache 8 kb instruction non-maskable interrupt (nmi) nmi & critical interrupt mmu 24 entry mpu 16 entry crossbar switch 5 44 4 core performance 0?150 mhz 0?150 mhz windowing software watchdog yes core nexus class 3+ class 3+ sram 192 kb 128 kb flash 4 mb 2 mb flash fetch accelerator 4 256-bit external bus 16-bit (incl 32-bit muxed) 4 128-bit calibration bus 16-bit (incl 32-bit muxed) none dma 64 ch. dma nexus none serial 3 esci_a yes (msc uplink) esci_b yes (msc uplink) esci_c yes can 3 can_a 64 buf can_b 64 buf can_c 64 buf spi 3 RM0029 introduction doc id 15177 rev 8 69/1740 micro second channel (msc) bus downlink yes dspi_a no dspi_b yes (with lvds) dspi_c yes (with lvds) dspi_d yes flexray yes system timers 5 pit channels 4 stm channels 1 software watchdog emios 24 ch. etpu 32 ch. etpu2 code memory 14 kb data memory 3 kb interrupt controller 486 ch. (1) adc 40 ch. adc_a yes adc_b yes temp sensor yes variable gain amp. yes decimation filter 2 2 sensor diagnostics yes crc yes fmpll yes vrc yes supplies 5 v, 3.3 v (2) low-power modes stop mode slow mode packages lqfp176 (3) lbga208 (3) pbga known good die (kgd) 496-pin csp (4) lqfp176 (3) lbga208 (3) pbga324 (1) 496-pin csp (4) 1. 199 interrupt vectors are reserved. 2. 5 v single supply only for lqfp176. 3. pinout compatible with stmicroelectronics? spc563m64 devices. 4. for st calibration tool only. table 1. spc564a80 and spc564a70 comparison (continued) feature spc564a80 spc564a70 introduction RM0029 70/1740 doc id 15177 rev 8 1.3 device block diagram figure 1 shows a top-level block diagram of the spc564a74xx, spc564a80xx. RM0029 introduction doc id 15177 rev 8 71/1740 figure 1. spc564a74xx, spc564a80xx block diagram adc ? analog to digital converter adci ? adc interface amux ? analog multiplexer bam ? boot assist module crc ? cyclic redundancy check unit dec ? decimation filter dts ? development trigger semaphore dspi ? deserial/serial peripheral interface ebi ? external bus interface ecsm ? error correction status module edma ? enhanced direct memory access emios ? enhanced modular input output system esci ? enhanced serial communications interface etpu2 ? second gen. enhanced time processing unit flexcan ? controller area network (flexcan) fmpll ? frequency-modulated phase locked loop jtag ? ieee 1149.1 test controller mmu ? memory management unit mpu ? memory protection unit pmc ? power management controller pit ? periodic interrupt timer rcosc ? low-speed rc oscillator reacm ? reaction module siu ? system integration unit spe ? signal processing extension sram ? static ram stm ? system timer module swt ? software watchdog timer vga ? variable gain amplifier vle ? variable length (instruction) encoding xosc ? xtal oscillator legend emios 24 channel 3 kb data ram 14 kb code ram etpu2 32 channel te m p s e n s adci dec x2 vga adc adc amux 4 mb flash 192 kb sram mpu crossbar switch interrupt controller edma 64 channel spe vle mmu 8 kb i-cache power architecture e200z4 tm jtag nexus ieee-isto 5001-2003/2010 flexray ext. bus interface cal bus interface flexcan 3 nexus class 3+ nexus i/o bridge fmpll crc bam pmc stm pit swt siu analog pll rcosc xosc voltage regulator standby regulator with switch dspi 3 esci 3 m4 m0 m6 m7 s0 s2 s7 s1 m1 reacm dts class 1 ecsm introduction RM0029 72/1740 doc id 15177 rev 8 1.4 feature summary 150 mhz e200z4 power architecture core ? variable length instruction encoding (vle) ? superscalar architecture with 2 execution units ? up to 2 integer or floating point instructions per cycle ? up to 4 multiply and accumulate operations per cycle memory organization ? 4 mb on-chip flash memory with ecc and read while write (rww) ? 192 kb on-chip sram with standby functionality (32 kb) and ecc ? 8 kb instruction cache (with line locking), configurable as 2- or 4-way ? 14 + 3 kb etpu code and data ram ?5 4 crossbar switch (xbar) ? 24-entry mmu ? external bus interface (ebi) with slave and master port fail safe protection ? 16-entry memory protection unit (mpu) ? crc unit with 3 sub-modules ? junction temperature sensor interrupts ? configurable interrupt controller (with nmi) ? 64-channel dma serial channels ?3 esci ?3 dspi (2 of which support downstream micro second channel [msc]) ?3 flexcan with 64 messages each ?1 flexray module (v2.1) up to 10 mbit/s with dual or single channel and 128 message objects and ecc 1 emios ? 24 unified channels 1 etpu2 (second generation etpu) ? 32 standard channels ?1 reaction module (6 channels with three outputs per channel) 2 enhanced queued analog-to-digital converters (eqadcs) ? forty 12-bit input channels (multiplexed on 2 adcs); expandable to 56 channels with external multiplexers ? 6 command queues ? trigger and dma support ? 688 ns minimum conversion time on-chip can/sci/flexray bootstrap loader with boot assist module (bam) nexus ? class 3+ for the e200z4 core ? class 1 for the etpu RM0029 introduction doc id 15177 rev 8 73/1740 jtag (5-pin) development trigger semaphore (dts) ? register of semaphores (32-bits) and an identification register ? used as part of a triggered data acquisition protocol ? evto pin is used to communicate to the external tool clock generation ? on-chip 4?40 mhz main oscillator ? on-chip fmpll (frequency-modulated phase-locked loop) up to 120 general purpose i/o lines ? individually programmable as input, output or special function ? programmable threshold (hysteresis) power reduction mode: slow, stop and stand-by modes flexible supply scheme ? 5 v single supply with external ballast ? multiple external supply: 5 v, 3.3 v and 1.2 v packages ?lqfp176 ? lbga208 ? pbga324 ? known good die (kgd) ? 496-pin csp (calibration tool only) introduction RM0029 74/1740 doc id 15177 rev 8 1.4.1 feature details 1.4.2 e200z4 core spc564a74xx, spc564a80xx devices have a high performance e200z448n3 core processor: dual issue, 32-bit power architecture embedded category cpu variable length encoding enhancements 8 kb instruction cache: 2- or 4- way set associative instruction cache thirty-two 64-bit general purpose registers (gprs) memory management unit (mmu) with 24-entry fully-associative translation look-aside buffer (tlb) harvard architecture: separate instruction bus and load/store bus vectored interrupt support non-maskable interrupt input critical interrupt input new ?wait for interrupt? instruction, to be used with new low power modes reservation instructions for implementing read-modify-write accesses signal processing extension (spe) apu single precision floating point (scalar and vector) nexus class 3+ debug process id manipulation for the mmu using an external tool 1.4.3 crossbar switch (xbar) the xbar multiport crossbar switch supports simultaneous connections between five master ports and four slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width. the crossbar allows three concurrent transactions to occur from the master ports to any slave port but each master must access a different slave. if a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. all other masters requesting that slave port are stalled until the higher priority master completes its transactions. requesting masters are treated with equal priority and are granted access to a slave port in round-robin fashion, RM0029 introduction doc id 15177 rev 8 75/1740 based upon the id of the last master to be granted access. the crossbar provides the following features: 5 master ports ? cpu instruction bus ? cpu data bus ?edma ?flexray ? external bus interface 4 slave ports ?flash ? calibration and ebi bus ?sram ? peripheral bridge 32-bit internal address, 64-bit internal data paths 1.4.4 edma the enhanced direct memory access (edma) controller is a second-generation module capable of performing complex data movements via 64 programmable channels, with minimal intervention from the host processor. the hardware micro-architecture includes a dma engine which performs source and destination address calculations, and the actual data movement operations, along with an sram-based memory containing the transfer control descriptors (tcd) for the channels. this implementation is utilized to minimize the overall block size. the edma module provides the following features: all data movement via dual-address transfers: read from source, write to destination programmable source and destination addresses, transfer size, plus support for enhanced addressing modes transfer control descriptor organized to support two-deep, nested transfer operations an inner data transfer loop defined by a ?minor? byte transfer count an outer data transfer loop defined by a ?major? iteration count channel activation via one of three methods: ? explicit software initiation ? initiation via a channel-to-channel linking mechanism for continuous transfers ? peripheral-paced hardware requests (one per channel) support for fixed-priority and round-robin channel arbitration channel completion reported via optional interrupt requests one interrupt per channel, optionally asserted at completion of major iteration count error termination interrupts optionally enabled support for scatter/gather dma processing ability to suspend channel transfers by a higher priority channel 1.4.5 interrupt controller the intc (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. introduction RM0029 76/1740 doc id 15177 rev 8 for high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (isr) has been minimized. the intc provides a unique vector for each interrupt request source for quick determination of which isr needs to be executed. it also provides an ample number of priorities so that lower priority isrs do not delay the execution of higher priority isrs. to allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. when multiple tasks share a resource, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource cannot preempt each other. the intc provides the following features: 9-bit vector addresses unique vector for each interrupt request source hardware connection to processor or read from register each interrupt source can assigned a specific priority by software preemptive prioritized interrupt requests to processor isr at a higher priority preempts executing isrs or tasks at lower priorities automatic pushing or popping of preempted priority to or from a lifo ability to modify the isr or task priority to implement the priority ceiling protocol for accessing shared resources low latency?three clocks from receipt of interrupt request from peripheral to interrupt request to processor this device also includes a non-maskable interrupt (nmi) pin that bypasses the intc and multiplexing logic. 1.4.6 memory protection unit (mpu) the memory protection unit (mpu) provides hardware access control for all memory references generated in a device. using preprogrammed region descriptors, which define memory spaces and their associated access rights, the mpu concurrently monitors all system bus transactions and evaluates the appropriateness of each transfer. memory references with sufficient access control rights are allowed to complete; references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. the mpu has these major features: support for 16 memory region descriptors, each 128 bits in size ? specification of start and end addresses provide granularity for region sizes from 32 bytes to 4 gb ? mpu is invalid at reset, thus no access restrictions are enforced ? two types of access control definitions: processor core bus master supports the traditional {read, write, execute} permissions with independent definitions for RM0029 introduction doc id 15177 rev 8 77/1740 supervisor and user mode accesses; the remaining non-core bus masters (edma, flexray, and ebi 1 ) support {read, write} attributes ? automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a coherent image of the descriptor ? alternate memory view of the access control word for each descriptor provides an efficient mechanism to dynamically alter the access rights of a descriptor only (a) ? for overlapping region descriptors, priority is given to permission granting over access denying as this approach provides more flexibility to system software support for two xbar slave port connections (sram and pbridge) ? for each connected xbar slave port (sram and pbridge), mpu hardware monitors every port access using the pre-programmed memory region descriptors ? an access protection error is detected if a memory reference does not hit in any memory region or the reference is flagged as illegal in all memory regions where it does hit. in the event of an access error, the xbar reference is terminated with an error response and the mpu inhibits the bus cycle being sent to the targeted slave device ? 64-bit error registers, one for each xbar slave port, capture the last faulting address, attributes, and detail information 1.4.7 fmpll the fmpll allows the user to generate high speed system clocks from a 4 mhz to 40 mhz crystal oscillator or external clock generator. further, the fmpll supports programmable frequency modulation of the system clock. the pll multiplication factor, output clock divider ratio are all software configurable. the pll has the following major features: input clock frequency from 4 mhz to 40 mhz reduced frequency divider (rfd) for reduced frequency operation without forcing the pll to relock 3 modes of operation ? bypass mode with pll off ? bypass mode with pll running (default mode out of reset) ? pll normal mode each of the three modes may be run with a crystal oscillator or an external clock reference a. ebi not available on all packages and is not available, as a master, for customer. introduction RM0029 78/1740 doc id 15177 rev 8 programmable frequency modulation ? modulation enabled/disabled through software ? triangle wave modulation up to 100 khz modulation frequency ? programmable modulation depth (0% to 2% modulation depth) ? programmable modulation frequency dependent on reference frequency lock detect circuitry reports when the pll has achieved frequency lock and continuously monitors lock status to report loss of lock conditions clock quality module ? detects the quality of the crystal clock and causes interrupt request or system reset if error is detected ? detects the quality of the pll output clock; if error detected, causes system reset or switches system clock to crystal clock and causes interrupt request programmable interrupt request or system reset on loss of lock self-clocked mode (scm) operation 1.4.8 siu the spc564a74xx, spc564a80xx siu controls mcu reset configuration, pad configuration, external interrupt, general purpose i/o (gpio), internal peripheral multiplexing, and the system reset operation. the reset configuration block contains the external pin boot configuration logic. the pad configuration block controls the static electrical characteristics of i/o pins. the gpio block provides uniform and discrete input/output control of the i/o pins of the mcu. the reset controller performs reset monitoring of internal and external reset sources, and drives the rstout pin. RM0029 introduction doc id 15177 rev 8 79/1740 communication between the siu and the e200z4 cpu core is via the crossbar switch. the siu provides the following features: system configuration ? mcu reset configuration via external pins ? pad configuration control for each pad ? pad configuration control for virtual i/o via dspi serialization system reset monitoring and generation ? power-on reset support ? reset status register provides last reset source to software ? glitch detection on reset input ? software controlled reset assertion external interrupt ? rising or falling edge event detection ? programmable digital filter for glitch rejection ? critical interrupt request ? non-maskable interrupt request gpio ? centralized control of i/o and bus pins ? virtual gpio via dspi serialization (requires external deserialization device) ? dedicated input and output registers for setting each gpio and virtual gpio pin internal multiplexing ? allows serial and parallel chaining of dspis ? allows flexible selection of eqadc trigger inputs ? allows selection of interrupt requests between external pins and dspi 1.4.9 flash memory the spc564a74xx, spc564a80xx provides up to 4 mb of programmable, non-volatile, flash memory. the non-volatile memory (nvm) can be used to store instructions or data, or both. the flash module includes a fetch accelerator that optimizes the performance of the flash array to match the cpu architecture. the flash module interfaces the system bus to a dedicated flash memory array controller. for cpu ?loads?, dma transfers and cpu instruction fetch, it supports a 64-bit data bus width at the system bus port, and 128- and 256-bit read data interfaces to flash memory. the module contains a prefetch controller which prefetches sequential lines of data from the flash array into the buffers. prefetch buffer hits allow no-wait responses. the flash memory provides the following features: supports a 64-bit data bus for instruction fetch, cpu loads and dma access. byte, halfword, word and doubleword reads are supported. only aligned word and doubleword writes are supported. fetch accelerator ? architected to optimize the performance of the flash ? configurable read buffering and line prefetch support ? four-entry 256-bit wide line read buffer ? prefetch controller introduction RM0029 80/1740 doc id 15177 rev 8 hardware and software configurable read and write access protections on a per-master basis interface to the flash array controller pipelined with a depth of one, allowing overlapped accesses to proceed in parallel for interleaved or pipelined flash array designs configurable access timing usable in a wide range of system frequencies multiple-mapping support and mapping-based block access timing (0-31 additional cycles) usable for emulation of other memory types software programmable block program/erase restriction control erase of selected block(s) read page size of 128 bits (four words) ecc with single-bit correction, double-bit detection program page size of 128 bits (four words) to accelerate programming ecc single-bit error corrections are visible to software minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ecc embedded hardware program and erase algorithm erase suspend, program suspend and erase-suspended program shadow information stored in non-volatile shadow block independent program/erase of the shadow block 1.4.10 bam the bam (boot assist module) is a block of read-only memory that is programmed once by st and is identical for all spc564a74xx, spc564a80xx mcus. the bam program is executed every time the mcu is powered-on or reset in normal mode. the bam supports different modes of booting. they are: booting from internal flash memory serial boot loading (a program is downloaded into ram via esci or the flexcan and then executed) booting from external memory on external bus the bam also reads the reset configuration ha lf word (rchw) from in ternal flash memory and configures the spc564a74xx, spc564a80xx hardware accordingly. the bam provides the following features: sets up mmu to cover all resources and mapping of all physical addresses to logical addresses with minimum address translation sets up mmu to allow user boot code to execute as either power architecture embedded category (default) or as vle code location and detection of user boot code automatic switch to serial boot mode if internal flash is blank or invalid supports user programmable 64-bit password protection for serial boot mode supports serial bootloading via flexcan bus and esci using standard protocol supports serial bootloading via flexcan bus and esci with auto baud rate sensing RM0029 introduction doc id 15177 rev 8 81/1740 supports serial bootloading of either power architecture code (default) or vle code supports booting from calibration bus interface supports censorship protection for internal flash memory provides an option to enable the core watchdog timer provides an option to disable the system watchdog timer 1.4.11 emios the emios timer module provides the capability to generate or measure events in hardware. the emios module features include: twenty-four 24-bit wide channels 3 channels? internal timebases can be shared between channels 1 timebase from etpu2 can be imported and used by the channels global enable feature for all emios and etpu timebases dedicated pin for each channel (not available on all package types) each channel (0?23) supports the following functions: general-purpose input/output (gpio) single-action input capture (saic) single-action output compare (saoc) output pulse-width modulation buffered (opwmb) input period measurement (ipm) input pulse-width measurement (ipwm) double-action output compare (daoc) modulus counter buffered (mcb) output pulse width and frequency modulation buffered (opwfmb) 1.4.12 etpu2 the etpu2 is an enhanced co-processor designed for timing control. operating in parallel with the host cpu, the etpu2 processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host intervention. consequently, for each timer event, the host cpu setup and service times are minimized or eliminated. a powerful timer subsystem is formed by combining the etpu2 with its own instruction and data ram. high-level assembler/compiler and documentation allows customers to develop their own functions on the etpu2. spc564a74xx, spc564a80xx devices feature the second generation of the etpu, called etpu2. enhancements of the etpu2 over the standard etpu include: the timer counter (tcr1), channel logic and digital filters (both channel and the external timer clock input [tcrclk]) now have an option to run at full system clock speed or system clock / 2. channels support unordered transitions: transition 2 can now be detected before transition 1. related to this enhancement, the transition detection latches (tdl1 and tdl2) can now be independently negated by microcode. introduction RM0029 82/1740 doc id 15177 rev 8 a new user programmable channel mode has been added: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode. microinstructions now provide an option to issue interrupt and data transfer requests selected by channel. they can also be requested simultaneously at the same instruction. channel flags 0 and 1 can now be tested for branching, in addition to selecting the entry point. channel digital filters can be bypassed. the etpu2 includes these distinctive features: 32 channels; each channel associated with one input and one output signal ? enhanced input digital filters on the input pins for improved noise immunity ? identical, orthogonal channels: each channel can perform any time function. each time function can be assigned to more than one channel at a given time, so each signal can have any functionality. ? each channel has an event mechanism which supports single and double action functionality in various combinations. it includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and equal-only comparators. ? input and output signal states visible from the host 2 independent 24-bit time bases for channel synchronization: ? first time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by output of second time base prescaler ? second time base counter can work as a continuous angle counter, enabling angle based applications to match angle instead of time ? both time bases can be exported to the emios timer module ? both time bases visible from the host event-triggered microengine: ? fixed-length instruction execution in two-system-clock microcycle ? 14 kb of code memory (scm) ? 3 kb of parameter (data) ram (spram) ? parallel execution of data memory, alu, channel control and flow control sub- instructions in selected combinations ? 32-bit microengine registers and 24-bit wide alu, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign extension and conditional execution ? additional 24-bit multiply/mac/divide unit which supports all signed/unsigned multiply/mac combinations, and unsigned 24-bit divide. the mac/divide unit works in parallel with the regular microcode commands. resource sharing features support channel use of common channel registers, memory and microengine time: ? hardware scheduler works as a ?task management? unit, dispatching event service routines by predefined, host-configured priority ? automatic channel context switch when a ?task switch? occurs, that is, one function thread ends and another begins to service a request from other channel: RM0029 introduction doc id 15177 rev 8 83/1740 channel-specific registers, flags and parameter base address are automatically loaded for the next serviced channel ? spram shared between host cpu and etpu2, supporting communication either between channels and host or inter-channel ? hardware implementation of four semaphores support coherent parameter sharing between both etpu engines ? dual-parameter coherency hardware support allows atomic access to two parameters by host test and development support features: ? nexus class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware breakpoints and watchpoints on several conditions ? software breakpoints ? scm continuous signature-check built-in self test (misc - multiple input signature calculator), runs concurrently with etpu2 normal operation 1.4.13 reaction module the reaction module provides the ability to modulate output signals to manage closed loop control without cpu assistance. it works in conjunction with the eqadc and etpu2 to increase system performance by removing the cpu from the current control loop. the reaction module has the following features: 6 reaction channels each channel output is a bus of 3 signals, providing ability to control 3 inputs. each channel can implement a peak and hold waveform, making it possible to implement up to six independent peak and hold control channels target applications include solenoid control for direct injection systems and valve control in automatic transmissions 1.4.14 eqadc the enhanced queued analog to digital converter (eqadc) block provides accurate and fast conversions for a wide range of applications. the eqadc provides a parallel interface to two on-chip analog to digital converters (adc), and a single master to single slave serial interface to an off-chip external device. both on-chip adcs have access to all the analog channels. the eqadc prioritizes and transfers commands from six command conversion command ?queues? to the on-chip adcs or to the external device. the block can also receive data from the on-chip adcs or from an off-chip external device into the six result queues, in parallel, independently of the command queues. the six command queues are prioritized with queue_0 having the highest priority and queue_5 the lowest. queue_0 also has the added ability to bypass all buffering and queuing and abort a currently running conversion on either adc and start a queue_0 conversion. this means that queue_0 will always have a deterministic time from trigger to start of conversion, irrespective of what tasks the adcs were performing when the trigger occurred. the eqadc supports software and external hardware triggers from other blocks to initiate transfers of commands from the queues to the on-chip adcs or to the external device. it also monitors the fullness of command queues and result queues, and accordingly generates dma or interrupt requests to control data movement between the queues and the system memory, which is external to the eqadc. introduction RM0029 84/1740 doc id 15177 rev 8 the adcs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used in a system for detecting engine knock. these features include differential inputs; integrated variable gain amplifiers for increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics. the eqadc also integrates a programmable decimation filter capable of taking in adc conversion results at a high rate, passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate results to the result fifos. this allows the adcs to sample the sensor at a rate high enough to avoid aliasing of out-of-band noise; while providing a reduced sample rate output to minimize the amount dsp processing bandwidth required to fully process the digitized waveform. the eqadc provides the following features: dual on-chip adcs ?2 12-bit adc resolution ? programmable resolution for increased conversion speed (12-bit, 10-bit, 8-bit) 12-bit conversion time: 938 ns (1 m sample/sec) 10-bit conversion time: 813 ns (1.2 m sample/second) 8-bit conversion time: 688 ns (1.4 m sample/second) ? up to 10-bit accuracy at 500 ksample/s and 8-bit accuracy at 1 msample/s ? differential conversions ? single-ended signal range from 0 to 5 v ? variable gain amplifiers on differential inputs ( 1, 2, 4) ? sample times of 2 (default), 8, 64 or 128 adc clock cycles ? provides time stamp information when requested ? allows time stamp information relative to etpu clock sources, such as an angle clock ? parallel interface to eqadc cfifos and rfifos ? supports both right-justified unsigned and signed formats for conversion results 40 single-ended input channels, expandable to 56 channels with external multiplexers (supports four external 8-to-1 muxes) 8 channels can be used as 4 pairs of differential analog input channels differential channels include variable gain amplifier for improved dynamic range differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics (200 k , 100 k , 5k ) additional internal channels for monitoring voltages (such as core voltage, i/o voltage, lvi voltages, etc.) inside the device an internal bandgap reference to allow absolute voltage measurements silicon die temperature sensor ? provides temperature of silicon as an analog value ? read using an internal adc analog channel ? may be read with either adc RM0029 introduction doc id 15177 rev 8 85/1740 2 decimation filters ? programmable decimation factor (1 to 16) ? selectable iir or fir filter ? up to 4th order iir or 8th order fir ? programmable coefficients ? saturated or non-saturated modes ? programmable rounding (convergent; two?s complement; truncated) ? prefill mode to precondition the filter before the sample window opens ? supports multiple cascading decimation filters to implement more complex filter designs ? optional absolute integrators on the output of decimation filters full duplex synchronous serial interface to an external device ? free-running clock for use by an external device ? supports a 26-bit message length priority based queues ? supports six queues with fixed priority. when commands of distinct queues are bound for the same adc, the higher priority queue is always served first ? queue_0 can bypass all prioritization, buffering and abort current conversions to start a queue_0 conversion a deterministic time after the queue trigger ? supports software and hardware trigger modes to arm a particular queue ? generates interrupt when command coherency is not achieved external hardware triggers ? supports rising edge, falling edge, high level and low level triggers ? supports configurable digital filter 1.4.15 dspi the deserial serial peripheral interface (dspi) block provides a synchronous serial interface for communication between the spc564a74xx, spc564a80xx mcu and external devices. the dspi supports pin count reduction through serialization and deserialization of etpu and emios channels and memory-mapped registers. the channels and register content are transmitted using a spi-like protocol. this spi-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion, etc. each bit in the frame may be configured to serialize either etpu channels, emios channels or gpio signals. the dspi can be configured to serialize data to an external device that implements the microsecond bus protocol. there are three identical dspi blocks on the spc564a74xx, spc564a80xx mcu. the dspi pins support 5 v logic levels or low voltage differential signalling (lvds) to improve high speed operation. dspi module features include: selectable lvds pads working at 40 mhz for sout and sck pins for dspi_b and dspi_c 3 sources of serialized data: etpu_a, emios output channels and memory-mapped register in the dspi 4 destinations for deserialized data: etpu_a and emios input channels, siu external interrupt input request, memory-mapped register in the dspi introduction RM0029 86/1740 doc id 15177 rev 8 32-bit dsi and tsb modes require 32 pcr registers, 32 gpo and gpi registers in the siu to select either gpio, etpu or emios bits for serialization the dspi module can generate and check parity in a serial frame 1.4.16 esci three enhanced serial communications interface (esci) modules provide asynchronous serial communications with peripheral devices and other mcus, and include support to interface to local interconnect network (lin) slave devices. each esci block provides the following features: full-duplex operation standard mark/space non-return-to-zero (nrz) format 13-bit baud rate selection programmable 8-bit or 9-bit, data format programmable 12-bit or 13-bit data format for timed serial bus (tsb) configuration to support the microsecond bus standard automatic parity generation lin support ? autonomous transmission of entire frames ? configurable to support all revisions of the lin standard ? automatic parity bit generation ? double stop bit after bit error ? 10- or 13-bit break support separately enabled transmitter and receiver programmable transmitter output parity 2 receiver wake-up methods: ? idle line wake-up ? address mark wake-up interrupt-driven operation with flags receiver framing error detection hardware parity checking 1/16 bit-time noise detection dma support for both transmit and receive data ? global error bit stored with receive data in system ram to allow post processing of errors 1.4.17 flexcan the spc564a74xx, spc564a80xx mcu includes three controller area network (flexcan) blocks. the flexcan module is a communication controller implementing the can protocol according to bosch specification version 2.0b. the can protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real- time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. each flexcan module contains 64 message buffers. RM0029 introduction doc id 15177 rev 8 87/1740 the flexcan modules provide the following features: full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? zero to eight bytes data length ? programmable bit rate up to 1 mbit/s content-related addressing 64 message buffers of zero to eight bytes data length individual rx mask register per message buffer each message buffer configurable as rx or tx, all supporting standard and extended messages includes 1088 bytes of embedded memory for message buffer storage includes 256-byte memory for storing individual rx mask registers full featured rx fifo with storage capacity for six frames and internal pointer handling powerful rx fifo id filtering, capable of matching incoming ids against 8 extended, 16 standard or 32 partial (8 bits) ids, with individual masking capability selectable backwards compatibility with previous flexcan versions programmable clock source to the can protocol interface, either system clock or oscillator clock listen only mode capability programmable loop-back mode supporting self-test operation 3 programmable mask registers programmable transmit-first scheme: lowest id, lowest buffer number or highest priority time stamp based on 16-bit free-running timer global network time, synchronized by a specific message maskable interrupts warning interrupts when the rx and tx error counters reach 96 independent of the transmission medium (an external transceiver is assumed) multi-master concept high immunity to emi short latency time due to an arbitration scheme for high-priority messages low power mode, with programmable wake-up on bus activity introduction RM0029 88/1740 doc id 15177 rev 8 1.4.18 flexray the spc564a74xx, spc564a80xx includes one dual-channel flexray module that implements the flexray communications system protocol specification, version 2.1 rev a. features include: single channel support flexray bus data rates of 10 mbit/s, 8 mbit/s, 5 mbit/s, and 2.5 mbit/s supported 128 message buffers, each configurable as: ? receive message buffer ? single buffered transmit message buffer ? double buffered transmit message buffer (combines two single buffered message buffer) 2 independent receive fifos ? 1 receive fifo per channel ? up to 255 entries for each fifo ecc support 1.4.19 system timers the system timers include two distinct types of system timer: periodic interrupts/triggers using the periodic interrupt timer (pit) operating system task monitors using the system timer module (stm) periodic interrupt timer (pit) the pit provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. the pit has no external input or output pins and is intended to provide system ?tick? signals to the operating system, as well as periodic triggers for eqadc queues. of the five channels in the pit, four are clocked by the system clock and one is clocked by the crystal clock. this one channel is also referred to as real-time interrupt (rti) and is used to wake up the device from low power stop mode. the following features are implemented in the pit: 5 independent timer channels each channel includes 32-bit wide down counter with automatic reload 4 channels clocked from system clock 1 channel clocked from crystal clock (wake-up timer) wake-up timer remains active when system stop mode is entered; used to restart system clock after predefined time-out period each channel optionally able to generate an interrupt request or a trigger event (to trigger eqadc queues) when timer reaches zero system timer module (stm) the system timer module (stm) is designed to implement the software task monitor as defined by autosar (b) . it consists of a single 32-bit counter, clocked by the system clock, b. autosar: automotive open system architecture (see www.autosar.org) RM0029 introduction doc id 15177 rev 8 89/1740 and four independent timer comparators. these comparators produce a cpu interrupt when the timer exceeds the programmed value. the following features are implemented in the stm: one 32-bit up counter with 8-bit prescaler four 32-bit compare channels independent interrupt source for each channel counter can be stopped in debug mode 1.4.20 software watchdog timer (swt) the software watchdog timer (swt) is a second watchdog module to complement the standard power architecture watchdog integrated in the cpu core. the swt is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can provide a system reset or interrupt request when the correct software key is not written within the required time window. the following features are implemented: 32-bit modulus counter clocked by system clock or crystal clock optional programmable watchdog window mode can optionally cause system reset or interrupt request on timeout reset by writing a software key to memory mapped register enabled out of reset configuration is protected by a software key or a write-once register 1.4.21 cyclic redundancy check (crc) module the crc computing unit is dedicated to the computation of crc off-loading the cpu. the crc features: support for crc-16-cci tt (x25 protocol): ?x 16 + x 12 + x 5 + 1 support for crc-32 (ethernet protocol): ?x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 zero wait states for each write/read operations to the crc_cfg and crc_inp registers at the maximum frequency 1.4.22 error correction status module (ecsm) the ecsm provides a myriad of miscellaneous control functions regarding program-visible information about the platform configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes, and information on platform memory errors reported by error-correcting codes and/or generic access error information for certain processor cores. introduction RM0029 90/1740 doc id 15177 rev 8 the error correction status module supports a number of miscellaneous control functions for the platform. the ecsm includes these features: registers for capturing information on platform memory errors if error-correcting codes (ecc) are implemented for test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the spc564a74xx, spc564a80xx. the sources of the ecc errors are: flash sram peripheral ram (flexray, can, etpu2 parameter ram) 1.4.23 external bus interface (ebi) the spc564a74xx, spc564a80xx device features an external bus interface that is available in pbga324 and calibration packages. the ebi supports operation at frequencies of system clock /1, /2 and /4, with a maximum frequency support of 80 mhz. customers running the device at 120 mhz or 132 mhz will use the /2 divider, giving an ebi frequency of 60 mhz or 66 mhz. customers running the device at 80 mhz will be able to use the /1 divider to have the ebi run at the full 80 mhz frequency. features include: 1.8 v to 3.3 v 10% i/o (1.6 v to 3.6 v) memory controller with support for various memory types 16-bit data bus, up to 22-bit address bus pin muxing included to support 32-bit muxed bus selectable drive strength configurable bus speed modes bus monitor configurable wait states 1.4.24 calibration ebi the calibration ebi controls data transfer across the crossbar switch to/from memories or peripherals attached to the calibration tool connector in the calibration address space. the calibration ebi is only available in the calibration tool. features include: 1.8 v to 3.3 v 10% i/o (1.6 v to 3.6 v) memory controller supports various memory types 16-bit data bus, up to 22-bit address bus pin muxing supports 32-bit muxed bus selectable drive strength configurable bus speed modes bus monitor configurable wait states RM0029 introduction doc id 15177 rev 8 91/1740 1.4.25 power management controller (pmc) the power management controller contains circuitry to generate the internal 3.3 v supply and to control the regulation of 1.2 v supply with an external npn ballast transistor. it also contains low voltage inhibit (lvi) and power-on reset (por) circuits for the 1.2 v supply, the 3.3 v supply, the 3.3 v/5 v supply of the closest i/o segment (vddeh1) and the 5 v supply of the regulators (vddreg). 1.4.26 nexus port controller the npc (nexus port controller) block provides real-time nexus class3+ development support capabilities for the spc564a74xx, spc564a80xx power architecture-based mcu in compliance with the ieee-isto 5001-2003 and 2010 standards. mdo port widths of 4 pins and 12 pins are available in all packages. 1.4.27 jtag the jtagc (jtag controller) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. testing is performed via a boundary scan technique, as defined in the ieee 1149.1-2001 standard. all data input to and output from the jtagc block is communicated in serial format. the jtagc block is compliant with the ieee 1149.1-2001 standard and supports the following features: ieee 1149.1-2001 test access port (tap) interface 4 pins (tdi, tms, tck, and tdo) a 5-bit instruction register that supports the following ieee 1149.1-2001 defined instructions: ? bypass, idcode, extest, sample, sample/preload, highz, clamp a 5-bit instruction register that supports the additional following public instructions: ? access_aux_tap_npc ? access_aux_tap_once ? access_aux_tap_etpu ? access_censor 3 test data registers to support jtag boundary scan mode ? bypass register ? boundary scan register ? device identification register a tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry censorship inhibit register ? 64-bit censorship password register ? if the external tool writes a 64-bit password that matches the serial boot password stored in the internal flash shadow row, censorship is disabled until the next system reset. 1.4.28 development trigger semaphore (dts) spc564a74xx, spc564a80xx devices include a system development feature, the development trigger semaphore (dts) module, that enables software to signal an external tool by driving a persistent (affected only by reset or an external tool) signal on an external introduction RM0029 92/1740 doc id 15177 rev 8 device pin. there is a variety of ways this module can be used, including as a component of an external real-time data acquisition system. RM0029 memory map doc id 15177 rev 8 93/1740 2 memory map 2.1 introduction ta ble 2 shows the memory map for the spc564a74xx, spc564a80xx. all addresses on the spc564a74xx, spc564a80xx, including those that are reserved, are identified in the table. the addresses represent the physical addresses assigned to each ip block. 2.2 memory map table 2. spc564a74xx, spc564a80xx memory map start address end address allocated size used size region name 0x0000_0000 0x003f_ffff 4 mb 4 mb flash 0x0040_0000 0x00ef_bfff ? ? reserved 0x00ef_c000 0x00ef_ffff 16 kb 16 kb flash shadow block - fl_a 0x00ff_0000 0x00ff_bfff ? ? reserved 0x00ff_c000 0x00ff_ffff 16 kb 16 kb flash shadow block - fl_b 0x0100_0000 0x1fff_ffff 507 mb ? emulation remapping of flash 0x2000_0000 0x2fff_ffff 256 mb ? external bus 0x3000_0000 0x3fff_ffff 256 mb ? calibration bus 0x4000_0000 0x4000_7fff 32 kb 32 kb sram array, standby powered 0x4000_8000 0x4002_ffff 160 kb 160 kb sram array 0x4003_0000 0xbfff_ffff 2gb ? 192kb ? reserved bridge a peripherals 0xc000_0000 0xc3ef_ffff 63 mb ? reserved 0xc3f0_0000 0xc3f0_3fff 16 kb ? reserved 0xc3f0_4000 0xc3f7_ffff ? ? reserved 0xc3f8_0000 0xc3f8_3fff 16 kb ? fmpll 0xc3f8_4000 0xc3f8_7fff 16 kb ? external bus interface (ebi) configuration 0xc3f8_8000 0xc3f8_bfff 16 kb ? flash_fl1 configuration 0xc3f8_c000 0xc3f8_ffff 16 kb ? flash_fl2 configuration 0xc3f9_0000 0xc3f9_3fff 16 kb ? siu 0xc3f9_4000 0xc3f9_bfff ? ? reserved 0xc3f9_c000 0xc3f9_ffff 16 kb ? dts 0xc3fa_0000 0xc3fa_3fff 16 kb ? emios 0xc3fa_4000 0xc3fb_bfff ? ? reserved 0xc3fb_c000 0xc3fb_ffff 16 kb ? pmc 0xc3fc_0000 0xc3fc_3fff 16 kb ? etpu registers memory map RM0029 94/1740 doc id 15177 rev 8 0xc3fc_4000 0xc3fc_6fff ? ? reserved 0xc3fc_7000 0xc3fc_77ff 2 kb ? reaction module (reacm) 0xc3fc_7800 0xffe6_7fff ? ? reserved 0xc3fc_8000 0xc3fc_bfff 16kb 3 kb etpu parameter ram 0xc3fc_c000 0xc3fc_ffff 16 kb 3 kb etpu parameter ram mirror 0xc3fd_0000 0xc3fd_37ff 14 kb 14 kb etpu code ram 0xc3fd_3800 0xc3fe_ffff ? ? reserved 0xc3ff_0000 0xc3ff_3fff 16 kb ? pit/rti 0xc3ff_4000 0xffe6_7fff ? ? reserved 0xffe6_8000 0xffe6_bfff 16 kb ? cyclic redundancy check unit (crc) 0xffe6_c000 0xffef_ffff ? ? reserved 0xfff0_0000 0xfff0_3fff 16 kb ? pbridge 0xfff0_4000 0xfff0_7fff 16 kb ? crossbar (xbar) 0xfff0_8000 0xfff0_ffff 16 kb ? reserved 0xfff1_0000 0xfff1_3fff 16 kb ? mpu 0xfff1_4000 0xfff3_7fff 144 kb ? reserved 0xfff3_8000 0xfff3_bfff 16 kb ? swt 0xfff3_c000 0xfff3_ffff 16 kb ? stm 0xfff4_0000 0xfff4_3fff 16 kb ? ecsm 0xfff4_4000 0xfff4_7fff 16 kb ? edma 0xfff4_8000 0xfff4_bfff 16 kb ? intc 0xfff4_c000 0xfff7_ffff 208 kb ? reserved 0xfff8_0000 0xfff8_3fff 16 kb ? eqadc 0xfff8_4000 0xfff8_7fff 16 kb ? reserved 0xfff8_8000 0xfff8_bfff 16 kb ? decimation filter a 0xfff8_c000 0xfff8_ffff 16 kb ? decimation filter b 0xfff9_0000 0xfff9_3fff 16 kb ? reserved 0xfff9_4000 0xfff9_7fff 16 kb ? dspi_b 0xfff9_8000 0xfff9_bfff 16 kb ? dspi_c 0xfff9_c000 0xfff9_ffff 16 kb ? dspi_d 0xfffa_0000 0xfffa_ffff 64 kb ? reserved 0xfffb_0000 0xfffb_3fff 16 kb ? esci_a 0xfffb_4000 0xfffb_7fff 16 kb ? esci_b 0xfffb_8000 0xfffb_bfff 16 kb ? esci_c 0xfffb_c000 0xfffb_ffff 16 kb ? reserved table 2. spc564a74xx, spc564a80xx memory map (continued) start address end address allocated size used size region name RM0029 memory map doc id 15177 rev 8 95/1740 0xfffc_0000 0xfffc_3fff 16 kb ? flexcan_a 0xfffc_4000 0xfffc_7fff 16 kb ? flexcan_b 0xfffc_8000 0xfffc_bfff 16 kb ? flexcan_c 0xfffc_c000 0xfffd_ffff 80 kb ? reserved 0xfffe_0000 0xfffe_3fff 16 kb ? flexray 0xfffe_4000 0xfffe_bfff 32 kb ? reserved 0xfffe_c000 0xfffe_ffff 16 kb ? system information module (temperature sensor calibration parameters and unique device id code) 0xffff_0000 0xffff_bfff 48 kb ? reserved 0xffff_c000 0xffff_ffff 16 kb 16 kb boot assist module table 2. spc564a74xx, spc564a80xx memory map (continued) start address end address allocated size used size region name signal description RM0029 96/1740 doc id 15177 rev 8 3 signal description this chapter describes signals that connect off chip. it includes a table of signal properties and the detailed descriptions of signals. 3.1 signal properties table 3. spc564a74xx, spc564a80xx signal properties name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 gpio emios14 (8) gpio[203] emios channel gpio p g 01 00 203 o i/o vddeh7 slow ? / up ? / up ? ? h20 emios15 (8) gpio[204] emios channel gpio p g 01 00 204 o i/o vddeh7 slow ? / up ?/ up ? ? h21 gpio[206] etrig0 gpio / eqadc trigger input g 00 206 i/o (9) vddeh7 slow (10) ? / up ? / up 143 r4 aa7 gpio[207] etrig1 gpio / eqadc trigger input g 00 207 i/o (9) vddeh7 slow ? / up ? / up 144 p5 y9 gpio[219] gpio g ? 219 (11) i/o vddeh7 multiv (12) ? / up ? / up 122 t6 ? reset / configuration reset external reset input p ? ? i vddeh6 slow i / up reset / up 97 l16 r22 rstout external reset output p 01 230 o vddeh6 slow rstout / low rstout / high 102 k15 p21 pllref irq [4] etrig2 gpio[208] fmpll mode selection external interrupt request eqadc trigger input gpio p a1 a2 g 001 010 100 000 208 i i i i/o vddeh6 slow pllref/ up ? / up 83 m14 v21 RM0029 signal description doc id 15177 rev 8 97/1740 pllcfg1 (13) irq [5] dspi_d_sout gpio[209] ? external interrupt request dspi d data output gpio ? a1 a2 g ? 010 100 000 209 ? i o i/o vddeh6 medium ? / up ? / up ? ? u20 rstcfg gpio[210] rstcfg gpio p g 01 00 210 i i/o vddeh6 slow ? / down ???p22 bootcfg[0] irq [2] gpio[211] boot config. input external interrupt request gpio p a1 g 01 10 00 211 i i i/o vddeh6 slow bootcfg[0] / down ? / down ? ? u21 bootcfg[1] irq [3] etrig3 gpio[212] boot config. input external interrupt request eqadc trigger input gpio p a1 a2 g 001 010 100 000 212 i i i i/o vddeh6 slow bootcfg[1] / down ? / down 85 m15 t20 wkpcfg nmi dspi_b_sout gpio[213] weak pull config. input non-maskable interrupt dspi d data output gpio p a1 a2 g 001 010 100 000 213 i i o i/o vddeh6 medium wkpcfg / up ? / up 86 l15 r19 external bus interface cs [0] addr[8] gpio[0] external chip selects external address bus gpio p a1 g 01 10 00 0 o i/o i/o vdde2 fast ? / up ? / up ? ? m4 cs [1] addr9 gpio[1] external chip selects external address bus gpio p a1 g 01 10 00 1 o i/o i/o vdde2 fast ? / up ? / up ? ? m3 cs [2] addr10 we[ 2]/be [2] cal_we [2]/be [2] gpio[2] external chip selects external address bus write/byte enable cal. bus write/byte enable gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 2 o i/o o o i/o vdde2 fast ? / up ? / up ? ? n2 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 98/1740 doc id 15177 rev 8 cs [3] addr11 we[ 3]/be [3] cal_we[ 3]/be [3] gpio[3] external chip selects external address bus write/byte enable cal bus write/byte enable gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 3 o i/o o o i/o vdde2 fast ? / up ? / up ? ? n1 addr12 gpio[8] external address bus gpio p g 01 00 8 i/o i/o vdde3 fast ? / up ? / up ? ? t3 addr13 we[ 2] gpio[9] external address bus write/byte enable gpio p a2 g 001 100 000 9 i/o o i/o vdde3 fast ? / up ? / up ? ? u3 addr14 we[ 3] gpio[10] external address bus write/byte enables gpio p a2 g 001 100 000 10 i/o o i/o vdde3 fast ? / up ? / up ? ? u4 addr15 gpio[11] external address bus gpio p g 01 00 11 i/o i/o vdde3 fast ? / up ? / up ? ? v3 addr16 fr_a_tx data16 gpio[12] external address bus flexray tx data channel a external data bus gpio p a1 a2 g 001 010 100 000 12 i/o o i/o i/o vdde-eh medium ? / up ? / up ? ? p1 addr17 fr_a_tx_en data17 gpio[13] external address bus flexray ch. a tx data enable external data bus gpio p a1 a2 g 001 010 100 000 13 i/o o i/o i/o vdde-eh medium ? / up ? / up ? ? p2 addr18 fr_a_rx data18 gpio[14] external address bus flexray rx data ch. a external data bus gpio p a1 a2 g 001 010 100 000 14 i/o i i/o i/o vdde-eh medium ? / up ? / up ? ? r1 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 99/1740 addr19 fr_b_tx data19 gpio[15] external address bus flexray tx data ch. b external data bus gpio p a1 a2 g 001 010 100 000 15 i/o o i/o i/o vdde-eh medium ? / up ? / up ? ? r2 addr20 fr_b_tx_en data20 gpio[16] external address bus flexray tx data enable for ch. b external data bus gpio p a1 a2 g 001 010 100 000 16 i/o o i/o i/o vdde-eh medium ? / up ? / up ? ? t1 addr21 fr_b_rx data21 gpio[17] external address bus flexray rx data channel b external data bus gpio p a1 a2 g 001 010 100 000 17 i/o i i/o i/o vdde-eh medium ? / up ? / up ? ? t2 addr22 data22 gpio[18] external address bus external data bus gpio p a2 g 001 100 000 18 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? u1 addr23 data23 gpio[19] external address bus external data bus gpio p a2 g 001 100 000 19 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? u2 addr24 data24 gpio[20] external address bus external data bus gpio p a2 g 001 100 000 20 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? v1 addr25 data25 gpio[21] external address bus external data bus gpio p a2 g 001 100 000 21 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? v2 addr26 data26 gpio[22] external address bus external data bus gpio p a2 g 001 100 000 22 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? w1 addr27 data27 gpio[23] external address bus external data bus gpio p a2 g 001 100 000 23 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? y2 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 100/1740 doc id 15177 rev 8 addr28 data28 gpio[24] external address bus external data bus gpio p a2 g 001 100 000 24 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? y1 addr29 data29 gpio[25] external address bus external data bus gpio p a2 g 001 100 000 25 i/o i/o i/o vdde-eh medium ? / up ? / up ? ? aa1 addr30 addr6 (8) data30 gpio[26] external address bus external address bus external data bus gpio p a1 a2 g 001 010 100 000 26 i/o o i/o i/o vdde-eh medium ? / up ? / up ? ? w3 addr31 addr7 (8) data31 gpio[27] external address bus external address bus external data bus gpio p a1 a2 g 001 010 100 000 27 i/o o i/o i/o vdde-eh medium ? / up ? / up ? ? v4 data0 addr16 gpio[28] external data bus external address bus gpio p a1 g 001 010 000 28 i/o i/o i/o vdde5 fast ? / up ? / up ? ? ab4 data1 addr17 gpio[29] external data bus external address bus gpio p a1 g 001 010 000 29 i/o i/o i/o vdde5 fast ? / up ? / up ? ? aa5 data2 addr18 gpio[30] external data bus external address bus gpio p a1 g 001 010 000 30 i/o i/o i/o vdde5 fast ? / up ? / up ? ? ab5 data3 addr19 gpio[31] external data bus external address bus gpio p a1 g 001 010 000 31 i/o i/o i/o vdde5 fast ? / up ? / up ? ? ab6 data4 addr20 gpio[32] external data bus external address bus gpio p a1 g 001 010 000 32 i/o i/o i/o vdde5 fast ? / up ? / up ? ? ab7 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 101/1740 data5 addr21 gpio[33] external data bus external address bus gpio p a1 g 001 010 000 33 i/o i/o i/o vdde5 fast ? / up ? / up ? ? aa8 data6 addr22 gpio[34] external data bus external address bus gpio p a1 g 001 010 000 34 i/o i/o i/o vdde5 fast ? / up ? / up ? ? ab8 data7 addr23 gpio[35] external data bus external address bus gpio p a1 g 001 010 000 35 i/o i/o i/o vdde5 fast ? / up ? / up ? ? aa9 data8 addr24 gpio[36] external data bus external address bus gpio p a1 g 001 010 000 36 i/o i/o i/o vdde5 fast ? / up ? / up ? ? y6 data9 addr25 gpio[37] external data bus external address bus gpio p a1 g 001 010 000 37 i/o i/o i/o vdde5 fast ? / up ? / up ? ? y7 data10 addr26 gpio[38] external data bus external address bus gpio p a1 g 001 010 000 38 i/o i/o i/o vdde5 fast ? / up ? / up ? ? y8 data11 addr27 gpio[39] external data bus external address bus gpio p a1 g 001 010 000 39 i/o i/o i/o vdde5 fast ? / up ? / up ? ? w9 data12 addr28 gpio[40] external data bus external address bus gpio p a1 g 001 010 000 40 i/o i/o i/o vdde5 fast ? / up ? / up ? ? w10 data13 addr29 gpio[41] external data bus external address bus gpio p a1 g 001 010 000 41 i/o i/o i/o vdde5 fast ? / up ? / up ? ? y10 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 102/1740 doc id 15177 rev 8 data14 addr30 gpio[42] external data bus external address bus gpio p a1 g 001 010 000 42 i/o i/o i/o vdde5 fast ? / up ? / up ? ? w11 data15 addr31 gpio[43] external data bus external address bus gpio p a1 g 001 010 000 43 i/o i/o i/o vdde5 fast ? / up ? / up ? ? y11 rd_wr gpio[62] external read/write gpio p g 01 00 62 i/o i/o vdde2 fast ? / up ? / up ? ? p3 bdip gpio[63] external burst data in progress gpio p g 01 00 63 o i/o vdde2 fast ? / up ? / up ? ? m1 we [0]/be [0] gpio[64] external write/byte enable gpio p g 01 00 64 o i/o vdde2 fast ? / up ? / up ? ? n4 we [1]/be [1] gpio[65] external write/byte enable gpio p g 01 00 65 o i/o vdde2 fast ? / up ? / up ? ? n3 oe gpio[68] external output enable gpio p g 01 00 68 o i/o vdde2 fast ? / up ? / up ? ? ab9 ts ale gpio[69] external transfer start address latch enable gpio[69] p a1 g 001 010 000 69 i/o o i/o vdde2 fast ? / up ? / up ? ? t4 ta ts 8 gpio[70] external transfer acknowledge external transfer start gpio p a1 g 001 010 000 70 i/o o i/o vdde2 fast ? / up ? / up ? ? r4 calibration bus cal_cs0 calibration chip select p 01 336 o vdde12 fast ?/? ? ? ? cal_cs2 cal_addr[10] cal_we [2]/be [2] calibration chip select calibration address bus calibration write/byte enable p a a2 001 010 100 338 o i/o o vdde12 fast ?/? ? ? ? table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 103/1740 cal_cs3 cal_addr[11] cal_we[ 3]/be [3] calibration chip select calibration address bus calibration write/byte enable p a a2 001 010 100 339 o i/o o vdde12 fast ?/? ? ? ? cal_addr[12] cal_we[ 2]/be [2] calibration address bus calibration write/byte enable p a 01 10 340 i/o o vdde12 fast ?/? ? ? ? cal_addr[13] cal_we[ 3]/be [3] calibration address bus calibration write/byte enable p a 01 10 340 i/o o vdde12 fast ?/? ? ? ? cal_addr[14] cal_data[31] calibration address bus calibration data bus p a 01 10 340 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[15] cal_ale calibration address bus calibration address latch enable p a1 01 10 340 i/o o vdde12 fast ?/? ? ? ? cal_addr[16] cal_data[16] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[17] cal_data[17] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[18] cal_data[18] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[19] cal_data[19] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[20] cal_data[20] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[21] cal_data[21] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[22] cal_data[22] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[23] cal_data[23] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 104/1740 doc id 15177 rev 8 cal_addr[24] cal_data[24] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[25] cal_data[25] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[26] cal_data[26] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[27] cal_data[27] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[28] cal_data[28] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[29] cal_data[29] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_addr[30] cal_data[30] calibration address bus calibration data bus p a 01 10 345 i/o i/o vdde12 fast ?/? ? ? ? cal_data[0] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[1] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[2] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[3] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[4] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[5] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[6] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 105/1740 cal_data[7] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[8] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[9] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[10] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[11] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[12] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[13] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[14] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_data[15] calibration data bus p 01 341 i/o vdde12 fast ? / up ? / up ? ? ? cal_rd_wr calibration read/write enable p 01 342 o vdde12 fast ?/? ? ? ? cal_we [0]/be [0] calibration write/byte enable p 01 342 o vdde12 fast ?/? ? ? ? cal_we[ 1]/be [1] calibration write/byte enable p 01 342 o vdde12 fast ?/? ? ? ? cal_oe calibration output enable p 01 342 o vdde12 fast ?/? ? ? ? cal_ts cal_ale calibration transfer start address latch enable p a 01 10 343 o o vdde12 fast ?/? ? ? ? table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 106/1740 doc id 15177 rev 8 cal_mdo[4] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[4] / ? ? ? ? cal_mdo[5] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[5] / ? ? ? ? cal_mdo[6] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[6] / ? ? ? ? cal_mdo[7] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[7] / ? ? ? ? cal_mdo[8] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[8] / ? ? ? ? cal_mdo[9] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[9] / ? ? ? ? cal_mdo[10] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[10] / ? ? ? ? cal_mdo[11] calibration nexus message data out p01 ? o vdde12 fast ? cal_mdo[11] / ? ? ? ? nexus evti nexus event in p 01 231 i vddeh7 multiv (12),(14) ? / up evti / up 116 e15 f21 evto nexus event out p 01 227 o vddeh7 multiv (12),(14), (15) ?evto / ? 120 d15 f22 mcko nexus message clock out p ? 219 11 o vrc33 fast ?mcko / ?14f15g20 mdo0 (16) nexus message data out p 01 220 o vrc33 fast ? mdo[0] / ? 17 a14 b20 mdo1 (16) nexus message data out p 01 221 o vrc33 fast ? mdo[1] / ? 18 b14 c19 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 107/1740 mdo2 (16) nexus message data out p 01 222 o vrc33 fast ? mdo[2] / ? 19 a13 c18 mdo3 (16) nexus message data out p 01 223 o vrc33 fast ? mdo[3] / ? 20 b13 d18 mdo4 (16) etpua2_o (8) gpio[75] nexus message data out etpu a channel (output only) gpio[ p a1 g 01 10 00 75 o o i/o vddeh7 multiv (12),(14) ? ? / ? 126 p10 b19 mdo5 (16) etpua4_o (8) gpio[76] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 76 o o i/o vddeh7 multiv (12),(14) ? ? / ? 129 t10 c17 mdo6 (16) etpua13_o (8) gpio[77] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 77 o o i/o vddeh7 multiv (12),(14) ? ? / ? 135 t11 d17 mdo7 (16) etpua19_o (8) gpio[78] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 78 o o i/o vddeh7 multiv (12),(14) ? ? / ? 136 n11 b18 mdo8 (16) etpua21_o (8) gpio[79] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 79 o o i/o vddeh7 multiv (12),(14) ? ? / ? 137 p11 a19 mdo9 (16) etpua25_o (8) gpio[80] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 80 o o i/o vddeh7 multiv (12),(14) ? ? / ? 139 t7 b17 mdo10 (16) etpua27_o (8) gpio[81] nexus message data out etpu a channel (output only) gpio p a1 g 01 10 00 81 o o i/o vddeh7 multiv (12),(14) ? ? / ? 134 r10 a18 mdo11 (16) etpua29_o (8) gpio[82] nexus message data out etpu a channel (output only) gpio[82] p a1 g 01 10 00 82 o o i/o vddeh7 multiv (12),(14) ? ? / ? 124 p9 a17 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 108/1740 doc id 15177 rev 8 mseo [0] (16) nexus message start/end out p 01 224 o vddeh7 multiv (12),(14) ?mseo[0] / ? 118 c15 g21 mseo [1] (16) nexus message start/end out p 01 225 o vddeh7 multiv 12,14 ?mseo[1] / ? 117 e16 g22 rdy nexus ready output p 01 226 o vddeh7 multiv (12),(14) ????g19 jtag tck jtag test clock input p 01 ? i vddeh7 multiv (12) tck / down tck / down 128 c16 d21 tdi jtag test data input p 01 232 i vddeh7 multiv (12) tdi / up tdi / up 130 e14 d22 tdo jtag test data output p 01 228 o vddeh7 multiv (12) tdo / up tdo / up 123 f14 e21 tms jtag test mode select input p 01 ? i vddeh7 multiv (12) tms / up tms / up 131 d14 e20 jcomp jtag tap controller enable p 01 ? i vddeh7 multiv (12) jcomp / down jcomp / down 121 f16 f20 flexcan can_a_tx sci_a_tx gpio[83] flexcan a tx esci a tx gpio p a1 g 01 10 00 83 o o i/o vddeh6 slow ? / up ? / up 81 p12 y17 can_a_rx sci_a_rx gpio[84] flexcan a rx esci a rx gpio p a1 g 01 10 00 84 i i i/o vddeh6 slow ? / up ? / up 82 r12 aa18 can_b_tx dspi_c_pcs[3] sci_c_tx gpio[85] flexcan b tx dspi c peripheral chip select esci c tx gpio p a1 a2 g 001 010 100 000 85 o o o i/o vddeh6 slow ? / up ? / up 88 t12 ab18 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 109/1740 can_b_rx dspi_c_pcs[4] sci_c_rx gpio[86] flexcan b rx dspi c peripheral chip select esci c rx gpio p a1 a2 g 001 010 100 000 86 i o i i/o vddeh6 slow ? / up ? / up 89 r13 ab19 can_c_tx dspi_d_pcs[3] gpio[87] flexcan c tx dspi d peripheral chip select gpio p a1 g 01 10 00 87 o o i/o vddeh6 medium ? / up ? / up 101 k13 p19 can_c_rx dspi_d_pcs[4] gpio[88] flexcan c rx dspi d peripheral chip select gpio p a1 g 01 10 00 88 i o i/o vddeh6 slow ? / up ? / up 98 l14 r20 esci sci_a_tx emios13 (8) gpio[89] esci a tx emios channel gpio p a1 g 01 10 00 89 o o i/o vddeh6 medium ? / up ? / up 100 j14 n20 sci_a_rx emios15 (8) gpio[90] esci a rx emios channel gpio p a1 g 01 10 00 90 i o i/o vddeh6 medium ? / up ? / up 99 k14 p20 sci_b_tx dspi_d_pcs[1] gpio[91] esci b tx dspi d peripheral chip select gpio p a1 g 01 10 00 91 o o i/o vddeh6 medium ? / up ? / up 87 l13 r21 sci_b_rx dspi_d_pcs[5] gpio[92] esci b rx dspi d peripheral chip select gpio p a1 g 01 10 00 92 i o i/o vddeh6 medium ? / up ? / up 84 m13 t19 sci_c_tx gpio[244] esci c tx gpio p g 01 00 244 o i/o vddeh6 medium ? / up ? / up ? ? w18 sci_c_rx gpio[245] esci c rx gpio p g 01 00 245 i i/o vddeh6 medium ? / up ? / up ? ? y19 dspi table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 110/1740 doc id 15177 rev 8 dspi_a_sck (17) dspi_c_pcs[1] gpio[93] ? dspi c peripheral chip select gpio ? a1 g ? 10 00 93 ? o i/o vddeh7 medium ? / up ? / up ? ? l22 dspi_a_sin (17) dspi_c_pcs[2] gpio[94] ? dspi c peripheral chip select gpio ? a1 g ? 10 00 94 ? o i/o vddeh7 medium ? / up ? / up ? ? l21 dspi_a_sout (17) dspi_c_pcs[5] gpio[95] ? dspi c peripheral chip select gpio ? a1 g ? 10 00 95 ? o i/o vddeh7 medium ? / up ? / up ? ? l20 dspi_a_pcs[0] (17) dspi_d_pcs[2] gpio[96] ? dspi d peripheral chip select gpio ? a1 g ? 10 00 96 ? o i/o vddeh7 medium ? / up ? / up ? ? m20 dspi_a_pcs[1] (17) dspi_b_pcs[2] gpio[97] ? dspi b peripheral chip select gpio ? a1 g ? 10 00 97 ? o i/o vddeh7 medium ? / up ? / up ? ? m19 cs[2] dspi_d_sck gpio[98] ? spi clock pin for dspi module gpio ? a1 g ? 10 00 98 ? i/o i/o vddeh7 medium ? / up ? / up 141 j15 m21 cs[3] dspi_d_sin gpio[99] ? dspi d data input gpio ? a1 g ? 10 00 99 ? i i/o vddeh7 medium ? / up ? / up 142 h13 k19 dspi_a_pcs[4] (17) dspi_d_sout gpio[100] ? dspi d data output gpio ? a1 g ? 10 00 100 o i/o vddeh7 medium ? / up ? / up ? ? n19 dspi_a_pcs[5] (17) dspi_b_pcs[3] gpio[101] ? dspi b peripheral chip select gpio ? a1 g ? 10 00 101 o i/o vddeh7 medium ? / up ? / up ? ? n21 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 111/1740 dspi_b_sck dspi_c_pcs[1] gpio[102] spi clock pin for dspi module dspi c peripheral chip select gpio p a1 g 01 10 00 102 i/o o i/o vddeh6 medium ? / up ? / up 106 j16 k21 dspi_b_sin dspi_c_pcs[2] gpio[103] dspi b data input dspi c peripheral chip select gpio p a1 g 01 10 00 103 i o i/o vddeh6 medium ? / up ? / up 112 g15 h22 dspi_b_sout dspi_c_pcs[5] gpio[104] dspi b data output dspi c peripheral chip select gpio p a1 g 01 10 00 104 o o i/o vddeh6 medium ? / up ? / up 113 g13 j19 dspi_b_pcs[0] dspi_d_pcs[2] gpio[105] dspi b peripheral chip select dspi d peripheral chip select gpio p a1 g 01 10 00 105 i/o o i/o vddeh6 medium ? / up ? / up 111 g16 j21 dspi_b_pcs[1] dspi_d_pcs[0] gpio[106] dspi b peripheral chip select dspi d peripheral chip select gpio p a1 g 01 10 00 106 o i/o i/o vddeh6 medium ? / up ? / up 109 h16 j22 dspi_b_pcs[2] dspi_c_sout gpio[107] dspi b peripheral chip select dspi c data output gpio p a1 g 01 10 00 107 o o i/o vddeh6 medium ? / up ? / up 107 h15 k22 dspi_b_pcs[3] dspi_c_sin gpio[108] dspi b peripheral chip select dspi c data input gpio p a1 g 01 10 00 108 o i i/o vddeh6 medium ? / up ? / up 114 g14 j20 dspi_b_pcs[4] dspi_c_sck gpio[109] dspi b peripheral chip select spi clock pin for dspi module gpio p a1 g 01 10 00 109 o i/o i/o vddeh6 medium ? / up ? / up 105 h14 k20 dspi_b_pcs[5] dspi_c_pcs[0] gpio[110] dspi b peripheral chip select dspi c peripheral chip select gpio p a1 g 01 10 00 110 o i/o i/o vddeh6 medium ? / up ? / up 104 j13 l19 eqadc table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 112/1740 doc id 15177 rev 8 an0 (18) dan0+ single ended analog input positive terminal diff. input p? ? i i vdda analog i / ? an[0] / ? 172 b5 b8 an1 (18) dan0- single ended analog input negative terminal diff. input p? ? i i vdda analog i / ? an[1] / ? 171 a6 a8 an2 (18) dan1+ single ended analog input positive terminal diff. input p? ? i i vdda analog i / ? an[2] / ? 170 d6 d10 an3 (18) dan1- single ended analog input negative terminal diff. input p? ? i i vdda analog i / ? an[3] / ? 169 c7 c9 an4 (18) dan2+ single ended analog input positive terminal diff. input p? ? i i vdda analog i / ? an[4] / ? 168 b6 b9 an5 (18) dan2- single ended analog input negative terminal diff. input p? ? i i vdda analog i / ? an[5] / ? 167 a7 a9 an6 (18) dan3+ single ended analog input positive terminal diff. input p? ? i i vdda analog i / ? an[6] / ? 166 d7 d11 an7 (18) dan3- single ended analog input negative terminal diff. input p? ? i i vdda analog i / ? an[7] / ? 165 c8 c10 an8 anw single-ended analog input multiplexed analog input p01 ? i vdda analog i / ? an[8] / ? 9 b3 d6 an9 anx single-ended analog input external multiplexed analog input p01 ? i i vdda analog i / ? an[9] / ? 5 a2 d7 an10 any single-ended analog input multiplexed analog input p01 ? i vdda analog i / ? an[10] / ? ? ? d8 an11 anz single-ended analog input multiplexed analog input p01 ? i vdda analog i / ? an[11] / ? 4 a3 a5 an12 - sds ma0 etpua19_o (8) sds single-ended analog input mux address 0 etpu a channel (output only) eqadc serial data select p a1 a2 g 001 010 100 000 215 i o o i/o vddeh7 (19) medium i / ? an[12] / ? 148 a12 a16 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 113/1740 an13 - sdo ma1 etpua21_o (8) sdo single-ended analog input mux address 1 etpu a channel (output only) eqadc serial data out p a1 a2 g 001 010 100 000 216 i o o o vddeh7 19 medium i / ? an[13] / ? 147 b12 b16 an14 - sdi ma2 etpua27_o (8) sdi single-ended analog input mux address 2 etpu a channel (output only) eqadc serial data in p a1 a2 g 001 010 100 000 217 i o o i vddeh7 19 medium i / ? an[14] / ? 146 c12 c16 an15 - fck fck etpua29_o (8) single-ended analog input eqadc free running clock etpu a channel (output only) p a1 a2 001 010 100 218 i o o vddeh7 19 medium i / ? an[15] / ? 145 c13 d16 an16 single-ended analog input p ? ? i vdda analog i / ? an[16] / ? 3 c6 b7 an17 single-ended analog input p ? ? i vdda analog i / ? an[17] / ? 2 c4 c6 an18 single-ended analog input p ? ? i vdda analog i / ? an[18] / ? 1 d5 d9 an19 single-ended analog input p ? ? i vdda analog i / ? an[19] / ? ? ? b6 an20 single-ended analog input p ? ? i vdda analog i / ? an[20] / ? ? ? c7 an21 single-ended analog input p ? ? i vdda analog i / ? an[21] / ? 173 b4 c8 an22 single-ended analog input p ? ? i vdda analog i / ? an[22] / ? 161 b8 c11 an23 single-ended analog input p ? ? i vdda analog i / ? an[23] / ? 160 c9 b11 an24 single-ended analog input p ? ? i vdda analog i / ? an[24] / ? 159 d8 d12 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 114/1740 doc id 15177 rev 8 an25 single-ended analog input p ? ? i vdda analog i / ? an[25] / ? 158 b9 c12 an26 single-ended analog input p ? ? i vdda analog i / ? an[26] / ? ? ? b12 an27 single-ended analog input p ? ? i vdda analog i / ? an[27] / ? 157 a10 a12 an28 single-ended analog input p ? ? i vdda analog i / ? an[28] / ? 156 b10 a13 an29 single-ended analog input p ? ? i vdda analog i / ? an[29] / ? ? ? d13 an30 single-ended analog input p ? ? i vdda analog i / ? an[30] / ? 155 d9 c13 an31 single-ended analog input p ? ? i vdda analog i / ? an[31] / ? 154 d10 b13 an32 single-ended analog input p ? ? i vdda analog i / ? an[32] / ? 153 c10 b14 an33 single-ended analog input p ? ? i vdda analog i / ? an[33] / ? 152 c11 c14 an34 single-ended analog input p ? ? i vdda analog i / ? an[34] / ? 151 c5 d14 an35 single-ended analog input p ? ? i vdda analog i / ? an[35] / ? 150 d11 a14 an36 single-ended analog input p ? ? i vdda analog i / ? an[36] / ? 174 f4 b4 an37 single-ended analog input p ? ? i vdda analog i / ? an[37] / ? 175 e3 a4 an38 single-ended analog input p ? ? i vdda analog i / ? an[38] / ? ? ? c5 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 115/1740 an39 single-ended analog input p ? ? i vdda analog i / ? an[39] / ? 8 d2 b5 vrh voltage reference high p ? ? i vdda ? i / ? vrh 163 a8 a10 vrl voltage reference low p ? ? i vdda ? i / ? vrl 162 a9 a11 refbybc reference bypass capacitor input p? ? i vdda analog i / ? refbypc 164 b7 b10 etpu2 tcrclka irq [7] gpio[113] etpu a tcr clock external interrupt request gpio p a1 g 01 10 00 113 i i i/o vddeh4 slow ? / up ? / up ? l4 m2 etpua0 etpua12_o (8) etpua19_o (8) gpio[114] etpu a channel etpu a channel (output only) etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 114 i/o o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg 61 n3 l3 etpua1 etpua13_o (8) gpio[115] etpu a channel etpu a channel (output only) gpio p a1 g 01 10 00 115 i/o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg 60 m3 l4 etpua2 etpua14_o (8) gpio[116] etpu a channel etpu a channel (output only) gpio p a1 g 01 10 00 116 i/o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg 59 p2 k3 etpua3 etpua15_o (8) gpio[117] etpu a channel etpu a channel (output only) gpio p a1 g 01 10 00 117 i/o o i/o vddeh4 slow ? / wkpcfg gpio / wkpcfg 58 p1 l2 etpua4 etpua16_o (8) fr_b_tx gpio[118] etpu a channel etpu a channel (output only) flexray tx data channel b gpio p a1 a3 g 0001 0010 1000 0000 118 i/o o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg 56 n2 l1 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 116/1740 doc id 15177 rev 8 etpua5 etpua17_o (8) dspi_b_sck_lvd s- fr_b_tx_en gpio[119] etpu a channel etpu a channel (output only) lvds negative dspi clock flexray tx data enable for ch. b gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 119 i/o o o o i/o vddeh4 slow + lvds ? / wkpcfg ? / wkpcfg 54 m4 k4 etpua6 etpua18_o (8) dspi_b_sck_lvd s+ fr_b_rx gpio[120] etpu a channel etpu a channel (output only) lvds positive dspi clock flexray rx data channel b gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 120 i/o o o i i/o vddeh4 medium + lvds ? / wkpcfg ? / wkpcfg 53 l3 j3 etpua7 etpua19_o (8) dspi_b_sout_lv ds- etpua6_o (8) gpio[121] etpu a channel etpu a channel (output only) lvds negative dspi data out etpu a channel (output only) gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 121 i/o o o o i/o vddeh4 slow + lvds ? / wkpcfg ? / wkpcfg 52 k3 k2 etpua8 etpua20_o (8) dspi_b_sout_lv ds+ gpio[122] etpu a channel etpu a channel (output only) lvds positive dspi data out gpio p a1 a2 g 001 010 100 000 122 i/o o o i/o vddeh4 slow + lvds ? / wkpcfg ? / wkpcfg 51 n1 k1 etpua9 etpua21_o (8) rch1_b gpio[123] etpu a channel etpu a channel (output only) reaction channel 1b gpio p a1 a2 g 001 010 100 000 123 i/o o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg 50 m2 j4 etpua10 etpua22_o (8) rch1_c gpio[124] etpu a channel etpu a channel (output only) reaction channel 1c gpio p a1 a2 g 001 010 100 000 124 i/o o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 49 m1 h3 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 117/1740 etpua11 etpua23_o (8) rch4_b gpio[125] etpu a channel etpu a channel (output only) reaction channel 4b gpio p a1 a2 g 001 010 100 000 125 i/o o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 48 l2 j2 etpua12 dspi_b_pcs[1] rch4_c gpio[126] etpu a channel dspi b peripheral chip select reaction channel 4c gpio p a1 a2 g 001 010 100 000 126 i/o o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 47 l1 j1 etpua13 dspi_b_pcs[3] gpio[127] etpu a channel dspi b peripheral chip select gpio p a1 g 01 10 00 127 i/o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 46 j4 g4 etpua14 dspi_b_pcs[4] etpua9_o (8) rch0_a gpio[128] etpu a channel dspi b peripheral chip select etpu a channel (output only) reaction channel 0a gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 128 i/o o o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 42 j3 g3 etpua15 dspi_b_pcs[5] rch1_a gpio[129] etpu a channel dspi b peripheral chip select reaction channel 1a gpio p a1 a2 g 001 010 100 000 129 i/o o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 40 k2 h2 etpua16 dspi_d_pcs[1] rch2_a gpio[130] etpu a channel dspi d peripheral chip select reaction channel 2a gpio p a1 a2 g 001 010 100 000 130 i/o o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 39 k1 h1 etpua17 dspi_d_pcs[2] rch3_a gpio[131] etpu a channel dspi d peripheral chip select reaction channel 3a gpio p a1 a2 g 001 010 100 000 131 i/o o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 38 h3 f3 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 118/1740 doc id 15177 rev 8 etpua18 dspi_d_pcs[3] rch4_a gpio[132] etpu a channel dspi d peripheral chip select reaction channel 4a gpio p a1 a2 g 001 010 100 000 132 i/o o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 37 h4 f4 etpua19 dspi_d_pcs[4] rch5_a gpio[133] etpu a channel dspi d peripheral chip select reaction channel 5a gpio p a1 a2 g 001 010 100 000 133 i/o o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 36 j2 g2 etpua20 irq [8] rch0_b fr_a_tx gpio[134] etpu a channel external interrupt request reaction channel 0b flexray tx data channel a gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 134 i/o i o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 35 j1 g1 etpua21 irq [9] rch0_c fr_a_rx gpio[135] etpu a channel external interrupt request reaction channel 0c flexray rx channel a gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 135 i/o i o i i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 34 g4 e4 etpua22 irq [10] etpua17_o (8) gpio[136] etpu a channel external interrupt request etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 136 i/o i o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 32 h2 f2 etpua23 irq [11] etpua21_o (8) fr_a_tx_en gpio[137] etpu a channel external interrupt request etpu a channel (output only) flexray ch. a tx enable gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 137 i/o i o o i/o vddeh1 slow ? / wkpcfg ? / wkpcfg 30 h1 f1 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 119/1740 etpua24 irq [12] dspi_c_sck_lvd s- gpio[138] etpu a channel external interrupt request lvds negative dspi clock gpio p a1 a2 g 001 010 100 000 138 i/o i o i/o vddeh1 slow + lvds ? / wkpcfg ? / wkpcfg 28 g1 e1 etpua25 irq [13] dspi_c_sck_lvd s+ gpio[139] etpu a channel external interrupt request lvds positive dspi clock gpio p a1 a2 g 001 010 100 000 139 i/o i o i/o vddeh1 medium + lvds ? / wkpcfg ? / wkpcfg 27 g3 e3 etpua26 irq [14] dspi_c_sout_lv ds- gpio[140] etpu a channel external interrupt request lvds negative dspi data out gpio p a1 a2 g 001 010 100 000 140 i/o i o i/o vddeh1 slow + lvds ? / wkpcfg ? / wkpcfg 26 f3 d3 etpua27 irq [15] dspi_c_sout_lv ds+ dspi_b_sout gpio[141] etpu a channel external interrupt request lvds positive dspi data out dspi data out gpio p a1 a2 a3 g 0001 0010 0100 1000 0000 141 i/o i o o i/o vddeh1 slow + lvds ? / wkpcfg ? / wkpcfg 25 g2 e2 etpua28 dspi_c_pcs[1] rch5_b gpio[142] etpu a channel dspi c peripheral chip select reaction channel 5b gpio p a1 a2 g 001 010 100 000 142 i/o o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 24 f1 d1 etpua29 dspi_c_pcs[2] rch5_c gpio[143] etpu a channel dspi c peripheral chip select reaction channel 5c gpio p a1 a2 g 001 010 100 000 143 i/o o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 23 f2 d2 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 120/1740 doc id 15177 rev 8 etpua30 dspi_c_pcs[3] etpua11_o (8) gpio[144] etpu a channel dspi c peripheral chip select etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 144 i/o o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 22 e1 c1 etpua31 dspi_c_pcs[4] etpua13_o (8) gpio[145] etpu a channel dspi c peripheral chip select etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 145 i/o o o i/o vddeh1 medium ? / wkpcfg ? / wkpcfg 21 e2 c2 emios emios0 etpua0_o (8) etpua25_o (8) gpio[179] emios channel etpu a channel (output only) etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 179 i/o o o i/o vddeh4 slow ? / up ? / up 63 t4 ab10 emios1 etpua1_o (8) gpio[180] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 180 i/o o i/o vddeh4 slow ? / up ? / up 64 t5 ab11 emios2 etpua2_o (8) rch2_b gpio[181] emios channel etpu a channel (output only) reaction channel 2b gpio p a1 a2 g 001 010 100 000 181 i/o o o i/o vddeh4 slow ? / up ? / up 65 n7 w12 emios3 etpua3_o (8) gpio[182] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 182 i/o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg 66 r6 aa11 emios4 etpua4_o (8) rch2_c gpio[183] emios channel etpu a channel (output only) reaction channel 2c gpio p a1 a2 g 001 010 100 000 183 i/o o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg 67 r5 ab12 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 121/1740 emios5 etpua5_o (8) gpio[184] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 184 i/o o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg ? ? aa12 emios6 etpua6_o (8) gpio[185] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 185 i/o o i/o vddeh4 slow ? / down ? / down 68 p7 y12 emios7 etpua7_o (8) gpio[186] emios channel etpu a channel (output only) gpio p a1 g 01 10 00 186 i/o o i/o vddeh4 slow ? / down ? / down 69 ? ab13 emios8 etpua8_o (8) sci_b_tx gpio[187] emios channel etpu a channel (output only) esci b tx gpio p a1 a2 g 001 010 100 000 187 i/o o o i/o vddeh4 slow ? / up ? / up 70 p8 w13 emios9 etpua9_o (8) sci_b_rx gpio[188] emios channel etpu a channel (output only) esci b rx gpio p a1 a2 g 001 010 100 000 188 i/o o i i/o vddeh4 slow ? / up ? / up 71 r7 aa13 emios10 dspi_d_pcs[3] rch3_b gpio[189] emios channel dspi d peripheral chip select reaction channel 3b gpio p a1 a2 g 001 010 100 000 189 i/o o o i/o vddeh4 medium ? / wkpcfg ? / wkpcfg 73 n8 y13 emios11 dspi_d_pcs[4] rch3_c gpio[190] emios channel dspi d peripheral chip select reaction channel 3c gpio p a1 a2 g 001 010 100 000 190 i/o o o i/o vddeh4 medium ? / wkpcfg ? / wkpcfg 75 r8 ab14 emios12 dspi_c_sout etpua27_o (8) gpio[191] emios channel dspi c data output etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 191 i/o o o i/o vddeh4 medium ? / wkpcfg ? / wkpcfg 76 n10 w15 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 122/1740 doc id 15177 rev 8 emios13 dspi_d_sout gpio[192] emios channel dspi d data output gpio p a1 g 01 10 00 192 i/o o i/o vddeh4 medium ? / wkpcfg ? / wkpcfg 77 t8 aa14 emios14 irq [0] etpua29_o (8) gpio[193] emios channel external interrupt request etpu a channel (output only) gpio p a1 a2 g 001 010 100 000 193 i/o i o i/o vddeh4 slow ? / down ? / down 78 r9 ab15 emios15 irq [1] gpio[194] emios channel external interrupt request gpio p a1 g 01 10 00 194 i/o i i/o vddeh4 slow ? / down ? / down 79 t9 y14 emios16 gpio[195] emios channel gpio p g 01 00 195 i/o i/o vddeh4 slow ? / up ? / up ? ? aa15 emios17 gpio[196] emios channel gpio p g 01 00 196 i/o i/o vddeh4 slow ? / up ? / up ? ? y15 emios18 gpio[197] emios channel gpio p g 01 00 197 i/o i/o vddeh4 slow ? / up ? / up ? ? ab16 emios19 gpio[198] emios channel gpio p g 01 00 198 i/o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg ? ? aa16 emios20 gpio[199] emios channel gpio p g 01 00 199 i/o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg ? ? ab17 emios21 gpio[200] emios channel gpio p g 01 00 200 i/o i/o vddeh4 slow ? / wkpcfg ? / wkpcfg ??w16 emios22 gpio[201] emios channel gpio p g 01 00 201 i/o i/o vddeh4 slow ? / down ? / down ? ? y16 emios23 gpio[202] emios channel gpio p g 01 00 202 i/o i/o vddeh4 slow ? / down ? / down 80 r11 aa17 clock synthesizer table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 123/1740 xtal crystal oscillator output p 01 ? o vddeh6 analog ? ? 93 p16 v22 extal extclk crystal oscillator input external clock input p a 01 10 ?i vddeh6 analog ? ? 92 n16 u22 clkout system clock output p 01 229 o vdde5 fast ? clkout ? ? aa20 engclk engineering clock output p 01 214 o vdde5 fast ? engclk ? t14 ab21 power / ground vddreg voltage regulator supply ? ? i 5 v i / ? vddreg 10 k16 m22 vrcctl voltage regulator control output ? ? o ? o / ? vrcctl 11 n14 v20 vrc33 (20) internal regulator output ? ? o 3.3 v i/o / ? vrc33 13 a15, d1, n6, n12 a21, b1, p4, w7, y22 input for external 3.3 v supply ? ? 3.3 v vdda eqadc high reference voltage ? ? i 5 v i / ? vdda 6 ? ? vssa eqadc ground/low reference voltage ? ? i ? i / ? vssa 7 ? ? vdda0 (21) eqadc high reference voltage ? ? i 5 v i / ? vdda0 ? b11 a6 vssa0 (22) eqadc ground/low reference voltage ? ? i ? i / ? vssa0 ? a11 a7 vdda1 (21) eqadc high reference voltage ? ? i 5 v i / ? vdda1 ? a4 c15 vssa1 (22) eqadc ground/low reference voltage ? ? i ? i / ? vssa1 ? a5 a15, b15 vddpll fmpll supply voltage ? ? i 1.2 i / ? vddpll 91 r16 w22 vstby power supply for standby ram ? ? i 0.9 v - 6 v i / ? vstby 12 c1 a3 table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 124/1740 doc id 15177 rev 8 vdd core supply for input or decoupling ? ? i 1.2 v i / ? vdd 33, 45, 62, 103, 132, 149, 176 b1, b16, c2, d3, e4, n5, p4, p13, r3, r14, t2, t15 a2, a20, b3, c4, c22, d5, v19, w5, w20, y4, y21, aa3, aa22, ab2 vdde12 external supply input for calibration bus interfaces ? ? i 1.8 v - 3.3 v i / ? vdde12 ? ? ? vdde2 (23) external supply input for ebi interfaces ? ? i 1.8 v - 3.3 v i / ? vdde2 (24) ?? m9, m10, n11, p11, w6, w8, y5, aa4, aa6, aa10, ab3 vdde5 external supply input for engclk, clkout and ebi signals data[0:15] ? ? i 1.8 v - 3.3 v i / ? vdde5 ? t13 w17, y18, aa19, ab20 vdde-eh external supply for ebi interfaces ? ? i 3.0 v - 5 v i / ? vdde-eh ? ? r3, w2 vddeh1a (25) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh1a (25) 31 ? ? vddeh1b (25) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh1b (25) 41 ? ? vddeh1ab (25) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh1ab (25) ?k4 h4 vddeh4 (26) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh4 (26) ?? ? vddeh4a (26) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh4a (26) 55 ? ? vddeh4b (26) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh4b (26) 74 ? ? table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 125/1740 vddeh4ab (26) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh4ab (26) ?n9 w14 vddeh6 (27) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh6 (27) ?? ? vddeh6a (27) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh6a (27) 95 ? ? vddeh6b (27) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh6b (27) 110 ? ? vddeh6ab (27) i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh6ab (27) ? f13 h19, u19 vddeh7 i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh7 ? d12 d15 vddeh7a i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh7a 125 ? ? table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 signal description RM0029 126/1740 doc id 15177 rev 8 vddeh7b i/o supply input ? ? i 3.3 v - 5.0 v i / ? vddeh7b 138 ? ? vss ground ? ? i ? i / ? vss 15, 29, 43, 57, 72, 90, 94, 96, 108, 115, 127, 133, 140 a1, a16, b2, b15, c3, c14, d4, d13, g7, g8, g9, g10, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10, m16, n4, n13, p3, p14, r2, r15, t1, t16 a1, a22, b2, b21, c3, c20, d4, d19, j9, j10, j11, j12, j13, k9, k10, k11, k12, k13, k14, l9, l10, l11, l12, l13, l14, m11, m12, m13, m14, n9, n10, n12, n13, n14, p9, p10, p12, p13, p14, t21, t22, w4,w19, y3, y20, aa2, aa21, ab1, ab22 1. for each pin in the table, each line in the function column is a separate function of the pin. for all i/o pins the selection of primary pin function or secondary function or gpio is done in the siu except where explicitly noted. see the signal details table for a description of each signal. 2. the p/a/g column indicates the position a signal occupies in t he muxing order for a pin?primary, alternate 1, alternate 2, al ternate 3, or gpio. signals are selected by setting the pa field value in the appropriate pcr register in the siu module. the pa field values are as follows: p - 0b0001, a 1 - 0b0010, a2 - 0b0100, a3 - 0b1000, or g - 0b0000. depending on the register, the pa field size can vary in length. for pa fields having fewer than four bits, remove the appropriate number of leading zeroes from these values. 3. the pad configuration register (pcr) pa field is used by software to select pin function. 4. values in the pcr no. column refer to registers in the system integration unit (siu). the actual register name is ?siu_pcr? s uffixed by the pcr number. for example, pcr[190] refers to the siu register named siu_pcr190. 5. the vdde and vddeh supply inputs are broken into segments. each segment of slow i/o pins (vdde h) may have a separate supply i n the 3.3 v to 5.0 v range (- 10%/+5%). each segment of fast i/o (vdde) may have a separate supply in the 1.8 v to 3.3 v range (+/- 10%). 6. see table 4 for details on pad types. table 3. spc564a74xx, spc564a80xx signal properties (continued) name function (1) p a g (2) pcr pa field (3) pcr (4) i/o type voltage (5) / pad type (6) status (7) package pin # during reset after reset 176 208 324 RM0029 signal description doc id 15177 rev 8 127/1740 7. the status during reset pin is sampled after the internal po r is negated. prior to exiting por, the signal has a high impedan ce. terminology is o - output, i - input, up - weak pull up enabled, down - weak pull down enabled, low - output driven low, high - output driven high. a dash for the functio n in this column denotes that both the input and output buffer are turned off. the signal name to the left or right of the slash indicates the pin is enabled. 8. output only. 9. when used as etrig, this pin must be configured as an input. for gpio it can be configured either as an input or output. 10. maximum frequency is 50 khz. 11. the siu_pcr219 register is unusual in that it contro ls pads for two separate device pins: gpio[219] and mcko. section , pad configuration register 219 (siu_pcr219) ?. 12. multivoltage pads are automatically confi gured in low swing mode when a jtag or nexus function is selected, otherwise they a re high swing. 13. on lqfp176 and lbga208 packages, th is pin is tied low internally. 14. nexus multivoltage pads default to 5 v operation until the nexus module is enabled. 15. evto should be clamped to 3.3 v to prevent possible dam age to external tools that only support 3.3 v. 16. do not connect pin directly to a power supply or ground. 17. this signal name is used to support legacy naming. 18. during and just after por negates, internal pull resistors can be ena bled, resulting in as much as 4 ma of current draw. the pull resistors are disabled when the system clock propagates through the device. 19. for pins an12-an15, if the analog features are used the vddeh7 input pins should be tied to v dda because that segment must m eet the vdda specification to support analog input function. 20. do not use vrc33 to dr ive external circuits. 21. vdda0 and vdda1 are short ed together internally in bga packages. in the qfp package the two pads are double bonded on one pi n called vdda. 22. vssa0 and vssa1 are shorted together internally in bga packages. in the qfp package the two pads are double bonded on one pi n called vssa. 23. vdde2 and vdde3 are shorted toge ther in all production packages. 24. vdde2 and vdde3 are shorted toge ther in all production packages. 25. vddeh1a, vddeh1b, and vddeh1ab are short ed together in all production packages. the s eparation of the signal names is presen t to support legacy naming, however they should be considered as the same signal in this document. 26. vddeh4, vddeh4a, vddeh4b, and vddeh4ab ar e shorted together in all production package s. the separation of the signal names i s present to support legacy naming, however they should be consider ed as the same signal in this document. 27. vddeh6, vddeh6a, vddeh6b, and vddeh6ab ar e shorted together in all production package s. the separation of the signal names i s present to support legacy naming, however they should be consider ed as the same signal in this document. signal description RM0029 128/1740 doc id 15177 rev 8 table 4. pad types pad type i/o voltage range slow 3.0v - 5.5 v medium 3.0 v - 5.5 v fast 3.0 v - 3.6 v multiv (1),(2) 1. multivoltage pads are automatically configured in low swing mode when a jtag or nexus function is selected, otherwise they are high swing. 2. vddeh7 supply cannot be below 4.5 v when in low-swing mode. 3.0 v - 5.5 v (high swing mode) 3.0 v - 3.6 v (low swing mode) analog 0.0 - 5.5 v lvds ? RM0029 signal description doc id 15177 rev 8 129/1740 3.2 signal details table 5. signal details signal module or function description clkout clock generation spc564a74xx, spc564a80xx clock output for the external/calibration bus interface engclk clock generation clock for external asic devices extal clock generation input pin for an external crystal oscillator or an external clock source based on the value driven on the pllref pin at reset. pllref clock generation reset/configuration pllref is used to select whether the oscillator operates in xtal mode or external reference mode from reset. pllref=0 selects external reference mode. on the 324bga package, pllref is bonded to the ball used for pllcfg[0] for compatibility with previous devices . for the 176-pin qfp and 208-ball bga packages: 0: external reference clock is selected. 1: xtal oscillator mode is selected for the 324 ball bga package: if rstcfg is 0: 0: external reference clock is selected. 1: xtal oscillator mode is selected. if rstcfg is 1, xtal oscillator mode is selected. xtal clock generation crystal oscillator input dspi_b_sck_lvds- dspi_b_sck_lvds+ dspi lvds pair used for dspi_b tsb mode transmission dspi_b_sout_lvds- dspi_b_sout_lvds+ dspi lvds pair used for dspi_b tsb mode transmission dspi_c_sck_lvds- dspi_c_sck_lvds+ dspi lvds pair used for dspi_c tsb mode transmission dspi_c_sout_lvds- dspi_c_sout_lvds+ dspi lvds pair used for dspi_c tsb mode transmission pcs_b[0] pcs_c[0] pcs_d[0] dspi_b - dspi_d peripheral chip select when device is in master mode?slave select when used in slave mode pcs_b[1:5] pcs_c[1:5] pcs_d[1:5] dspi_b - dspi_d peripheral chip select when device is in master mode?not used in slave mode sck_b sck_c sck_d dspi_b - dspi_d dspi clock?output when device is in master mode; input when in slave mode signal description RM0029 130/1740 doc id 15177 rev 8 sin_b sin_c sin_d dspi_b - dspi_d dspi data in sout_b sout_c sout_d dspi_b - dspi_d dspi data out addr[10:31] ebi the addr[10:31] signals specify the physical address of the bus transaction. the 26 address lines correspond to bits 3-31 of the ebi?s 32-bit internal address bus. addr[15:31] can be used as address and data signals when configured appropriately for a multiplexed external bus. this allows 32-bit data operations, or 16-bit data operations without using data[0:15] signals. ale ebi the address latch enable (ale) signal is used to demultiplex the address from the data bus. it is asserted while the least significant 16 bits of the address are present in the multiplexed address/data bus. bdip ebi bdip is asserted to indicate that the master is requesting another data beat following the current one. cs [0:3] ebi cs x is asserted by the master to indicate that this transaction is targeted for a particular memory bank on the primary external bus. data[0:31] ebi the data[0:31] signals contain the data to be transferred for the current transaction. oe ebi oe is used to indicate when an external memory is permitted to drive back read data. external memories must have their data output buffers off when oe is negated. oe is only asserted for chip-select accesses. rd_wr ebi rd_wr indicates whether the current transaction is a read access or a write access. ta ebi ta is asserted to indicate that the slave has received the data (and completed the access) for a write cycle, or returned data for a read cycle. if the transaction is a burst read, ta is asserted for each one of the transaction beats. for write transactions, ta is only asserted once at access completion, even if more than one write data beat is transferred. ts ebi the transfer start signal (ts ) is asserted by the spc564a74xx, spc564a80xx to indicate the start of a transfer. we [2:3] ebi write enables are used to enable program operations to a particular memory. we [2:3] are only asserted for write accesses table 5. signal details (continued) signal module or function description RM0029 signal description doc id 15177 rev 8 131/1740 we [0:3]/be [0:3] ebi write enables are used to enable program operations to a particular memory. these signals can also be used as byte enables for read and write operation by setting the webs bit in the appropriate ebi base register (ebi_br n ). we [0:3] are only asserted for write accesses. be [0:3] are asserted for both read and write accesses emios[0:23] emios emios i/o channels an[0:39] eqadc single-ended analog inputs for analog-to-digital converter fck eqadc eqadc free running clock for eqadc ssi. ma[0:2] eqadc these three control bits are output to enable the selection for an external analog mux for expansion channels. refbypc eqadc bypass capacitor input sdi eqadc serial data in sdo eqadc serial data out sds eqadc serial data select vrh eqadc voltage reference high input vrl eqadc voltage reference low input sci_a_rx sci_b_rx sci_c_rx esci_a - esci_c esci receive sci_a_tx sci_b_tx sci_c_tx esci_a - esci_c esci transmit etpu_a[0:31] etpu etpu i/o channel rch0_[a:c] rch1_[a:c] rch2_[a:c] rch3_[a:c] rch4_[a:c] rch5_[a:c] etpu2 reaction module etpu2 reaction channels. used to control external actuators, e.g., solenoid control for direct injection systems and valve control in automatic transmissions tcrclka etpu2 input clock for tcr time base can_a_tx can_b_tx can_c_tx flexcan_a - flexcan_c flexcan transmit can_a_rx can_b_rx can_c_rx flexcan_a - flexcan_c flexcan receive fr_a_rx fr_b_rx flexray flexray receive (channels a, b) table 5. signal details (continued) signal module or function description signal description RM0029 132/1740 doc id 15177 rev 8 fr_a_tx_en fr_b_tx_en flexray flexray transmit enable (channels a, b) fr_a_tx fr_b_tx flexray flexray transmit (channels a, b) jcomp jtag enables the jtag tap controller. tck jtag clock input for the on-chip test logic. tdi jtag serial test instruction and data input for the on-chip test logic. tdo jtag serial test data output for the on-chip test logic. tms jtag controls test mode operations for the on-chip test logic. evti nexus evti is an input that is read on the negation of reset to enable or disable the nexus debug port. after reset, the evti pin is used to initiate program synchronization messages or generate a breakpoint. evto nexus output that provides timing to a development tool for a single watchpoint or breakpoint occurrence. mcko nexus mcko is a free running clock output to the development tools which is used for timing of the mdo and mseo signals. mdo[0:11] (1) nexus trace message output to development tools. this pin also indicates the status of the crystal oscillator clock following a power-on reset, when mdo[0] is driven high until the crystal oscillator clock achieves stability and is then negated. mseo [0:1] (1) nexus output pin?indicates the start or end of the variable length message on the mdo pins rdy nexus nexus ready output (rdy ) is an output that indicates to the development tools the data is ready to be read from or written to the nexus read/write access registers. table 5. signal details (continued) signal module or function description RM0029 signal description doc id 15177 rev 8 133/1740 bootcfg[0:1] siu - configuration two bootcfg signals are implemented in spc564a74xx, spc564a80xx mcus. the bam program uses the bootcfg0 bit to determine where to read the reset configuration word, and whether to initiate a flexcan or esci boot. the bootcfg1 pin is sampled during the assertion of the rstout signal, and the value is used to update the rsr and the bam boot mode see section 4.7.1: reset configuration half word (rchw) for details on the rchw. table 387 in section 21.5.2: bam program operation , defines the boot modes specified by the bootcfg1 pin. the following values are for bootcfg[0:1}: 00:boot from internal flash memory 01:flexcan/esci boot 10:boot from external memory using ebi 11:reserved note: for the 176-pin qfp and 208-ball bga packages bootcfg[0] is always 0 since the ebi interface is not available. wkpcfg siu - configuration the wkpcfg pin is applied at the assertion of the internal reset signal (assertion of rstout ), and is sampled 4 clock cycles before the negation of the rstout pin. the value is used to configure whether the etpu and emios pins are connected to internal weak pull up or weak pull down devices after reset. the value latched on the wkpcfg pin at reset is stored in the reset status register (rsr), and is updated for all reset sources except the debug port reset and software external reset. 0:weak pulldown applied to etpu and emios pins at reset 1:weak pullup applied to etpu and emios pins at reset. etrig[2:3] siu - eqadc triggers external signal etrigx triggers eqadc cfifox gpio[206] etrig0 (input) siu - eqadc triggers external signal etrigx triggers eqadc cfifox gpio[207] etrig1 (input) siu - eqadc triggers external signal etrigx triggers eqadc cfifox table 5. signal details (continued) signal module or function description signal description RM0029 134/1740 doc id 15177 rev 8 irq [0:5] irq [7:15] siu - external interrupts the irq [0:15] pins connect to the siu irq inputs. imux select register 1 is used to select the irq [0:15] pins as inputs to the irqs. see section 16.6.19: external irq input select register (siu_eiisr) for more detail. nmi siu - external interrupts non-maskable interrupt gpio[0:3] gpio[8:43] gpio[62:65] gpio[68:70] gpio[75:145] gpio[179:204] gpio[208:213] gpio[219] gpio[244:245] siu - gpio configurable general purpose i/o pins. each gpio input and output is separately controlled by an 8-bit input (gpdi) or output (gpdo) register. additionally, each gpio pins is configured using a dedicated siu_pcr register. the gpio pins are generally multiplexed with other i/o pin functions. see the following sections for more information: ? section 16.6.15: pad configuration registers (siu_pcr) ? section 16.6.16: gpio pin data output registers (siu_gpdo0_3 ? siu_gpdo412_413) ? section 16.6.17: gpio pin data input registers (siu_gpdi0_3 ? siu_gpdi_232) reset siu - reset the reset pin is an active low input. the reset pin is asserted by an external device during a power-on or external reset. the internal reset signal asserts only if the reset pin asserts for 10 clock cycles. assertion of the reset pin while the device is in reset causes the reset cycle to start over. the reset pin has a glitch detector which detects spikes greater than two clock cycles in duration that fall below the switch point of the input buffer logic of the vddeh input pins. the switch point lies between the maximum vil and minimum vih specifications for the vddeh input pins. table 5. signal details (continued) signal module or function description RM0029 signal description doc id 15177 rev 8 135/1740 rstcfg siu - reset used to enable or disable the pllref and the bootcfg[0:1] configuration signals. 0:get configuration information from bootcfg[0:1] and pllref 1:use default configuration of booting from internal flash with crystal clock source for the 176-pin qfp and 208-ball bga packages rstcfg is always 0, so pllref and bootcfg signals are used. rstout siu - reset the rstout pin is an active low output that uses a push/pull configuration. the rstout pin is driven to the low state by the mcu for all internal and external reset sources. there is a delay between initiation of the reset and the assertion of the rstout pin. see section 4.3.2: rstout for details. 1. do not connect pin directly to a power supply or ground. table 5. signal details (continued) signal module or function description table 6. power/ground segmentation power segment voltage i/o pins powered by segment vdde2 1.8 v - 3.3 v cs0, cs1, cs2, cs3,rd_wr, bdip, we0, we1, oe, ts, ta vdde3 1.8 v - 3.3 v addr12, addr13, addr14, addr15 vdde5 1.8 v - 3.3 v data0, data1, data2, data3, data4, data5, data6, data7, data8, data9, data10, data11, data12, data13, data14, data15, clkout, engclk vdde12 1.8 v - 3.3 v cal_cs0, cal_cs2, cal_cs3 cal_addr12, cal_addr13, cal_addr14, cal_addr15, cal_addr16, cal_addr17, cal_addr18, cal_addr19, cal_addr20, cal_addr21, cal_addr22, cal_addr23, cal_addr24, cal_addr25, cal_addr26, cal_addr27, cal_addr28, cal_addr29, cal_addr30, cal_data0, cal_data1, cal_data2, cal_data3, cal_data4, cal_data5, cal_data6, cal_data7, cal_data8, cal_data9, cal_data10, cal_data11, cal_data12, cal_data13, cal_data14, cal_data15, cal_rd_wr, cal_we0, cal_we1, cal_oe, cal_ts vdde-eh 3.0 v - 5 v addr16, addr17, addr18, addr19, addr20, addr21, addr22, addr23, addr24, addr25, addr26, addr27, addr28, addr29, addr30, addr31 vddeh1 3.3 v - 5.0 v etpua10, etpua11, etpua12, etpua13, etpua14, etpua15, etpua16, etpua17, etpua18, etpua19, etpua20, etpua21, etpua22, etpua23, etpua24, etpua25, etpua26, etpua27, etpua28, etpua29, etpua30, etpua31 signal description RM0029 136/1740 doc id 15177 rev 8 vddeh4 3.3 v - 5.0 v emios0, emios1, emios2, emios3, emios4, emios5, emios6, emios7, emios8, em ios9, emios10, emios11, emios12, emios13, emios14, emios15, emios16, emios17, emios18, emios19, emios20, emios21, emios22, emios23, tcrclka, etpua0, etpua1, etpua2, etpua3, etpua4, etpua5, etpua6, etpua7, etpua8, etpua9, etpua0 vddeh6 3.3 v - 5.0 v reset , rstout , pllref, pllcfg1, rstcfg, bootcfg0, bootcfg1, wkpcfg, can_a_tx, can_a_rx, can_b_tx, can_b_rx, can_c_tx, can_c_rx, sci_a_tx, sci_a_rx, sci_b_tx, sci_c_rx, dspi_b_sck, dspi_b_sin, dspi_b_sout, dspi_b_pcs[0], dspi_b_pcs[1], dspi_b_pcs[2], dspi_b_pcs[3], dspi_b_pcs[4], dspi_b_pcs[5], sci_b_rx, sci_c_tx, extal, xtal vddeh7 3.3 v - 5.0 v emios14, emios 15, gpio98, gpio99, gpio203, gpio204, gpio206, gpio207, gpio219, evti, evto, mdo4, mdo5, mdo6, mdo7, mdo8, mdo9, mdo10, mdo11, mseo0, mseo1, rdy, tck, tdi, tdo, tms, jcomp, dspi_a_sck, dspi_a_sin, dspi_a_sout, dspi_a_pcs[0], dspi_a_pcs[1], dspi_a_pcs[4], dspi_a_pcs[5], an12-sds, an13-sdo, an14-sdi, an15- fck vdda 5 v an0, an1, an2, an3, an4, an5, an6, an7, an8, an9, an10, an11, an16, an17, an18 , an19, an20, an21, an22, an23, an24, an25, an26, an27, an28, an29, an30, an31, an32, an33, an34, an35, an36, an37, an38, an39, vrh, vrl, refbybc vrc33 (1) 3.3 v mcko, mdo0, mdo1, mdo2, mdo3 other power segments vddreg 5 v ? vrcctl ? ? vddpll 1.2 v ? vstby 0.95?1.2 v (unregulated mode) ? 2.0?5.5 v (regulated mode) ? vss ? ? 1. do not use vrc33 to dr ive external circuits. table 6. power/ground segmentation power segment voltage i/o pins powered by segment RM0029 resets doc id 15177 rev 8 137/1740 4 resets note: throughout this text the phrase ?reset configuration pins? is used to refer to wkpcfg, bootcfg, and pllref pins. not all packages have bootcfg[0]. in this case, bootcfg[0] is sampled as 0b0. 4.1 reset sources this device supports the following system reset sources: power-on reset external reset loss of lock reset loss of clock reset watchdog timer/debug reset jtag reset software system reset software external reset (resets external resources but not the device) all reset sources are processed by the reset controller, which monitors the reset input sources, and upon detection of a reset event, resets internal logic and controls the assertion of the rstout pin. the software external reset only causes the rstout pin to be asserted for a number of clock cycles determined by the pll mode (refer to section 4.3.2, rstout ), and does not reset the device. for all reset sources, the bootcfg[0:1] and pllref signals are used to determine the boot mode and configuration of the fmpll, respectively. ta ble 7 shows the options for bootcfg[0:1] and table 8 for pllcfg[0:2]. refer to 17, frequency-modulated phase locked loop (fmpll) , for information on the fmpll during reset. table 7. bootcfg options bootcfg[0] boot cfg[1] meaning 0 0 boot from internal flash memory 0 1 flexcan / esci boot 1 0 boot from external memory (no arbitration) (1) 1. this mode is only available in packages that have an ebi. 11reserved table 8. pllref options pllref clock mode 0 normal mode with external reference 1 normal mode with crystal reference resets RM0029 138/1740 doc id 15177 rev 8 the reset status register (siu_rsr) gives the source, or sources, of the last reset and indicates whether a glitch has occurred on the reset pin. the siu_rsr is updated for all reset sources except jtag reset. all reset sources initiate execution of the boot assist module (bam) program with the exception of the software external reset. the reset configuration half word (rchw) det ermines the mcu configuration after reset. the rchw is stored in internal flash, or a default configuration is used. during reset, the rchw is read from internal flash memory. the bootcfg[0:1] (c) pins are defined in chapter 16: system integration unit (siu). the bam program reads the value of the bootcfg[0:1] pins from field siu_rsr[bootcfg], then reads the rchw from the specified location, and then uses the rchw va lue to determine and execute the specified boot procedure. note: the reset controller latches the value on the bootcfg input to the siu four clock cycles prior to the negation of rstout . 4.2 reset vector the reset vector for this device is 0xffff_fffc. this is a fixed location in the bam. the bam program executes after every internal reset. the bam program determines where to branch after its execution completes based on the value on the bootcfg[0:1] pins. see the bam chapter?s functional description for details on the bam program operation and branch location to application software. 4.3 reset pins 4.3.1 reset the reset pin is an active low input. the reset pin must be asserted by an external device during a power-on or whenever an external reset is required. the internal reset signal asserts only if the reset pin asserts for 10 clock cycles. assertion of the reset pin while the reset state machine is already processing a reset causes the reset cycle to start over. the reset pin has a glitch detector which detects spikes greater than two clocks in duration that fall below the switch point of the input buffer logic of the vddeh input pins. the switch point lies between the maximum vil and minimum vih specifications for the vddeh input pins. figure 2 and figure 3 show logic flows of the reset state machine on assertion of reset . 4.3.2 rstout the rstout pin is an active low output that uses a push/pull configuration. the rstout pin is driven to the low state by the mcu for all internal and external reset sources. depending on the pll configuration, external reference or crystal mode, the rstout pin is asserted after a delay defined in table 9 , plus four cycles for sampling of the configuration pins. c. bootcfg[0] is not available on all packages. RM0029 resets doc id 15177 rev 8 139/1740 the rstout pin can also be asserted by a write to the ser bit of the system reset control register (siu_srcr). asserting siu_srcr[ser], the rstout duration will follow the value specified in ta ble 9 . 4.4 fmpll lock gating signal the fmpll loss of lock reset request is connected to both a reset request and a reset gating signal in the siu. the fmpll asserts the loss of lock reset request until the pll has achieved lock. 4.5 reset source descriptions for the following reset source descriptions refer to the reset flow diagrams in figure 2 and figure 3 . figure 2 shows the reset flow for assertion of the reset pin. figure 3 shows the internal processing of reset for all reset sources. table 9. timing for reset sources reset source description number of clocks crystal reference external reference por power on reset 2400 16000 er external reset (reset pin) 2900 16500 llr loss of lock reset 3400 17000 wtr watchdog timer (core) or debug reset 3900 17500 swtr system software watchdog reset 4900 18500 lcr loss of clock reset 5400 19000 ssr siu software external reset 5900 19500 ser siu software system reset 6400 20000 resets RM0029 140/1740 doc id 15177 rev 8 figure 2. external reset flow diagram asserted? f t reset f t asserted? reset asserted? reset a wait 2 clock cycles set latch, wait 8 clock set rgf bit to entry point in internal reset flow f t cycles RM0029 resets doc id 15177 rev 8 141/1740 figure 3. internal reset flow diagram f t rstout assert negated? software asserted? external reset update reset status register asserted? software system reset f t f t clock cycles clock cycles f t latch wkpcfg pin latch pllref and bootcfg[0:1] reset request rstout negate internal resets and wait cnt 1 wait 4 clock cycles wait cnt 1 apply wkpcfg pin rstout assert internal resets and a entry point from values asserted? internal reset f t crystal stable? external reset flow and por notes: 1. the clock count cnt depends on the reset source and type of clock reference. please refer to table 9 . resets RM0029 142/1740 doc id 15177 rev 8 4.5.1 power-on reset (por) the internal power-on reset signal is asserted when either the supply voltages, nominally 3.3 v or 1.2 v or the reset supply (vddeh6a) fall below defined values. see the device data sheet for the threshold specifications of these voltages. the output signals from the power-on reset circuits are active low signals. all power-on reset output signals are combined into one por signal at the 1.2 v level and input to the reset controller. although assertion of the power-on reset signal causes reset, the reset pin must be asserted during a power-on reset to guarantee proper operation of the mcu. the pllref pin determines the source of reference clock, either crystal or external, at the negation of rstout . during the assertion of rstout , the system clock will switch to the input specified by the pllref pin. the value on the pllref pin must be kept constant during reset to avoid transients in the system clock. see section 17.2.3, modes of operation , for more details. the signal on the wkpcfg pin determines whether weak pull up or pull down devices are enabled after reset on the etpu and emios pins. the wkpcfg pin is applied on the assertion of the internal reset signal (assertion of rstout ). see section 4.7.3, reset weak pull up/down configuration , for more information. once a power-on-reset is triggered, if the clock reference is the crystal (pllref = 1), then the clock to the whole chip, including the reset state machine, is kept frozen until the clock quality monitor detects that the crystal oscillator has already stabilized. if the clock reference is external (pllref = 0) the clock is released to the system immediately. when the clock is stable and released to the chip, the reset controller counts a predetermined number of clock cycles (refer to section 4.3.2, rstout ) before negating the rstout pin. the wkpcfg and bootcfg[0:1] pins are sampled four clock cycles before the negation of rstout , and the associated bits/fields are updated in the siu_rsr. in addition, siu_rsr[pors] and siu_rsr[ers] are set, and all other reset status bits are cleared in the siu_rsr. 4.5.2 external reset when the reset controller detects assertion of the reset pin, the internal reset signal and rstout pin are asserted. the values on the wkpcfg pin and pllcfg pins are applied at the assertion of the internal reset signal (assertion of rstout ). once the reset pin is negated and the fmpll loss of lock reset request signal is negated, the reset controller waits for a predetermined number of clock cycles (refer to section 4.3.2, rstout ). once the clock count finishes, the reset configuration pins are latched. the reset controller then waits four clock cycles before negating rstout , and the associated bits/fields are updated in the siu_rsr. in addition, siu_rsr[ers] is set, and all other reset status bits in the siu_rsr are cleared. 4.5.3 loss of lock a loss of lock reset occurs when the fmpll loses lock and the loss of lock reset enable (lolre) bit in the fmpll synthesizer control register (syncr) is set. the internal reset signal and rstout pin are asserted. the value on the wkpcfg pin is applied at the assertion of the internal reset signal (assertion of rstout ), as is the pllref value. once the fmpll loss of lock reset request signal is negated, the reset controller waits for a predetermined number of clock cycles (refer to section 4.3.2, rstout ). once the clock count finishes, the wkpcfg and bootcfg[0:1] pins are sampled. the reset controller then waits four clock cycles before negating rstout , and the RM0029 resets doc id 15177 rev 8 143/1740 associated bits/fields are updated in the siu_rsr. in addition, siu_rsr[llrs] is set, and all other reset status bits in the siu_rsr are cleared. refer to section 17.5.3, lock detection, for more information on loss of lock. 4.5.4 loss of clock a loss of clock reset occurs when the clock quality monitor module (cqm) detects a failure in either the reference signal or fmpll output, and the loss of clock reset enable (locre) bit in the syncr is set. the internal reset signal and rstout pin are asserted. the value on the wkpcfg pin is applied at the assertion of the internal reset signal (assertion of rstout ), as is the pllref value. once the loss of clock reset request signals is negated, the reset controller waits for a predetermined number of clock cycles (refer to section 4.3.2, rstout ). once the clock count finishes, the wkpcfg and bootcfg[0:1] pins are sampled. the reset controller then waits four clock cycles before negating rstout , and the associated bits/fields are updated in the siu_rsr. in addition, siu_rsr[lcrs] is set, and all other reset status bits in the siu_rsr are cleared. refer to section 17.5.3, lock detection, for more information on loss of clock. the cqm module, when enabled, can generate either a system reset or an interrupt signal (refer to section 17.5.4, loss-of-clock detection, for details). 4.5.5 core watchdog timer/debug reset there are two watchdog timer resets: a core watchdog and a platform watchdog. a core watchdog timer reset occurs when the e200z4 core watchdog timer is enabled (the e200z4 core watchdog is counting core clocks, which is different than the peripheral/platform clocks), and a time-out occurs with the enable next watchdog timer (ewt) and watchdog timer interrupt status (wis) bits set in the timer status register, and with the watchdog reset control (wrc) field in the timer control register configured for a reset. siu_rsr[wdrs] is also set when a debug reset command is issued from a debug tool. to determine whether siu_rsr[wdrs] was set due to a watchdog timer or debug reset, see the wrs field in the e200z4 core timer status register. the effect of a watchdog timer or debug reset request is the same for the reset controller. the internal reset signal and rstout pin are asserted. the value on the wkpcfg pin is applied at the assertion of the internal reset signal (assertion of rstout ), as is the pllref value. once the watchdog timer/debug reset request is negated and the fmpll loss of lock reset request signal is negated, the reset controller waits for a predetermined number of clock cycles (refer to section 4.3.2, rstout ). once the clock count finishes the reset configuration pins are sampled. the reset controller then waits four clock cycles before negating rstout , and the associated bits/fields are updated in the siu_rsr. in addition, siu_rsr[wdrs] is set, and all other reset status bits in the siu_rsr are cleared. refer to the e200z4 power architecture ? core reference manual for descriptions of the timer status register and timer control register, as for more information on the core watchdog timer and debug operation.refer to 20, software watchdog timer (swt) , for more information on the platform watchdog. 4.5.6 jtag reset a system reset occurs when jtag is enabled and either the extest, clamp, or highz instructions are executed by the jtag controller. the internal reset signal is asserted. the resets RM0029 144/1740 doc id 15177 rev 8 state of the rstout pin is determined by the jtag instruction. the value on the wkpcfg pin is applied at the assertion of the internal reset signal, as is the pllref value. after the jtag reset request is negated, the reset controller waits for a predetermined number of clock cycles (refer to section 4.3.2, rstout ). once the clock count finishes the wkpcfg and bootcfg[0:1] pins are sampled, and the associated bits/fields are updated in the siu_rsr. the reset status bits in the siu_rsr are unaffected. refer to 36, jtag controller (jtagc), for more information. 4.5.7 software system reset a software system reset is caused by a write to field siu_srcr[ssr]; see section 16.6.5, system reset control register (siu_srcr). a write of ?1? to siu_srcr[ssr] causes an internal reset of the mcu. the internal reset signal and rstout pin are asserted. the value on the wkpcfg pin is applied at the assertion of the internal reset signal (assertion of rstout ), as is the pllref value. siu_srcr[ssr] is automatically cleared and the reset controller waits for a predetermined number of clock cycles (refer to section 4.3.2, rstout ). once the clock count finishes the wkpcfg and bootcfg[0:1] pins are sampled. the reset controller then waits four clock cycles before negating rstout , and the associated bits/fields are updated in the siu_rsr. in addition, siu_rsr[ssrs] is set, and all other reset status bits in the siu_rsr are cleared. 4.5.8 software external reset a write of ?1? to field siu_srcr[ser] causes the external rstout pin to be asserted for a predetermined number of clock cycles (refer to section 4.3.2, rstout ). siu_srcr[ser] automatically clears after the clock counting expires. a software external reset does not cause a reset of the mcu, the bam program is not executed, the pllref, bootcfg, and wkpcfg pins are not sampled. field siu_rsr[serf] is set, but no other status bits are affected. siu_rsr[serf] is not automatically cleared and remains set until cleared by software or another reset besides the software external reset occurs. for a software external reset, the e200z4 core will continue to execute instructions, timers that are enabled will continue to operate, and interrupt requests will continue to be processed. the application must ensure that devices connected to rstout are not accessed during a software external reset, and it must determine how to manage mcu resources when using the software external reset. 4.6 reset registers in the siu the system integration unit (siu) on this device includes two registers, siu_rsr and siu_srcr, that affect the reset behavior of this device. see chapter 16: system integration unit (siu), for descriptions of these registers. 4.7 reset configuration 4.7.1 reset configuration half word (rchw) rchw overview the reset configuration half word (rchw) defines boot options and must be programmed in a choice of predefined locations in internal flash. the word at the word address boundary RM0029 resets doc id 15177 rev 8 145/1740 after the rchw must be programmed with the us er application?s starting address. the bam passes control to the user application at this starting address. on every reset except the software external reset (ser), in internal or external boot modes, the bam attempts to read the rchw from internal or external memory respectively. the locations for the rchw are given in tab le 10 . for internal boot, the predefined locations are searched in the order given in the table. if a valid rchw is not found in internal boot mode or in external boot mode, the bam initiates the serial boot mode. note that in serial boot mode, a user defined start address must still be supplied as part of the download protocol. refer to the bam chapter for complete details. rchw structure when booting from the external flash device, the rchw must reside in the first 16 bits of memory. table 10. rchw location boot mode address external 0x0000_0000 internal 0x0000_0000 0x0000_4000 0x0001_0000 0x0001_c000 0x0002_0000 0x0003_0000 figure 4. reset configuration half word boot_block_address + 0x0000_0000 0123456789101112131415 swtwteps0vle01011010 boot identifier = 0x5a table 11. reset configuration half word (rchw) field descriptions field description 0?3 reserved these bit values are ignored when the halfword is read. program to 0 for future compatibility. swt software watchdog timer enable this bit determines if the software watchdog timer is enabled after passing control to the user application code. 0 disable software watchdog timer 1 enable software watchdog timer after reset. the timeout period is 261,600 system clocks. wte mcu core watchdog timer enable this bit determines if the core software watchdog timer is enabled.after passing control to the user application code. 0 disable core software watchdog timer 1 enable core watchdog timer after reset. the timeout period is 2.5*2 17 system clocks. resets RM0029 146/1740 doc id 15177 rev 8 when enabled by rchw[swt, wte] bits, the watchdog timeout periods are as shown in ta ble 12 . note the following: the swt clock source is directly from the crystal oscillator. the core wd is clocked by the pll. the core wd timeouts reported here correspond to the pll settings after reset. core wd timeouts will change as soon as the pll is programmed with different multipliers. 4.7.2 reset configuration timing the timing diagram in figure 5 shows the sampling of the bootcfg[0:1], wkpcfg, and pllref pin for a power-on reset. the timing diagram is also valid for internal/external resets assuming that vdd and vrc33 are within valid operating ranges. the value of the pllref pin is latched at the negation of the rstout pin. the value of the wkpcfg signal is applied at the assertion of the internal reset signal (assertion of rstout ). the values of ps0 port size defines the width of the data bus connected to the memory on d_cs0. after system reset, the bam changes d_cs0 to a 16-bit port to fetch the rchw from either 16- or 32-bit external memories. then the bam reconfigures the ebi as a 16- or 32-bit port, depending on this bit. 0 32-bit d_cs0 port size 1 16-bit d_cs0 port size used in development bus boot modes only (not available on all packages). do not clear this bit if the device only has a 16-bit data bus. vle vle code indicator this bit configures the mmu entries 1?3 coded as power architecture embedded category instructions or as vle instructions. 0 user code executes as classic book e code 1 user code executes as vle code bootid boot identifier this field serves two functions: ? indicates which block in flash memory contains the boot program ? indicates if the flash memory is programmed (bootid=0x5a) or invalid table 11. reset configuration half word (rchw) field descriptions field description table 12. watchdog timeout periods crystal frequency (mhz) core wd timeout (1) (ms) 1. 327,680 system clocks swt timeout (2) (ms) 2. 261,600 system clocks 840.132.7 12 27.3 21.8 16 20.5 16.35 20 16.4 13.08 40 8.2 6.54 RM0029 resets doc id 15177 rev 8 147/1740 the wkpcfg and bootcfg[0:1] pins are latched four clock cycles before the negation of the rstout pin and stored in the siu_rsr. figure 5. reset configuration timing 4.7.3 reset weak pull up/down configuration the signal on the wkpcfg pin determines whether specified etpu and emios pins are connected to weak pull up or weak pull down devices at reset (see the signal description chapter for the etpu and emios pins that are affected by wkpcfg). for all reset sources except the software external reset, the wkpcfg pin is applied at the assertion of the internal reset signal (assertion of rstout ). if the wkpcfg signal is logic high at this time, pull up devices will be enabled on the etpu and emios pins. if the wkpcfg signal is logic low at the assertion of the internal reset signal, pull down devices will be enabled on those pins. the value on wkpcfg must be held constant during reset to avoid oscillations on the etpu and emios pins caused by switching pull up/down states. the final value of wkpcfg is latched four clock cycles before the negation of rstout . after reset, software may modify the weak pull up/down selection for all i/o pins through the pcr registers in the siu. rstout reset internal reset vdd por pll xtal clock ready crystal powering up or acquiring lock wkpcfg, pllref, user drives config pins relative to rstout pllref is (4 clock cycles) cnt 1 clock cycles ?don?t care? and wkpcfg is treated as ?1? during por assertion. pllref and wkpcfg are applied, but not latched. note: 1. the clock count cnt depends on the reset source and type of clock reference. please refer to table 9 . bootcfg[0:1] operating modes and clocking RM0029 148/1740 doc id 15177 rev 8 5 operating modes and clocking 5.1 overview this section gives a brief overview of the operating modes of this device. 5.2 modes of operation 5.2.1 normal mode normal mode is the functional mode of this device. 5.2.2 debug mode debug mode provides access to powerful debugging and development features of this device. the debug and development features are distributed between nexus blocks in the e200z4 core, edma and the etpu, and some of the peripheral modules. the nexus debug and development features are described in chapter 37: nexus port controller (npc) . the peripheral blocks that implement debug mode are: dspi b, dspi c, dspi d flexcan a, flexcan b, flexcan c emios eqadc etpu (referenced as halt state in chapter 24: enhanced time processing unit (etpu2) ) see the ?modes of operation? section of the individual module for a description of how the debug mode affects the behavior of the module. 5.2.3 low power modes this device can be configured such that the clock to some or all of the modules can be stopped to reduce the power consumption. a tiered approach towards clock gating is implemented. in the first tier (module disable mode) some modules can be configured to stop the clock to the non-memory mapped registers within the module. in the second tier (module halt mode) the clock to each of the modules, including the cpu, can be completely stopped. module disable mode module disable mode is a low-power mode supported by some of the modules on this device, in which the clock to the non-memory mapped registers within the module is gated- off. tab le 1 4 lists the modules that support module disable mode. the register and bit in each module that must be written to enter or exit this mode are also listed. see the ?modes of operation? section of the individual module for a description of how the module disable mode affects the behavior of the module. RM0029 operating modes and clocking doc id 15177 rev 8 149/1740 module halt mode module halt mode is a low power mode in which the clock to all registers within each module can be completely halted. the control of the clock gating is centralized in the siu_hlt register, which has one control bit for each module to be halted. the cpu itself can also be halted. standby mode in this mode, the power is removed from all functions except the standby ram. standby mode is entered by removing all power supplies except the one on the vstby pin. the device is recovered from the standby mode when powered again; see chapter 4: resets for more information. 5.3 clock architecture the following sections detail the spc564a74xx, spc564a80xx clocking architecture. 5.3.1 overview this section describes different sources for the system clocks. the spc564a74xx, spc564a80xx clocking architecture consists of the following: on-chip mhz oscillator: range (4?40 mhz) relaxation oscillator (rcosc): 16 mhz phase-locked loop (pll): vco range (256?512 mhz) pllref top level pin to control pll reference clock quality monitor system clock divider (sysdiv) used to further reduce the system clock frequency register to control system clock source and programming of pll parameter clock gating for individual modules controlled by either siu_hlt register or module?s mdis register bit operating modes and clocking RM0029 150/1740 doc id 15177 rev 8 5.3.2 block diagram figure 6. system clock diagram figure 7. fmpll 5.3.3 system clock sources the on-chip mhz oscillator, pll and the top level pin are the possible sources of system clock. the system clock can be generated using any of the following options: pll disabled ? mhz crystal oscillator with crystal as the reference ? mhz crystal oscillator bypassed pll enabled ? mhz crystal oscillator (with crystal as the reference) output used as pll reference frequency ? mhz crystal oscillator (bypassed) output used as pll reference frequency 0 1 1 0 xtal osc fmpll xtal extal pllref clkcfg[0] sysdiv /2, /4, /8, /16 bypass_sysdiv siu_system_div[1:0] idf pd odf ndiv lock control & status registers phi clkin clock quality monitor (cqm) loss of vco loss of reference system clock rcosc pfd charge pump low pass filter vco /ndiv /idf clkin /odf fmpll phi fm controller /6 phi1 RM0029 operating modes and clocking doc id 15177 rev 8 151/1740 upon reset, the system clock source is the oscillator clock with either crystal as reference or bypassed based on the pllref pin value driven during system reset. please note the following: 1. rcosc is never used as a source of system clock. 2. phi1 output from pll is never used as a source of system clock. it is used as one of the clock sources for the flexray module. 3. see the fmpll chapter for details on fmpll operation. support for 150 mhz system clock generation the oscillator and pll support generation of a 150 mhz system clock while using the 40 mhz crystal required for flexray operation. a possible pll configuration is shown below: input clock (crystal frequency): 40 mhz eprediv/idf divider = /8 (1?15 range supported) emfd/ndiv loop divider = 60 (32?96 supported) vco clock out = 300 mhz (256?512 mhz range supported) erfd/odf output divider = /2 (/2, /4, /8, /16 supported) sysdiv divider = /1 (/1, /2, /4, /8, /16 supported) system clock = 150 mhz support for 100 mhz system clock generation the oscillator and pll support generation of a 100 mhz system clock while using the 40 mhz crystal required fro flexray operation. a possible pll configuration is shown below: input clock (crystal frequency): 40 mhz eprediv/idf divider = /8 (1?15 range supported) emfd/ndiv loop divider = 80 (32?96 supported) vco clock out = 400 mhz (256?512 mhz range supported) erfd/odf output divider = /4 (/2, /4, /8, /16 supported) sysdiv divider = /1 (/1, /2, /4, /8, /16 supported) system clock = 100 mhz support for flexray operation the spc564a74xx, spc564a80xx mcu supports generation of the clock signals needed for the operation of the flexray module. two options are supported for the generation of the flexray clock: if the pll is used with frequency modulation enabled, a 40 mhz crystal or external clock source must be used to supply the flexray clock. if the pll is configured to generate a 120 mhz system clock without frequency modulation, then the flexray module can be clocked from the system clock, allowing the use of other crystal frequencies. in this mode of operation, the vco frequency would be 480 mhz (256?512 mhz vco range supported) with the /4 output divider to achieve 120 mhz system clock. the vco/6 (80 mhz) output from pll(phi1) would be selected as the clock source for flexray by configuration of the mcf[clksel] control bit on the flexray module. operating modes and clocking RM0029 152/1740 doc id 15177 rev 8 support for can interface operation the flexcan modules have two distinct software controlled clock domains. one of the clock domains is always derived from the system clock. this clock domain includes the message buffer logic. the source for the second clock domain can be either the system clock or a direct feed from the crystal oscillator pin. the logic in the second clock domain controls the can interface pins. field flexcan_cr[clksrc] selects between the system clock and the on-chip mhz oscillator clock as the clock source for the second domain. selecting the oscillator as the clock source ensures very low jitter on the can bus. software can gate both clocks by writing to flexcan_mcr[mdis] or by writing to the siu_hlt register. 5.3.4 fmpll modes of operation upon reset, the fmpll operational mode is bypass with pll running, and the source of the reference clock, either the crystal oscillator or external clock, is determined by the state of the clkcfg[] bit of the fmpll_esyncr1 register. the reset state of this bit comes from an external signal to the module connected to a package pin called pllref. after reset, a different operational mode can be selected by writing to fmpll_esyncr1[clkcfg]. the available modes are specified in table 13 . the reset state of the fmpll is enabled with the pre-divider set such that it inhibits the clock to the pll phase detector, making the vco run within its free-running frequency range of 25 mhz to 125 mhz, unconnected from the system clock (since bypass is the default mode at reset). if using crystal reference, after power-on reset the clock quality monitor (cqm) inhibits the system clock and keep system reset asserted while the crystal oscillator has not stabilized. the pllref pin must be kept stable during the whole period while system reset is asserted. table 13. clock mode selection clkcfg[] (bypass ) clkcfg[1] (1) (pll enable) clkcfg[] (2) (clock source) clock mode 0 0 0 bypass mode with external reference and pll off 0 0 1 bypass mode with crystal reference and pll off 0 1 0 bypass mode with external reference and pll running 0 1 1 bypass mode with crystal reference and pll running 1 0 0 reserved 1 0 1 reserved 1 1 0 normal mode with external reference 1 1 1 normal mode with crystal reference 1. clkcfg[1] is not writable to zero while clkcfg[]=1. 2. the reset state of this bit is determined by the logical state applied to the pllref pin. RM0029 operating modes and clocking doc id 15177 rev 8 153/1740 bypass mode with crystal reference in the bypass mode with crystal reference, the fmpll is completely bypassed and the system clock is driven from the crystal oscillator. the user must supply a crystal that is within the appropriate frequency range, the crystal manufacturer recommended external support circuitry, and short signal route from the mcu to the crystal. in bypass mode the pll itself may or may not be running, depending on the state of the clkcfg[1] bit of the fmpll_esyncr1 register, but the pll output is not connected to the system clock. consequently, frequency modulation is not available. the pre-divider is also bypassed, but the system clock divider (sysdiv) can be used to reduce the system clock frequency. the system clock divider can be programmed by writing to siu_ sysdiv[sysdiv]. bypass mode with crystal reference is the default mode at reset if the pllref pin is driven high. after reset, this mode can be entered by programming fmpll_esyncr1[clkcfg] as shown in ta ble 13 . figure 8. bypass mode with crystal reference bypass mode with external reference the bypass mode with external reference functions the same as bypass mode with crystal reference, except that the system clock is driven by an external clock generator connected to the extal pin, rather than a crystal oscillator. the input frequency range is the same and frequency modulation is not available. bypass mode with external reference is the default mode at reset if the pllref pin is driven low. after reset, this mode can be entered by programming fmpll_esyncr1[clkcfg] as shown in table 13 . 0 1 0 1 xtal osc fmpll xtal extal pllref clkcfg[0] sysdiv /2, /4, /8, /16 bypass_sysdiv siu_system_div[1:0] idf pd odf ndiv lock control & status registers phi clkin clock quality monitor (cqm) loss of vco loss of reference system clock rcosc operating modes and clocking RM0029 154/1740 doc id 15177 rev 8 figure 9. bypass mode with external reference normal mode with crystal reference in the normal mode with crystal reference, the fmpll receives an input clock frequency from the crystal oscillator and the pre-divider, and multiplies the frequency to create the fmpll output clock. the user must supply a crystal that is within the appropriate frequency range, the crystal manufacturer recommended external support circuitry, and short signal route from the mcu to the crystal. in normal mode with crystal reference, the fmpll can generate a frequency-modulated clock or a non-modulated clock (locked on a single frequency). the modulation rate, modulation depth, output divider (rfd) and whether the fmpll is modulating or not can be programmed by writing to the fmpll registers. the system clock divider (sysdiv) can also be used to further reduce the system clock frequency in addition to the fmpll output divider. the system clock divider can be programmed by writing to siu_sysdiv[sysdiv]. see section 16.6.31, system clock register (siu_sysdiv) for details. note: the pll output frequency (before the system clock divider) must not exceed the maximum device operating frequency. therefore, when operating at the maximum operating frequency, the only division factor allowed in the system clock divider is divide-by-1. 0 1 0 1 xtal osc fmpll xtal extal pllref clkcfg[0] sysdiv /2, /4, /8, /16 bypass_sysdiv siu_system_div[1:0] idf pd odf ndiv lock control & status registers phi clkin clock quality monitor (cqm) loss of vco loss of reference system clock rcosc RM0029 operating modes and clocking doc id 15177 rev 8 155/1740 figure 10. normal mode with crystal reference normal mode with external reference the normal mode with external reference functions the same as normal mode with crystal reference, except that the input clock reference to the fmpll is driven by an external clock generator connected to the extal pin, rather than a crystal oscillator. the input frequency range is the same and frequency modulation is available. figure 11. normal mode with external reference software controlled power management software controlled power management and clock gating is supported on a peripheral by peripheral basis, using a three tiered approach. the first tier is a clock gating feature 0 1 0 1 xtal osc fmpll xtal extal pllref clkcfg[0] sysdiv /2, /4, /8, /16 bypass_sysdiv siu_system_div[1:0] idf pd odf ndiv lock control & status registers phi clkin clock quality monitor (cqm) loss of vco loss of reference system clock rcosc 0 1 0 1 xtal osc fmpll xtal extal pllref clkcfg[0] sysdiv /2, /4, /8, /16 bypass_sysdiv siu_system_div[1:0] idf pd odf ndiv lock control & status registers phi clkin clock quality monitor (cqm) loss of vco loss of reference system clock rcosc operating modes and clocking RM0029 156/1740 doc id 15177 rev 8 implemented in some of the ip modules, which allows software to disable the non-memory- mapped portions of the modules by setting the module disable (mdis (d) ) bits in the registers within the modules. the second tier is provided by the siu_hlt register, which can be used to halt the clock of both memory-mapped and non-memory-mapped portions of each module. the third tier is provided by the wait instruction of the power architecture instruction set, which controls the clock gating of the cpu itself. figure 12 illustrates how the mdis and halt bits affect the clocks to the modules. figure 12. mdis and halt clock gating mdis clock gating the mdis bit disables the clock to some or all of the non-memory-mapped registers of the module. the memory-mapped portion of the modules are clocked by the system clock when they are accessed. when the npc module is disabled by mdis, the mcko clock is disabled. furthermore, the npc can be configured to disable the mcko clock when there are no messages pending. when the ebi module is disabled by mdis, the clkout clock is disabled. furthermore, the ebi automatically disables the clkout clock when there are no transactions on the external (calibration) bus. the flash memory array can be disabled by writing to a bit in the flash memory map. d. for compatibility with legacy devices, the default value of mdis bit is zero. mdis ip ipg_stop_ack ipg_stop system_clk_enable siu hlt hltack memory mapped registers non memory mapped affected by mdis system_clk_s ip inactive ips_module_en system_clk system_clk non memory mapped, not affected by mdis system_clk RM0029 operating modes and clocking doc id 15177 rev 8 157/1740 the modules that implement the mdis function are listed in table 14 , along with the registers and bits that disable each module. the software controlled clocks are enabled when the cpu comes out of reset. halt clock gating software controlled clock gating can be done via the centralized halt mechanism. the siu_hlt register bits corresponding to individual modules are configured to determine which modules are clock gated. the siu_hlt register bits are used to drive a stop request signal to the modules. after the module completes a clean shut down, the module asserts a stop acknowledge handshake signal that is used to gate the clock to the module (see figure 12 ). the stop acknowledge signals are also captured in the siu_hltack read-only register bits. the halted modules recover when the corresponding siu_hlt register bit is cleared by software. once the bit is cleared, logic will re-enable the clocks to the modules and then negate the stop request signal after the required timing has been met. cpu clock gating the siu_hlt register has a bit to halt the clock to the cpu, but in order to prevent accidental cpu halting, a stop request is only activated if the cpu is in wait state due to the execution of the wait instruction. table 14. mdis support (1) block name register name bit name dspi_b dspi_b_mcr mdis dspi_c dspi_c_mcr mdis dspi_d dspi_d_mcr mdis ebi ebi_mcr mdis etpu etpuecr_1 mdis flexcan a flexcan_a_mcr mdis flexcan b flexcan_b_mcr mdis flexcan c flexcan_c_mcr mdis emios emios_mcr mdis esci_a esci_a_scicr3 mdis esci_b esci_b_scicr3 mdis esci_c esci_c_scicr3 mdis decimation filter decfiltermcr mdis red line module tbd mdis npc npc_pcr mcko_en, mcko_gt flash memory array flash_mcr stop 1. the mdis bit default reset value is zero. operating modes and clocking RM0029 158/1740 doc id 15177 rev 8 note: to gate the cpu clock you need to first program the siu_hlt register bit assigned for cpu and then execute the cpu wait instruction. the cpu recovers from the halted state when one of the following events happens: a valid pending interrupt is detected by the core a request to enter debug mode is made by setting the dr bit in the once control register (ocr) the processor is in a debug session a request to enable the cpu clock input has been made by setting the wkup bit in the ocr when one of these events is detected, the cpu asserts an asynchronous output signal that re-enables the clock to the cpu so that it can exit the stopped state. typically, the wake-up interrupt request will come from one of three sources: periodic interval timer (pit) interrupt, external pin interrupt or can wake-up interrupt. when the clock to the cpu is gated, the clocks to the platform, the system ram and the flash memory are also gated. the platform logic includes the cross-bar, peripheral bridge, dma and flash memory controller. note that the interrupt controller (intc) and the siu are not clock gated to allow interrupts to be used to recover the cpu halt state. clock dividers the mcu provides five clock dividers: system clock divider (sysdiv) external bus clock divider (clkout-div) nexus message clock divider (mcko-div) engineering clock divider (engdiv) flexcan clock divider (can2:1) system clock divider (sysdiv) the system clock divider is placed right at the output of the system clock mux (selection between fmpll and the crystal clock) and before the clock is used by any other circuits, including the other clock dividers. it affects the clock in both normal mode and bypass mode. the system clock divider can be programmed to divide by 1, 2, 4, 8, or 16 depending on the values of fields bypass and sysclkdiv in the siu_sysdiv register. siu_sysdiv[bypass] determines whether or not the system clock divider is bypassed. the siu_sysdiv[bypass] reset value ?1? causes the system clock divider to be bypassed and results in a divide-by-1 reset configuration of the system clock divider. only if the siu_sysdiv[bypass] value is ?0? can field siu_sysdiv[sysclkdiv] be programmed to divide by 2, 4, 8, or 16. external bus clock (clkout) the external bus clock (clkout) divider can be programmed to divide the system clock by one, two or four based on the settings of the ebdf field in the siu external clock control register (siu_eccr). the reset value of siu_eccr[ebdf] selects a clkout frequency of one half of the system clock frequency. the ebi supports gating of the clkout signal when there are no external bus accesses in progress. the hold time for external bus pins can be changed by writing to siu_eccr[ebts] (external bus tap select bit). RM0029 operating modes and clocking doc id 15177 rev 8 159/1740 note: the clkout pin is only available in the 324-pin package. nexus message clock (mcko) the nexus message clock (mcko) divider can be programmed to divide the system clock by two, four or eight based on the mcko_div field in the port configuration register (pcr) in the nexus port controller (npc). the reset value of npc_pcr[mcko_div] selects an mcko clock frequency one half of the system clock frequency. the mcko divider is configured by writing to the npc through the jtag port. engineering clock divider (engdiv) the engineering clock divider (engdiv) can be programmed to divide system clock. this clock is mainly used to clock some asic devices integrated on the board. there is no timing relation of this clock with respect to any other clock in the design. refer to section 16.6.26: external clock control register (siu_eccr) for engdiv register bit programming. flexcan clock divider (can2:1) the flexcan module has the ability to run from the system clock. it is possible, at the input to the flexcan module, to perform a divide-by-1 or a divide-by-2 division of the system clock. this flexcan system clock divider can be programmed by configuring the flexcan2:1 mode bit (field siu_sysdiv[can_src]). the reset value is to divide-by-1. the flexcan module does not support a divide-by-1 of the system clock above a certain frequency, defined in the devicedatasheet. when running at maximum system frequency this setting will have to be adjusted from its default value. device performance optimization RM0029 160/1740 doc id 15177 rev 8 6 device performance optimization 6.1 introduction the spc564a74xx, spc564a80xx contains several features that can influence the overall level of performance provided by the device. some of these features may be initialized upon negation of reset either by a software program called the boot assist module (bam), by a hardware state machine or by appropriate default register settings. although the device exits the reset state into a functional state it does not necessarily have the default optimum performance settings for any given application. this chapter provides guidance for users to fully optimize their application to achieve the highest possible performance from the spc564a74xx, spc564a80xx. it provides a description of the areas that should be focused on when optimizing an application for performance by describing the features and recommending settings to be applied. it focuses on hardware configurations although certain aspects of the application software such as compiler settings and optimizations will be discussed. 6.2 features the spc564a74xx, spc564a80xx has the following hardware features that can be configured to impact the overall performance of the device: branch prediction ? branch target buffer ? branch prediction control frequency-modulated pll flash bus interface unit ? flash access wait state and address pipelining control ? flash instruction prefetching ? flash data prefetching crossbar switch system cache ? instruction cache memory management unit further application level features can impact the application performance: hardware single precision floating point signal processing extension (spe-apu) variable length encoding (vle) compiler optimizations RM0029 device performance optimization doc id 15177 rev 8 161/1740 further factors that impact the overall application performance are the use of the intelligent peripherals: use of dma rather than cpu to transfer data efficiently use of dma service requests rather than cpu interrupts to avoid software polling off-loading tasks from the cpu to the etpu2 or edma careful allocation of cache usage for code and data ranges, particularly when using with external memories. different items in this list will have different performance impacts in a real system. features like the system cache, the fmpll and the flash access times tend to provide the most significant performance impacts in terms of hardware settings. the subsequent sections in this chapter describe how to configure and use these features. 6.3 configuring hardware features 6.3.1 branch target buffer (btb) description to resolve branch instructions and improve the accuracy of branch predictions the e200z4 core implements a dynamic branch prediction mechanism using a branch target buffer (btb), a fully associative address cache of branch target addresses. its purpose is to accelerate the execution of software loops with some potential change of flow within the loop body. in addition, the btb on the e200z4 has a subroutine call stack that speeds up indirect branches. recommended configuration by default, this btb is disabled following negation of reset. it is controlled by the branch unit control and status register (bucsr). the btb?s contents should be flushed and invalidated by writing bucsr[bbfi] = 1, and it may be enabled by subsequently writing bucsr[bpen] = 1. additional control is available in bucsr[bpred] and bucsr[balloc] to control whether forward or backward branches (or both) are candidates for entry into the btb, and thus for branch prediction. by default the bucsr[bpred] and bucsr[balloc] fields are set to 0b00, which enables forward and backward branch prediction. it is recommended to not disable branch prediction although for extremely fine tuning of a given application the optimum setting of bucsr[bpred] and bucsr[balloc] should be assessed. . figure 13. branch unit control and status register (bucsr) 0 bbfi 0 balloc 0 bpred bpen 012345678910111213141516171819202122232425262728293031 spr - 1013; read/write; reset - 0x0 device performance optimization RM0029 162/1740 doc id 15177 rev 8 further details of the bucsr can be found in the e200z4 power architecture? core reference manual. 6.3.2 frequency-modulated pll description the frequency-modulated phase-locked loop (fmpll) allows the user to generate high speed system clocks from a crystal oscillator or external clock generator. further, the fmpll supports programmable frequency modulation of the system clock. this module is typically configured early in the initialization code to ensure satisfactory performance levels are achieved. recommended configuration the default operating frequency of the spc564a74xx, spc564a80xx device is 2 to 3 times the crystal reference frequency depending on the state of the pll configuration pins as reset negates. typically, the system frequency is increased shortly after reset negates to provide acceptable performance. 17, frequency-modulated phase locked loop (fmpll) , table 15. bucsr field descriptions field description bbfi branch target buffer flash invalidate when set, bbfi flash clears the valid bit of all btb entries; clearing occurs regardless of the value of the enable bit (bpen). note : bbfi is always read as 0. balloc branch target buffer allocation control 00: branch target buffer allocation for all branches is enabled. 01: branch target buffer allocation is disabled for backward branches. 10: branch target buffer allocation is disabled for forward branches. 11: branch target buffer allocation is disabled for both branch directions. this field controls btb allocation for branch acceleration when bpen = 1. note that btb hits are not affected by the settings of this field. note that for branches with aa = ?1?, the msb of the displacement field is still used to indicate forward/backward, even though the branch is absolute. bpred branch prediction control (static) 00: branch predicted taken on btb miss for all branches. 01: branch predicted taken on btb miss only for forward branches. 10: branch predicted taken on btb miss only for backward branches. 11: branch predicted not taken on btb miss for both branch directions. this field controls operation of static prediction mechanism on a btb miss. unless disabled, fetching of the predicted target location will be performed for branch acceleration. bpred operates independently of bpen, and with a bpen setting of 0, will be used to perform static prediction of all unresolved branches. note that btb hits are not affected by the settings of this field. note that for certain applications, setting bpred to a non-default value may result in improved performance. bpen branch target buffer (btb) enable 0: btb prediction disabled. no hits are generated from the btb and no new entries are allocated. entries are not automatically invalidated when bpen is cleared; bbfi controls entry invalidation. 1: btb prediction enabled (enables btb to predict branches). RM0029 device performance optimization doc id 15177 rev 8 163/1740 provides details on how the frequency-modulated phase-locked loop should be initialized in an application. the maximum frequency of operation for this device is specified in the device data sheet. system performance cannot be linearly extrapolated with system frequency, as is often the expectation. it is due to the insertion of additional flash wait states as system frequency increases that system performance does not scale linearly. take care to ensure that the correct internal and/or external flash configuration is chosen for the selected system frequency. the specific flash access times to be applied are detailed in section , bus interface unit configuration register (biucr) . 6.3.3 flash bus interface unit description the flash bus interface unit (fbiu) interfaces the system bus to the flash memory array controller. the fbiu contains prefetch buffers and a prefetch controller which, if enabled, speculatively prefetches sequential lines of data from the flash array into the buffer. prefetch buffer hits allow zero-wait state responses. the flash bus interface configuration registers (biucrx) control access to the internal flash array. its settings define the number of cycles required to access the array, access times, and how the prefetch buffering scheme operates. following negation of reset and execution of the bam, the instruction and data prefetching is disabled, and the number of cycles required to access the internal flash array is set to its maximum value of fifteen additional wait states. recommended configuration as the operating frequency of the device is set by configuring the fmpll (see section 6.3.2, frequency-modulated pll ), the number of cycles required to access the internal array should be configured accordingly. note that the flash biucrx registers cannot be altered by code executing from the flash array. code for configuring the flash should be executed from a separate memory array i.e copied to and executed from system ram. section , bus interface unit configuration register (biucr) , documents the register fields used to configure flash wait state settings. the ? platform flash controller electrical characteristics? section of the device data sheet contains the specific values for the flash wait state settings for a given operating frequency. this also provides recommendations for the prefetch buffer settings. note that the biucrx settings may vary between revisions of the spc564a74xx, spc564a80xx. 6.3.4 crossbar switch description the multi-port crossbar switch (xbar) supports simultaneous connections between master ports and slave ports. the xbar allows for concurrent transactions to occur from any master port to any slave port. if a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. all other masters requesting that slave port are stalled until the higher priority master completes its transactions. by default, requesting masters are granted access based on a fixed priority. a round-robin priority mode also is available. device performance optimization RM0029 164/1740 doc id 15177 rev 8 the main goal of the xbar is to increase overall system performance by allowing multiple masters to communicate concurrently with multiple slaves. in order to maximize data throughput it is essential to keep arbitration delays to a minimum. the configuration of the crossbar can have implications for the performance of a system and particular care should be taken when assigning master priorities in a fixed priority application. further, by correctly parking saves on relevant masters the initial access times to the slaves can be minimized by negating any initial arbitration penalties. recommended configuration the specific settings for a given situation are application dependent and thus should be assessed by the user. however, some general guidelines are available. optimal xbar settings are application dependent, but in e200z4/7 (harvard configuration) based devices assigning the cpu data bus to have highest priority and parking the slave port associated with system ram on this master generally provides the best overall performance. to reconfigure the xbar as described on the spc564a74xx, spc564a80xx, write the following registers: 1. xbar_sgpcr2 = 0x0000_0001. this parks slave 2 (internal sram) on master port 1 (cpu data bus). 2. write xbar_mpr0 = 0x5432_0001. this sets slave port 0 (flash) to give the master port 1 (cpu data bus) highest priority. on the e200z4 based devices it may also be beneficial to assign the edma to have highest priority for the flash slave port depending upon the application. more details of the xbar register configuration can be found in section 9.2, xbar registers . 6.3.5 cache description the spc564a74xx, spc564a80xx provides an 8 kb instruction, 2-way or 4-way set- associative, harvard cache design with a 32-byte line size. the cache is disabled by default when reset is negated. the cache improves system performance by providing low-latency instructions to the e200z4 instruction pipelines, which decouples processor performance from system memory performance. there are several stages to enabling the cache. not only does the cache itself have to be invalidated then enabled, but memory regions upon which it can operate must be configured in the mmu to permit cache access. recommended configuration the exact usage of cache is application dependent but some general guidelines for using cache to improve performance in a typical application are listed below: enable instruction cache for all internal and external memories that code is being executed from. consider locking critical performance routines in cache. RM0029 device performance optimization doc id 15177 rev 8 165/1740 the process of enabling the instruction cache involves first invalidating the cache (by setting l1csr1[icinv]) then when invalidation is completed (l1csr1[icinv, icabt] = 0) enabling the cache (by setting l1csr1[ice]). the l1csr1 special purpose register is detailed below.for further details of cache configuration registers, refer to the e200z4 power architecture? core reference manual. figure 14. l1 cache control and status register 1 (l1csr1) 0 icece icei 0 icedt 0 icul iclo iclfc icloa icea icorg icabt icinv ice 012345678910111213141516171819202122232425262728293031 spr - 1011; read/write; reset - 0x0 table 16. l1csr1 field descriptions field description icece instruction cache error checking enable icei instruction cache error injection enable icedt instruction cache error detection type icul instruction cache unable to lock iclo instruction cache lock overflow iclfc instruction cache lock bits flash clear icloa instruction cache lock overflow allocate icea instruction cache error action icorg cache organization 0 the cache is organized as 64 sets and 2 ways 1 the cache is organized as 32 sets and 4 ways icabt instruction cache operation aborted indicates a cache invalidate or a cache lock bits flash clear operation was aborted prior to completion. this bit is set by hardware on an aborted condition, and will remain set until cleared by software writing 0 to this bit location. icinv instruction cache invalidate 0: no cache invalidate 1: cache invalidation operation when written to a ?1?, a cache invalidation operation is initiated by hardware. once complete, this bit is reset to ?0?. writing a ?1? while an invalidation operation is in progress will result in an undefined operation. writing a ?0? to this bit while an invalidation operation is in progress will be ignored. cache invalidation operations require approximately 36 cycles to complete. invalidation occurs regardless of the enable (ice) value. during cache invalidations, the parity check bits are written with a value dependent on the icedt selection. icedt should be written with the desired value for subsequent cache operation when icinv is set to ?1? for proper operation of the cache. device performance optimization RM0029 166/1740 doc id 15177 rev 8 note that configuration of the cache has to be performed in conjunction with configuration of the memory management unit. refer to section 6.3.6, memory management unit (mmu) . 6.3.6 memory management unit (mmu) description the memory management unit is a 32-bit power architecture compliant implementation which provides functionality that includes address translation and application of access attributes to memory ranges defined in translation lookaside buffer entries. although the mmu does not directly impact performance, it is within the mmu that memory regions are configured to permit the use of system cache to improve performance and variable length encoding (vle) to enhance code density. thus it is essential that the mmu is correctly configured to ensure optimal application performance is achieved. recommended configuration the core uses mmu assist registers (masx) which are special purpose registers to facilitate reading, writing and searching the translation lookaside buffer (tlb) entries. these mas registers are software managed by tlbre , tlbwe , tlbsx , tlbsync , and tlbivax instructions. refer to the core reference manual for full details of the mmu and its configurations. there are several mmu assist register registers (mas0?3) that require configuring. details of these are provided in the e200z4 power architecture? core reference manual. specifically, the mas2 register contains the fields to control whether a specified memory region described by the valid tlb entry is cache inhibited or whether vle encoding is valid. ice instruction cache enable 0: cache is disabled 1: cache is enabled when disabled, cache lookups are not performed for instruction accesses. other l1csr0 cache control operations are still available. table 16. l1csr1 field descriptions (continued) field description figure 15. mmu assist register 2 (mas2) epn 0 vle wimge 012345678910111213141516171819202122232425262728293031 spr - 626; read/write table 17. mas2 field descriptions field description epn effective page number [0:21] vle vle 0: this page is a standard booke page 1: this page is a vle page RM0029 device performance optimization doc id 15177 rev 8 167/1740 refer to the e200z4 power architecture? core reference manual for further details of mmu configuration registers. 6.4 application software 6.4.1 compiler optimizations the most significant opportunity for influencing the performance of a given application is by compiler and linker optimizations. optimizing is a trade off between code size and performance. typically higher performance of the application comes at the expense of larger code size. compilers use a host of features, such as loop unrolling, function inlining, and application profile feedback to make the desired trade-offs between enhanced performance and minimized code size. the data in figure 16 shows the effects of compiler optimization on a simple application. in this case, the dhrystone benchmark was run under three conditions: optimized for small code size optimized for high performance a trade-off between code size and performance although this is an extreme example, it highlights how significant the role of the compiler and linker is in determining the overall performance of an application. w write-through required i cache inhibited 0: this page is considered cacheable 1: this page is considered cache-inhibited m memory coherence required g guarded e endianness table 17. mas2 field descriptions (continued) field description device performance optimization RM0029 168/1740 doc id 15177 rev 8 figure 16. influence of compiler settings on application performance and code size note: data measured using dhrystone version 2.1 run on a power architecture based powertrain device that uses a standard commercial compiler. the compiler optimizations do not necessarily have to be applied to the entire application. analysis of an application can identify time critical functions that may subsequently be targeted for performance optimization, without incurring the impact of optimizing the entire application. there are several other aspects of the compiler and linker that should be considered. in particular, the use of small data areas (sdas, sometimes referred to as special data areas) can make a significant performance improvement. refer to compiler documentation for usage guidelines on small data areas. 6.4.2 signal processing extension to further optimize time critical functions, the signal processing extension auxiliary processing unit (spe-apu) may be used. the spe-apu provides a set of single instruction multiple data (simd) instructions. these simd instructions typically involve performing the same operation on multiple data elements stored within a single 64-bit register. through the implementation of simd instructions, including vector multiply and accumulate (mac) instructions, the spe apu provides digital signal processing (dsp) functionality. this can be used to accelerate signal processing routines, such as finite impulse response (fir), infinite impulse response (iir) and discrete fourier transforms (dft). a more general benefit of the spe instruction set is the ability to load/store 64-bits of data in single instruction. thus highly load/store intensive functions make good candidates for spe optimization. 0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 1.2 performance vs. code size normalized execution time normalized code size size optimized trade-off speed optimized RM0029 device performance optimization doc id 15177 rev 8 169/1740 6.4.3 hardware single precision floating point the spe-apu also supports 32-bit ieee ? -754 single-precision floating-point formats, and supports vector and scalar single-precision floating-point operations. most compiler vendors include libraries that can emulate floating point functionality. however, by specifying the correct compiler options, the single precision floating point instructions may be used. to enable use of hardware floating point the msr[spe] field must be set. refer to section 6.4.2, signal processing extension for register details. 6.4.4 variable length encoding in addition to the base power architecture instruction set support, the e200z4 core also implements the vle (variable-length encoding) apu, providing improved code density. the vle-apu can be viewed as a supplement to the existing power architecture instruction set that can be conditionally applied to a portion of, or an entire application for which improved code density is desired. using it is straightforward: figure 17. machine state register (msr) 0 ucle spe 0 we ce 0 ee pr fp me 0 de 0 is ds 0 ri 0 012345678910111213141516171819202122232425262728293031 read / write; reset - 0x0 table 18. msr field descriptions field description ucle user cache lock enable spe spe available 0: execution of spe apu vector instructions is disabled; spe unavailable exception taken instead, and spe bit is set in esr. 1: execution of spe apu vector instructions is enabled. we wait state (power management) enable ce critical interrupt enable ee external interrupt enable pr problem state fp floating-point available me machine check enable de debug interrupt enable is instruction address space ds data address space ri recoverable interrupt device performance optimization RM0029 170/1740 doc id 15177 rev 8 1. select the appropriate compiler target and option to generate vle code. 2. configure the memory management unit (mmu) to specify vle attributes for the relevant mmu pages. refer to the register description in section 6.3.6, memory management unit (mmu) . vle-enabled cores run both power architecture and vle instruction encodings on a page by page basis, with pages defined by the mmu. the reduction is code size is typically between 25% and 30%. 6.5 peripherals and genera l application guidelines optimizing the device configuration and compiler setup is only one part of optimizing an entire application. correct use of the peripherals can also dramatically improve overall system performance. in particular, use of the interrupt controller, the enhanced direct memory access (edma), and intelligent peripherals such as the enhanced timer processing unit (etpu2), can off-load significant work from the cpu. for example, edma may be used to shift data to avoid unnecessary cpu loading. most peripheral modules can generate edma requests to trigger data transfers. an example of a typical application is to use the edma to pass conversion commands to the analog to digital converter (adc) ,while maintaining circular buffers results of the adc in the system ram, with no core intervention. section 6.6, performance optimization checklist provides several system level examples of how to optimize an application. RM0029 device performance optimization doc id 15177 rev 8 171/1740 6.6 performance optimization checklist table 19. performance optimization checklist?part 1. hardware configuration description register(s) details branch target buffer flush with bucsr[bbfi] enable with bucsr[bpen] flush and enable to improve accuracy of branch predictions. branch prediction bucsr[bpred] bucsr[balloc] consider fine tuning of btb operation for specific applications. system frequency fmpll_esyncr1 fmpll_esyncr2 select desired frequency taking into account the performance impact of additional wait states. flash wait states biucr[apc, ww, rwsc] refer to flash chapter section : bus interface unit configuration register (biucr) , for biucr settings for fmpll frequency ranges. flash prefetching biucr[dpfen, ipfen, pflim, bfen] enable prefetching for instructions. prefetching for data should be assessed for the specific application. flash prefetch algorithm biucr2[lbcfg] allocate buffers to data and/or instructions. fine tune for specific applications. crossbar switch park slave sram on master port with xbar_sgpcr2. set flash slave port to highest priority with xbar_mpr0. for e200z7 based devices reconfigure to optimize for harvard architecture. cache invalidate icache with l1csr1[icinv] enable icache with l1csr1[ice] invalidate and the enable the cache for instructions. memory management unit tlb_mas2[vle, i] configure relevant pages for cache and vle by setting mmu tlb attributes. table 20. performance optimization checklist?part 2. software configuration description registers details compiler optimization ? use the features of the compiler to select the optimum trade off between code size and performance improvements. hardware single precision floating point enable with msr[spe] set compiler switches to specify using hardware single precision floating point as opposed to software emulation. signal processing extensions enable with msr[spe] take advantage of the spe-apu to encode time critical functions using spe assembly code. variable length encoding enabled with tlb_mas2[vle] set compiler switches and configure the mmu to take advantage of the vle-apu. device performance optimization RM0029 172/1740 doc id 15177 rev 8 table 21. performance optimization checklist?pa rt 3. peripherals and general application guidelines peripherals and general application guidelines use edma rather than the core to move data where possible. most peripherals can generate edma requests to shift data. ? use edma to control movement of commands and results from adc and to maintain circular buffers in system memory. ? create circular buffers so that adc results can be stored in ram with no core overhead. shift loading from the cpu to the etpu2 whenever possible. ? the etpu2 can provide effective cpu off-loading for time and angle based operations. ? the etpu2 can trigger the adc directly with no need for cpu interruption. avoid software polling and allow peripherals to trigger interrupts or request edma servicing. ? use hardware instead of software vectored interrupts to reduce latency. ? trigger edma requests rather than interrupting the cpu to move data/results. configure the external memory interface. ? enable bursting on the external bus. ? reduce external bus wait states from default maximum settings. ? place time critical functions in internal memory. ? small, but frequently executed routines can be considered as candidates to be locked in cache. RM0029 e200z4 core doc id 15177 rev 8 173/1740 7 e200z4 core this chapter contains an overview of the e200z4 processor core integrated in spc564a74xx, spc564a80xx devices.for detailed information see the publication e200z4 power architecture core reference manual. note: there are two differences between the processor core in spc564a74xx, spc564a80xx devices and the e200z4 documented in the core reference manual. spc564a74xx, spc564a80xx devices feature a e200z448n3 core with 8 kb of instruction cache (vs. 4 kb) and 24 mmu entries (vs. 16). 7.1 overview the microcontroller?s cost-efficient e200z4 host processor core is built on the power architecture technology and designed specifically for embedded applications. the e200z4 is a dual-issue, 32-bit power architecture compliant design with 64-bit general purpose registers (gprs). power architecture floating-point instructions are not supported by this core in hardware, but are trapped and may be emulated by software. an embedded floating-point (efpu) apu is provided to support real-time single-precision embedded numerics operations using the general-purpose registers. a signal processing extension (spe) apu is provided to support real-time simd fixed point and single-precision, embedded numerics operations using the general-purpose registers. all arithmetic instructions that execute in the core operate on data in the general purpose registers (gprs). the gprs have been extended to 64-bits in order to support vector instructions defined by the spe apu. these instructions operate on a vector pair of 16-bit or 32-bit data types, and deliver vector and scalar results. in addition to the base power architecture instruction set support, the e200z4 core also implements the vle (variable-length encoding) technology, providing improved code density. the e200z4 processor integrates a pair of integer execution units, a branch control unit, instruction fetch unit and load/store unit, and a multi-ported register file capable of sustaining six read and three write operations per clock. most integer instructions execute in a single clock cycle. branch target prefetching is performed by the branch unit to allow single-cycle branches in many cases. the e200z4 contains an 8 kb instruction cache as well as a memory management unit. a nexus class 3 module is also integrated. e200z4 core RM0029 174/1740 doc id 15177 rev 8 7.2 features features of the e200z4 core include: dual issue, 32-bit power architecture compliant cpu implements the vle apu for reduced code footprint in-order execution and retirement precise exception handling branch processing unit ? dedicated branch address calculation adder ? branch target prefetching using 8-entry btb supports independent instruction and data accesses to different memory subsystems, such as sram and flash memory via independent instruction and data bius load/store unit ? 2 cycle load latency ? fully pipelined ? big and little endian support ? misaligned access support 64-bit general purpose register file 64-bit instruction bus, 64-bit data bus memory management unit (mmu) with 24-entry fully-associative tlb and multiple page size support 8 kb, 2-way or 4-way set associative instruction cache signal processing extension (spe1.1) apu supporting simd fixed-point operations using the 64-bit general purpose register file. embedded floating-point (efp2) apu supporting scalar and vector simd single- precision floating-point operations, using the 64-bit general purpose register file. nexus class 3 real-time development unit power management ? power saving mode: wait process id manipulation for the mmu using an external tool 7.3 microarchitecture summary the e200z4 utilizes a five-stage pipeline for instruction execution. these stages are: instruction fetch (stage 1) instruction decode/register file read/effective address calculation (stage 2) execute 0/memory access 0 (stage 3) execute 1/memory access 1 (stage 4) register writeback (stage 5) the stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. RM0029 e200z4 core doc id 15177 rev 8 175/1740 the integer execution unit consists of a 32-bit arithmetic unit (au), a logic unit (lu), a 32- bit barrel shifter (shifter), a mask-insertion unit (miu), a condition register manipulation unit (cru), a count-leading-zeros unit (clz), a 32x32 hardware multiplier array, and result feed-forward hardware. integer eu1 also supports hardware division. most arithmetic and logical operations are executed in a single cycle with the exception of multiply, which is implemented with a 2-cycle pipelined hardware array, and the divide instructions. a count-leading-zeros unit operates in a single clock cycle. the instruction unit contains a pc incrementer and dedicated branch address adders to minimize delays during change of flow operations. sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. branch target prefetching using the btb is performed to accelerate taken branches. prefetched instructions are placed into an 8-entry instruction buffer, with each entry capable of holding a single 32-bit instruction or a pair of 16-bit instructions. branch target addresses are calculated in parallel with branch instruction decode. conditional branches, which are not taken execute in a single clock. branches with successful btb target prefetching have an effective execution time of one clock if correctly predicted. memory load and store operations are provided for byte, halfword, word (32-bit), and doubleword data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. these instructions can be pipelined to allow effective single cycle throughput. load and store multiple word instructions allow low overhead context save and restore operations. the load/store unit contains a dedicated effective address adder to allow effective address generation to be optimized. there is a single load- to-use bubble for load instructions. the condition register unit supports the condition register (cr) and condition register operations defined by the power architecture technology. the condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provides a mechanism for testing and branching. vectored and autovectored interrupts are supported by the cpu. vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead. the spe apu supports vector instructions operating on 16 and 32-bit fixed-point data types, as well as 32-bit ieee-754 single-precision floating-point formats, and supports single- precision floating-point operations in a pipelined fashion. the 64-bit general purpose register file is used for source and destination operands, and there is a unified storage model for single-precision floating-point data types of 32-bits and the normal integer type. low latency fixed-point and floating-point add, subtract, multiply, multiply-add, multiply-sub, divide, compare, and conversion operations are provided, and most operations can be pipelined. e200z4 core RM0029 176/1740 doc id 15177 rev 8 figure 18. e200z4 block diagram 7.3.1 instruction unit features the features of e200z4 instruction unit are: 64-bit path to cache supports fetching of two 32-bit instruction per clock instruction buffer holds up to eight 32-bit instructions dedicated pc incrementer supporting instruction prefetches branch unit with dedicated branch address adder, and branch lookahead logic (btb) supporting single cycle execution of successfully predicted branches cpu control logic load/ data memory management unit address store unit instruction unit branch unit pc unit instruction buffer gpr cr spr multiply units spe unit data bus interface unit control 32 64 n extended functional control inst data once/nexus control logic unit interface interface control data (mtspr/mfspr) integer execution units external spr ctr xer lr data address instruction bus interface unit control 32 64 n instruction cache RM0029 e200z4 core doc id 15177 rev 8 177/1740 7.3.2 integer unit features the e200z4 integer units support single cycle execution of most integer instructions: 32-bit au for arithmetic and comparison operations 32-bit lu for logical operations 32-bit priority encoder for count leading zero?s function 32-bit single cycle barrel shifter for static shifts and rotates 32-bit mask unit for data masking and insertion divider logic for signed and unsigned divide in <=14 clocks with minimized execution timing (eu1 only) pipelined 32x32 hardware multiplier array supports 32x32->32 multiply with 2 clock latency, 1 clock throughput 7.3.3 load/store unit features the e200z4 load/store unit supports load, store, and the load multiple / store multiple instructions: 32-bit effective address adder for data memory address calculations pipelined operation supports throughput of one load or store operation per cycle dedicated 64-bit interface to memory supports saving and restoring of up to two registers per cycle for load multiple and store multiple word instructions 7.3.4 cache features the features of the e200z4 cache are as follows: 8 kb, 2- or 4-way configurable set-associative instruction cache linefill buffer 32-bit address bus plus attributes and control supports cache line locking supports way allocation supports tag and data parity supports tag and data double error detection correction/auto-invalidation capability 7.3.5 mmu features the features of the mmu are as follows: virtual memory support 32-bit virtual and physical addresses 8-bit process identifier 24-entry fully-associative tlb per-entry multiple page size support from 1 kbyte to 4 gbyte entry flush protection process id manipulation for the mmu using an external tool e200z4 core RM0029 178/1740 doc id 15177 rev 8 7.3.6 e200z4 system bus features the features of the e200z4 system bus interface are as follows: independent instruction and data buses 32-bit address bus, 64-bit data bus, plus attributes and control data interface provides separate unidirectional 64-bit read and write data buses 7.3.7 nexus 3 features the nexus 3 module is compliant with class 3 of the ieee-isto 5001? - 2003 standard, with certain additional class 4 features available. the following features are implemented: program trace via branch trace messaging (btm). branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. thus, static code may be traced. data trace via data write messaging (dwm) and data read messaging (drm). this provides the capability for the development tool to trace reads and/or writes to selected internal memory resources. ownership trace via ownership trace messaging (otm). otm facilitates ownership trace by providing visibility of which process id or operating system task is activated. an ownership trace message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow. run-time access to the processor memory map via the jtag port. this allows for enhanced download/upload capabilities. watchpoint messaging via the auxiliary interface. watchpoint trigger enable of program and/or data trace messaging. data acquisition messaging (dqm) allows code to be instrumented to export customized information to the nexus auxiliary output port. auxiliary interface for higher data input/output. registers for program trace, data trace, ownership trace, data acquisition, and watchpoint trigger control. all features controllable and configurable via the jtag port. RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 179/1740 8 enhanced direct memory access controller (edma) 8.1 introduction this device includes an enhanced direct memory access controller (edma) block. the edma is a second-generation platform block capable of performing complex data movements through 64 programmable channels with minimal intervention from the host processor. the hardware microarchitecture includes a dma engine that performs source and destination address calculations, and the actual data movement operations, along with an sram-based memory containing the transfer control descriptors (tcd) for the channels. 8.1.1 block diagram figure 19 shows a simplified block diagram of the edma. figure 19. edma block diagram slave interface edma edma done system bus data path control address program model/ slave write data slave write address bus write data slave read data bus address edma engine tcd0 tcd n ?1* edma peripheral request bus read data channel arbitration path sram transfer control descriptor ( tcd ) sram * n = 64 channels for edma enhanced direct memory access controller (edma) RM0029 180/1740 doc id 15177 rev 8 8.1.2 features the edma has these major features: all data movement via dual-address transfers: read from source, write to destination ? programmable source, destination addresses, transfer size, and support for enhanced addressing modes both 32- and 64-channel implementation performs complex data transfers with minimal intervention from a host processor ? 32 bytes of data registers, used as temporary storage to support burst transfers (refer to ssize bit) ? connections to the crossbar switch for bus mastering the data movement transfer control descriptor organized to support two-deep, nested transfer operations ? an inner data transfer loop defined by a minor byte transfer count ? an outer data transfer loop defined by a major iteration count channel activation via 1 of 3 methods: ? explicit software initiation ? initiation via a channel-to-channel linking mechanism for continuous transfers ? peripheral-paced hardware requests (one per channel) all three methods require one activation per execution of the minor loop support for fixed-priority and round-robin channel arbitration support for complex data structures support to cancel transfers via software channel completion reported via optional interrupt requests ? 1 interrupt per channel, optionally asserted at completion of major iteration count ? error terminations are optionally enabled per channel and logically summed together to form a single error interrupt (32-channel edma) or two error interrupts (64-channel edma). support for scatter-gather dma processing support for complex data structures any channel can be programmed to be suspended by a higher priority channel?s activation, before completion of a minor loop. 8.1.3 modes of operation there are two main operating modes of edma: normal mode and debug mode. these modes are briefly described in this section. normal mode in normal mode, the edma is used to transfer data between a source and a destination. the source and destination can be a memory block or an i/o block capable of operation with the edma. debug mode in debug mode, the edma does not accept new transfer requests when its debug input signal is asserted. if the signal is asserted during transfer of a block of data described by a RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 181/1740 minor loop in the current active channel?s tcd, the edma continues operation until completion of the minor loop. 8.2 external signal description the edma has no external signals. 8.3 memory map and registers this section provides a detailed description of all edma registers. 8.3.1 module memory map the edma memory map is shown in table 22 . the address of each register is given as an offset to the edma base address. registers are listed in address order, identified by complete name and mnemonic, and list the type of accesses allowed. table 23 shows a graphical representation of the same memory map. in register names, an ? x ? is used to indicate a or b, depending on which edma?s register you are using. if a register only exists in one of the edmas, the register description will state that. the edma?s programming model is partitioned into two regions: the first region defines a number of registers providing control functions; however, the second region corresponds to the local transfer control descriptor memory. some registers are implemented as two 32-bit registers, and include h and l suffixes, signaling the high and low portions of the control function. table 22. edma memory map offset from edma_base register location size edma_base (0xfff4_4000) edma_cr?edma control register on page 8-188 32 edma_base + 0x0004 edma_esr?edma error status register on page 8-191 32 edma_base + 0x0008 edma_erqrh?edma enable request high register (channels 63?32) on page 8-194 32 edma_base + 0x000c edma_erqrl?edma enable request low register (channels 31?00) on page 8-194 32 edma_base + 0x0010 edma_eeirlh?edma enable error interpol register (channels 63?32) on page 8-195 32 edma_base + 0x0014 edma_eeirl?edma enable error interrupt register (channels 31?00) on page 8-195 32 edma_base + 0x0018 edma_serqr?edma set enable request register on page 8-196 8 edma_base + 0x0019 edma_cerqr?edma clear enable request register on page 8-197 8 edma_base + 0x001a edma_seeir?edma set enable error interrupt register on page 8-198 8 edma_base + 0x001b edma_ceeir?edma clear enable error interrupt register on page 8-198 8 edma_base + 0x001c edma_cirqr?edma clear interrupt request register on page 8-199 8 enhanced direct memory access controller (edma) RM0029 182/1740 doc id 15177 rev 8 edma_base + 0x001d edma_cer?edma clear error register on page 8-199 8 edma_base + 0x001e edma_ssbr?edma set start bit register on page 8-200 8 edma_base + 0x001f edma_cdsbr?edma clear done status bit register on page 8-201 8 edma_base + 0x0020 edma_irqrh?edma interrupt request register (channels 63?32) on page 8-201 32 edma_base + 0x0024 edma_irqrl?edma interrupt request register (channels 31?00) on page 8-201 32 edma_base + 0x0028 edma_erh?edma error register (channels 63?32) on page 8-202 32 edma_base + 0x002c edma_erl?edma error register (channels 31?00) on page 8-202 32 edma_base + 0x0030 edma_hrsh?edma hardware request status register (channels 63?32) on page 8-204 32 edma_base + 0x0034 edma_hrsl?edma hardware request status register (channels 31?00) on page 8-204 32 edma_base + 0x0038? edma_base + 0x00ff reserved edma_base + 0x0100 edma_cpr0?edma channel 0 priority register on page 8-205 8 edma_base + 0x0101 edma_cpr1?edma channel 1 priority register on page 8-205 8 edma_base + 0x0102 edma_cpr2?edma channel 2 priority register on page 8-205 8 edma_base + 0x0103 edma_cpr3?edma channel 3 priority register on page 8-205 8 edma_base + 0x0104 edma_cpr4?edma channel 4 priority register on page 8-205 8 edma_base + 0x0105 edma_cpr5?edma channel 5 priority register on page 8-205 8 edma_base + 0x0106 edma_cpr6?edma channel 6 priority register on page 8-205 8 edma_base + 0x0107 edma_cpr7?edma channel 7 priority register on page 8-205 8 edma_base + 0x0108 edma_cpr8?edma channel 8 priority register on page 8-205 8 edma_base + 0x0109 edma_cpr9?edma channel 9 priority register on page 8-205 8 edma_base + 0x010a edma_cpr10?edma channel 10 priority register on page 8-205 8 edma_base + 0x010b edma_cpr11?edma channel 11 priority register on page 8-205 8 edma_base + 0x010c edma_cpr12?edma channel 12 priority register on page 8-205 8 edma_base + 0x010d edma_cpr13?edma channel 13 priority register on page 8-205 8 edma_base + 0x010e edma_cpr14?edma channel 14 priority register on page 8-205 8 edma_base + 0x010f edma_cpr15?edma channel 15 priority register on page 8-205 8 edma_base + 0x0110 edma_cpr16?edma channel 16 priority register on page 8-205 8 edma_base + 0x0111 edma_cpr17?edma channel 17 priority register on page 8-205 8 edma_base + 0x0112 edma_cpr18?edma channel 18 priority register on page 8-205 8 edma_base + 0x0113 edma_cpr19?edma channel 19 priority register on page 8-205 8 table 22. edma memory map (continued) offset from edma_base register location size RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 183/1740 edma_base + 0x0114 edma_cpr20?edma channel 20 priority register on page 8-205 8 edma_base + 0x0115 edma_cpr21?edma channel 21 priority register on page 8-205 8 edma_base + 0x0116 edma_cpr22?edma channel 22 priority register on page 8-205 8 edma_base + 0x0117 edma_cpr23?edma channel 23 priority register on page 8-205 8 edma_base + 0x0118 edma_cpr24?edma channel 24 priority register on page 8-205 8 edma_base + 0x0119 edma_cpr25?edma channel 25 priority register on page 8-205 8 edma_base + 0x011a edma_cpr26?edma channel 26 priority register on page 8-205 8 edma_base + 0x011b edma_cpr27?edma channel 27 priority register on page 8-205 8 edma_base + 0x011c edma_cpr28?edma channel 28 priority register on page 8-205 8 edma_base + 0x011d edma_cpr29?edma channel 29 priority register on page 8-205 8 edma_base + 0x011e edma_cpr30?edma channel 30 priority register on page 8-205 8 edma_base + 0x011f edma_cpr31?edma channel 31 priority register on page 8-205 8 edma_base + 0x0120 edma_cpr32?edma channel 32 priority register on page 8-205 8 edma_base + 0x0121 edma_cpr33?edma channel 33 priority register on page 8-205 8 edma_base + 0x0122 edma_cpr34?edma channel 34 priority register on page 8-205 8 edma_base + 0x0123 edma_cpr35?edma channel 35 priority register on page 8-205 8 edma_base + 0x0124 edma_cpr36?edma channel 36 priority register on page 8-205 8 edma_base + 0x0125 edma_cpr37?edma channel 37 priority register on page 8-205 8 edma_base + 0x0126 edma_cpr38?edma channel 38 priority register on page 8-205 8 edma_base + 0x0127 edma_cpr39?edma channel 39 priority register on page 8-205 8 edma_base + 0x0128 edma_cpr40?edma channel 40 priority register on page 8-205 8 edma_base + 0x0129 edma_cpr41?edma channel 41 priority register on page 8-205 8 edma_base + 0x012a edma_cpr42?edma channel 42 priority register on page 8-205 8 edma_base + 0x012b edma_cpr43?edma channel 43 priority register on page 8-205 8 edma_base + 0x012c edma_cpr44?edma channel 44 priority register on page 8-205 8 edma_base + 0x012d edma_cpr45?edma channel 45 priority register on page 8-205 8 edma_base + 0x012e edma_cpr46?edma channel 46 priority register on page 8-205 8 edma_base + 0x012f edma_cpr47?edma channel 47 priority register on page 8-205 8 edma_base + 0x0130 edma_cpr48?edma channel 48 priority register on page 8-205 8 edma_base + 0x0131 edma_cpr49?edma channel 49 priority register on page 8-205 8 edma_base + 0x0132 edma_cpr50?edma channel 50 priority register on page 8-205 8 edma_base + 0x0133 edma_cpr51?edma channel 51 priority register on page 8-205 8 edma_base + 0x0134 edma_cpr52?edma channel 52 priority register on page 8-205 8 edma_base + 0x0135 edma_cpr53?edma channel 53 priority register on page 8-205 8 table 22. edma memory map (continued) offset from edma_base register location size enhanced direct memory access controller (edma) RM0029 184/1740 doc id 15177 rev 8 edma_base + 0x0136 edma_cpr54?edma channel 54 priority register on page 8-205 8 edma_base + 0x0137 edma_cpr55?edma channel 55 priority register on page 8-205 8 edma_base + 0x0138 edma_cpr56?edma channel 56 priority register on page 8-205 8 edma_base + 0x0139 edma_cpr57?edma channel 57 priority register on page 8-205 8 edma_base + 0x013a edma_cpr58?edma channel 58 priority register on page 8-205 8 edma_base + 0x013b edma_cpr59?edma channel 59 priority register on page 8-205 8 edma_base + 0x013c edma_cpr60?edma channel 60 priority register on page 8-205 8 edma_base + 0x013d edma_cpr61?edma channel 61 priority register on page 8-205 8 edma_base + 0x013e edma_cpr62?edma channel 62 priority register on page 8-205 8 edma_base + 0x013f edma_cpr63?edma channel 63 priority register on page 8-205 8 edma_base + 0x0140? edma_base + 0x0fff reserved edma_base + 0x1000 edma_tcd00?edma transfer control descriptor 00 on page 8-206 256 edma_base + 0x1020 edma_tcd01?edma transfer control descriptor 01 on page 8-206 256 edma_base + 0x1040 edma_tcd02?edma transfer control descriptor 02 on page 8-206 256 edma_base + 0x1060 edma_tcd03?edma transfer control descriptor 03 on page 8-206 256 edma_base + 0x1080 edma_tcd04?edma transfer control descriptor 04 on page 8-206 256 edma_base + 0x10a0 edma_tcd05?edma transfer control descriptor 05 on page 8-206 256 edma_base + 0x10c0 edma_tcd06?edma transfer control descriptor 06 on page 8-206 256 edma_base + 0x10e0 edma_tcd07?edma transfer control descriptor 07 on page 8-206 256 edma_base + 0x1100 edma_tcd08?edma transfer control descriptor 08 on page 8-206 256 edma_base + 0x1120 edma_tcd09?edma transfer control descriptor 09 on page 8-206 256 edma_base + 0x1140 edma_tcd10?edma transfer control descriptor 10 on page 8-206 256 edma_base + 0x1160 edma_tcd11?edma transfer control descriptor 11 on page 8-206 256 edma_base + 0x1180 edma_tcd12?edma transfer control descriptor 12 on page 8-206 256 edma_base + 0x11a0 edma_tcd13?edma transfer control descriptor 13 on page 8-206 256 edma_base + 0x11c0 edma_tcd14?edma transfer control descriptor 14 on page 8-206 256 edma_base + 0x11e0 edma_tcd15?edma transfer control descriptor 15 on page 8-206 256 edma_base + 0x1200 edma_tcd16?edma transfer control descriptor 16 on page 8-206 256 edma_base + 0x1220 edma_tcd17?edma transfer control descriptor 17 on page 8-206 256 edma_base + 0x1240 edma_tcd18?edma transfer control descriptor 18 on page 8-206 256 edma_base + 0x1260 edma_tcd19?edma transfer control descriptor 19 on page 8-206 256 edma_base + 0x1280 edma_tcd20?edma transfer control descriptor 20 on page 8-206 256 edma_base + 0x12a0 edma_tcd21?edma transfer control descriptor 21 on page 8-206 256 table 22. edma memory map (continued) offset from edma_base register location size RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 185/1740 edma_base + 0x12c0 edma_tcd22?edma transfer control descriptor 22 on page 8-206 256 edma_base + 0x12e0 edma_tcd23?edma transfer control descriptor 23 on page 8-206 256 edma_base + 0x1300 edma_tcd24?edma transfer control descriptor 24 on page 8-206 256 edma_base + 0x1320 edma_tcd25?edma transfer control descriptor 25 on page 8-206 256 edma_base + 0x1340 edma_tcd26?edma transfer control descriptor 26 on page 8-206 256 edma_base + 0x1360 edma_tcd27?edma transfer control descriptor 27 on page 8-206 256 edma_base + 0x1380 edma_tcd28?edma transfer control descriptor 28 on page 8-206 256 edma_base + 0x13a0 edma_tcd29?edma transfer control descriptor 29 on page 8-206 256 edma_base + 0x13c0 edma_tcd30?edma transfer control descriptor 30 on page 8-206 256 edma_base + 0x13e0 edma_tcd31?edma transfer control descriptor 31 on page 8-206 256 edma_base + 0x1400 edma_tcd32?edma transfer control descriptor 32 on page 8-206 256 edma_base + 0x1420 edma_tcd33?edma transfer control descriptor 33 on page 8-206 256 edma_base + 0x1440 edma_tcd34?edma transfer control descriptor 34 on page 8-206 256 edma_base + 0x1460 edma_tcd35?edma transfer control descriptor 35 on page 8-206 256 edma_base + 0x1480 edma_tcd36?edma transfer control descriptor 36 on page 8-206 256 edma_base + 0x14a0 edma_tcd37?edma transfer control descriptor 37 on page 8-206 256 edma_base + 0x14c0 edma_tcd38?edma transfer control descriptor 38 on page 8-206 256 edma_base + 0x14e0 edma_tcd39?edma transfer control descriptor 39 on page 8-206 256 edma_base + 0x1500 edma_tcd40?edma transfer control descriptor 40 on page 8-206 256 edma_base + 0x1520 edma_tcd41?edma transfer control descriptor 41 on page 8-206 256 edma_base + 0x1540 edma_tcd42?edma transfer control descriptor 42 on page 8-206 256 edma_base + 0x1560 edma_tcd43?edma transfer control descriptor 43 on page 8-206 256 edma_base + 0x1580 edma_tcd44?edma transfer control descriptor 44 on page 8-206 256 edma_base + 0x15a0 edma_tcd45?edma transfer control descriptor 45 on page 8-206 256 edma_base + 0x15c0 edma_tcd46?edma transfer control descriptor 46 on page 8-206 256 edma_base + 0x15e0 edma_tcd47?edma transfer control descriptor 47 on page 8-206 256 edma_base + 0x1600 edma_tcd48?edma transfer control descriptor 48 on page 8-206 256 edma_base + 0x1620 edma_tcd49?edma transfer control descriptor 49 on page 8-206 256 edma_base + 0x1640 edma_tcd50?edma transfer control descriptor 50 on page 8-206 256 edma_base + 0x1660 edma_tcd51?edma transfer control descriptor 51 on page 8-206 256 edma_base + 0x1680 edma_tcd52?edma transfer control descriptor 52 on page 8-206 256 edma_base + 0x16a0 edma_tcd53?edma transfer control descriptor 53 on page 8-206 256 edma_base + 0x16c0 edma_tcd54?edma transfer control descriptor 54 on page 8-206 256 edma_base + 0x16e0 edma_tcd55?edma transfer control descriptor 55 on page 8-206 256 table 22. edma memory map (continued) offset from edma_base register location size enhanced direct memory access controller (edma) RM0029 186/1740 doc id 15177 rev 8 edma_base + 0x1700 edma_tcd56?edma transfer control descriptor 56 on page 8-206 256 edma_base + 0x1720 edma_tcd57?edma transfer control descriptor 57 on page 8-206 256 edma_base + 0x1740 edma_tcd58?edma transfer control descriptor 58 on page 8-206 256 edma_base + 0x1760 edma_tcd59?edma transfer control descriptor 59 on page 8-206 256 edma_base + 0x1780 edma_tcd60?edma transfer control descriptor 60 on page 8-206 256 edma_base + 0x17a0 edma_tcd61?edma transfer control descriptor 61 on page 8-206 256 edma_base + 0x17c0 edma_tcd62?edma transfer control descriptor 62 on page 8-206 256 edma_base + 0x17e0 edma_tcd63?edma transfer control descriptor 63 on page 8-206 256 table 22. edma memory map (continued) offset from edma_base register location size table 23. edma 32-bit memory map?graphical view address register 0xfff4_4000 edma control register (edma_cr) 0xfff4_4004 edma error status (edma_esr) 0xfff4_4008 edma enable request high register (edma_erqrh) 0xfff4_400c edma enable request (edma_erqrl, channels 31?16) edma enable request (edma_erqrl, channels 15?00) 0xfff4_4010 edma enable error interrupt high (edma_eeirh, channels 63?48) edma enable error interrupt high (edma_eeirh, channels 47?32) 0xfff4_4014 edma enable error interrupt low (edma_eeirl, channels 31?16) edma enable error interrupt low (edma_eeirl, channels 15?00) 0xfff4_4018 edma set enable request (edma_serqr) edma clear enable request (edma_cerqr) edma set enable error interrupt (edma_seeir) edma clear enable error interrupt (edma_ceeir) 0xfff4_401c edma clear interrupt request (edma_cirqr) edma clear error (edma_cer) edma set start bit, activate channel (edma_ssbr) edma clear done status bit (edma_cdsbr) 0xfff4_4020 edma interrupt request high (edma_irqrh channels 63?48) edma interrupt request high (edma_irqrh, channels 47?32) 0xfff4_4024 edma interrupt request low (edma_irqrl, channels 31?16) edma interrupt request low (edma_irqrl, channels 15?00) 0xfff4_4028 edma error high (edma_erl, channels 63?48) edma error high (edma_erl, channels 47?32) 0xfff4_402c edma error low (edma_erl, channels 31?16) edma error low (edma_erl, channels 15?00) 0xfff4_4030 edma hardware request status high (edma_hrsl, channels 63?48) edma hardware request status high (edma_hrsl, channels 47?32) RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 187/1740 0xfff4_4034 edma hardware request status low (edma_hrsl, channels 31?16) edma hardware request status low (edma_hrsl, channels 15?00) 0xfff4_4038 ? 0xfff4_40fc reserved 0xfff4_4100 edma channel 0 priority (edma_cpr0) edma channel 1 priority (edma_cpr1) edma channel 2 priority (edma_cpr2) edma channel 3 priority (edma_cpr3) 0xfff4_4104 edma channel 4 priority (edma_cpr4) edma channel 5 priority (edma_cpr5) edma channel 6 priority (edma_cpr6) edma channel 7 priority edma_cpr7) 0xfff4_4108 edma channel 8 priority (edma_cpr8) edma channel 9 priority (edma_cpr9) edma channel 10 priority (edma_cpr10) edma channel 11 priority (edma_cpr11) 0xfff4_410c edma channel 12 priority (edma_cpr12) edma channel 13 priority (edma_cpr13) edma channel 14 priority (edma_cpr14) edma channel 15 priority (edma_cpr15) 0xfff4_4110 edma channel 16 priority (edma_cpr16) edma channel 17 priority (edma_cpr17) edma channel 18 priority (edma_cpr18) edma channel 19 priority (edma_cpr19) 0xfff4_4114 edma channel 20 priority (edma_cpr16) edma channel 21 priority (edma_cpr17) edma channel 22 priority (edma_cpr18) edma channel 23 priority (edma_cpr19) 0xfff4_4118 edma channel 24 priority (edma_cpr16) edma channel 25 priority (edma_cpr17) edma channel 26 priority (edma_cpr18) edma channel 27 priority (edma_cpr19) 0xfff4_411c edma channel 28 priority (edma_cpr16) edma channel 29 priority (edma_cpr17) edma channel 30 priority (edma_cpr18) edma channel 31 priority (edma_cpr19) 0xfff4_4100 edma channel 32 priority (edma_cpr32) edma channel 33 priority (edma_cpr33) edma channel 34 priority (edma_cpr34) edma channel 35 priority (edma_cpr35) 0xfff4_4104 edma channel 36 priority (edma_cpr36) edma channel 37 priority (edma_cpr37) edma channel 38 priority (edma_cpr38) edma channel 39 priority edma_cpr39) 0xfff4_4108 edma channel 40 priority (edma_cpr40) edma channel 41 priority (edma_cpr41) edma channel 42 priority (edma_cpr42) edma channel 43 priority (edma_cpr43) 0xfff4_410c edma channel 44 priority (edma_cpr44) edma channel 45 priority (edma_cpr45) edma channel 46 priority (edma_cpr46) edma channel 47 priority (edma_cpr47) 0xfff4_4110 edma channel 48 priority (edma_cpr48) edma channel 49 priority (edma_cpr49) edma channel 50 priority (edma_cpr50) edma channel 51 priority (edma_cpr51) table 23. edma 32-bit memory map?graphical view (continued) address register enhanced direct memory access controller (edma) RM0029 188/1740 doc id 15177 rev 8 8.3.2 register descriptions this section lists the edma registers in address order and describes the registers and their bitfields. reading reserved bits in a register returns the value of zero. writes to reserved bits in a register are ignored. reading or writing to a reserved memory location generates a bus error. many of the control registers have a bit width that matches the number of channels implemented in the module: 64 bits for edma (made up of two 32-bit registers: high and low?for example, edma_erqrh has upper 32 channels of edma) edma control register (edma_cr) the 32-bit edma_cr defines the basic operating configuration of the edma. the edma arbitrates channel service requests in four (edma) groups (0, 1, 2, 3) of 16 channels each: group 0 contains channels 0?15 group 1 contains channels 16?31 group 2 contains channels 32?47 (edma only) group 3 contains channels 48?63 (edma only) arbitration within a group can be configured to use a fixed priority or a round robin. in fixed- priority arbitration, the highest priority channel requesting service is selected to execute. the priorities are assigned by the channel priority registers. see section , edma channel n 0xfff4_4114 edma channel 52 priority (edma_cpr52) edma channel 53 priority (edma_cpr53) edma channel 54 priority (edma_cpr54) edma channel 55 priority (edma_cpr55) 0xfff4_4118 edma channel 56 priority (edma_cpr56) edma channel 57 priority (edma_cpr57) edma channel 58 priority (edma_cpr58) edma channel 59 priority (edma_cpr59) 0xfff4_411c edma channel 60 priority (edma_cpr60) edma channel 61 priority (edma_cpr61) edma channel 62 priority (edma_cpr62) edma channel 63 priority (edma_cpr63) 0xfff4_5000 ? 0xfff4_51fc edma_tcd00?edma_tcd15 0xfff4_5200 ? 0xfff4_53fc edma_tcd16?edma_tcd31 0xfff4_5400 ? 0xfff4_55fc edma_tcd32?edma_tcd47 0xfff4_5600 ? 0xfff4_57fc edma_tcd48?edma_tcd63 0xfff4_5800 reserved table 23. edma 32-bit memory map?graphical view (continued) address register RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 189/1740 priority registers (edma_cprn). in round-robin arbitration mode, the channel priorities are ignored and the channels within each group are cycled through, from channel 15 down to channel 0,without regard to priority. the group priorities operate in a similar fashion. in group fixed-priority arbitration mode, channel service requests in the highest priority group are executed first where priority level 3 (edma) is the highest and priority level 0 is the lowest. the group priorities are assigned in the grp n pri fields of the edma control register (edma_cr). all group priorities must have unique values prior to any channel service requests occur, otherwise a configuration error is reported. in group round-robin mode, the group priorities are ignored and the groups are cycled through, from group 3 (edma) down to group 0, without regard to priority. minor loop offsets are address offset values added to the final source address (saddr) or destination address (daddr) upon minor l oop completion. when minor loop offsets are enabled, the minor loop offset (mloff) is added to the final source address (saddr) or to the final destination address (daddr) or to both addresses prior to the addresses being written back into the tcd. if the major loop is complete, the minor loop offset is ignored and the major loop address offsets (slast and dlast_sga) are used to compute the next edma_tcd[saddr] and edma_tcd[daddr] values. when minor loop mapping is enabled (edma_cr[emlm] = 1), tcd n word2 is redefined. a portion of tcd n word2 is used to specify multiple fields: a source enable bit (smloe) to specify that the minor loop offset should be applied to the source address (saddr) upon minor loop completion, a destination enable bit (dmloe) to specify the minor loop offset should be applied to the destination addres s (daddr) upon minor loop completion, and the sign extended minor loop offset value (mloff). the same offset value (mloff) is used for both source and destination minor loop offsets. when either of the minor loop offsets is enabled (smloe is set or dmloe is set), the nbytes field is reduced to 10 bits. when both minor loop offsets are disabled (smloe is cleared and dmloe is cleared), the nbytes field becomes a 30-bit vector. when minor loop mapping is disabled (edma_cr[emlm] = 0), all 32 bits of tcd n word2 are assigned to the nbytes field. see section , transfer control descriptor (tcd) for more details. figure 20. edma control register (edma_cr) offset: edma_base + 0x0000 access: user read/write 01234567 8 9101112131415 r00000000 0 000 0 0 cx ecx w reset00000000 0 000 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r grp3pri grp2pri grp1pri grp0pri emlm clm halt hoe erga erca edbg 0 w reset11100100 0 000 0 0 0 0 enhanced direct memory access controller (edma) RM0029 190/1740 doc id 15177 rev 8 table 24. edma_cr field descriptions field description cx cancel transfer 0 normal operation 1 cancel the remaining data transfer. stop the executing channel and force the minor loop to be finished. the cancel takes effect after the last write of the current read/write sequence. the cx bit clears itself after the cancel has been honored. this cancel retires the channel normally as if the minor loop was completed. ecx error cancel transfer 0 normal operation 1 cancel the remaining data transfer in the same fashion as the cx cancel transfer. stop the executing channel and force the minor loop to be finished. the cancel takes effect after the last write of the current read/write sequence. the ecx bit clears itself after the cancel has been honored. in addition to cancelling the transfer, the ecx treats the cancel as an error condition; thus updating the edma_esr register and generating an optional error interrupt. see section , edma error status register (edma_esr). grp3pri channel group 3 priority group 3 priority level when fixed priority group arbitration is enabled. grp2pri channel group 2 priority group 2 priority level when fixed priority group arbitration is enabled. grp1pri channel group 1 priority group 1 priority level when fixed priority group arbitration is enabled. grp0pri channel group 0 priority group 0 priority level when fixed priority group arbitration is enabled. emlm enable minor loop mapping 0 minor loop mapping disabled. tcd word 2 is defined as a 32-bit nbytes field. 1 minor loop mapping enabled. when set, tcd n word 2 is redefined to include individual enable fields, an offset field and the nbytes field. the individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. the nbytes field is reduced when either offset is enabled. clm continuous link mode 0 a minor loop channel link made to itself goes through channel arbitration before being activated again. 1 a minor loop channel link made to itself does not go through channel arbitration before being activated again. upon minor loop completion, the channel is active again if that channel has a minor loop channel link enabled and the link channel is itself. this effectively applies the minor loop offsets and restarts the next minor loop. halt halt dma operations 0 normal operation 1 stall the start of any new channels. executing channels are allowed to complete. channel execution resumes when the halt bit is cleared. hoe halt on error 0 normal operation 1 any error causes the halt bit to be set. subsequently, all service requests are ignored until the halt bit is cleared. RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 191/1740 edma error status register (edma_esr) the edma_esr provides information about the last recorded channel error. channel errors can be caused by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority register setting in fixed-arbitration mode) or an error termination to a bus master read or write cycle. a configuration error is caused when the starting source or destination address, source or destination offsets, minor loop byte count, and the transfer size represent an inconsistent state. the addresses and offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a multiple of the source and destination transfer sizes. all source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. in fixed-arbitration mode, a configuration error is generated when any two channel priority levels are equal and any channel is activated. the errchn field is undefined for this type of error. all channel priority levels must be unique before any service requests are made. if a scatter-gather operation is enabled on channel completion, a configuration error is reported if the scatter-gather address (dlast_sga) is not aligned on a 32-byte boundary. if minor loop channel linking is enabled on channel completion, a configuration error is reported when the link is attempted if bit edma_tcd[citer.e_link] is not equal to bit edma_tcd[biter.e_link]. all configuration error conditions except scatter-gather and minor loop link error are reported as the channel is activated and assert an error interrupt request if enabled. when properly enabled, a scatter-gather configuration error is reported when the scatter-gather operation begins at major loop completion. a minor loop channel link configuration error is reported when the link operation is serviced at minor loop completion. if a system bus read or write is terminated with an error, the data transfer is immediately stopped and the appropriate bus error flag is set. in this case, the state of the channel?s transfer control descriptor is updated by the dma engine with the current source address, destination address, and minor loop byte count at the point of the fault. if a bus error occurs on the last read prior to beginning the write sequence, the write is executed using the data captured during the bus error. if a bus error occurs on the last write prior to switching to the next read sequence, the read sequence is executed before the channel is terminated due to the destination bus error. erga enable round-robin group arbitration 0 fixed-priority arbitration is used for selection among the groups. 1 round-robin arbitration is used for selection among the groups. erca enable round-robin channel arbitration 0 fixed-priority arbitration is used for channel selection within each group. 1 round-robin arbitration is used for channel selection within each group. edbg enable debug 0 the assertion of the system debug control input is ignored. 1 the assertion of the system debug control input causes the edma to stall the start of a new channel. executing channels are allowed to complete. channel execution resumes when either the system debug control input is negated or the edbg bit is cleared. table 24. edma_cr field descriptions (continued) field description enhanced direct memory access controller (edma) RM0029 192/1740 doc id 15177 rev 8 a transfer may be cancelled by software via the bit edma_cr[cx]. when a cancel transfer request is recognized, the edma engine stops processing the channel. the current read- write sequence is allowed to finish. if the cancel occurs on the last read-write sequence of a major or minor loop, the cancel request is discarded and the channel retires normally. the error cancel transfer is the same as a cancel transfer except the dmaes register is updated with the cancelled channel number and error cancel bit is set. the tcd of a cancelled channel has the source address and destination address of the last transfer saved in the tcd. it is the responsibility of the user to initialize the tcd again should the channel need to be restarted because the aforementioned fields have been modified by the edma engine and no longer represent the original parameters. when a transfer is cancelled via the error cancel transfer mechanism (setting edma_cr[ecx]), the channel number is loaded into field edma_esr[errchn] and the bits edma_esr[ecx] and edma_esr[vld] are set. in addition, an error interrupt may be generated if enabled. refer to section , edma error registers (edma_erh, edma_erl) . the occurrence of any type of error causes the dma engine to stop the active channel and the appropriate channel bit in the edma error register to be asserted. at the same time, the details of the error condition are loaded into the edma_esr. the major loop complete indicators, setting the transfer control descriptor done flag and the possible assertion of an interrupt request, are not affected when an error is detected. after the error status has been updated, the dma engine continues to operate by servicing the next appropriate channel. a channel that experiences an error condition is not automatically disabled. if a channel is terminated by an error and then issues another service request before the error is fixed, that channel will execute and terminate with the same error condition. figure 21. edma error status register (edma_esr) offset: edma_base + 0x0004 access: user read-only 0123456789101112131415 rvld00000000000000ecx w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r gpe cpe errchn sae soe dae doe nce sge sbe dbe w reset0000000000000000 table 25. edma_esr field descriptions field description vld valid bit logical or of all edma_erl status bits. 0 no edma_er bits are set. 1 at least one edma_er bit is set indicating a valid error exists that has not been cleared. ecx transfer canceled 0 no canceled transfers 1 the last recorded entry was a canceled transfer via the error cancel transfer input. RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 193/1740 gpe group-priority error 0 no group-priority error 1 the last recorded error was a configuration error among the group priorities indicating not all group priorities are unique. cpe channel-priority error 0 no channel-priority error 1 the last recorded error was a configuration error in the channel priorities within a group, indicating not all channel priorities within a group are unique. errchn error channel number or canceled channel number channel number of the last recorded error (excluding gpe and cpe errors) or last recorded transfer that was error cancelled. do not rely on the number in the errchn field group for channel-priority errors. group- and channel- priority errors must be resolved by inspection. the application code must interrogate the priority registers to find groups or channels with duplicate priority level. sae source address error 0 no source address configuration error 1 the last recorded error was a configuration error detected in field edma_tcd[saddr], indicating edma_tcd[saddr] is inconsistent with edma_tcd[ssize]. soe source offset error 0 no source offset configuration error 1 the last recorded error was a configuration error detected in field edma_tcd[soff], indicating edma_tcd[soff] is inconsistent with edma_tcd[ssize]. dae destination address error 0 no destination address configuration error 1 the last recorded error was a configuration error detected in field edma_tcd[daddr], indicating edma_tcd[daddr] is inconsistent with edma_tcd[dsize]. doe destination offset error 0 no destination offset configuration error 1 the last recorded error was a configuration error detected in field edma_tcd[doff], indicating edma_tcd[doff] is inconsistent with edma_tcd[dsize]. nce nbytes/citer configuration error 0 no nbytes/citer configuration error 1 the last recorded error was a configuration error detected in fields edma_tcd[nbytes] or edma_tcd[citer], indicating the following conditions exist: ? edma_tcd[nbytes] is not a multiple of edma_tcd[ssize] and edma_tcd[dsize], or ? edma_tcd[citer] is equal to zero, or ? edma_tcd[citer.e_link] is not equal to edma_tcd[biter.e_link]. sge scatter-gather configuration error 0 no scatter-gather configuration error 1 the last recorded error was a configuration error detected in field edma_tcd[dlast_sga], indicating edma_tcd[dlast_sga] is not on a 32-byte boundary. this field is checked at the beginning of a scatter-gather operation after major loop completion if edma_tcd[e_sg] is enabled. table 25. edma_esr field descriptions (continued) field description enhanced direct memory access controller (edma) RM0029 194/1740 doc id 15177 rev 8 edma enable request registers (edma_erqrh, edma_erqrl) the edma_erqrh and edma_erqrl provide a bitmap for the 32 (or 64 for edma) channels to enable the request signal for each channel. edma_erqrh supports channels 63?32, while edma_erqrl covers channels 31?0. the state of any given channel enable is directly affected by writes to these registers; the state is also affected by writes to the edma_serqr and edma_cerqr. the edma_cerqr and edma_serqr are provided so that the request enable for a single channel can be modified without performing a read-modify-write sequence to the edma_erqrh and edma_erqrl. both the edma request input signal and this enable request flag must be asserted before a channel?s hardware service request is accepted. the state of the edma enable request flag does not effect a channel service request made through software or a linked channel request. sbe source bus error 0 no source bus error 1 the last recorded error was a bus error on a source read. dbe destination bus error 0 no destination bus error 1 the last recorded error was a bus error on a destination write. table 25. edma_esr field descriptions (continued) field description figure 22. edma enable request high register (edma_erqrh) address: edma_base + 0x0008 access: user r/w 0123456789101112131415 r erq63 erq62 erq61 erq60 erq59 erq58 erq57 erq56 erq55 erq54 erq53 erq52 erq51 erq50 erq49 erq48 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r erq47 erq46 erq45 erq44 erq43 erq42 erq41 erq40 erq39 erq38 erq37 erq36 erq35 erq34 erq33 erq32 w reset0000000000000000 RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 195/1740 as a given channel completes processing its major iteration count, there is a flag in the transfer control descriptor that may affect the ending state of the edma_erqr bit for that channel. if bit edma_tcd[d_req] is set, then the corresponding edma_erqr bit is cleared after the major loop is complete, disabling the edma hardware request. otherwise if the d_req bit is cleared, the state of the edma_erqr bit is unaffected. edma enable error interrupt registers (edma_eeirh, edma_eeirl) the edma_eeirh and edma_eeirl provide a bitmap for the 32 (or 64 for edma) channels to enable the error interrupt signal for each channel. edma_eeirh supports channels 63?32, while edma_eeirl covers channels 31?0. the state of any given channel?s error interrupt enable is directly affected by writes to these registers; it is also affected by writes to the edma_seeir and edma_ceeir. the edma_seeir and edma_ceeir are provided so that the error interrupt enable for a single channel can be modified without the performing a read-modify-write sequence to the edma_eeirh and edma_eeirl. both the edma error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted. figure 23. edma enable request register (edma_erqrl) offset: edma_base + 0x000c access: user read/write 0123456789101112131415 r erq31 erq30 erq29 erq28 erq27 erq26 erq25 erq24 erq23 erq22 erq21 erq20 erq19 erq18 erq17 erq16 w reset0000000000000000 16 17 19 19 20 21 22 23 24 25 26 27 28 29 30 31 r erq15 erq14 erq13 erq12 erq11 erq10 erq09 erq08 erq07 erq06 erq05 erq04 erq03 erq02 erq01 erq00 w reset0000000000000000 table 26. edma_erqrl field descriptions field description erq n enable edma hardware service request n 0 the edma request signal for channel n is disabled. 1 the edma request signal for channel n is enabled. enhanced direct memory access controller (edma) RM0029 196/1740 doc id 15177 rev 8 edma set enable request register (edma_serqr) the edma_serqr provides a simple memory-mapped mechanism to set a given bit in the edma_erqrh or edma_erqrl to enable the edma request for a given channel. the data value on a register write causes the corresponding bit in the edma_erqrh or edma_erqrl to be set. setting bit 1 (serq[0]) provides a global set function, forcing the entire contents of edma_erqrh and edma_erqrl to be asserted. reads of this register return all zeroes. if bit 0 is set, the serq command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. figure 24. edma enable error interrupt high register (edma_eeirh) address: edma_base + 0x0010 access: user read/write 0123456789101112131415 r eei63 eei62 eei61 eei60 eei59 eei58 eei57 eei56 eei55 eei54 eei53 eei52 eei51 eei50 eei49 eei48 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eei47 eei46 eei45 eei44 eei43 eei42 eei41 eei40 eei39 eei38 eei37 eei36 eei35 eei34 eei33 eei32 w reset0000000000000000 figure 25. edma enable error interrupt low register (edma_eeirl) address: edma_base + 0x0014 access: user r/w 0123456789101112131415 r eei31 eei30 eei29 eei28 eei27 eei26 eei25 eei24 eei23 eei22 eei21 eei20 eei19 eei18 eei17 eei16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eei15 eei14 eei13 eei12 eei11 eei10 eei09 eei08 eei07 eei06 eei05 eei04 eei03 eei02 eei01 eei00 w reset0000000000000000 table 27. edma_eeirl field descriptions field description eei n enable error interrupt n 0 the error signal for channel n does not generate an error interrupt. 1 the assertion of the error signal for channel n generate an error interrupt request. RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 197/1740 edma clear enable request register (edma_cerqr) the edma_cerqr provides a simple memory-mapped mechanism to clear a given bit in the edma_erqrh or edma_erqrl to disable the dma request for a given channel. the data value on a register write causes the corresponding bit in the edma_erqrh or edma_erqrl to be cleared. setting bit 1 (cerq[0]) provides a global clear function, forcing the entire contents of edma_erqrh and edma_erqrl to be zeroed, disabling all edma request inputs. reads of this register return all zeroes. if bit 0 is set, the cerq command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. figure 26. edma set enable request register (edma_serqr) offset: edma_base + 0x0018 access: user write-only 01234567 r w nop serq[0:6] reset00000000 table 28. edma_serqr field descriptions field descriptions 0 nop no operation 0 normal operation. 1 no operation, ignore bits 1?7. 1?7 serq[0:6] set enable request 0?32 (64 for edma) set corresponding bit in edma_erqrh or edma_erqrl. 64?127 set all bits in edma_erqrh and edma_erqrl. figure 27. edma clear enable request register (edma_cerqr) offset: edma_base + 0x0019 access: user write-only 01234567 r w nop cerq[0:6] reset00000000 table 29. edma_cerqr field descriptions field description 0 nop no operation 0 normal operation 1 no operation, ignore bits 1?7. 1?7 cerq[0:6] clear enable request 0?32 (64 for edma) clear corresponding bit in edma_erqrh or edma_erqrl. 64?127 clear all bits in edma_erqrh and edma_erqrl. enhanced direct memory access controller (edma) RM0029 198/1740 doc id 15177 rev 8 edma set enable error interrupt register (edma_seeir) the edma_seeir provides a memory-mapped mechanism to set a given bit in the edma_eeirh or edma_eeirl to enable the error interrupt for a given channel. the data value on a register write causes the corresponding bit in the edma_eeirh or edma_eeirl to be set. setting bit 1 (seei[0]) provides a global set function, forcing the entire contents of edma_eeirh or edma_eeirl to be asserted. reads of this register return all zeroes. if bit 0 is set, the seei command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. edma clear enable error interrupt register (edma_ceeir) the edma_ceeir provides a memory-mapped mechanism to clear a given bit in the edma_eeirh or edma_eeirl to disable the error interrupt for a given channel. the data value on a register write causes the corresponding bit in the edma_eeirh or edma_eeirl to be cleared. setting bit 1 (ceei[0]) provides a global clear function, forcing the entire contents of the edma_eeirh or edma_eeirl to be zeroed, disabling error interrupts for all channels. reads of this register return all zeroes. if bit 0 is set, the ceei command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. figure 28. edma set enable error interrupt register (edma_seeir) offset: edma_base + 0x001a access: user write-only 01234567 r w nop seei[0:6] reset00000000 table 30. edma_seeir field descriptions field description 0 nop no operation 0 normal operation 1 no operation, ignore bits 1?7. 1?7 seei[0:6] set enable error interrupt 0?32 (64 for edma) set corresponding bit in edma_eirrh or edma_eirrl. 64?127 set all bits in edma_eirrh or edma_eeirl. figure 29. edma clear enable error interrupt register (edma_ceeir) offset: edma_base + 0x001b access: user write-only 01234567 r w nop ceei[0:6] reset00000000 RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 199/1740 edma clear interrupt request register (edma_cirqr) the edma_cirqr provides a memory-mapped mechanism to clear a given bit in the edma_irqrh or edma_irqrl to disable the interrupt request for a given channel. the given value on a register write causes the corresponding bit in the edma_irqrh or edma_irqrl to be cleared. setting bit 1 (cint[0]) provides a global clear function, forcing the entire contents of the edma_irqrh or edma_irqrl to be zeroed, disabling all edma interrupt requests. reads of this register return all zeroes. if bit 0 is set, the cint command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. edma clear error register (edma_cer) the edma_cer provides a memory-mapped mechanism to clear a given bit in the edma_erh or edma_erl to disable the error condition flag for a given channel. the given value on a register write causes the corresponding bit in the edma_erh or edma_erl to be cleared. setting bit 1 (cerr[0]) provides a global clear function, forcing the entire contents of the edma_erh or edma_erl to be zeroed, clearing all channel error indicators. reads of this register return all zeroes. table 31. edma_ceeir field descriptions field description nop no operation 0 normal operation 1 no operation, ignore bits 1-7. ceei[0:6] clear enable error interrupt 0?32 (64 for edma) clear corresponding bit in edma_eeirh or edma_eeirl. 64?127 clear all bits in edma_eeirh or edma_eeirl. figure 30. edma clear interrupt request (edma_cirqr) offset: edma_base + 0x001c access: user write-only 01234567 r w nop cint[0:6] reset00000000 table 32. edma_cirqr field descriptions field description nop no operation 0 normal operation 1 no operation, ignore bits 1?7. cint[0:6] clear interrupt request 0?32 (64 for edma) clear corresponding bit in edma_irqrh or edma_irqrl. 64?127 clear all bits in edma_irqrh or edma_irqrl. enhanced direct memory access controller (edma) RM0029 200/1740 doc id 15177 rev 8 if bit 0 is set, the cerr command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. edma set start bit register (edma_ssbr) the edma_ssbr provides a memory-mapped mechanism to set the start bit in the tcd of the given channel. the data value on a register write causes the start bit in the corresponding transfer control descriptor to be set. setting bit 1 (ssb[0]) provides a global set function, forcing all start bits to be set. reads of this register return all zeroes. if bit 0 is set, the ssb command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. figure 31. edma clear error register (edma_cer) offset: edma_base + 0x001d access: user write-only 01234567 r w nop cerr[0:6] reset00000000 table 33. edma_cer field descriptions field description nop no operation 0 normal operation 1 no operation, ignore bits 1?7. cerr[0:6] clear error indicator 0?32 (64 for edma) clear corresponding bit in edma_erh or edma_erl. 64?127 clear all bits in edma_erh or edma_erl. figure 32. edma set start bit register (edma_ssbr) offset: edma_base + 0x001e access: user write-only 01234567 r w nop ssb[0:6] reset00000000 table 34. edma_ssbr field descriptions field description nop no operation 0 normal operation 1 no operation, ignore bits 1?7. ssb[0:6] set start bit (channel service request) 0?32 (64 for edma) set the corresponding channel?s tcd start bit. 64?127 set all tcd start bits. RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 201/1740 edma clear done status bit register (edma_cdsbr) the edma_cdsbr provides a memory-mapped mechanism to clear the done bit in the tcd of the given channel. the data value on a register write causes the done bit in the corresponding transfer control descriptor to be cleared. setting bit 1 (cdsb[0]) provides a global clear function, forcing all done bits to be cleared. if bit 0 is set, the cdsb command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of this register return all zeroes. edma interrupt request registers (edma_irqrh, edma_irqrl) the edma_irqrh and edma_irqrl provides a bitmap for the 32 channels signaling the presence of an interrupt request for each channel. edma_irqrh maps to channels 63?32 and edma_irqrl maps to channels 31?0. the dma engine signals the occurrence of a programmed interrupt on the completion of a data transfer as defined in the transfer control descriptor by setting the appropriate bit in this register. the outputs of this register are directly routed to the interrupt controller (intc). during the execution of the interrupt service routine associated with any given channel, software must clear the appropriate bit, negating the interrupt request. typically, a write to the edma_cirqr in the interrupt service routine is used for this purpose. the state of any given channel?s interrupt request is directly affected by writes to this register; it is also affected by writes to the edma_cirqr. on writes to the edma_irqrh or edma_irqrl, a 1 in any bit position clears the corresponding channel?s interrupt request. a 0 in any bit position has no effect on the corresponding channel?s current interrupt status. the edma_cirqr is provided so the interrupt request for a single channel can be cleared without performing a read-modify-write sequence to the edma_irqrh and edma_irqrl. figure 33. edma clear done status bit register (edma_cdsbr) offset: edma_base + 0x001f access: user write-only 01234567 r w nop cdsb[0:6] reset00000000 table 35. edma_cdsbr field descriptions field description nop no operation 0 normal operation 1 no operation, ignore bits 1?7. cdsb[0:6] clear done status bit 0?32 (64 for edma) clear the corresponding channel?s done bit. 64?127 clear all tcd done bits. enhanced direct memory access controller (edma) RM0029 202/1740 doc id 15177 rev 8 edma error registers (edma_erh, edma_erl) register edma_erh and edma_erl provide a bitmap for the 32 channels signaling the presence of an error for each channel. edma_erh supports channels 63?32 (for edma) and edma_erl maps to channels 31-0. the dma engine signals the occurrence of a error condition by setting the appropriate bit in this register. the outputs of this register are enabled by the contents of the edma_eeir, then logically summed across 32 (64 for edma) channels to form an error interrupt request, which is then routed to the interrupt controller. during the execution of the interrupt service routine associated with any edma errors, it is software?s responsibility to clear the appropriate bit, negating the error interrupt request. typically, a write to the edma_cer in the interrupt service routine is used for this purpose. the normal edma channel completion figure 34. edma interrupt request high register (edma_irqrh) address: edma_base + 0x0020 access: user r/w 0123456789101112131415 r int63 int62 int61 int60 int59 int58 int57 int56 int55 int54 int53 int52 int51 int50 int49 int48 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r int47 int46 int45 int44 int43 int42 int41 int40 int39 int38 int37 int36 int35 int34 int33 int32 w reset0000000000000000 figure 35. edma interrupt request register (edma_irqrl) address: edma_base + 0x0024 access: user read/write 0123456789101112131415 r int31 int30 int29 int28 int27 int26 int25 int24 int23 int22 int21 int20 int19 int18 int17 int16 w reset0000000000000000 16 17 19 19 20 21 22 23 24 25 26 27 28 29 30 31 r int15 int14 int13 int12 int11 int10 int09 int08 int07 int06 int05 int04 int03 int02 int01 int00 w reset0000000000000000 table 36. edma_irqrl field descriptions field description 0?31 int n edma interrupt request n 0 the interrupt request for channel n is cleared. 1 the interrupt request for channel n is active. RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 203/1740 indicators, setting the transfer control descriptor done flag and the possible assertion of an interrupt request, are not affected when an error is detected. the contents of this register can also be polled and a non-zero value indicates the presence of a channel error, regardless of the state of the edma_eeir. bit edma_esr[vld] is a logical or of all bits in this register and it provides a single bit indication of any errors. the state of any given channel?s error indicators is affected by writes to this register; it is also affected by writes to the edma_cer. on writes to edma_erh or edma_erl, a ?1? in any bit position clears the corresponding channel?s error status. a ?0? in any bit position has no effect on the corresponding channel?s current error status. the edma_cer is provided so the error indicator for a single channel can be cleared. figure 36. edma error high register (edma_erh) address: edma_base + 0x0028 access: user r/w 0123456789101112131415 r err63 err62 err61 err60 err59 err58 err57 err56 err55 err54 err53 err52 err51 err50 err49 err48 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r err47 err46 err45 err44 err43 err42 err41 err40 err39 err38 err37 err36 err35 err34 err33 err32 w reset0000000000000000 figure 37. edma error register (edma_erl) address: edma_base + 0x002c access: user read/write 0123456789101112131415 r err31 err30 err29 err28 err27 err26 err25 err24 err23 err22 err21 err20 err19 err18 err17 err16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r err15 err14 err13 err12 err11 err10 err09 err08 err07 err06 err05 err04 err03 err02 err01 err00 w reset0000000000000000 table 37. edma_erl field descriptions field description 0?31 err n edma error n 0 an error in channel n has not occurred. 1 an error in channel n has occurred. enhanced direct memory access controller (edma) RM0029 204/1740 doc id 15177 rev 8 dma hardware request status registers (edma_hrsh, edma_hrsl) registers edma_hrsh and edma_hrsl provide a bitmap for the implemented channels (32 or 64) to show the current hardware request status for each channel. edma_hrsh maps to channels 64?32 and edma_hrsl maps to channels 31-00. figure 38. edma hardware request status register high (edma_hrsh) figure 39. edma hardware request status register low (edma_hrsl) address: edma_base + 0x0030 access: user r/w 0123456789101112131415 r hrs63 hrs62 hrs61 hrs60 hrs59 hrs58 hrs57 hrs56 hrs55 hrs54 hrs53 hrs52 hrs51 hrs50 hrs49 hrs48 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hrs47 hrs46 hrs45 hrs44 hrs43 hrs42 hrs41 hrs40 hrs39 hrs38 hrs37 hrs36 hrs35 hrs34 hrs33 hrs32 w reset0000000000000000 address: edma_base + 0x0034 access: user read/write 0123456789101112131415 r hrs31 hrs30 hrs29 hrs28 hrs27 hrs26 hrs25 hrs24 hrs23 hrs22 hrs21 hrs20 hrs19 hrs18 hrs17 hrs16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hrs15 hrs14 hrs13 hrs12 hrs11 hrs10 hrs09 hrs08 hrs07 hrs06 hrs05 hrs04 hrs03 hrs02 hrs01 hrs00 w reset0000000000000000 table 38. edma_hrsl field descriptions field description 0?31 hrs n dma hardware request status 0 a hardware service request for channel n is not present. 1 a hardware service request for channel n is present. the hardware request status reflects the state of the r equest as seen by the arbitration logic. therefore, this status is affected by bit edma_erqrl[erq n ]. RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 205/1740 edma channel n priority registers (edma_cpr n ) when the fixed-priority channel arbitration mode is enabled (edma_cr[erca] = 0), the contents of these registers define the unique priorities associated with each channel. the channel priorities are evaluated by numeric value; that is, 0 is the lowest priority, 1 is the next higher priority, then 2, 3, etc. if software modifies channel priority values, then the software must ensure that the channel priorities contain unique values. otherwise, a configuration error is reported. the range of the priority value is limited to the values of 0 through 15. when read, the grppri bits of the edma_cpr n register reflect the current priority level of the group of channels in which the corresponding channel resides. grppri bits are not affected by writes to the edma_cpr n registers. the group priority is assigned in the edma_cr. see figure 20 and ta ble 24 for the edma_cr definition. channel pre-emption is enabled on a per-channel basis by setting the ecp bit in the edma_cpr n register. channel pre-emption allows the executing channel?s data transfers to be temporarily suspended in favor of starting a higher priority channel. after the pre- empting channel has completed all its minor loop data transfers, the pre-empted channel is restored and resumes execution. after the restored channel completes one read/write sequence, it is again eligible for pre-emption. if any higher priority channel requests service, the restored channel is suspended and the higher priority channel is serviced. nested pre- emption (attempting to pre-empt a pre-empting channel) is not supported. after a pre- empting channel begins execution, it cannot be pre-empted. pre-emption is available only when fixed arbitration is selected for both group and channel arbitration modes. a channel?s ability to pre-empt another channel can be disabled by setting edma_cpr[dpa]. when a channel?s pre-empt ability is disabled, that channel cannot suspend a lower priority channel?s data transfer; regardless of the lower priority channel?s ecp setting. this allows for a pool of low priority, large data moving channels to be defined. these low priority channels can be configured to not pre-empt each other, thus preventing a low priority channel from consuming the pre-empt slot normally available a true, high priority channel. figure 40. edma channel n priority register (edma_cpr n ) address: edma_base + 0x0100 + n access: user read/write 01234567 r ecp dpa grppri chpri w reset 0 0 0 0 ? (1) 1. the reset value for the channel priority field, chpri[0?3], is equal to the corresponding channel number for each priority register; that is, edma_cpri0[chpri] = 0b0000 and edma_cpr15[chpri] = 0b1111. table 39. edma_cprn field descriptions field description ecp enable channel pre-emption 0 channel n cannot be suspended by a higher priority channel?s service request. 1 channel n can be temporarily suspended by the service request of a higher priority channel. dpa disable pre-empt ability 0 channel n can suspend a lower priority channel. 1 channel n cannot suspend any channel, regardless of channel priority. enhanced direct memory access controller (edma) RM0029 206/1740 doc id 15177 rev 8 transfer control descriptor (tcd) each channel requires a 32-byte transfer control descriptor for defining the desired data movement operation. the channel descriptors are stored in the local memory in sequential order: channel 0, channel 1,... channel 31 (63 for edma). the definitions of the tcd are presented as eight 32-bit values. ta ble 40 is a field list of the basic tcd structure. figure 41 and table 41 define the fields of the tcd n structure. grppri[0:1] channel n current group priority group priority assigned to this channel group when fixed-priority arbitration is enabled. these two bits are read-only; writes are ignored. the reset value for the group priority fields, is equal to the corresponding channel number for each priority register; that is, edma_cpr31[grppri] = 0b01. chpri[0:3] channel n arbitration priority channel priority when fixed-priority arbitration is enabled. the reset value for the channel priority fields chpri[0?3], is equal to the corresponding channel number for each priority register; that is, edma_cpr31[chpri] = 0b1111. table 39. edma_cprn field descriptions (continued) field description table 40. tcd n 32-bit memory structure edma offset tcd n field 0x1000+(32 x n )+0x0000 source address (saddr) 0x1000+(32 x n )+0x0004 transfer attributes signed source address offset (soff) 0x1000+(32 x n )+0x0008 inner minor byte count (nbytes) 0x1000+(32 x n )+0x000c last source address adjustment (slast) 0x1000+(32 x n )+0x0010 destination address (daddr) 0x1000+(32 x n )+0x0014 current major iteration count (citer) signed destination address offset (doff) 0x1000 (32 x n ) 0x0018 last destination address adjustment / scatter-gather address (dlast_sga) 0x1000+(32 x n )+0x001c beginning major iteration count (biter) channel control/status RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 207/1740 note: the tcd structures for the edma channels shown in figure 41 are implemented in internal sram. these structures are not initialized at reset; therefore, all channel tcd parameters must be initialized by the application code before activating that channel. figure 41. tcd structure word offset 012345678910111213141516171819202122232425262728293031 0x0000 saddr 0x0004 smod ssize dmod dsize soff 0x0008 nbytes (1) 0x0008 smloe (1) dmloe (1) mloff or nbytes (1) nbytes 1 0x000c slast 0x0010 daddr 0x0014 citer.e_ link citer or citer.linkch citer doff 0x0018 dlast_sga 0x001c biter.e_ link biter or biter.linkch biter bwc major linkch done active major.e_link e_sg d_req int_half int_maj start 012345678910111213141516171819202122232425262728293031 1. the fields implemented in word 2 depend on whether edma_cr(emlm) is set to ?0? or ?1?. refer to table 24 . enhanced direct memory access controller (edma) RM0029 208/1740 doc id 15177 rev 8 table 41. tcdn field descriptions bits / word offset [n:n] name description 0?31 / 0x0 [0:31] saddr [0:31] source address memory address pointing to the source data. word 0x0, bits 0?31. 32?36 / 0x4 [0:4] smod [0:4] source address modulo 0 source address modulo feature is disabled. non-0 this value defines a specific address range that is specified to be the value after saddr + soff calculation is performed or the original register value. the setting of this field provides the ability to easily implement a circular data queue. for data queues requiring power-of- 2 size bytes, the queue should start at a 0-modulo-size address and the smod field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. the value programmed into this field specifies the number of lower address bits that are allowed to change. for this circular queue application, the soff is typically set to the transfer size to implement post-increment addressing with the smod function constraining the addresses to a 0- modulo-size range. 37?39 / 0x4 [5:7] ssize [0:2] source data transfer size 000 8-bit 001 16-bit 010 32-bit 011 64-bit 100 reserved 101 32-byte (64-bit, 4 beat, wrap4 burst) 110 reserved 111 reserved the attempted specification of a reserved encoding causes a configuration error. 40?44 / 0x4 [8:12] dmod [0:4] destination address modulo see the smod[0:5] definition. 45?47 / 0x4 [13:15] dsize [0:2] destination data transfer size see the ssize[0:2] definition. 48?63 / 0x4 [16:31] soff [0:15] source address signed offset sign-extended offset applied to the current source address to form the next- state value as each source read is completed. 64 0x8 [0] smloe 0 source minor loop offset enable this flag selects whether the minor loop offset is applied to the source address upon minor loop completion. 0 the minor loop offset is not applied to the saddr. 1 the minor loop offset is applied to the saddr. RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 209/1740 65 0x8 [1] dmloe 1 destination minor loop offset enable this flag selects whether the minor loop offset is applied to the destination address upon minor loop completion. 0 the minor loop offset is not applied to the daddr. 1 the minor loop offset is applied to the daddr. 66?85 0x8 [2-21] mloff or nbytes [0:19] inner ?minor? byte transfer count or minor loop offset if both smloe and dmloe are cleared, this field is part of the byte transfer count. if either smloe or dmloe are set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop is completed. 86?95 / 0x8 [22:31] nbytes inner ?minor? byte transfer count number of bytes to be transferred in each service request of the channel. as a channel is activated, the contents of the appropriate tcd is loaded into the edma engine, and the appropriate reads and writes performed until the complete byte transfer count has been transferred. this is an indivisible operation and cannot be stalled or halted. once the minor count is exhausted, the current values of the saddr and daddr are written back into the local memory, the major iteration count is decremented and restored to the local memory. if the major iteration count is completed, additional processing is performed. the nbytes value of 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a 4 gb transfer. 96?127 / 0xc [0:31] slast [0:31] last source address adjustment adjustment value added to the source address at the completion of the outer major iteration count. this value can be applied to ?restore? the source address to the initial value, or adjust the address to reference the next data structure. 128?159 / 0x10 [0:31] daddr [0:31] destination address memory address pointing to the destination data. 160 / 0x14 [0] citer.e_link enable channel-to-channel linking on minor loop completion as the channel completes the inner minor loop, this flag enables the linking to another channel, defined by citer.linkch[0:5]. the link target channel initiates a channel service request via an internal mechanism that sets the bit edma_tcd[start] of the specified channel. if channel linking is disabled, the citer value is extended to 15 bits in place of a link channel number. if the major loop is exhausted, this link mechanism is suppressed in favor of the major.e_link channel linking. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. this bit must be equal to the biter.e_link bit. otherwise, a configuration error is reported. table 41. tcdn field descriptions (continued) bits / word offset [n:n] name description enhanced direct memory access controller (edma) RM0029 210/1740 doc id 15177 rev 8 161?166 / 0x14 [1:6] citer [0:5] or citer.linkch [0:5] current major iteration count or link channel number if channel-to-channel linking is disabled (edma_tcd[citer.e_link] = 0), then ? no channel-to-channel linking (or chaining) is performed after the inner minor loop is exhausted. tcd bits [161:175] are used to form a 15-bit citer field. otherwise, ? after the minor loop is exhausted, the dma engine initiates a channel service request at the channel defined by citer.linkch[0:5] by setting that channel?s edma_tcd[start] bit. 167?175 / 0x14 [7:15] citer [6:14] current major iteration count this 9 or 15-bit count represents the current major loop count for the channel. it is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. after the major iteration count is exhausted, the channel performs a number of operations (for example, final source and destination address calculations), optionally generating an interrupt to signal channel completion before reloading the citer field from the beginning iteration count (biter) field. when the citer field is initially loaded by software, it must be set to the same value as that contained in the biter field. if the channel is configured to execute a single service request, the initial values of biter and citer should be 0x0001. 176?191 / 0x14 [16:31] doff [0:15] destination address signed offset sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. 192?223 / 0x18 [0:31] dlast_sga [0:31] last destination address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter-gather). if scatter-gather processing for the channel is disabled (edma_tcd[e_sg] = 0) then ? adjustment value added to the destination address at the completion of the outer major iteration count. this value can be applied to restore the destination address to the initial value, or adjust the address to reference the next data structure. otherwise, ? this address points to the beginning of a 0-modulo-32 byte region containing the next transfer control descriptor to be loaded into this channel. this channel reload is performed as the major iteration count completes. the scatter-gather address must be 0-modulo-32 byte, otherwise a configuration error is reported. table 41. tcdn field descriptions (continued) bits / word offset [n:n] name description RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 211/1740 224 / 0x1c [0] biter.e_link enables channel-to-channel linking on minor loop complete as the channel completes the inner minor loop, this flag enables the linking to another channel, defined by biter.linkch[0:5]. the link target channel initiates a channel service request via an internal mechanism that sets the bit edma_tcd[start] of the specified channel. if channel linking is disabled, the biter value is extended to 15 bits in place of a link channel number. if the major loop is exhausted, this link mechanism is suppressed in favor of the major.e_link channel linking. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. when the tcd is first loaded by software, this field must be set equal to the corresponding citer field. otherwise, a configuration error is reported. as the major iteration count is exhausted, the contents of this field is reloaded into the citer field. 225?230 / 0x1c [1:6] biter [0:5] or biter.linkch[0:5] starting major iteration count or link channel number if channel-to-channel linking is disabled (edma_tcd[biter.e_link] = 0), then ? no channel-to-channel linking (or chaining) is performed after the inner minor loop is exhausted. tcd bits [225:239] are used to form a 15-bit biter field. otherwise, ? after the minor loop is exhausted, the dma engine initiates a channel service request at the channel, defined by biter.linkch[0:5], by setting that channel?s edma_tcd[start] bit. when the tcd is first loaded by software, this field must be set equal to the corresponding citer field. otherwise, a configuration error is reported. as the major iteration count is exhausted, the contents of this field is reloaded into the citer field. 231?239 / 0x1c [7:15] biter [6:14] starting major iteration count as the transfer control descriptor is first loaded by software, this field must be equal to the value in the citer field. as the major iteration count is exhausted, the contents of this field are reloaded into the citer field. if the channel is configured to execute a single service request, the initial values of biter and citer should be 0x0001. 240?241 / 0x1c [16:17] bwc [0:1] bandwidth control this two-bit field provides a mechanism to effectively throttle the amount of bus bandwidth consumed by the edma. in general, as the edma processes the inner minor loop, it continuously generates read/write sequences until the minor count is exhausted. this field forces the edma to stall after the completion of each read/write access to control the bus request bandwidth seen by the system bus crossbar switch (xbar). 00 no dma engine stalls 01 reserved 10 dma engine stalls for 4 cycles after each r/w 11 dma engine stalls for 8 cycles after each r/w table 41. tcdn field descriptions (continued) bits / word offset [n:n] name description enhanced direct memory access controller (edma) RM0029 212/1740 doc id 15177 rev 8 242?247 / 0x1c [18:23] major.linkch [0:5] link channel number if channel-to-channel linking on major loop complete is disabled (edma_tcd[major.e_link] = 0) then, ? no channel-to-channel linking (or chaining) is performed after the outer major loop counter is exhausted. otherwise ? after the major loop counter is exhausted, the dma engine initiates a channel service request at the channel defined by major.linkch[0:5] by setting that channel?s edma_tcd[start] bit. 248 / 0x1c [24] done channel done this flag indicates the edma has completed the outer major loop. it is set by the dma engine as the citer count reaches zero; it is cleared by software or hardware when the channel is activated (when the dma engine has begun processing the channel, not when the first data transfer occurs). this bit must be cleared to write the major.e_link or e_sg bits. 249 / 0x1c [25] active channel active this flag signals the channel is currently in execution. it is set when channel service begins, and is cleared by the dma engine as the inner minor loop completes or if any error condition is detected. 250 / 0x1c [26] major.e_link enable channel-to-channel linking on major loop completion as the channel completes the outer major loop, this flag enables the linking to another channel, defined by major.linkch[0:5]. the link target channel initiates a channel service request via an internal mechanism that sets bit edma_tcd[start] of the specified channel. to support the dynamic linki ng coherency model, this field is forced to zero when written to while the bit edma_tcd[done] is set. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. 251 / 0x1c [27] e_sg enable scatter-gather processing as the channel completes the outer major loop, this flag enables scatter- gather processing in the current channel. if enabled, the dma engine uses dlast_sga as a memory pointer to a 0-modulo-32 address containing a 32-byte data structure which is loaded as the transfer control descriptor into the local memory. to support the dynamic scatter-gather c oherency model, this field is forced to zero when written to while the bit edma_tcd[done] is set. 0 the current channel?s tcd is normal format. 1 the current channel?s tcd specifies a scatter gather format. the dlast_sga field provides a memory pointer to the next tcd to be loaded into this channel after the outer major loop completes its execution. table 41. tcdn field descriptions (continued) bits / word offset [n:n] name description RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 213/1740 8.4 functional description this section provides an overview of the microarchitecture and functional operation of the edma block. the edma module is partitioned into two major modules: the dma engine and the transfer control descriptor local memory. the dma engine is further partitioned into four submodules, which are detailed below. dma engine ? address path: this module implements registered versions of two channel transfer control descriptors: channel x and channel y, and is responsible for all the master bus address calculations. all the implemented channels provide the same functionality. this hardware structure allows the data transfers associated with one channel to be pre-empted after the completion of a read/write sequence if a higher 252 / 0x1c [28] d_req disable hardware request if this flag is set, the edma hardware automatically clears the corresponding edma_erqh or edma_erql bit when the current major iteration count reaches zero. 0 the channel?s edma_erqh or edma_erql bit is not affected. 1 the channel?s edma_erqh or edma_erql bit is cleared when the outer major loop is complete. 253 / 0x1c [29] int_half enable an interrupt when major counter is half complete if this flag is set, the channel generates an interrupt request by setting the appropriate bit in the edma_erqh or edma_erql when the current major iteration count reaches the halfway point. specifically, the comparison performed by the edma engine is (citer == (biter >> 1)). this halfway point interrupt request is provided to support double-buffered (aka ping- pong) schemes, or other types of data movement where the processor needs an early indication of the transfer?s progress. citer = biter = 1 with int_half enabled will generate an interrupt as it satisfies the equation (citer == (biter >> 1)) after a single activation. 0 the half-point interrupt is disabled. 1 the half-point interrupt is enabled. 254 / 0x1c [30] int_maj enable an interrupt when major iteration count completes if this flag is set, the channel generates an interrupt request by setting the appropriate bit in the edma_erqh or edma_erql when the current major iteration count reaches zero. 0 the end-of-major loop interrupt is disabled. 1 the end-of-major loop interrupt is enabled. 255 / 0x1c [31] start channel start if this flag is set the channel is requesting service. the edma hardware automatically clears this flag after the channel begins execution. 0 the channel is not explicitly started. 1 the channel is explicitly started via a software initiated service request. table 41. tcdn field descriptions (continued) bits / word offset [n:n] name description enhanced direct memory access controller (edma) RM0029 214/1740 doc id 15177 rev 8 priority channel service request is asserted while the first channel is active. after a channel is activated, it runs until the minor loop is completed unless pre-empted by a higher priority channel. this capability provides a mechanism (optionally enabled by edma_cpr n [ecp]) where a large data move operation can be pre- empted to minimize the time another channel is blocked from execution. ? when another channel is activated, the contents of its transfer control descriptor is read from the local memory and loaded into the registers of the other address path channel{x,y}. after the inner minor loop completes execution, the address path hardware writes the new values for the tcd n .{saddr, daddr, citer} back into the local memory. if the major iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the tcdn.citer field, and a possible fetch of the next tcd n from memory as part of a scatter-gather operation. ? data path: this module implements the actual bus master read/write datapath. it includes 32 bytes of register storage (matching the maximum transfer size) and the necessary mux logic to support any required data alignment. the system read data bus is the primary input, and the system write data bus is the primary output. ? the address and data path modules directly support the two-stage pipelined system bus. the address path module represents the 1st stage of the bus pipeline (the address phase), while the data path module implements the second stage of the pipeline (the data phase). ? program model/channel arbitration: this module implements the first section of edma?s programming model and also the channel arbitration logic. the programming model registers are connected to the slave bus (not shown). the edma peripheral request inputs and edma interrupt request outputs are also connected to this module (via the control logic). ? control: this module provides all the control functions for the dma engine. for data transfers where the source and destination sizes are equal, the dma engine performs a series of source read, destination write operations until the number of bytes specified in the inner minor loop byte count has been moved. a minor loop interaction is defined as the number of bytes to transfer ( n bytes) divided by the transfer size. transfer size is defined as: if (ssize < dsize) transfer size = destination transfer size (# of bytes) else transfer size = source transfer size (# of bytes) minor loop tcd variables are soff, smod, doff, dmod, nbytes, saddr, daddr, bwc, active, and start. major loop tcd variables are dlast, slast, citer, biter, done, d_req, int_maj, major_lnkch, and int_half. for descriptors where the sizes are not equal, multiple access of the smaller size data are required for each reference of the larger size. for example, if the source size references 16-bit data and the destination is 32-bit data, two reads are performed, then one 32-bit write. tcd local memory ? memory controller: this logic implements the required dual-ported controller, handling accesses from both the dma engine as well as references from the slave bus. as noted earlier, in the event of simultaneous accesses, the dma engine is RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 215/1740 given priority and the slave transaction is stalled. the hooks to a bist controller for the local tcd memory are included in this module. ? memory array: the tcd is implemented using a single-ported, synchronous compiled ram memory array. 8.4.1 edma basic data flow the edma transfers data based on a two-deep, nested flow. the basic flow of a data transfer can be partitioned into three segments. as shown in figure 42 , the first segment involves the channel service request. in the diagram, this example uses the assertion of the edma peripheral request signal to request service for channel n . channel service request via software and the tcdn.start bit follows the same basic flow as an edma peripheral request. the edma peripheral request input signal is registered internally and then routed to through the dma engine, first through the control module, then into the program model/channel arbitration module. in the next cycle, the channel arbitration is performed using the fixed-priority or round-robin algorithm. after the arbitration is complete, the activated channel number is sent through the address path and converted into the required address to access the tcd local memory. next, the tcd memory is accessed and the required descriptor read from the local memory and loaded into the dma engine address path channel{x,y} registers. the tcd memory is organized 64-bits in width to minimize the time needed to fetch the activated channel?s descriptor and load it into the edma engine address path channel{x,y} registers. enhanced direct memory access controller (edma) RM0029 216/1740 doc id 15177 rev 8 figure 42. edma operation, part 1 in the second part of the basic data flow as shown in figure 43 , the modules associated with the data transfer (address path, data path, and control) sequence through the required source reads and destination writes to perform the actual data movement. the source reads are initiated and the fetched data is temporarily stored in the data path module until it is gated onto the system bus during the destination write. this source read/destination write processing continues until the inner minor byte count has been transferred. the edma done handshake signal is asserted at the end of the minor byte count transfer. slave interface edma edma peripheral request system bus data path control address program model/ slave write data slave write address bus write data slave read data bus address edma engine tcd0 tcd n ?1* edma interrupt request bus read data channel arbitration edma done handshake path sram transfer control descriptor ( tcd ) sram * n = 32 (64 for edma) channels RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 217/1740 figure 43. edma operation, part 2 after the inner minor byte count has been moved, the final phase of the basic data flow is performed. in this segment, the address path logic performs the required updates to certain fields in the channel?s tcd; for example, saddr, daddr, citer. if the outer major iteration count is exhausted, then there are additional operations performed. these include the final address adjustments and reloading of the biter field into the citer. additionally, assertion of an optional interrupt request occurs at this time, as does a possible fetch of a new tcd from memory using the scatter-gather address pointer included in the descriptor. the updates to the tcd memory and the assertion of an interrupt request are shown in figure 44 . slave interface edma edma interrupt request system bus program model/ slave write data slave write address bus write data slave read data bus address edma engine tcd0 tcd n? 1* edma peripheral bus read data channel arbitration request sram transfer control descriptor (tcd) sram data path control address path edma done handshake * n = 32 (64 for edma) channels enhanced direct memory access controller (edma) RM0029 218/1740 doc id 15177 rev 8 figure 44. edma operation, part 3 8.5 initialization / application information 8.5.1 edma initialization a typical initialization of the edma has the following sequence: 1. write the edma_cr if a configuration other than the default is desired. 2. write the channel priority levels into the edma_cpr n registers if a configuration other than the default is desired. 3. enable error interrupts in the edma_eeirl and/or edma_eeirh registers if desired. 4. write the 32-byte tcd for each channel that may request service. 5. enable any hardware service requests via the edma_erqrh and/or edma_erqrl registers. 6. request channel service by software (setting bit edma_tcd[start]) or by hardware (slave device asserting its dma peripheral request signal). slave interface edma edma done system bus slave write data slave write address bus write data slave read data bus address edma engine tcd0 tcd n? 1* edma peripheral bus read data request sram transfer control descriptor (tcd) sram data path address path control program model/ channel arbitration * n = 32 (64 for edma) channels RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 219/1740 after any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model. the dma engine reads the entire tcd, including the primary transfer control parameter shown in table 42 , for the selected channel into its internal address path module. as the tcd is being read, the first transfer is initiated on the system bus unless a configuration error is detected. transfers from the source (as defined by the source address, edma_tcd[saddr]) to the destination (as defined by the destination address, ed ma_tcd.daddr) continue until the specified number of bytes (edma_tcd[nbytes]) have been transferred. when the transfer is complete, the dma engine's local edma_tcd[saddr], edma_tcd.daddr, and edma_tcd.citer are written back to the main tcd memory and any minor loop channel linking is performed, if enabled. if the major loop is exhausted, further post processing is executed; for example, interrupts, major loop channel linking, and scatter-gather operations, if enabled. figure 45 shows how each dma request initiates one minor loop transfer (iteration) without cpu intervention. dma arbitration can occur after each minor loop, and one level of minor loop dma pre-emption is allowed. the number of minor loops in a major loop is specified by the beginning iteration count (biter). table 42. tcd primary control and status fields tcd field name description start control bit to start channel when using a software initiated dma service (automatically cleared by hardware) active status bit indicating the channel is currently in execution done status bit indicating major loop completion (cleared by software when using a software initiated dma service) d_req control bit to disable dma request at end of major loop completion when using a hardware-initiated dma service bwc control bits for throttling bandwidth control of a channel e_sg control bit to enable scatter-gather feature int_half control bit to enable interrupt when major loop is half complete int_maj control bit to enable interrupt when major loop completes enhanced direct memory access controller (edma) RM0029 220/1740 doc id 15177 rev 8 figure 45. example of multiple loop iterations figure 46 lists the memory array terms and how the tcd settings interrelate. figure 46. memory array terms 8.5.2 dma programming errors the dma performs various tests on the transfer control descriptor to verify consistency in the descriptor data. most programming errors are reported on a per-channel basis with the dma request minor loop 3 current major loop iteration count (citer) example memory array ? ? ? dma request minor loop 2 ? ? ? dma request minor loop 1 ? ? ? major loop xaddr: (starting address) xsize: (size of one data minor loop (nbytes in minor loop, often the same value as xsize) offset (xoff): number of bytes added to current address after each transfer (often the same value as xsize) ? minor loop each dma source (s) and destination (d) has its own: ? address (xaddr) ? size (xsize) ? offset (xoff) xlast: number of bytes added to current address peripheral queues typically have size and offset equal to nbytes ? ? after major loop (typically used to loop back) transfer) ? ? ? ? ? ? last minor loop ? modulo (xmod) ? last address adjustment (xlast) where x = s or d ? ? ? RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 221/1740 exception of two errors: group-priority error and channel-priority error, or edma_esr[gpe] and edma_esr[cpe], respectively. for all error types other than group- or channel-priority errors, the channel number causing the error is recorded in the edma_esr. if the error source is not removed before the next activation of the problem channel, the error is detected and recorded again. channel-priority errors are identified within a group after that group has been selected as the active group. for example, all of the channel priorities in group 1 are unique, but some of the channel priorities in group 0 are the same: 1. the dma is configured for fixed-group and fixed-channel arbitration modes. 2. group 1 is the highest priority and all channels are unique in that group. 3. group 0 is the next highest priority and has two channels with the same priority level. 4. if group 1 has any service requests, those requests are executed. 5. after all of group 1 requests have completed, group 0 becomes the next active group. 6. if group 0 has a service request, then an undefined channel in group 0 is selected and a channel-priority error will occur. 7. this repeats until the all of group 0 requests have been removed or a higher priority group 1 request comes in. in this sequence, for item 2, the dma acknowledge lines assert only if the selected channel is requesting service via the dma peripheral request signal. if interrupts are enabled for all channels, the user receives an error interrupt, but the channel number for the edma_er and the error interrupt request line are undetermined because they reflect the undefined channel. a group-priority error is global and any request in any group causes a group- priority error. if priority levels are not unique, the highest (channel/group) priority that has an active request is selected, but the lowest numbered (channel/group) with that priority is selected by arbitration and executed by the dma engine. the hardware service request handshake signals, error interrupts, and error reporting are associated with the selected channel. 8.5.3 dma request assignments the assignments between the dma requests from the modules to the channels of the edma are shown in ta ble 43 . the source column is written in c language syntax. the syntax is module_instance.register[bit]. table 43. dma request summary for edma dma request channel source description eqadc_fisr0_cfff0 0 eqadc.fisr0[cfff0] eqadc command fifo 0 fill flag eqadc_fisr0_rfdf0 1 eqadc.fisr0[rfdf0] eqadc receive fifo 0 drain flag eqadc_fisr1_cfff1 2 eqadc.fisr1[cfff1] eqadc command fifo 1 fill flag eqadc_fisr1_rfdf1 3 eqadc.fisr1[rfdf1] eqadc receive fifo 1 drain flag eqadc_fisr2_cfff2 4 eqadc.fisr2[cfff2] eqadc command fifo 2 fill flag eqadc_fisr2_rfdf2 5 eqadc.fisr2[rfdf2] eqadc receive fifo 2 drain flag eqadc_fisr3_cfff3 6 eqadc.fisr3[cfff3] eqadc command fifo 3 fill flag eqadc_fisr3_rfdf3 7 eqadc.fisr3[rfdf3] eqadc receive fifo 3 drain flag enhanced direct memory access controller (edma) RM0029 222/1740 doc id 15177 rev 8 eqadc_fisr4_cfff4 8 eqadc.fisr4[cfff4] eqadc command fifo 4 fill flag eqadc_fisr4_rfdf4 9 eqadc.fisr4[rfdf4] eqadc receive fifo 4 drain flag eqadc_fisr5_cfff5 10 eqadc.fisr5[cfff5] eqadc command fifo 5 fill flag eqadc_fisr5_rfdf5 11 eqadc.fisr5[rfdf5] eqadc receive fifo 5 drain flag dspib_sr_tfff 12 dspib.sr[tfff] dspib transmit fifo fill flag dspib_sr_rfdf 13 dspib.sr[rfdf] dspib receive fifo drain flag dspic_sr_tfff 14 dspic.sr[tfff] dspic transmit fifo fill flag dspic_sr_rfdf 15 dspic.sr[rfdf] dspic receive fifo drain flag dspid_sr_tfff 16 dspid.sr[tfff] dspid transmit fifo fill flag dspid_sr_rfdf 17 dspid.sr[rfdf] dspid receive fifo drain flag escia_combtx 18 escia.sr[tdre] || escia.sr[tc] || escia.sr[txrdy] escia combined dma request of the transmit data register empty, transmit complete, and lin transmit data ready dma requests escia_combrx 19 escia.sr[rdrf] || escia.sr[rxrdy] escia combined dma request of the receive data register full and lin receive data ready dma requests emios_gfr_f0 20 emios.gfr[f0] emios channel 0 flag emios_gfr_f1 21 emios.gfr[f1] emios channel 1 flag emios_gfr_f2 22 emios.gfr[f2] emios channel 2 flag emios_gfr_f3 23 emios.gfr[f3] emios channel 3 flag emios_gfr_f4 24 emios.gfr[f4] emios channel 4 flag emios_gfr_f8 25 emios.gfr[f8] emios channel 8 flag emios_gfr_f9 26 emios.gfr[f9] emios channel 9 flag etpu_cdtrsr_a_dtrs0 27 etpu.cdtrsr_a[dtrs0] etpua channel 0 data transfer request status etpu_cdtrsr_a_dtrs1 28 etpu.cdtrsr_a[dtrs1] etpua channel 1 data transfer request status etpu_cdtrsr_a_dtrs2 29 etpu.cdtrsr_a[dtrs2] etpua channel 2 data transfer request status etpu_cdtrsr_a_dtrs14 30 etpu.cdtrsr_a[dtrs14] etpua channel 14 data transfer request status etpu_cdtrsr_a_dtrs15 31 etpu.cdtrsr_a[dtrs15] etpua channel 15 data transfer request status no request 32 ? no request 33 ? table 43. dma request summary for edma (continued) dma request channel source description RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 223/1740 escib_combtx 34 escib.sr[tdre] || escib.sr[tc] || escib.sr[txrdy] escib combined dma request of the transmit data register empty, transmit complete, and lin transmit data ready dma requests escib_combrx 35 escib.sr[rdrf] || escib.sr[rxrdy] escib combined dma request of the receive data register full and lin receive data ready dma requests emios_gfr_f6 36 emios.gfr[f6] emios channel 6 flag emios_gfr_f7 37 emios.gfr[f7] emios channel 7 flag emios_gfr_f10 38 emios.gfr[f10] emios channel 10 flag emios_gfr_f11 39 emios.gfr[f11] emios channel 11 flag emios_gfr_f16 40 emios.gfr[f16] emios channel 16 flag emios_gfr_f17 41 emios.gfr[f17] emios channel 17 flag emios_gfr_f18 42 emios.gfr[f18] emios channel 18 flag emios_gfr_f19 43 emios.gfr[f19] emios channel 19 flag etpu_cdtrsr_a_dtrs12 44 etpu.cdtrsr_a[dtrs12] etpua channel 12 data transfer request status etpu_cdtrsr_a_dtrs13 45 etpu.cdtrsr_a[dtrs13] etpua channel 13 data transfer request status etpu_cdtrsr_a_dtrs28 46 etpu.cdtrsr_a[dtrs28] etpua channel 28 data transfer request status etpu_cdtrsr_a_dtrs29 47 etpu.cdtrsr_a[dtrs29] etpua channel 29 data transfer request status siu_eisr_eif0 48 siu.siu_eisr[eif0] siu external interrupt flag 0 siu_eisr_eif1 49 siu.siu_eisr[eif1] siu external interrupt flag 1 siu_eisr_eif2 50 siu.siu_eisr[eif2] siu external interrupt flag 2 siu_eisr_eif3 51 siu.siu_eisr[eif3] siu external interrupt flag 3 decfil_fill_buf_a 52 decfil_a.decfilter_ib[inpb uf] decimation filter a fill buffer decfil_drain_buf_a 53 decfil_a.decfilter_ob[out buf] decimation filter a drain buffer decfil_fill_buf_b 54 decfil_b.decfilter_ib[inpb uf] decimation filter b fill buffer decfil_drain_buf_b 55 decfil_b.decfilter_ob[out buf] decimation filter b drain buffer escic_combtx 56 escic.sr[tdre] || escic.sr[tc] || escic.sr[txrdy] escic combined dma request of the transmit data register empty, transmit complete, and lin transmit data ready dma requests table 43. dma request summary for edma (continued) dma request channel source description enhanced direct memory access controller (edma) RM0029 224/1740 doc id 15177 rev 8 8.5.4 dma arbitration mode considerations fixed-group arbitration, fixed-channel arbitration in this mode, the channel service request from the highest priority channel in the highest priority group is selected to execute. if the edma is programmed so the channels within one group use fixed priorities, and that group is assigned the highest fixed priority of all groups, it is possible for that group to take all the bandwidth of the edma controller. that is, no other groups can be serviced if there is always at least one dma request pending on a channel in the highest priority group when the controller arbitrates the next dma request. the advantage of this scenario is that latency can be small for channels that need to be serviced quickly. pre-emption is available in this scenario only. round-robin group arbitration, fixed-channel arbitration when one or more dma requests arrive from one or more groups, the channel with the highest priority from a specific group is serviced first. groups are serviced starting with the highest group number with a service request and rotating through to the lowest group number containing a service request. after the channel request is serviced, the group round robin algorithm selects the highest pending request from the next group in the round-robin sequence. servicing continues round robin, always servicing the highest priority channel in the next group in the sequence, or skipping a group if it has no pending requests. if a channel requests service at a rate that equals or exceeds the round robin service rate, then that channel is always serviced before lower priority channels in the same group, and the lower priority channels are never serviced. the advantage of this scenario is that no one group can consume all the edma bandwidth. the highest priority channel selection latency is potentially greater than fixed/fixed arbitration. excessive request rates on high-priority channels can prevent the servicing of lower priority channels in the same group. round-robin group arbitration, round-robin channel arbitration groups are serviced as described in section , round-robin group arbitration, fixed-channel arbitration but this time channels are serviced in channel number order. one channel only is serviced from each requesting group for each round robin pass through the groups. within each group, channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to channel priority levels. because channels are serviced in round-robin manner, any channel that generates dma requests faster than a combination of the group round-robin service rate and the channel service rate for its group does not prevent the servicing of other channels in its group. any dma requests that are not serviced are simply lost, but at least one channel gets serviced. escic_combrx 57 escib.sr[rdrf] || escib.sr[rxrdy] escic combined dma request of the receive data register full and lin receive data ready dma requests no request 58-63 ? table 43. dma request summary for edma (continued) dma request channel source description RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 225/1740 this scenario ensures that all channels are guaranteed service at some point, regardless of the request rates. however, the potential latency could be high. all channels are treated equally. priority levels are not used in round-robin/round-robin mode. fixed-group arbitration, round-robin channel arbitration the highest priority group with a request is serviced. lower priority groups are serviced if no pending requests exist in the higher priority groups. within each group, channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels assigned within the group. this scenario could cause the same bandwidth consumption problem as indicated in section , fixed-group arbitration, fixed-channel arbitration but all the channels in the highest priority group get serviced. service latency is short on the highest priority group, but could potentially get longer and longer as the group priority decreases. 8.5.5 dma transfer single request to perform a simple transfer of n bytes of data with one activation, set the major loop to ?1? (edma_tcd[citer] = edma_tcd[biter] = 1). the data transfer begins after the channel service request is acknowledged and the channel is selected to execute. after the transfer is complete, bit edma_tcd[done] is set and an interrupt is generated if properly enabled. for example, the following tcd entry is configured to transfer 16 bytes of data. the edma is programmed for one iteration of the major loop transferring 16 bytes per iteration. the source memory has a byte wide memory port located at 0x1000. the destination memory has a word wide port located at 0x2000. the address offsets are programmed in increments to match the size of the transfer; one byte for the source and four bytes for the destination. the final source and destination addresses are adjusted to return to their beginning values. edma_tcd[citer] = edma_tcd[biter] = 1 edma_tcd[nbytes] = 16 edma_tcd[saddr] = 0x1000 edma_tcd[soff] = 1 edma_tcd[ssize] = 0 edma_tcd[slast] = ?16 edma_tcd[daddr] = 0x2000 edma_tcd[doff] = 4 edma_tcd[dsize] = 2 edma_tcd[dlast_sga] = ?16 edma_tcd[int_maj] = 1 edma_tcd[start] = 1 (must be written last after all other fields have been initialized) all other tcd fields = 0 this would generate the following sequence of events: enhanced direct memory access controller (edma) RM0029 226/1740 doc id 15177 rev 8 1. slave write to the edma_tcd[start] bit requests channel service. 2. the channel is selected by arbitration for servicing. 3. edma engine writes: edma_tcd[done] = 0, edma_tcd[start] = 0, edma_tcd[active] = 1. 4. edma engine reads: channel tcd data from local memory to internal register file. 5. the source to destination transfers are executed as follows: a) read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003) b) write_word(0x2000) ? first iteration of the minor loop c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007) d) write_word(0x2004) ? second iteration of the minor loop e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b) f) write_word(0x2008) ? third iteration of the minor loop g) read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f) h) write_word(0x200c) ? last iteration of the minor loop ? major loop complete 6. edma engine writes: edma_tcd[saddr] = 0x1000, edma_tcd[daddr] = 0x2000, edma_tcd[citer] = 1 (edma_tcd[biter]). 7. edma engine writes: edma_tcd[active] = 0, edma_tcd[done] = 1, edma_irqr n =1. 8. the channel retires. the edma goes idle or services the next channel. multiple requests the next example is the same as previous, excepting transferring 32 bytes via two hardware requests. the only fields that change are the major loop iteration count and the final address offsets. the edma is programmed for two iterations of the major loop transferring 16 bytes per iteration. after the channel?s hardware requests are enabled in the edma_erqr, channel service requests are initiated by the slave device (erqr should be set after tcd). note that edma_tcd[start] = 0. edma_tcd[citer = edma_tcd[biter] = 2 edma_tcd[nbytes] = 16 edma_tcd[saddr] = 0x1000 edma_tcd[soff] = 1 edma_tcd[ssize] = 0 edma_tcd[slast] = ?32 edma_tcd[daddr] = 0x2000 edma_tcd[doff] = 4 edma_tcd[dsize] = 2 edma_tcd[dlast_sga] = ?32 edma_tcd[int_maj] = 1 edma_tcd[start] = 0 (must be written last after all other fields have been initialized) all other tcd fields = 0 this generates the following sequence of events: RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 227/1740 1. first hardware (edma peripheral request) request for channel service. 2. the channel is selected by arbitration for servicing. 3. edma engine writes: edma_tcd[done] = 0, edma_tcd[start] = 0, edma_tcd[active] = 1. 4. edma engine reads: channel tcd data from local memory to internal register file. 5. the source to destination transfers are executed as follows: a) read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003) b) write_word(0x2000) ? first iteration of the minor loop c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007) d) write_word(0x2004) ? second iteration of the minor loop e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b) f) write_word(0x2008) ? third iteration of the minor loop g) read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f) h) write_word(0x200c) ? last iteration of the minor loop 6. edma engine writes: edma_tcd[saddr] = 0x1010, edma_tcd[daddr] = 0x2010, edma_tcd[citer] = 1. 7. edma engine writes: edma_tcd[active] = 0. 8. the channel retires ? one iteration of the major loop. the edma goes idle or services the next channel. 9. second hardware (edma peripheral request) requests channel service. 10. the channel is selected by arbitration for servicing. 11. edma engine writes: edma_tcd[done] = 0, edma_tcd[start] = 0, edma_tcd[active] = 1. 12. edma engine reads: channel tcd data from local memory to internal register file. 13. the source to destination transfers are executed as follows: a) read_byte(0x1010), read_byte(0x1011), read_byte(0x1012), read_byte(0x1013) b) write_word(0x2010) ? first iteration of the minor loop c) read_byte(0x1014), read_byte(0x1015), read_byte(0x1016), read_byte(0x1017) d) write_word(0x2014) ? second iteration of the minor loop e) read_byte(0x1018), read_byte(0x1019), read_byte(0x101a), read_byte(0x101b) f) write_word(0x2018) ? third iteration of the minor loop g) read_byte(0x101c), read_byte(0x101d), read_byte(0x101e), read_byte(0x101f) h) write_word(0x201c) ? last iteration of the minor loop ? major loop complete 14. edma engine writes: edma_tcd[saddr] = 0x1000, edma_tcd[daddr] = 0x2000, edma_tcd[citer] = 2 (edma_tcd[biter]). 15. edma engine writes: edma_tcd[active] = 0, edma_tcd[done] = 1, edma_irqr n =1. 16. the channel retires ? major loop complete. the edma goes idle or services the next channel. modulo feature the modulo feature of the edma provides the ability to implement a circular data queue in which the size of the queue is a power of two. mod is a 5-bit bitfield for both the source and enhanced direct memory access controller (edma) RM0029 228/1740 doc id 15177 rev 8 destination in the tcd and specifies which lower address bits are allowed to increment from their original value after the address + offset calculation. all upper address bits remain the same as in the original value. a setting of 0 for this field disables the modulo feature. ta ble 44 shows how the transfer addresses are specified based on the setting of the mod field. here a circular buffer is created where the address wraps to the original value while the 28 upper address bits (0x1234567x) retain their original value. in this example the source address is set to 0x12345670, the offset is set to 4 bytes and the mod field is set to 4, allowing for a 2 4 byte (16-byte) size queue. 8.5.6 tcd status minor loop complete there are two methods to test for minor loop completion when using software initiated service requests. the first method is to read the field edma_tcd[citer] and test for a change. another method may be extracted from the sequence below. the second method is to test the bit edma_tcd[start] and the bit edma_tcd[active]. the minor loop complete condition is indicated by both bits reading zero after edma_tcd[start] was written to a ?1?. polling the edma_tcd[active] bit may be inconclusive because the active status may be missed if the channel execution is short in duration. the tcd status bits execute the following sequence for a software activated channel: 1. edma_tcd[start] = 1, edma_tcd[active] = 0, edma_tcd[done] = 0 (channel service request via software). 2. edma_tcd[start] = 0, edma_tcd[active] = 1, edma_tcd[done] = 0 (channel is executing). 3. edma_tcd[start] = 0, edma_tcd[active] = 0, edma_tcd[done] = 0 (channel has completed the minor loop and is idle), or 4. edma_tcd[start] = 0, edma_tcd[active] = 0, edma_tcd[done] = 1 (channel has completed the major loop and is idle). the best method to test for minor loop completion when using hardware initiated service requests is to read field edma_tcd[citer] and test for a change. the hardware request and acknowledge handshakes signals are not visible in the programmer?s model. the tcd status bits execute the following sequence for a hardware activated channel: table 44. modulo feature example transfer number address 1 0x12345670 2 0x12345674 3 0x12345678 4 0x1234567c 5 0x12345670 6 0x12345674 RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 229/1740 1. edma peripheral request asserts (channel service request via hardware). 2. edma_tcd[start] = 0, edma_tcd[active] = 1, edma_tcd[done] = 0 (channel is executing). 3. edma_tcd[start] = 0, edma_tcd[active] = 0, edma_tcd[done] = 0 (channel has completed the minor loop and is idle), or 4. edma_tcd[start] = 0, edma_tcd[active] = 0, edma_tcd[done] = 1 (channel has completed the major loop and is idle). for both activation types, the major loop complete status is explicitly indicated via bit edma_tcd[done]. bit edma_tcd[start] is cleared automatically when the channel begins execution, regardless of how the channel was activated. active channel tcd reads the edma will read back the true edma_tcd[saddr], edma_tcd[daddr], and edma_tcd[nbytes] values if read while a channel is executing. the true values of the saddr, daddr, and nbytes are the values th e edma engine is currently using in its internal register file and not the values in the tcd local memory for that channel. the addresses (saddr and daddr) and nbytes (d ecrements to zero as the transfer progresses) can give an indication of the progress of the transfer. all other values are read back from the tcd local memory. pre-emption status pre-emption is available only when fixed arbitration is selected for both group- and channel- arbitration modes. a pre-emptable situation is one in which a pre-empt-enabled channel is running and a higher priority request becomes active. when the edma engine is not operating in fixed group, fixed-channel arbitration mode, the determination of the relative priority of the actively running and the outstanding requests become undefined. channel and group priorities are treated as equal (or more exactly, constantly rotating) when round- robin arbitration mode is selected. bit edma_tcd[active] for the pre-empted channel remains asserted throughout the pre- emption. the pre-empted channel is temporarily suspended while the pre-empting channel executes one iteration of the major loop. two edma_tcd[active] bits set at the same time in the overall tcd map indicates a higher priority channel is actively pre-empting a lower priority channel. 8.5.7 channel linking channel linking (or chaining) is a mechanism in which one channel sets bit edma_tcd[start] of another channel (or itself), thus initiating a service request for that channel. this operation is automatically performed by the edma engine at the conclusion of the major or minor loop when properly enabled. the minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major loop). field edma_tcd[citer.e_link] is used to determine whether a minor loop link is requested. when enabled, the channel link is made after each iteration of the minor loop except for the last. when the major loop is exhausted, only the major loop enhanced direct memory access controller (edma) RM0029 230/1740 doc id 15177 rev 8 channel link fields are used to determine if a channel link should be made. for example, with the initial fields of: edma_tcd[citer.e_link] = 1 edma_tcd[citer.linkch] = 0xc edma_tcd[citer] value = 0x4 edma_tcd[major.e_link] = 1 edma_tcd[major.linkch] = 0x7 will execute as: 1. minor loop done ? set channel 12 edma_tcd[start] bit 2. minor loop done ? set channel 12 edma_tcd[start] bit 3. minor loop done ? set channel 12 edma_tcd[start] bit 4. minor loop done, major loop done ? set channel 7 edma_tcd[start] bit when minor loop linking is enabled (edma_tcd[citer.e_link] = 1), field edma_tcd[citer] uses a 9-bit vector to form the current iteration count. when minor loop linking is disabled (edma_tcd[citer.e_link] = 0), field edma_tcd[citer] uses a 15-bit vector to form the current iteration count. the bits associated with field edma_tcd[citer.linkch] are concatenated onto the citer value to increase the range of the citer. note: after configuration, bit edma_tcd[citer.e_link] and bit edma_tcd[biter.e_link] must be equal or a configuration error is reported. the citer and biter vector widths must be equal to calculate the major loop, halfway done interrupt point. ta ble 45 summarizes how a dma channel can link to another dma channel, that is, use another channel?s tcd, at the end of a loop. 8.5.8 dynamic programming dynamic channel linking dynamic channel linking is the process of setting the tcd.major.e_link bit during channel execution. this bit is read from the tcd local memory at the end of channel execution, thus allowing the user to enable the feature during channel execution. because the user is allowed to change the configuration during execution, a coherency model is needed. consider the scenario where the user attempts to execute a dynamic channel link by enabling the tcd.major.e_link bit at the same time the edma engine is table 45. channel linking parameters desired link behavior tcd control field name description link at end of minor loop citer.e_link enable channel-to-channel linking on minor loop completion (current iteration). citer.linkch link channel number when linking at end of minor loop (current iteration). link at end of major loop major.e_link enable channel-to-channel linking on major loop completion. major.linkch link channel number when linking at end of major loop. RM0029 enhanced direct memory access controller (edma) doc id 15177 rev 8 231/1740 retiring the channel. the tcd.major.e_link would be set in the programmer?s model, but it would be unclear whether the actual link was made before the channel retired. the coherency model in ta ble 46 is recommended when executing a dynamic channel link request. for this request, the tcd local memory controller forces the tcd.major.e_link bit to zero on any writes to a channel?s tcd.word7 after that channel?s tcd.done bit is set, indicating the major loop is complete. note: the user must clear the tcd.done bit before writing the tcd.major.e_link bit. the tcd.done bit is cleared automatically by the edma engine after a channel begins execution. dynamic scatter/gather dynamic scatter/gather is the process of setting the tcd.e_sg bit during channel execution. this bit is read from the tcd local memory at the end of channel execution, thus allowing the user to enable the feature during channel execution. because the user is allowed to change the configuration during execution, a coherency model is needed. consider the scenario where the user attempts to execute a dynamic scatter/gather operation by enabling the tcd.e_sg bit at the same time the edma engine is retiring the channel. the tcd.e_sg would be set in the programmer?s model, but it would be unclear whether the actual scatter/gather request was honored before the channel retired. two methods for this coherency model are shown in the following subsections. method 1 has the advantage of reading the major.linkch field and the e_sg bit with a single read. for both dynamic channel linking and scatter/gather requests, the tcd local memory controller forces the tcd.major.e_link and tcd.e_sg bits to zero on any writes to a channel?s tcd.word7 if that channel?s tcd.done bit is set indicating the major loop is complete. note: the user must clear the tcd.done bit before writing the tcd.major.e_link or tcd.e_sg bits. the tcd.done bit is cleared automatically by the edma engine after a channel begins execution. method 1 (channel not using major loop channel linking) for a channel not using major loop channel linking, the coherency model in table 47 may be used for a dynamic scatter/gather request. when the tcd.major.e_link bit is zero, the tcd.major.linkch field is not used by the edma. in this case, the tcd.major.linkch bits may be used for other purposes. this method uses the tcd.major.linkch field as a tcd indentification (id). table 46. coherency model for a dynamic channel link request step action 1 write 1b to the tcd.major.e_link bit. 2 read back the tcd.major.e_link bit. 3 test the tcd.major.e_link request status: ? if tcd.major.e_link = 1b, the dynamic link attempt was successful. ? if tcd.major.e_link = 0b, the attempted dynamic link did not succeed (the channel was already retiring). enhanced direct memory access controller (edma) RM0029 232/1740 doc id 15177 rev 8 method 2 (channel using major loop linking) for a channel using major loop channel linking, the coherency model in ta ble 48 may be used for a dynamic scatter/gather request. this method uses the tcd.dlast_sga field as a tcd indentification (id). table 47. coherency model for method 1 step action 1 when the descriptors are built, write a unique tcd id in the tcd.major.linkch field for each tcd associated with a channel using dynamic scatter/gather. 2 write 1b to thetcd.d_req bit. should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a future hardware activation of this channel. this stops the c hannel from executing with a destination address (daddr) that was calculated using a scatter/gather address (written in the next step) instead of a dlast final offest value. 3 write thetcd.dlast_sga field with the scatter/gather address. 4 write 1b to the tcd.e_sg bit. 5 read back the 16 bit tcd control/status field. 6 test the tcd.e_sg request status and tcd.major.linkch value: ? if e_sg = 1b, the dynamic link attempt was successful. ? if e_sg = 0b and the major.linkch (id) did not change, the attempted dynamic link did not succeed (the channel was already retiring). ? if e_sg = 0b and the major.linkch (id) changed, the dynamic link attempt was successful (the new tcd?s e_sg value cleared the e_sg bit). table 48. coherency model for method 2 step action 1 write 1b to thetcd.d_req bit. should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a future hardware activation of this channel. this stops the c hannel from executing with a destination address (daddr) that was calculated using a scatter/gather address (written in the next step) instead of a dlast final offest value. 2 write thetcd.dlast_sga field with the scatter/gather address. 3 write 1b to the tcd.e_sg bit. 4 read back the tcd.e_sg bit. 5 test the tcd.e_sg request status: ? if e_sg = 1b, the dynamic link attempt was successful. ? if e_sg = 0b, read the 32 bit tcd dlast_sga field. ? if e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not succeed (the channel was already retiring). ? if e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the new tcd?s e_sg value cleared the e_sg bit). RM0029 multi-layer ahb crossbar switch (xbar) doc id 15177 rev 8 233/1740 9 multi-layer ahb crossbar switch (xbar) 9.1 introduction 9.1.1 overview this section provides an overview of the multi-layer ahb crossbar switch (xbar). the purpose of the xbar is to concurrently support simultaneous connections between master ports and slave ports. the xbar supports a 32-bit address bus width. only a single data bus width is supported throughout the design, thus, all master and slave ports have the same data bus width. the xbar has five master ports and four slave ports. figure 47 shows a block diagram of the xbar. figure 47. xbar device-specific block diagram the port mappings are shown in ta ble 49 . crossbar switch master modules slave modules e200z4 (data/nexus) m1 edma m4 e200z4 (instruction) m0 ebi m7 flash s0 ebi/cal s1 sram s2 peripheral bridge s7 flexray m6 table 49. master/slave mappings module port physical master id type logical number e200z4 core instruction master m0 0 e200z4 core load/store master m1 0 e200z4 core nexus master m1 8 edma master m4 4 flexray interface master m6 6 ebi (1) master m7 7 multi-layer ahb crossbar switch (xbar) RM0029 234/1740 doc id 15177 rev 8 9.1.2 features the xbar has the ability to gain control of all the slave ports and prevent any masters from making accesses to the slave ports. this feature is useful for turning off the clocks to the system and ensuring that no bus activity will be interrupted. the xbar can put each slave port into a low power park mode so that the slave port will not dissipate any power transitioning address, control or data signals when not being actively accessed by a master port. each slave port can also support multiple master priority schemes?the user can dynamically change master priority levels on a slave port by slave port basis. the xbar allows concurrent transactions to occur from any master port to any slave port. it is possible for all master ports and slave ports to be in use at the same time as a result of independent master requests. if a slave port is simultaneously requested by more than one master port, arbitration logic will select the higher priority master and grant it ownership of the slave port. all other masters requesting that slave port will stalled until the higher priority master completes its transactions. the xbar has a 32-bit internal address bus and a 64-bit internal data bus. 9.1.3 limitations the xbar routes bus transactions initiated on the master ports to the appropriate slave ports. there is no provision included to route transactions initiated on the slave ports to other slave ports or to master ports. simply put, the slave ports do not support the bus request/bus grant protocol; the xbar assumes it is the sole master of each slave port. 9.1.4 general operation when a master makes an access to the xbar the access will be immediately taken by the xbar. if the targeted slave port of the access is available then the access will be immediately presented on the slave port. it is possible to make single clock (zero wait state) accesses through the xbar. if the targeted slave port of the access is busy or parked on a different master port the requesting master will simply see wait states inserted until the targeted slave port can service the master?s request. the latency in servicing the request depends on each master?s priority level and the responding peripheral?s access time. flash memory slave s0 ? ebi/calibration bus (2) slave s1 ? sram slave s2 ? peripheral bridge slave s7 ? 1. the ebi (external bus interface) is connected as a master but is not implemented with a multi-master mode so it is, in effect, ?parked?. regardless, it must be configured as with other supported masters. 2. the calibration bus is only available on the calibration package. table 49. master/slave mappings module port physical master id type logical number RM0029 multi-layer ahb crossbar switch (xbar) doc id 15177 rev 8 235/1740 since the xbar appears to be just another slave to the master device, the master device will have no knowledge of whether or not it actually owns the slave port it is targeting. while the master does not have control of the slave port it is targeting it will simply be wait stated. a master is given control of the targeted slave port only after a previous access to a different slave port has completed, regardless of its priority on the newly targeted slave port. this prevents deadlock from occurring when a master has an outstanding request to one slave port that has a long response time, has a pending access to a different slave port, and a lower priority master is also making a request to the same slave port as the pending access of the higher priority master. once the master has control of the slave port it is targeting, the master remains in control of that slave port until it gives up the slave port by running an idle cycle or by leaving that slave port for its next access. the master could also lose control of the slave port if another higher priority master makes a request to the slave port; however, if the master is running a locked or fixed length burst transfer it retains control of the slave port until that transfer is completed. the xbar will terminate all master idle transfers (as opposed to allowing the termination to come from one of the slave busses). additionally, when no master is requesting access to a slave port the xbar will drive idle transfers onto the slave bus, even though a default master may be granted access to the slave port. when a slave bus is being idled by the xbar it can park the slave port on the master port indicated by the park bits in the sgpcr (slave general purpose control register). this can be done in an attempt to save the initial clock of arbitration delay that would otherwise be seen if the master had to arbitrate to gain control of the slave port. the slave port can also be put into low power park mode in attempt to save power. 9.2 xbar registers this section provides information on xbar registers. 9.2.1 register summary there are two registers that reside in each slave port of the xbar. these registers are ip bus compliant registers. read and write transfers both require two ip bus clock cycles. read and writen operations can be performed on these registers only in supervisor mode. additionally, these registers can only be read from or written to by 32-bit accesses. the registers are fully decoded and an error response is returned if an unimplemented location is accessed within the xbar. the slave registers also feature a bit, which when written with a 1, will prevent the registers from being written to again. the registers will still be readable, but future write attempts will have no effect on the registers and will be terminated with an error response. the memory map for the xbar program-visible registers is shown in ta ble 50 . table 50. xbar register configuration summary address register location xbar_base (0xfff0_4000) mpr0 ? master priority register for slave port 0 on page 9- 237 multi-layer ahb crossbar switch (xbar) RM0029 236/1740 doc id 15177 rev 8 9.2.2 xbar register descriptions the following paragraphs provide detailed descriptions of the various xbar registers. refer to figure 48 for the various bit configurations that appear in the register maps. xbar_base + 0x004 ? xbar_base + 0x00f reserved ? xbar_base + 0x010 sgpcr0 ? general purpose control register for slave port 0 on page 9- 239 xbar_base + 0x014 ? xbar_base + 0x0ff reserved ? xbar_base + 0x100 mpr1 ? master priority register for slave port 1 on page 9- 237 xbar_base + 0x104 ? xbar_base + 0x10f reserved ? xbar_base + 0x110 sgpcr1 ? general purpose control register for slave port 1 on page 9- 239 xbar_base + 0x114 ? xbar_base + 0x1ff reserved ? xbar_base + 0x200 mpr2 ? master priority register for slave port 2 on page 9- 237 xbar_base + 0x204 ? xbar_base + 0x20f reserved ? xbar_base + 0x210 sgpcr2 ? general purpose control register for slave port 2 on page 9- 239 xbar_base + 0x214 ? xbar_base + 0x6ff reserved ? xbar_base + 0x700 mpr7 ? master priority register for slave port 7 on page 9- 237 xbar_base + 0x704 ? xbar_base + 0x70f reserved ? xbar_base + 0x710 sgpcr7 ? general purpose control register for slave port 7 on page 9- 239 xbar_base + 0x714 ? xbar_base + 0xf03 reserved ? table 50. xbar register conf iguration summary (continued) address register location figure 48. key to register fields always reads 1 1 always reads 0 0 r/w bit bit (1) read- only bit bit (1) write- only bit write 1 to clear bit (1) self- clear bit 0 n/a bit (1) w1c bit (1) 1. ?bit? refers to a field name in the register. some fields span multiple bits. RM0029 multi-layer ahb crossbar switch (xbar) doc id 15177 rev 8 237/1740 master priority register (xbar_mprn) the master priority register (mpr) resides in each slave port and sets the priority of each master port on a per slave port basis, e.g., mpr0 sets priority for each master port for slave port 0. figure 49. master priority register (xbar_mprn) mpr0: address: xbar_base (0xfff0_4000) + 0x0000 mpr1: address: xbar_base (0xfff0_4000) + 0x0100 mpr2: address: xbar_base (0xfff0_4000) + 0x0200 mpr7: address: xbar_base (0xfff0_4000) + 0x0700 access: supervisor 0 1 2 3 4 5 6 7 8 9 101112131415 r0 mstr7 0 mstr6 00000 mstr4 w reset0 1 00001100000010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0000000 mstr1 0 mstr0 w reset0 0 00000000010000 = not implemented table 51. xbar master priority register field descriptions field description 0 reserved this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. 1:3 mstr7 master 7 priority these bits set the arbitration priority for master port 7 (ebi) on the associated slave port. these bits are initialized by hardware reset. the reset value is 111. 000: this master has the highest priority when accessing the slave port. ... 111: this master has the lowest priority when accessing the slave port. 4 reserved this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. multi-layer ahb crossbar switch (xbar) RM0029 238/1740 doc id 15177 rev 8 5:7 mstr6 master 6 priority these bits set the arbitration priority for master port 6 (flexray) on the associated slave port. these bits are initialized by hardware reset. the reset value is 110. 000: this master has the highest priority when accessing the slave port. ... 111: this master has the lowest priority when accessing the slave port. 8 reserved this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. 9:11 reserved these bits are reserved for future expansion. they are read as zero and should be written with zero for upward compatibility. 12 reserved this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. 13:15 mstr4 master 4 priority these bits set the arbitration priority for master port 4 (edma) on the associated slave port. these bits are initialized by hardware reset. the reset value is 100. 000: this master has the highest priority when accessing the slave port. ... 111: this master has the lowest priority when accessing the slave port. 16 reserved this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. 17:19 reserved these bits are reserved for future expansion. they are read as zero and should be written with zero for upward compatibility. 20 reserved this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. 21:23 reserved these bits are reserved for future expansion. they are read as zero and should be written with zero for upward compatibility. 24 reserved this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. table 51. xbar master priority register field descriptions (continued) field description RM0029 multi-layer ahb crossbar switch (xbar) doc id 15177 rev 8 239/1740 the master priority register can only be accessed in supervisor mode with 32-bit accesses. once the ro (read only) bit has been set in the slave general purpose control register the master priority register can only be read from, attempts to write to it will have no effect on the mpr and result in an error response. note: no two available master ports may be programmed with the same priority level. attempts to program two or more available masters with the same priority level will result in an error response and the mpr will not be updated. slave general purpose control register (xbar_sgpcrn) the slave general purpose control register (sgpcr) controls several features of each slave port. the read only (ro) bit will prevent any registers associated with this slave port from being written to once set. this bit may be written with 0 as many times as the user desires, but once it is written to a 1 only a reset condition will allow it to be written again. the pctl bits determine how the slave port will park when no master is actively making a request. the available options are to park on the master defined by the park bits, park on the last master to use the slave port, or go into a low power park mode which will force all the outputs of the slave port to inactive states when no master is requesting an access. the low power park feature can result in an overall power savings if a the slave port is not saturated; however, it will force an extra clock of latency whenever any master tries to access it when it is not in use because it will not be parked on any master. 25:27 mstr1 master 1 priority these bits set the arbitration priority for master port 1 (e200z4 core load/store bus and e200z4 core nexus) on the associated slave port. these bits are initialized by hardware reset. the reset value is 001. 000: this master has the highest priority when accessing the slave port. ... 111: this master has the lowest priority when accessing the slave port. 28 reserved this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. 29:31 mstr0 master 0 priority these bits set the arbitration priority for master port 0 (e200z4 core instruction bus) on the associated slave port. these bits are initialized by hardware reset. the reset value is 000 000: this master has the highest priority when accessing the slave port. ... 111: this master has the lowest priority when accessing the slave port. table 51. xbar master priority register field descriptions (continued) field description multi-layer ahb crossbar switch (xbar) RM0029 240/1740 doc id 15177 rev 8 the park bits determine which master the slave will park on when no master is making an active request. please use caution to only select master ports that are actually present in the design. if the user programs the park bits to a master not present in the current design implementation undefined behavior will result. note: the sgpcr can only be accessed in supervisor mode with 32-bit accesses. once the ro (read only) bit has been set in the sgpcr the sgpcr can only be read, attempts to write to it will have no effect on the sgpcr and result in an error response. figure 50. slave general purpose control register (xbar_sgpcrn) sgpcr0: address: xbar_base + 0x0010 + 0x0000 (0xfff0_4010) sgpcr1: address: xbar_base + 0x0010 + 0x0100 (0xfff0_4110) sgpcr2: address: xbar_base + 0x0010 + 0x0200 (0xfff0_4210) sgpcr7: address: xbar_base + 0x0010 + 0x0700 (0xfff0_4710) access: supervisor 0 1 2 3 4 5 6 7 8 9 101112131415 r ro 0 000000 hpe7 hpe6 0 hpe4 00 hpe1 hpe0 w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 arb 00 pctl 0 park w reset0 0 00000000000000 = not implemented table 52. xbar slave general purpose control register field descriptions field description 0 ro read only this bit is used to force all of a slave port?s registers to be read only. once written to 1 it can only be cleared by hardware reset. this bit is initialized by hardware reset. the reset value is 0. 0: all this slave port?s registers can be written. 1: all this slave port?s registers are read only and cannot be written (attempted writes have no effect and result in an error response). 1:7 reserved these bits are reserved for future expansion. they read as zero and should be written with zero for upward compatibility. RM0029 multi-layer ahb crossbar switch (xbar) doc id 15177 rev 8 241/1740 8:15 hpex high priority enable these bits are used to enable the mx_high_priority inputs for the respective master. these bits are initialized by hardware reset. the reset value is 0. 0: the mx_high_priority input is disabled on this slave port 1: the mx_high_priority input is enabled on this slave port. 16:21 reserved these bits are reserved for future expansion. they are read as zero and should be written with zero for upward compatibility. 22:23 arb arbitration mode these bits are used to select the arbitration policy for the slave port. these bits are initialized by hardware reset. the reset value is 00. 00: fixed priority 01: round robin (rotating) priority 10: reserved 11: reserved 24:25 reserved these bits are reserved for future expansion. they are read as zero and should be written with zero for upward compatibility. 26:27 pctl parking control these bits determine the parking control used by this slave port. these bits are initialized by hardware reset. the reset value is 00. 00: when no master is making a request the arbiter will park the slave port on the master port defined by the park bit field. 01: when no master is making a request the arbiter will park the slave port on the last master to be in control of the slave port. 10: when no master is making a request the arbiter will park the slave port on no master and will drive all outputs to a constant safe state. 11: reserved 28 reserved this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. table 52. xbar slave general purpose control register field descriptions (continued) field description multi-layer ahb crossbar switch (xbar) RM0029 242/1740 doc id 15177 rev 8 9.2.3 coherency since the content of the registers has a real time effect on the operation of the xbar it is important for the user to understand that any register modifications take effect as soon as the register is written. the values of the registers do not track with slave port related ahb accesses but instead track only with ip bus accesses. 9.3 function this section describes in more detail the functionality of the xbar. 9.3.1 arbitration the xbar supports two arbitration schemes: a simple fixed-priority comparison algorithm and a simple round-robin fairness algorithm. the arbitration scheme is independently programmable for each slave port. fixed priority operation when operating in fixed-priority mode, each master is assigned a unique priority level in the mpr (master priority register). if two masters both request access to a slave port the master with the highest priority in the selected priority register will gain control over the slave port. any time a master makes a request to a slave port the slave port checks to see if the new requesting master?s priority level is higher than that of the master that currently has control over the slave port (unless the slave port is in a parked state). the slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has control of the slave port. if the new requesting master?s priority level is higher than that of the master that currently has control of the slave port the new requesting master will be granted control over the slave port at the next clock edge. the exception to this rule is if the master that currently has 29:31 park park these bits are used to determine which master port this slave port parks on when no masters are actively making requests and the pctl bits are set to 00. these bits are initialized by hardware reset. the reset value is 000. 000: park on master port 0 (e200z448n3 core instruction) 001: park on master port 1 (e200z448n3 core load/store) 010: reserved 011: reserved 100: park on master port 4 (edma) 101: reserved 110: park on master port 6 (flexray) 111: park on master port 7 (ebi) table 52. xbar slave general purpose control register field descriptions (continued) field description RM0029 multi-layer ahb crossbar switch (xbar) doc id 15177 rev 8 243/1740 control over the slave port is running a fixed length burst transfer or a locked transfer. in this case the new requesting master will have to wait until the end of the burst transfer or locked transfer before it will be granted control of the slave port. if the master is running an undefined length burst transfer the new requesting master must wait until an arbitration point for the undefined length burst transfer before it will be granted control of the slave port. arbitration points for an undefined length burst are defined in the mgpcr for each master. if the new requesting master?s priority level is lower than that of the master that currently has control of the slave port the new requesting master will be forced to wait until the master that currently has control of the slave port either runs an idle cycle or runs a non idle cycle to a location other than the current slave port. round-robin priority operation when operating in round-robin mode, each master is assigned a relative priority based on the master number.this relative priority is compared to the id of the last master to perform a transfer on the slave bus. the highest priority requesting master will become owner of the slave bus as the next transfer boundary (accounting for locked and fixed-length burst transfers). priority is based on how far ahead the id of the requesting master is to the id of the last master (id is defined by master port number). once granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. the next master in line will be granted access to the slave port if the current master has no pending access request. as an example of arbitration in round-robin mode, assume the xbar is implemented with master ports 0, 1, 4 and 5. if the last master of the slave port was master 1, and master 0, 4 and 5 make simultaneous requests, they will be serviced in the order 4, 5 and then 0. parking may still be used in a round-robin mode, but will not affect the round-robin pointer unless the parked master actually performs a transfer. handoff occurs to the next master in line after one cycle of arbitration. if the slave port is put into low power park mode the round- robin pointer is reset to point at master port 0, giving it the highest priority. parking if no master is currently requesting the slave port, the slave port is parked. the slave port parks in one of three places, indicated by the value of the pctl field in the xbar_sgpcr. if park-on-specific master mode is selected, the slave port parks on the master designated by the park field. when the master accesses the slave port again, a one clock arbitration penalty is incurred only for an access request made by another master port to the slave port. no other arbitration penalties are incurred. all other masters pay a one clock penalty. if park-on-last (pol) mode is selected, then the slave port parks on the last master to access it, passing that master?s signals through to the slave bus. when the master accesses the slave port again, no other arbitration penalties are incurred except that a one clock arbitration penalty is incurred for each access request to the slave port made by another master port. all other masters pay a one clock penalty. if the low-power-park (lpp) mode is selected, then the slave port enters low-power park mode. it is not under control by any master and does not transmit any master signals to the slave bus. all slave bus activity halts because all slave bus signals are not toggling. this saves power if the slave port is not used for some time. however, multi-layer ahb crossbar switch (xbar) RM0029 244/1740 doc id 15177 rev 8 when a master does make a request to a slave port parked in low-power-park, a one clock arbitration delay is incurred to get ownership of the slave port. 9.3.2 priority assignment each master port needs to be assigned a unique 3-bit priority level. if an attempt is made to program multiple master ports with the same priority level within a register (mpr) the xbar will respond with an error and the registers will not be updated. RM0029 peripheral bridge (pbridge) doc id 15177 rev 8 245/1740 10 peripheral bridge (pbridge) the peripheral bridge (pbridge) provides an interface between the system crossbar switch bus and the lower-bandwidth peripheral bus. 10.1 pbridge features the pbridge: is only meant for slave peripherals supports 32-bit peripherals (byte, halfword, and word reads and write are supported to each) supports a pair of accesses for 64-bit fetches 10.2 pbridge modes of operation the pbridge has only one operating mode. 10.3 pbridge block diagram the pbridge is the interface between the system bus interface and on-chip peripherals as shown in figure 51 . figure 51. pbridge interface off-platform ips peripheral on-platform ips (pbridge0) bridge b amba ahb crossbar switch peripheral bridge (pbridge) RM0029 246/1740 doc id 15177 rev 8 10.4 pbridge signal description the pbridge has no external signals. 10.5 pbridge functional description the pbridge functions as a protocol translator. support is provided for generating a pair of 32-bit slave bus instruction accesses (not data accesses) when targeted by a 64-bit system bus access. accesses which fall within the address space of the pbridge are decoded to provide individual module selects for peripheral devices. 10.5.1 read cycles two clock read accesses are possible with the pbridge when the requested access size is 32-bits or smaller, and is not misaligned across a 32-bit boundary. if the requested instruction access size is 64-bits, then a minimum of three clocks are required to complete the access. misaligned read accesses are not supported. 64-bit data reads (not instruction) are not supported. 10.5.2 write cycles three clock write accesses are possible with the pbridge when the requested access size is 32-bits or smaller, and is not misaligned across a 32-bit boundary. misaligned writes that do not cross a 32-bit boundary are supported. 64-bit data writes (not instruction) are not supported. 10.6 memory map and register description 10.6.1 memory map each register in the pbridge module has a size of 32 bits. the registers are listed in ta ble 53 . the memory map organization is shown in table 54 . the organizational hierarchy is as follows: the module has multiple registers with the same register name (mpcr, pacr, opacr), each at a different address offset. each register has multiple similarly-named fields, each with a different number. each field has subfields as defined elsewhere in this section. accesses to registers or register fields marked as reserved will return zeros on reads, and will be ignored on writes. table 53. pbridge registers offset from pbridge_base (0xfff0_0000) register location 0x0000?0x0007 (1) master privilege control registers (mpcr) on page 10- 248 0x0008?0x001f reserved RM0029 peripheral bridge (pbridge) doc id 15177 rev 8 247/1740 0x0020?0x003f 1 peripheral access control registers (pacr) on page 10- 248 0x0040?0x006f 1 off-platform peripheral access control registers (opacr) on page 10- 250 0x0070?0x3fff reserved 1. this memory range contains reserved areas. see table 54 . table 53. pbridge registers (continued) offset from pbridge_base (0xfff0_0000) register location table 54. pbridge memory map address offset register name bit numbers 0?3 4?7 8?11 12?15 16?19 20?23 24?27 28?31 0x0000 mpcr mpcr0 reserved mpcr4 reserved mpcr6 mpcr7 0x0004 mpcr8 reserved 0x0020 pacr reserved pacr1 reserved pacr4 reserved 0x0024 reserved pacr14 pacr15 0x0028 pacr16 pacr17 pacr18 reserved 0x002c reserved 0x0040 opacr opacr0 reserved opacr2 opacr3 reserved opacr5 opacr6 opacr7 0x0044 reserved opacr1 2 opacr1 3 opacr1 4 reserved 0x0048 opacr1 6 opacr1 7 opacr1 8 reserved 0x004c opacr2 4 reserved opacr2 7 reserved opacr3 1 0x0050 reserved 0x0054 reserved 0x0058 reserved 0x005c reserved opacr5 8 reserved 0x0060 opacr6 4 opacr6 5 opacr6 6 opacr6 7 opacr6 8 reserved opacr7 1 0x0064 opacr7 2 reserved opacr7 9 0x0068 opacr8 0 opacr8 1 opacr8 2 opacr8 3 opacr8 4 reserved 0x006c reserved opacr9 2 reserved peripheral bridge (pbridge) RM0029 248/1740 doc id 15177 rev 8 10.6.2 register descriptions master privilege control registers (mpcr) each mpcr register contains one or more 4-bit fields, called mpcr n , as shown in ta ble 54 . each of these fields defines the access privilege level associated with bus master n in the platform as well as specifies whether write accesses from this master are bufferable. the registers provide one field per bus master. see the ?logical master ids? section in the xbar chapter for a list of master numbers and names. each mpcr n field has the structure described in figure 52 and table 55 . figure 52. mpcr n field structure peripheral access control registers (pacr) each pacr register contains one or more 4-bit fields, called pacr n , as shown in table 54 . each of these fields defines the access levels supported by the associated module. the lists of modules and their corresponding numbers are shown in table 58 . 0123 r 0 mtr mtw mpl w reset 0111 table 55. mpcr n field structure descriptions subfield description mtr master trusted for reads this bit determines whether the master is trusted for read accesses. 0 this master is not trusted for read accesses. 1 this master is trusted for read accesses. mtw master trusted for writes this bit determines whether the master is trusted for write accesses. 0 this master is not trusted for write accesses. 1 this master is trusted for write accesses. mpl master privilege level this bit determines how the privilege level of the master is determined. 0 accesses from this master are forced to user-mode. 1 accesses from this master are not forced to user-mode. table 56. mpcr register fields register master name reset value mpcr 0 z4 core (instruction + load/store) 0b0111, meaning mtr = 1 mtw = 1 mpl = 1 mpcr 4 dma mpcr 6 flexray mpcr 8 z4 core nexus RM0029 peripheral bridge (pbridge) doc id 15177 rev 8 249/1740 each pacr n field has the structure described in figure 53 and table 57 . figure 53. pacr n field structure 0123 r 0 sp wp tp w reset 0100 table 57. pacr n field structure descriptions subfield description sp supervisor protect this bit determines whether the peripheral requires supervisor privilege level for access. 0 this peripheral does not require supervisor privilege level for accesses. 1 this peripheral requires supervisor privilege level for accesses. the mpcrx[mpl] control bit for the master must be set. if not, the access is terminated with an error response and no peripheral access is initiated on the ips bus. wp write protect this bit determines whether the peripheral allows write accesses. 0 this peripheral allows write accesses. 1 this peripheral is write protected. if a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the ips bus. tp trusted protect this bit determines whether the peripheral allows accesses from an untrusted master. 0 accesses from an untrusted master are allowed. 1 accesses from an untrusted master are not allowed. if an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the ips bus. table 58. peripheral access control register (pacr) fields register peripheral reset value pacr 1 crossbar 0100b, meaning sp = 1 wp = 0 tp = 0 pacr 4 mpu pacr 14 swt pacr 15 stm pacr 16 ecsm pacr 17 dma pacr 18 interrupt controller peripheral bridge (pbridge) RM0029 250/1740 doc id 15177 rev 8 off-platform peripheral access control registers (opacr) the opacr defines the access levels supported by the associated module. each opacr has a format identical to the pacr described in section , peripheral access control registers (pacr) . the lists of off-platform peripheral registers and their corresponding modules are listed in ta ble 59 . table 59. off-platform peripheral access control register (opacr) fields field peripheral reset value opacr 0 eqadc 0100b, meaning sp = 1 wp = 0 tp = 0 opacr 2 decimation filter a opacr 3 decimation filter b opacr 5 dspi b opacr 6 dspi c opacr 7 dspi d opacr 12 esci a opacr 13 esci b opacr 14 esci c opacr 16 flexcan a opacr 17 flexcan b opacr 18 flexcan c opacr 24 flexray opacr 27 system information module opacr 31 bam opacr 58 crc opacr 64 fm pll 0100b, meaning sp = 1 wp = 0 tp = 0 opacr 66 flash module a opacr 68 siu opacr 71 dts opacr 72 emios opacr 79 pmc opacr 80 etpu2 opacr 81 reaction module opacr 82 etpu parameter ram opacr 83 etpu parameter ram mirror opacr 84 etpu code ram opacr 92 pit RM0029 general-purpose static ram (sram) doc id 15177 rev 8 251/1740 11 general-purpose static ram (sram) 11.1 introduction the spc564a74xx, spc564a80xx includes 192 kbytes of general-purpose sram. the first 32 kbytes of sram is powered by its own power supply pin during standby operation. 11.2 features the sram controller includes these features: supports read/write accesses mapped to the sram memory from any master 32-kbyte block powered by separate supply for standby operation byte, halfword, word and doubleword addressable 7-bit ecc 11.3 modes of operation 11.3.1 normal (functional) mode allows reads and writes of the sram memory arrays. 11.3.2 standby mode preserves contents of the standby portion of the memory when the 1.2 v (v dd ) power drops below the level of the standby power supply voltage. there are two possible supplies for standby: 1.0 v directly from the vstby pin and 2 ? 5 volts (also on the vstby pin), which enables a standby regulator. vstby pad needs an external rc to slower the ramp to atleast 100 us to prevent a false esd trigger. updates to the standby portion of the sram are inhibited during system reset or during standby mode. 11.4 block diagram the sram block diagram is shown in figure 54 . figure 54. sram block diagram sram 160 kb v stby 32 kb v dd standby switch general-purpose static ram (sram) RM0029 252/1740 doc id 15177 rev 8 11.5 external signal description the external signal for sram is the v stby ram power supply. if the standby feature of the sram is not used, tie the v stby pin to v ss . 11.6 register memory map the sram occupies 192 kbytes of memory starting at the base address as shown in ta ble 60 . the internal sram has no registers. registers for the sram ecc are located in the ecsm. see chapter 18: error correction status module (ecsm) . note: the ecsm module contains the register mudcr that enables sram to be configured with an additional wait state. this is required when the cpu is configured to operate at its maximum frequency. see section 18.4.3, miscellaneous user-defined control register (ecsm_mudcr) , for details. 11.7 functional description ecc checks are performed during the read portion of an sram ecc read/write (r/w) operation, and ecc calculations are performed during the write portion of a read/write (r/w) operation. because the ecc bits can contain random data after the device is powered on, you must initialize the sram by executing 32-bit write instructions to the entire sram. for more information, see section 11.9, initialization and application information . 11.8 sram ecc mechanism the sram ecc detects the following conditions and produces the following results: detects and corrects all 1-bit errors detects and flags all 2-bit errors as non-correctable errors sram does not detect all errors greater than 2 bits. internal sram writes are done on byte boundaries: 1 byte (0:7 bits) 2 bytes (0:15 bits) 4 bytes or 1 word (0:31 bits) if the entire 32 data bits are written to sram, no read operation is performed and the ecc is calculated across the 32 bits of data. the 7-bit ecc is appended to the data segment and written to sram. if the write operation is less than the entire 32-bit data width (1- or 2-byte segment), the following occurs: table 60. sram memory map address register name register description size base (0x4000_0000) ? sram powered by v stby 32 kb base + 0x8000 ? 160-kb ram 160 kb RM0029 general-purpose static ram (sram) doc id 15177 rev 8 253/1740 1. the ecc mechanism checks the entire 32 bits of data for errors, detecting and either correcting or flagging errors. 2. the write data bytes (1- or 2-byte segment) are merged with the corrected 32 bits on the data bus. 3. the ecc is then calculated on the resulting 32 bits formed in the previous step. 4. the 7-bit ecc result is appended to the 32 bits from the data, and the 39-bit value is then written to sram. 11.8.1 access timing the system bus is a two stage pipelined bus, which makes the timing of any access dependent on the access during the previous clock. table 61 shows the wait states for accesses, current is the access being measured, previous is the ram access during the previous clock. 11.8.2 reset effects on sram accesses if a reset event asserts during a read or write operation to sram, the completion of that access depends on the cycle at which the reset occurs. data read from or written to sram before the reset event occurred is retained, and no other address locations are accessed or changed. if the system sram is cached, cache lines can retain indeterminate data that is not written to memory unless the region is set for write-through mode. note: standby memory can contain the previous data values if a reset occurs while cache is running in copy back mode. table 61. number of wait states required for ram operation current operation previous operation number of wait states read idle 0 (1) / 1 (2) 1. applies if additional sram read wait state in ecsm_mudcr is disabled 2. applies if additional sram read wait state in ecsm_mudcr is enabled read 0 (1) / 1 (2) 32 or 64-bit write 0 (1) / 1 (2) 8 or 16-bit write 1 (1) / 2 (2) 32 or 64-bit write idle 0 read 0 32 or 64-bit write 0 8 or 16-bit write 1 8 or 16-bit write idle 0 read 0 32 or 64-bit write 0 8 or 16-bit write 1 general-purpose static ram (sram) RM0029 254/1740 doc id 15177 rev 8 11.9 initialization and application information to use the sram, the ecc must check all bits that require initialization after power on. use either a 32-bit or 64-bit cache-inhibited write to each sram location to initialize the sram array as part of the application initialization code. all writes must specify an even number of registers performed on 32-bit or 64-bit word-aligned boundaries respectively. if the write is not the entire 32 bits (8 or 16 bits), a read/modify/write operation is generated that checks the ecc value upon the read. see section 11.8, sram ecc mechanism . note: you must initialize sram, even if the application does not use ecc reporting. 11.9.1 example code to initialize sram correctly, use a store multiple word ( stmw) instruction to implement 64- bit writes to all sram locations. the stmw instruction concatenates two 32-bit registers to implement a single 64-bit write. to ensure the writes are 64 bits, specify an even number of registers and write on 64-bit word-aligned boundaries. the following example code illustrates the use of the stmw instruction to initialize the sram ecc bits. init_ram: lis r11,0x4000 # base address of the sram, 64-bit word aligned ori r11,r11,0 # not needed for this address but could be for others li r12,1536 # loop counter to get all of sram; # 192*1024/4 bytes/32 gprs =1536 mtctr r12 init_ram_loop: stmw r0,0(r11) # write all 32 gprs to sram addi r11,r11,128 # inc the ram ptr; 32 gprs * 4 bytes = 128 bdnz init_ram_loop # loop for 192k of sram blr # done RM0029 flash memory doc id 15177 rev 8 255/1740 12 flash memory 12.1 introduction this section presents information about the following components on this device: the flash memory blocks the platform flash memory controller the primary function of the flash memory module is to serve as electrically programmable and erasable non-volatile memory. the nvm memory can be used for instruction and data storage. the block is a non-volatile solid-state silicon memory device consisting of blocks of single-transistor storage elements, an electrical means for selectively adding (programming) and removing (erasing) charge from these elements, and a means of selectively sensing (reading) the charge stored in these elements. the flash is addressable by word (32 bits) and page (128 bits). there are two flash array blocks (flash_a and flash_b). within each flash block are two functional units: the flash core (fc) and the memory interface (mi). the fc is composed of arrayed non-volatile storage elements, sense amplifiers, row selects, column selects, charge pumps, and redundancy logic. the arrayed storage elements in the fc are subdivided into physically separate units referred to as blocks. the mi contains the registers and logic which control the operation of the fc. the mi is also the interface to the platform flash bus interface unit (pfbiu). the flash array?s core has three address spaces: low-address space, mid-address space, and high-address space (see figure 55 ). flash memory RM0029 256/1740 doc id 15177 rev 8 figure 55. flash segmentation low-address space high-address space mid-address space 1x256kb 1x256kb 1x256kb 8 x 16 kb + 2 x 64 kb 2x128kb 1x256kb flash_b array blocks flash_a array blocks 1 x 256 kb 1x256kb 1 x 256 kb 1x256kb 3mb 256 kb 256 kb 128 bits wide 128 bits wide (256 bits wide) low-address space mid-address space 256 kb 256 kb (128 bits wide) (128 bits wide) (128 bits wide) (128 bits wide) 1x256kb 1x256kb 1 x 256 kb 1x256kb 1 x 256 kb 1x256kb RM0029 flash memory doc id 15177 rev 8 257/1740 12.1.1 block diagram figure 56 shows a block diagram of the flash memory module. the fbiu is addressed through the system bus while the flash control and status registers are addressed through the slave (peripheral) bus. figure 56. flash system block diagram flash bus interface unit (fbiu) flash memory flash_a memory module flash core control/status registers interface (mi) v flash_a v ss v dd slave bus system bus v pp is the only externally visible power supply that is necessary for the programming and erasing of the flash array (see section 12.2, external signal description ). flash memory flash_b memory module flash core control/status registers interface (mi) slave bus (xbar) v flash_b v ss v dd flash memory RM0029 258/1740 doc id 15177 rev 8 12.1.2 features the flash memory module has these major features: support for a 64-bit data bus for instruction fetch support for a 32-bit data bus for cpu loads and dma access. byte, halfword, word and doubleword reads are supported. only aligned word and doubleword writes are supported. configurable read buffering and line prefetch support. device flash has 2 sets of 4 line read buffers?1 set for the 128-bit wide low- and medium-address space and 1 set for the 256-bit wide high address space. hardware and software configurable (e) read and write access protections on a per- master basis interface to the flash array controller is pipelined with a depth of 1, allowing overlapped accesses to proceed in parallel for interleaved or pipelined flash array designs. configurable access timing allowing use in a wide range of system frequencies. multiple-mapping support and mapping-based block access timing (0?31 additional cycles) allowing use for emulation of other memory types software programmable block program/erase restriction control for low, mid and high address spaces erase of selected block(s) read page size of 128 bits (low/mid-address space) and 256 bits (for high-address space) ecc with single-bit correction, double-bit detection minimum program size is 2 consecutive 32 bit words, aligned on a 0-modulo-8 byte address, due to ecc. embedded hardware program and erase algorithm read-while-write with multiple partitions erase suspend, program suspend and erase-suspended program automotive flash which meets automotive endurance and reliability requirements shadow information stored in non-volatile shadow block independent program/erase of the shadow block 12.1.3 modes of operation flash user mode user mode is the default operating mode of the flash module. in this mode, it is possible to read and write, program and erase the flash module. e. software executing from flash must not write to register s that control flash behavior, e.g., wait state settings or prefetch enable/disable. doing so can cause data corruption. on spc564a74xx, spc564a80xx devices these registers include biucr, biuapr, and biucr2.further, fl ash configuration regist ers should be written only with 32-bit write operations to avoid any issues associ ated with register ?incoherenc y? caused by bit fields spanning smaller size (8- and 16-bit) boundaries. RM0029 flash memory doc id 15177 rev 8 259/1740 12.2 external signal description v flash is the only externally visible power supply that is necessary for programming and erasing the flash array. the other flash supplies are tied to the appropriate supply pads in the package. 12.3 memory map and registers this section provides a detailed description of all flash memory registers. 12.3.1 module memory map the flash memory map is shown in ta ble 62 . the addresses are given as an offset to the flash memory base address. there are no program-visible registers that physically reside in the flash. the flash controller contains the registers to control and configure the flash (see table 64 ). reference these registers only with 32-bit accesses. table 62. flash memory map offset from flash_base (0x0000_0000) use block partition data width (bits) block size (kbytes) 0x0000_0000 low-address space (flash a) l0 1 128 16 0x0000_4000 l1 128 16 0x0000_8000 l2 128 16 0x0000_c000 l3 128 16 0x0001_0000 l4 2 128 16 0x0001_4000 l5 128 16 0x0001_8000 l6 128 16 0x0001_c000 l7 128 16 0x0002_0000 l8 3 128 64 0x0003_0000 l9 128 64 0x0004_0000 mid-address space (flash a) m0 4 128 128 0x0006_0000 m1 128 128 0x0008_0000 low-address space (flash b) l0 5 128 256 0x000c_0000 mid-address space (flash b) m0 128 256 0x0010_0000 high-address space h0 6 256 512 0x0018_0000 h1 256 512 0x0020_0000 h2 7 256 512 0x0028_0000 h3 256 512 0x0030_0000 h4 8 256 512 0x0038_0000 h5 256 512 flash memory RM0029 260/1740 doc id 15177 rev 8 0x0040_0000 reserved 0x00ef_c000 shadow row (flash b) s0 all (1) 128 16 0x00f0_0000 reserved 0x00ff_c000 shadow row (flash a) s1 all (1) 128 16 0x0100_0000 reserved 1. for read-while-write operations, the shadow row behaves as if it is in all partitions. table 62. flash memory map (continued) offset from flash_base (0x0000_0000) use block partition data width (bits) block size (kbytes) table 63. flash shadow block mapping offset from flash_base (0x0000_0000) use 0x00ff_c000 ? 0x00ff_fdd7 general use 0x00ff_fdd8 serial passcode (0xfeed_face_cafe_beef) 0x00ff_fde0 censorship control word (0x55aa_55aa) 0x00ff_fde4 general use 0x00ff_fde8 lmlr reset configuration (0x0010_0000) 0x00ff_fdec general use 0x00ff_fdf0 hlr reset configuration (0x0fff_ffff) 0x00ff_fdf4 general use 0x00ff_fdf8 slmlr reset configuration (0x000f_ffff) 0x00ff_fdfd general use 0x00ff_fe10 nvusr0 0x00ff_fe14 ? 0x00ff_ffff general use table 64. flash configuration register memory map offset from flash_ x _ regs_base (1) register location 0x0000 mcr?module configuration register on page 12- 261 0x0004 lmlr?low-/mid-address space block lock register on page 12- 266 0x0008 hlr?high-address space block lock register on page 12- 267 0x000c slmlr?secondary low/mid-address space block lock register on page 12- 268 0x0010 lmsr?low-/mid-address space block select register on page 12- 269 RM0029 flash memory doc id 15177 rev 8 261/1740 12.3.2 register descriptions this section lists the flash memory registers in address order and describes the registers and their bitfields. module configuration register (mcr) 0x0014 hsr?high-address space block select register on page 12- 270 0x0018 ar?address register on page 12- 271 0x001c biucr (2) ?bus interface unit configuration register on page 12- 272 0x0020 biuapr (2) ?bus interface unit access protection register on page 12- 275 0x0024 biucr2 (2) ?bus interface unit configuration register 2 on page 12- 276 0x0028 ? 0x0038 reserved 0x003c flash_x_ut0?user test 0 register on page 12- 276 0x0040 flash_x_ut1?user test 1 register on page 12- 278 0x0044 flash_x_ut2?user test 2 register on page 12- 279 0x0048 umisr0?user multiple input signature register 0 on page 12- 280 0x004c umisr1?user multiple input signature register 1 on page 12- 280 0x0050 umisr2?user multiple input signature register 2 on page 12- 280 0x0054 umisr3?user multiple input signature register 3 on page 12- 280 0x0058 umisr4?user multiple input signature register 4 on page 12- 280 0x005c ? 0x3fff reserved 1. flash_a_regs_base = 0xc3f8_8000 flash_b_regs_base = 0xc3f8_c000 2. register is only accessible via flas h a. treat as ?reserved? in flash b. table 64. flash configuration register memory map (continued) offset from flash_ x _ regs_base (1) register location flash memory RM0029 262/1740 doc id 15177 rev 8 figure 57. module configur ation register (mcr) offset 0x0000 access: user read/write 0123456789101112131415 r00000 size 0 las 000mas w reset0000001101100000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eer rwe sbc 0 peas done peg0000 pgm psus ers esus ehv w w1c w1c w1c reset000000/11 0 0 0000000 table 65. mcr field description field description size[2:0] array space size the value of the size field is dependent upon the size of the flash module. size is read only. 000: 128 kb (only las option for this size is las = 2, and consists of two 16 kb and two 48 kb blocks, 128 kb of las available, and no mas or has available) 001: 256 kb (only las option for this size is las = 1, and las = 2, no mas or has available) 010: 512 kb (any las or mas option is available, no has available) 011: 1.0 mb (256 kb of las, 256 kb of mas, and 512 kb of has) 100: 1.5 mb (256 kb of las, 256 kb of mas, and 1 mb of has) 101: 2.0 mb (256 kb of las, 256 kb of mas, and 1.5 mb of has) 110: reserved 111: reserved las[2:0] low-address space the value of the las field corresponds to the configuration of the low-address space. las is read only. 000: one 256 kb block 001: two 128 kb blocks 010: four 16 kb, four 48 kb blocks 011: reserved 100: eight 16 kb, two 64 kb blocks 101: reserved 110: two 16 kb, two 48 kb, two 64 kb blocks 111: reserved mas mid-address space the value of the mas field corresponds to the configuration of the mid-address space. mas is read only. 0: two 128 kb blocks 1: one 256 kb block (only available if las = 0) RM0029 flash memory doc id 15177 rev 8 263/1740 eer ecc event error eer provides information on previous reads. if a double bit detection occurred, the eer bit is set to a 1. this bit must then be cleared, or a reset must occur before this bit returns to a 0 state. this bit may not be set by the user. in the event of a single bit detection and correction, this bit is not be set. if eer is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of eer) are correct. since this bit is an error flag, it must be cleared to a 0 by writing a 1 to the register location. a write of 0 has no effect. 0: reads are occurring normally. 1: an ecc error occurred during a previous read. rwe read while write event error rwe provides information on previous rww reads. if a read while write error occurs, this bit is set to 1. this bit must then be cleared, or a reset must occur before this bit returns to a 0 state. this bit may not be written to a 1 by the user. if rwe is not set, or remains 0, this indicates that all previous rww reads (from the last reset, or clearing of rwe) are correct. since this bit is an error flag, it must be cleared to a 0 by writing a 1 to the register location. a write of 0 has no effect. 0: reads are occurring normally. 1: a read while write error occurred during a previous read. sbc single bit correction sbc provides information on previous reads provided the ut0[spce] is set. if a single bit correction occurred, the sbc bit is set to a 1. this bit must then be cleared, or a reset must occur before this bit returns to a 0 state. if sbc is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of sbc) did not require a correction. since this bit is an error flag, it must be cleared to a 0 by writing a 1 to the register location. a write of 0 has no effect. 0: reads are occurring without corrections. 1: a single bit correction occurred during a previous read. peas program/erase access space peas is used to indicate which space is valid for program and erase operations, either main array space or shadow space. peas = 0 indicates that the main address space is active for all fc program and erase operations. peas = 1 indicates the shadow address space is active for program/erase. the value in peas is captured and held when the shadow block is enabled with the first interlock write done for program or erase operations. the value of peas is retained between sampling events (that is, subsequent first interlock writes). the value in peas may be changed during erase-suspended program, and reverts back to its? original state once the erase-suspended program is completed. peas is read only. 0: shadow address space is disabled for program/erase and main address space enabled. 1: shadow address space is enabled for program/erase and main address space disabled. done state machine status done indicates if the flash module is performing a high voltage operation. done is set to a 1 on termination of the flash module reset. done is read only. done is cleared within a 0 to 1 transition of ehv which initiates a high voltage operation. done is cleared of resuming a suspended operation. done is set to a 1 at the end of program and erase high voltage sequences. done is set to a 1 within a 1 to 0 transition of ehv which aborts a high voltage operation. 0: flash is executing a high voltage operation. 1: flash is not executing a high voltage operation. table 65. mcr field description (continued) field description flash memory RM0029 264/1740 doc id 15177 rev 8 peg program/erase good the peg bit indicates the completion status of the last flash program or erase sequence for which high voltage operations were initiated. the value of peg is updated automatically during the program and erase high voltage operations. aborting a program/erase high voltage operation causes peg to be cleared, indicating the sequence failed. peg is set to a 1 when the module is reset. peg is read only. the value of peg is valid only when pgm = 1 and/or ers = 1 and after done transitions from 0 to 1 due to an abort or the completion of a program/erase operation. peg is valid until pgm/ers makes a 1 to 0 transition or ehv makes a 0 to 1 transition. the value in peg is not valid after a 0 to 1 transition of done caused by psus or esus being set to logic 1. if pgm and ers are both 1 when done makes a qualifying 0 to 1 transition the value of peg indicates the completion status of the pgm sequence. this happens in an erase-suspended program operation. 0: program or erase operation failed 1: program or erase operation successful if program or erases are atte mpted on blocks that are locked, the response from flash is peg = 1, indicating that the operation was successful, and the contents of the bloc k are properly protected fr om the program or erase operation. pgm program pgm is used to set up flash for a program operation. a 0 to 1 transition of pgm initiates a program sequence. a 1 to 0 transition of pgm ends the program sequence. pgm can be set only under one of the following conditions: ? user mode read (ers is low and ute is low) ? erase suspend (ers and esus are 1) with ehv low pgm can be cleared by the user only when psus and ehv are low and done is high. pgm is cleared on reset. 0: flash is not executing a program sequence. 1: flash is executing a program sequence. in an erase-suspended program, programmi ng flash locations in blocks which were being operated on in the erase may corrupt fc data. this should be avoided due to reliability implications. psus program suspend psus is used to indicate the flash module is in program suspend or in the process of entering a suspend state. the module is in program suspend when psus = 1 and done = 1. psus can be set high only when pgm and ehv are high. a 0 to 1 transition of psus starts the sequence which sets done and places the flash module in program suspend. the module enters suspend within this transition. psus can be cleared only when done and ehv are high. a 1 to 0 transition of psus with ehv = 1 starts the sequence which clears done and returns the flash module to program. the module cannot exit program suspend and clear done while ehv is low. psus is cleared on reset. 0: program sequence is not suspended. 1: program sequence is suspended. ers erase ers is used to set up flash for an erase operation. a 0 to 1 transition of ers initiates an erase sequence. a 1 to 0 transition of ers ends the erase sequence. ers can only be set only in user mode read (pgm is low and ute is low). ers can be cleared by the user only when esus and ehv are low and done is high. ers is cleared on reset. 0: flash is not executing an erase sequence. 1: flash is executing an erase sequence. table 65. mcr field description (continued) field description RM0029 flash memory doc id 15177 rev 8 265/1740 mcr simultaneous register writes a number of mcr bits are protected against write when another bit, or set of bits, is in a specific state. these write locks are covered on a bit by bit basis in the preceding section. the write locks detailed in the previous section do not consider the effects of trying to write two or more bits simultaneously. the effects of writing bits simultaneously which put the module in an illegal state are detailed here. the flash module does not allow the user to write bits simultaneously which put the device into an illegal state. this is implemented through a priority mechanism among the bits. the bit changing priorities are detailed in table 66 . esus erase suspend esus is used to indicate that the flash module is in erase suspend or in the process of entering a suspend state. the module is in erase suspend when esus = 1 and done = 1. esus can be set high only when ers and ehv are high and pgm is low. a 0 to 1 transition of esus starts the sequence which sets done and places the flash in erase suspend. the flash module enters suspend within this transition. esus can be cleared only when done and ehv are high and pgm is low. a 1 to 0 transition of esus with ehv = 1 starts the sequence which clears done and returns the module to erase. the flash module cannot exit erase suspend and clear done while ehv is low. esus is cleared on reset. 0: erase sequence is not suspended. 1: erase sequence is suspended. ehv enable high voltage the ehv bit enables the flash module for a high voltage program/erase operation. ehv is cleared on reset. ehv must be set after an interlock write to start a program/erase sequence. ehv may be set, initiating a program/erase, after an interlock under one of the following conditions: ? erase (ers = 1, esus = 0) ? program (ers = 0, esus = 0, pgm = 1, psus = 0) ? erase-suspended program (ers = 1, esus = 1, pgm = 1, psus = 0) if a program operation is to be initiated while an erase is suspended the user must clear ehv while in erase suspend before setting pgm. in normal operation, a 1 to 0 transition of ehv with done high, psus and esus low terminates the current program/erase high voltage operation. when an operation is aborted, there is a 1 to 0 transition of ehv with done low and the suspend bit for the current program/erase sequence low. an abort causes the value of peg to be cleared, indicating a failed program/erase; address locations being operated on by the aborted operation contain indeterminate data after an abort. a suspended operation cannot be aborted. ehv may be written during suspend. ehv must be high for the flash module to exit suspend. ehv may not be written after a suspend bit is set high and before done transitions high. ehv may not be set low after the current suspend bit is set low and before done transitions low. 0: flash is not enabled to perform a high voltage operation. 1: flash is enabled to perform a high voltage operation. aborting a high voltage operation leaves fc addresses in an indeterminate data state. this may be recovered by executing an erase on the affected blocks. table 65. mcr field description (continued) field description flash memory RM0029 266/1740 doc id 15177 rev 8 if the user attempts to write two or more mcr bits simultaneously then only the bit with the lowest priority level is written. setting two bits with the same priority level is prevented by existing write locks or do not put the flash in an illegal state. for example, setting ers and pgm simultaneously results in only ers being set. attempting to clear ehv while setting psus results in ehv being cleared, while psus is unaffected. low/mid-address space block lock register (lmlr) the low/mid-address space block lock register (lmlr) provides a means to protect blocks from being modified. these bits, along with the sllock bits in the slmlr, determine if the block is locked from program or erase. an ?or? of lmlr and slmlr determines the final lock status. note: a reset value of 1* in figure 58 indicates that the reset value of these registers is determined by flash values in the shadow block. an erased shadow block causes the reset value to be 1. table 66. mcr bit set/clear priority levels priority level mcr bit(s) 1ers 2pgm 3ehv 4 esus, psus figure 58. low/mid-address space block lock register (lmlr) offset 0x0004 access: user read/write r lme0000000000slock0 0 mlock w reset 0 0000000000 x 0 0 x x r 0 00000 llock w reset 0 00000 1* 1* 1* 1* 1* 1* 1* 1* 1* 1* = unimplemented or reserved RM0029 flash memory doc id 15177 rev 8 267/1740 high-address space block lock register (hlr) the high-address space block lock register (hlr) provides a means to protect blocks from being modified. table 67. lmlr field descriptions field description lme low/mid-address lock enable the lme bit is used to enable the lock fields (slock, mlock and llock) to be set or cleared by register writes. lme is a status bit only, and may not be written or cleared, and the reset value is 0. the method to set lme is to write a password, and if the password matches, lme is set to reflect the status of enabled, and is enabled until a reset operation occurs. for lme, the password 0xa1a1_1111 must be written to the lmlr. 0: low/mid-address locks are disabled, and can not be modified. 1: low/mid-address locks are enabled to be written. slock shadow lock this slock bit is used to lock the shadow block from programs and erases. 1: shadow block is locked for program and erase. 0: shadow block is available to receive program and erase pulses. slock is not writable once an interlock write is completed until mcr[done] is set at the completion of the requested operation. likewise, slock is not writable if a high voltage operation is suspended. slock is also not writeable during utest operations, when aie is high. upon reset, information from the shadow block is loaded into slock. the slock bit may be written as a register. reset causes the bits to go back to their shadow block value. the default value of the slock bit (assuming erased shadow location) is locked. slock is not writable unless lme is high. mlock[1:0] mid-address space block lock a value of 1 in a bit of the lock register signifies that the corresponding block is locked for program and erase. a value of 0 in the lock register signifies that the corresponding block is available to receive program and erase pulses. the block numbering for mid-address space starts with mlock[0] and continues until all blocks are accounted. the lock register is not writable once an interlock write is completed until mcr[done] is set at the completion of the requested operation. likewise, the lock register is not writable if a high voltage operation is suspended. mlock is also not writeable during utest operations, when aie is high. upon reset, information from the shadow block is loaded into the block registers. the lock bits may be written as a register. reset causes the bits to go back to their shadow block value. the default value of the lock bits (assuming erased shadow location) is locked. in the event that blocks are not present (due to configuration or total memory size), the lock bits default to be locked, and are not writable. the reset value is always 1 (independent of the shadow block), and register writes have no effect. mlock is not writable unless lme is high. llock[9:0] low-address space block lock a value of 1 in a bit of the lock register signifies that the corresponding block is locked for program and erase. a value of 0 in the lock register signifies that the corresponding block is available to receive program and erase pulses. the block numbering for low-address space starts with llock[0] and continues until all blocks are accounted. for more details on llock, please see mlock field description. llock is not writable unless lme is high. flash memory RM0029 268/1740 doc id 15177 rev 8 note: a reset value of 1* in figure 59 indicates that the reset value of these registers is determined by flash values in the shadow block. an erased shadow block causes the reset value to be 1. t secondary low/mid-address space block lock register (slmlr) the secondary low/mid-address space block lock register (slmlr) provides an alternative means to protect blocks from being modified. this has the effect of creating a ?tiered? locking scheme to enable different flash users to provide different default locking on blocks. these bits, along with the llock bits in the lmlr, determine if the block is locked from program or erase. an ?or? of lmlr and slmlr determine the final lock status. note: a reset value of 1* in figure 60 indicates that the reset value of these registers is determined by flash values in the shadow block. an erased shadow block causes the reset value to be 1. figure 59. high-address space block lock register (hlr) offset 0x0008 access: user read/write r hbe000000000000000 w reset 0000000000000000 r 0000000000 hblock w reset 00000000001*1*1*1*1*1* = unimplemented or reserved table 68. hlr field descriptions field description hbe high-address lock enable this bit is used to enable the lock registers (hblock) to be set or cleared by register writes. this bit is a status bit only, and may not be written or cleared, and the reset value is 0. the method to set this bit is to provide a password, and if the password matches, the hbe bit is set to reflect the status of enabled, and is enabled until a reset operation occurs. for hbe, the password b2b2_2222h must be written to the hlr. 0: high-address locks are disabled, and can not be modified. 1: high-address locks are enabled to be written. hblock[5:0] high-address space block lock hblock has the same characteristics as llock. please see this description for more information. the block numbering for high-address space starts with hblock[0] and continues until all blocks are accounted. hblock is not writable unless hbe is high. RM0029 flash memory doc id 15177 rev 8 269/1740 low/mid-address space block select register (lmsr) the low/mid-address space block select register (lmsr) provides a means to select blocks to be operated on during erase. figure 60. secondary low/mid-address space block lock register (slmlr) offset 0x000c access: user read/write r sle0000000000 sslock 00smlock w reset 000000000001*001*1* r 000000 sllock w reset 0 0 0 0 0 0 1*1*1*1*1*1*1*1*1*1* = unimplemented or reserved table 69. slmlr field descriptions field description sle secondary low/mid-address lock enable the sle bit is used to enable the lock fields (sslock, smlock, and sllock) to be set or cleared by register writes. sle is a status bit only, and may not be written or cleared, and the reset value is 0. the method to set sle is to provide a password, and if the password matches, sle is set to reflect the status of enabled, and is enabled until a reset operation occurs. for sle, the password 0xc3c3_3333 must be written to the slmlr. 0: secondary low/mid-address locks are disabled, and can not be modified. 1: secondary low/mid-address locks are enabled to be written. sslock secondary shadow lock the sslock bit is an alternative method that may be used to lock the shadow block from programs and erases. sslock has the same description as slock. sslock is not writable unless sle is high. smlock[1:0] secondary mid-address block lock the smlock field is an alternative method that may be used to lock the mid-address space blocks from programs and erases. smlock has the same description as mlock. smlock is not writable unless sle is high. sllock[9:0] secondary low-address block lock the sllock field is an alternative method that may be used to lock the low-address space blocks from programs and erases. sllock has the same description as llock. sllock is not writable unless sle is high. flash memory RM0029 270/1740 doc id 15177 rev 8 high-address space block select register (hsr) the high-address space block select register (hsr) provides a means to select blocks to be operated on during erase. figure 61. low/mid-address space block select register (lmsr) offset 0x0010 access: user read/write r 00000000000000 msel w reset 0000000000000000 r 000000 lsel w reset 0000000000000000 = unimplemented or reserved table 70. lmsr field descriptions field description msel[1:0] mid-address space block select a value of 1 in the select register signifies that the block is selected for erase. a value of 0 in the select register signifies that the block is not selected. the reset value for the select registers is 0, or unselected. the blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed until mcr[done] is set at the completion of the requested operation, or if a high voltage operation is suspended. msel is also not writable during utest operations, when aie is high. in the event that blocks are not present (due to configuration or total memory size), the corresponding select bits default to unselected, and are not writable. the reset value is always 0, and register writes have no effect. lsel[9:0] low-address space block select a value of 1 in the select register signifies that the block is selected for erase. a value of 0 in the select register signifies that the block is not selected. the reset value for the select registers is 0, or unselected. the blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed until mcr[done] is set at the completion of the requested operation, or if a high voltage operation is suspended. lsel is also not writable during utest operations, when aie is high. in the event that blocks are not present (due to configuration or total memory size), the corresponding select bits default to unselected, and are not writable. the reset value is always 0, and register writes have no effect. RM0029 flash memory doc id 15177 rev 8 271/1740 address register (ar) the address register (ar) provides the first failing address in the event module failures (ecc or pgm/erase state machine) figure 62. high-address space block select register (hsr) offset 0x0014 access: user read/write r 0000000000000000 w reset 0000000000000000 r 0000000000 hsel w reset 0000000000000000 = unimplemented or reserved table 71. hsr field descriptions field description hsel[26:31] high-address space block select high-address block select has the same characteristics as lsel. figure 63. address register (ar) offset 0x0018 access: user read/write r sad0000000000000addr[14-13] w reset 0000000000000000 r addr[12-0] 0 0 0 w reset 0000000000000000 = unimplemented or reserved flash memory RM0029 272/1740 doc id 15177 rev 8 bus interface unit configuration register (biucr) the bus interface unit configuration register (biucr) is used to specify operation of the dual-flash controller. table 72. ar field descriptions field description sad shadow address the sad bit qualifies the address captured during an ecc event error, single bit correction, or state machine operation. the sad register is not writable. 0: address captured is from main array space. 1: address captured is from shadow array space. addr[14:0] address the addr field provides the first failing address in the event of ecc event error (mcr[eer] set), single bit correction (mcr[sbc] set), as well as providing the address of a failure that may have occurred in a state machine operation (mcr[peg] cleared). ecc event errors take priority over single bit corrections, which take priority over state machine errors. this is especially valuable in the event of a rww operation, where the read senses an ecc error or single bit correction, and the state machine fails simultaneously. this address is always a double word address that selects 64 bits. the addr field is writable, and can be used in the utest ecc logic check. if the ecc logic check is enabled (ut0[eie] = 1) then the ar will not update for ecc event error, single bit correction or state machine errors. if mcr[eer] or mcr[sbc] are set, the ar is locked from writing. mcr[peg] does not affect the writability of the addr field. figure 64. bus interface unit configuration register (biucr) offset: flash_regs_base + 0x001c access: user read/write 0123456789101112131415 r000000000 m6pfe 0 m4pfe 00 m1pfe m0pfe w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r apc wwsc rwsc 0 dpfen 0 ifpfen 0 pflim bfen w reset1111111100000000 RM0029 flash memory doc id 15177 rev 8 273/1740 table 73. biucr field descriptions field description m n pfe master n prefetch enable these bits are used to control whether prefetching may be triggered based on the master id of a requesting master. these bits are cleared by hardware reset. 0: no prefetching may be triggered by this master 1: prefetching may be triggered by this master these bits refer to the master id, not the master port number, as shown in the following: apc address pipelining control this field is used to control the number of cycles between pipelined access requests. it must be set to a value corresponding to the operating frequency of the pflash (1) . higher operating frequencies require non-zero settings for this field for proper flash operation. this field is set to 0b111 by hardware reset. 000: accesses may be pipelined back-to-back 001: access requests require one additional hold cycle 010: access requests require two additional hold cycles ... 110: access requests require six additional hold cycles 111: no address pipelining the settings for apc and rwsc should be the same. wwsc write wait state control this field is used to control the number of wait-states to be added to the best-case flash array access time for writes. the best-case flash array access time for writes is two cycles. this field must be set to a value corresponding to the operating frequency of the pflash 1 . higher operating frequencies require non-zero settings for this field for proper flash operation. this field is set to 0b11 by hardware reset. 00: no additional wait-states are added 01: one additional wait-state is added 10: two additional wait-states are added 11: three additional wait-states are added master id module 0 z4 core instruction 1 z4 core load/store 4edma 6flexray 7 external bus interface (ebi) flash memory RM0029 274/1740 doc id 15177 rev 8 rwsc read wait state control this field is used to control the number of wait-states to be added to the best-case flash array access time for reads. the best-case flash array access time for reads is one cycle. this field must be set to a value corresponding to the operating frequency of the pflash and the actual read access time of the pflash (1) . higher operating frequencies require non-zero settings for this field for proper flash operation. this field is set to 0b111 by hardware reset. 000: no additional wait-states are added 001: one additional wait-state is added ... 111: seven additional wait-states are added the settings for apc and rwsc should be the same. dpfen data prefetch enable this field enables or disables prefetching initiated by a data read access. this field is cleared by hardware reset. 0: no prefetching is triggered by a data read access 1: prefetching may be triggered by any data read access ipfen instruction prefetch enable this bit enables or disables prefetching initiated by an instruction read access. this field is cleared by hardware reset. 0: no prefetching is triggered by an instruction read access 1: prefetching may be triggered by any instruction read access pflim pflash prefetch limit this field controls the prefetch algorithm used by the pflash prefetch controller. this field defines a limit on the maximum number of sequential prefetches which will be attempted between buffer misses. in all situations when enabled, only a single prefetch is initiated on each buffer miss or hit. this field is cleared by hardware reset. 00: no prefetching or buffering is performed. 01: the referenced line is prefetched on a buffer miss, that is, prefetch on miss. 1x: the referenced line is prefetched on a buffer miss, or the next sequential line is prefetched on a buffer hit (if not already present), that is, prefetch on miss or hit. bfen pflash line read buffers enable this bit enables or disables line read buffer hits. it is also used to invalidate the buffers. this bit is cleared by hardware reset. 0: the line read buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1: the line read buffers are enabled to satisfy read requests on hits. buffer valid bits may be set when the buffers are successfully filled. 1. valid settings are specif ied in the device datasheet. table 73. biucr field descriptions (continued) field description RM0029 flash memory doc id 15177 rev 8 275/1740 bus interface unit access protection register (biuapr) figure 65. bus interface unit access protection register (biuapr) offset: flash_regs_base + 0x0020 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 m6ap 00 m4ap 0000 m1ap m0ap w reset0000000011111111 table 74. biuapr field descriptions field description m n ap master n access protection these fields are used to control whether read and write accesses to the flash are allowed based on the master id of a requesting master. 00: no accesses may be performed by this master 01: only read accesses may be performed by this master 10: only write accesses may be performed by this master 11: both read and write accesses may be performed by this master these bits refer to the master id, not the master port number, as shown in the following: master id module 0 z4 core instruction 1 z4 core load/store 4edma 6flexray 7 external bus interface (ebi) flash memory RM0029 276/1740 doc id 15177 rev 8 bus interface unit configuration register 2 (biucr2) user test 0 (ut0) register the user test 0 (ut0) register provides a means to control utest. the utest mode gives the users of the flash module the ability to perform test features on the flash. this register is only writable when the flash is put into utest mode by writing a passcode. figure 66. bus interface unit configuration register 2 (biucr2) offset: flash_regs_base + 0x0024 access: user read/write 0123456789101112131415 r lbcfg 11111111111111 w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r1111111111111111 w reset1111111111111111 table 75. biucr2 field descriptions field description lbcfg line buffer configuration this field controls the configuration of all the line buffers in the pflash controller. the buffers can be organized as a ?pool? of available resources, or with a fixed partition between instruction and data buffers. in all cases, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the group and the just-fetched entry then marked as most-recently-used. if the flash access is for the next-sequential line, the buffer is not marked as most-recently-used until the given address produces a buffer hit. this field is initialized by hardware reset to the value contained in address 0x7e00 of the shadow block of the flash array. an erased or unprogrammed flash sets this field to 0b11. this field controls the configuration of both the 4 x 128 and 4 x 256 line buffers. 00: all four buffers are available for any flash access, that is, there is no partitioning of the buffers based on the access type. 01: reserved 10: the buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses. 11: the buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and buffer 3 for data accesses. RM0029 flash memory doc id 15177 rev 8 277/1740 figure 67. user test 0 (ut0) register offset: flash_regs_base + 0x003c access: user read/write 0123456789101112131415 r ute scbe 000000 dsi w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000ea0 mre mrv eie ais aie aid w reset0000000000000001 table 76. ut0 field descriptions field description ute utest enable this status bit gives indication when utest is enabled. all bits in ut0, ut1, ut2, umisr0, umisr1, umisr2, umisr3, and umisr4 are locked when this bit is 0. this bit is not writable to a 1, but may be cleared. the reset value is 0. the method to set this bit is to provide a password, and if the password matches, the ute bit is set to reflect the status of enabled, and is enabled until it is cleared by a register write. the ute password will only be accepted if mcr[pgm] = 0 and mcr [ers] = 0 (program and erase are not being requested). ute can only be cleared if ut0[aid] = 1, ut0[aie] and ut0[eie] = 0. while clearing ute, writes to set aie or set eie will be ignored. for ute, the password 0xf9f9_9999 must be written to the ut0 register. scbe single bit correction enable sbc enables single bit correction results to be observed in mcr[sbc]. also is used as an enable for interrupt signals created by the c90fl module. ecc corrections that occur when sbce is cleared will not be logged. 0: single bit corrections observation is disabled. 1: single bit correction observation is enabled. dsi data syndrome input these bits enable checks of ecc logic by allowing check bits to be input into the ecc logic and then read out by doing array reads or array integrity checks. the dsi[7:0] correspond to the 8 ecc check bits on a double word. ea ecc algorithm. ea is a status bit that provides information about the ecc algorithm used within the flash. either a modified hamming code is used, or a modified hsiao code is used. 0: default ecc algorithm, modified hamming algorithm. 1: optional/alternative ecc algorithm, modified hsiao algorithm. mre margin read enable mre combined with mrv enables factory margin reads to be done. margin reads are only active during array integrity checks. normal user reads are not affected by mre. mre is not writable if aid is low. 0: margin reads are not enabled. 1: margin reads are enabled during array integrity checks. flash memory RM0029 278/1740 doc id 15177 rev 8 user test 1 (ut1) register the user test 1 (ut1) register provides added controllability to utest. mrv margin read value mrv selects the margin level that is being checked. margin can be checked to an erased level (mrv = 1) or to a programmed level (mrv = 0). in order for this value to be valid, mre must also be set. mrv is not writable if aid is low. 0: zero?s margin reads are requested. 1: one?s margin reads are requested. eie ecc data input enable eie enables the input registers (dsi and dai) to be the source of data for the array. this is useful in the ecc logic check. if this bit is set, data read through a biu read request will be from the dsi and dai registers when an address match is achieved to the ar. eie is not simultaneously writable to a 1 as uti is being cleared to a 0. 0: data read is from the flash array. 1: data read is from the dsi and dai registers. ais array integrity sequence ais determines the address sequence to be used during array integrity checks. the default sequence (ais = 0) is meant to replicate sequences normal ?user? code follows, and thoroughly checks the read propagation paths. this sequence is proprietary. the alternative sequence (ais = 1) is just logically sequential. it should be noted that the time to run a sequential sequence is significantly shorter than the time to run the proprietary sequence. if mre is set, ais has no effect. 0: array integrity sequence is proprietary sequence. 1: array integrity sequence is sequential. aie array integrity enable aie set to one starts the array integrity check done on all selected and unlocked blocks. the address sequence selected is determined by bit ais, and the misr (umisr0 through umisr4) can be checked after the operation is complete, to determine if a correct signature is obtained. once an array integrity operation is requested (aie = 1), it may be terminated by clearing aie if the operation has finished (aid = 1) or aborted by clearing aie if the operation is ongoing (aid = 0). aie is not simultaneously writable to a 1 as uti is being cleared to a 0. 0: array integrity checks are not enabled. 1: array integrity checks are enabled. aid array integrity done aid is cleared upon an array integrity check being enabled (to signify the operation is ongoing). once completed, aid is set to indicate that the array integrity check is complete. at this time the misr (umisr registers) can be checked. aid can not be written, and is status only. 0: array integrity check is ongoing. 1: array integrity check is done. table 76. ut0 field descriptions (continued) field description RM0029 flash memory doc id 15177 rev 8 279/1740 user test 2 (ut2) register figure 68. user test 1 (ut1) register offset: flash_regs_base + 0x0040 access: user read/write 0123456789101112131415 r dai w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dai w reset0000000000000000 table 77. ut1 field descriptions field description dai [31:0] data array input these bits enable checks of ecc logic by allowing data bits to be input into the ecc logic and then read out by doing array reads or array integrity checks. the dai[31:0] correspond to the 32 array bits representing word 0 of the double word selected in the ar. figure 69. user test 2 (ut2) register offset: flash_regs_base + 0x0044 access: user read/write 0123456789101112131415 r dai w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dai w reset0000000000000000 table 78. ut2 field descriptions field description dai [63:32] data array input these bits enable checks of ecc logic by allowing data bits to be input into the ecc logic and then read out by doing array reads or array integrity checks. the dai[63:32] correspond to the 32 array bits representing word 1of the double word selected in the ar. flash memory RM0029 280/1740 doc id 15177 rev 8 user multiple input signature register [0:4] (umisr n ) the user multiple input signature registers (umisr n ) provide a means to evaluate array integrity. figure 70. user multiple input signature register 0 (umisr0) offset: flash_regs_base + 0x0048 access: user read/write r ms[031-016] w reset 0000000000000000 r ms[015-000] w reset 0000000000000000 = unimplemented or reserved figure 71. user multiple input signature register 1 (umisr1) offset: flash_regs_base + 0x004c access: user read/write r ms[063-048] w reset 0000000000000000 r ms[047-032] w reset 0000000000000000 = unimplemented or reserved figure 72. user multiple input signature register 2 (umisr2) offset: flash_regs_base + 0x0050 access: user read/write r ms[095-080] w reset 0000000000000000 r ms[079-064] w reset 0000000000000000 = unimplemented or reserved RM0029 flash memory doc id 15177 rev 8 281/1740 figure 73. user multiple input signature register 3 (umisr3) offset: flash_regs_base + 0x0054 access: user read/write r ms[127-112] w reset 0000000000000000 r ms[111-096] w reset 0000000000000000 = unimplemented or reserved figure 74. user multiple input signature register 4 (umisr4) offset: flash_regs_base + 0x0058 access: user read/write r0000000000000000 w reset 0000000000000000 r ms[143-128] w reset 0000000000000000 = unimplemented or reserved flash memory RM0029 282/1740 doc id 15177 rev 8 table 79. umisr n field descriptions field description ms multiple input signature register bits the ms bitfields accumulate a signature from an array integrity event. the misr captures all data fields, as well as ecc fields, and the read transfer error signal. the misr can be seeded to any value by writing the umisr registers. the umisr provides a means to calculate an misr during array integrity operations. the misr can be represented by the following polynomial: x 145 +x 6 +x 5 +x 1 +1 the misr is calculated by taking the previous misr value and then ?exclusive oring? the new data. in addition the most significant bit (in this case it is misr[144]), is then ?exclusive ored? into input of misr[6], misr[5], misr[1], and misr[0]. the result of the ?exclusive or? is shifted left on each read. the misr is used in array integrity operations. if during address sequencing, reads extend into an invalid address location (i.e., greater than the maximum address for a given array size) or locked/unselected blocks, reads are still executed to the array, but the results from the array read are not deterministic. in this instance, the signature is not recalculated and the previous value is retained. after running the user-test-mode margin read (also referenced as factory margin read) sequence on the c90fl flash module, the misr registers cannot be written such that the next user-test-mode margin read sequence cannot seed the misrs as desired. this will cause the generated misrs to be unexpected for the next user margin read sequences, in case customers want to run the user margin read more than once. to be able to write the misr registers: 1) assert reset after each user margin read sequence so that misrs can be written again. 2) do a dummy program to a locked block after user margin read. RM0029 flash memory doc id 15177 rev 8 283/1740 12.4 functional description 12.4.1 flash user mode in user mode the flash module can be read and written (register writes and interlock writes), programmed or erased. the following subsections define all actions that can be performed in user mode. 12.4.2 flash read and write the default state of the flash module is read. the main and shadow address space can be read only in the read state. the module configuration register (mcr) is always available for read. the flash module enters the read state on reset. the flash module is in the read state under three sets of conditions: the read state is active when pgm = 1 or ers = 1 in the mcr and high-voltage operation is ongoing (read while write). note: reads done to the partition(s) being operated on (either erased or programmed) will result in an error and the rwe bit in the mcr will be set. the read state is active when pgm = 1 and psus = 1 in the mcr (program suspend). the read state is active when ers = 1 and esus = 1 and pgm = 0 in the mcr (erase suspend). note: fc reads are done through the biu. in many cases the biu will do page buffering to allow sequential reads to be done with higher performance. this can create a data coherency issue that must be handled with software. data coherency can be an issue after a program, erase, or shadow row operations. in flash user mode, registers can be written. array can be written to do interlock writes. array reads attempted to invalid locations will result in indeterminate data. invalid locations occur when addressing is done to blocks that do not exist in non 2 n array sizes. interlock writes attempted to invalid locations (due to blocks that do not exist in non 2 n array sizes), will result in an interlock occurring, but attempts to program or erase these blocks will not occur since they are forced to be locked. 12.4.3 read while write (rww) the flash core is divided into partitions. partitions always comprise two or more blocks. partitions are used to determine read-while-write (rww) groupings. while a write (program or erase) is being done within a given partition, a read can be simultaneously executed to any other partition. partitions are listed in table 62 . each partition in high address space comprises two 128 kb blocks. the shadow block has unique rww restrictions described in section 12.4.7, flash shadow block . the fc is also divided into blocks to implement independent erase or program protection. the shadow block exists outside the normal address space and is programmed, erased, and read independently of the other blocks. the shadow block is included to support systems that require nvm for security or system initialization information. a software mechanism is provided to independently lock or unlock each block in high-, mid- , and low-address space against program and erase. two hardware locks are also provided to enable/disable the fc for program/erase. see section , software locking for more information. flash memory RM0029 284/1740 doc id 15177 rev 8 12.4.4 utest mode utest mode is a mode that customers can put the flash module in to do specific tests to check the integrity of the flash module. array integrity self check array integrity is checked using a pre-defined address sequence (based on ut0[ais]), and this operation is executed on selected blocks. the data to be read is customer specific, thus a customer can provide user code into the flash and the correct misr value is calculated. the customer is free to provide any random or non-random code, and a valid misr signature is calculated. once the operations is completed, the results of the reads can be checking by reading the misr value, to determine if an incorrect read, or ecc detection was noted. array integrity is controlled by the system clock (ipg), and it is required that the read wait states and address pipelined control registers in the biu be set to match the user defined frequency being used. note: while array integrity is being executed, flash memory array accesses through the biu should not be requested. the array integrity check consists of the following sequence of events: 1. enable utest mode. 2. select the block, or blocks to receive array integrity check by writing ones to the appropriate registers in lms or hbs registers. note: locked blocks can be tested with array integrity if selected in lms and hbs. note: it is not possible to do utest operations on the shadow block. 3. if desired, set the ut0[ais] bit to 1 for sequential addressing only. note: for normal integrity checks of the flash memory, sequential addressing is recommended. if it is required to more fully check the read path (in a diagnostic mode), it is recommend that ais be left at 0, to use the address sequence that checks the read path more fully, and examine read transitions. this sequence takes more time. 4. seed the misr umisr0 through umisr4 with desired values. 5. set the ut0[aie] bit. a) if desired, the array integrity operation may be aborted prior to ut0[aid] going high. this may be done by clearing the ut0[aie] bit and then continuing to the next step. it should be noted that in the event of an aborted array integrity check the misr registers will contain a signature for the portion of the operation that was completed prior to the abort, and will not be deterministic. prior to doing another array integrity operation, the umisr0, umisr1, umisr2, and umisr3 registers may need to be initialized to the desired seed value by doing register writes. 6. wait until the ut0[aid] bit goes high. 7. read values in the misr registers (umisr0 through umisr4) to ensure correct signature. 8. write a logic 0 to the ut0[aie] bit. factory margin read factory margin read must be done following ?initial factory conditions?. one factory margin read is allowed per erase. RM0029 flash memory doc id 15177 rev 8 285/1740 factory margin read may be done to selected and unlocked blocks by combining ut0[mre] and ut0[mrv] with the array integr ity check. if ut0[mre] is set, ut0[ais] has no affect, and the reads will be done sequentially. the data to be read is customer specific, thus a customer can provide user code into the flash and the correct misr value is calculated. the customer is free to provide any random or non-random code, and a valid misr signature is calculated. once the operations is completed, the results of the reads can be checking by reading the misr value. factory margin read is a self timed event, and is independent of system clocks, or wait states selected. margin ecc corrections or detections are not done during the factory margin read test: 1. enable utest mode. 2. select the block, or blocks to be receive margin read check by writing ones to the appropriate registers in lms or hbs/ehs registers. make sure that selected blocks are also unlocked. note: it is not possible to do utest operations on the shadow block. note: it is possible to do user mode array reads during the factory margin read test, if desired, but the partition rules for read while write used during program and erase are in effect during factory margin reads. 3. set the ut0[mre] bit. 4. set the ut0[mrv] bit to desired value depending on it is desired to do one?s margin or zero?s margin. 5. seed the misr umisr0 thru umisr4 with desired values. 6. set the ut0[aie] bit. a) if desired, the margin read operation may be aborted prior to ut0[aid] going high. this may be done by clearing the ut0[aie] bit and then continuing to the next step. it should be noted that in the event of an aborted margin read check the misr registers will contain a signature for the portion of the operation that was completed prior to the abort, and will not be deterministic. 7. wait until the ut0[aid] bit goes high. 8. read values in the misr registers (umisr0 through umisr4) to ensure correct signature. 9. write a logic 0 to the ut0[aie] bit. note: if it is desired to do two or more margin reads, and it is desired to re-seed the misr, a reset must be done between operations. if the subsequent margin reads can be done with the previously calculated misr value, then a reset is not required. ecc logic check ecc logic can be checked by providing data to be read in the ut0[dsi], ut1[dai] and/or ut2[dai] registers. then array reads can be done, ensuring expected results. the ecc logic check consists of the following sequence of events: flash memory RM0029 286/1740 doc id 15177 rev 8 1. enable utest mode. 2. write ut0[eie] to 1. 3. write ut0[dsi], ut1[dai] and/or ut2[dai] bits to provide data and check bit values to be read. single or double bit detections/corrections can be simulated by properly choosing data and check bit combinations. 4. write double word address to receive the data inputted in step 3 into the adr register. 5. reads can now be done through the biu in a read request type fashion. in the event of a biu read requested from an address that matches the address in the adr register, expected data, and corrections or detections should be observed based on data written into the ut0[dsi], ut1[dai] and/or ut2[dai] registers. mcr[eer] and mcr[sbcsbc] can be checked to evaluate the status of reads done. note: in the event of an ecc error or single bit correction, during the ecc logic check (uto[eie] high), the adr register will not be loaded, and the address tagged to receive the ut0[dsi], ut1[dai] and/or ut2[dai] values will be persevered. 6. once completed, clear the ut0[eie] bit to 0. 12.4.5 flash programming programming changes the value stored in an array bit from logic 1 to logic 0 only. programming cannot change a stored logic 0 to a logic 1. addresses in locked/disabled blocks cannot be programmed. the user can program the values in any or all of four words within a page in a single program sequence. word addresses are selected using bits 3:2 of the page-bound word. whenever a program operation occurs, ecc bits are programmed. ecc is handled on a 64- bit boundary. thus, if only one word in any given 64-bit ecc segment is programmed, the adjoining word (in that segment) should not be programmed because ecc calculation has already completed for that 64-bit segment. attempts to program the adjoining word will probably result in an operation failure. it is recommended that all programming operations be from 64 bits to 128 bits, and be 64-bit aligned. the programming operation should completely fill selected ecc segments within the page. the program operation consists of the following sequence of events: 1. change the value in the mcr[pgm] bit from a 0 to a 1. note: ensure the block that contains the address to be programmed is unlocked. see section , low/mid-address space block lock register (lmlr), section , high-address space block lock register (hlr) and section , secondary low/mid-address space block lock register (slmlr) for more information. 2. write the first address to be programmed in the flash module with the program data. this write is referred to as a program data interlock write. an interlock write may be either be an aligned word or doubleword. 3. if more than one word or doubleword is to be programmed, write each additional address in the page with data to be programmed. this is referred to as a program data write. all unwritten data words default to 0xffff_ffff. 4. write a logic 1 to the mcr[ehv] bit to start the internal program sequence or skip to step 9 to terminate. RM0029 flash memory doc id 15177 rev 8 287/1740 5. wait until the mcr[done] bit goes high. 6. confirm mcr[peg] = 1. 7. write a logic 0 to the mcr[ehv] bit. 8. if more addresses are to be programmed, return to step 2. 9. write a logic 0 to the mcr[pgm] bit to terminate the program sequence. the program sequence is presented graphically in figure 75 . the program suspend operation detailed in figure 75 is discussed in section , flash program suspend/resume . the first write after a program is initiated determines the page address to be programmed. program may be initiated with the 0 to 1 transition of the mcr[pgm] bit or by clearing the mcr[ehv] bit at the end of a previous program. this first write is referred to as an interlock write. if the program is not an erase-suspended program, the interlock write determines if the shadow or normal array space will be programmed and causes mcr[peas] to be set/cleared. in the case of an erase-suspended program, the value in mcr[peas], is retained from the erase. an interlock write must be performed before setting mcr[ehv]. the user may terminate a program sequence by clearing mcr[pgm] prior to setting mcr[ehv]. if multiple writes are done to the same location the data for the last write is used in programming. while mcr[done] is low, mcr[ehv] is high, and mcr[psus] is low, the user may clear mcr[ehv], resulting in a program abort. a program abort forces the module to step 8 of the program sequence. an aborted program will result in mcr[peg] being set low, indicating a failed operation. the data space being operated on before the abort will contain indeterminate data. the user may not abort a program sequence while in program suspend. caution: aborting a program operation will leave the flash core addresses being programmed in an indeterminate data state. this may be recovered by executing an erase on the affected blocks. flash memory RM0029 288/1740 doc id 15177 rev 8 figure 75. program sequence erase suspend user mode read state write mcr pgm = 1 program write step 1 step 2 step 3 write mcr ehv = 1 high voltage active access mcr done step 4 write psus = 1 read mcr done = 1 program suspend pgm = 0 user mode read state peg = 0 read mcr done = 1 done = 0 write mcr psus = 0 ehv = 1 abort write ehv = 0 step 5 step 6 peg success peg = 1 write mcr failure peg = 0 step 7 ehv = 0 pgm more words step 8 ? no yes write mcr pgm = 0 user mode read state step 9 go to step 2 note: peg will remain valid under this condition until ehv is set high or pgm is cleared. note: psus cannot be cleared while ehv = 0. psus and ehv cannot both be changed in a single write operation. peg valid period last write ? yes no esus ? 0 1 erase suspend or erase suspend ? value ? RM0029 flash memory doc id 15177 rev 8 289/1740 software locking a software mechanism is provided to independently lock/unlock each high-, mid-, and low- address space against program and erase. software locking is done through the lmlr (low/mid-address space block lock register), slmlr (secondary low/mid-address space block lock register), or hlr (high-address space block lock register). these can be written through register writes and read through register reads. when the program/erase operations are enabled through hardware, software locks are enforced through doing register writes. flash program suspend/resume the program sequence may be suspended to allow read access to the flash core. it is not possible to erase or program during a program suspend. interlock writes should not be attempted during program suspend. a program suspend can be initiated by changing the value of the mcr[psus] bit from a 0 to a 1. mcr[psus] can be set high at any time when mcr[pgm] and mcr[ehv] are high. a 0 to 1 transition of mcr[psus] causes the flash module to start the sequence to enter program suspend, which is a read state. the module is not suspended until mcr[done] = 1. at this time flash core reads may be attempted. after it is suspended, the flash core may be read only. reads to the blocks being programmed/erased return indeterminate data. the program sequence is resumed by writing a logic 0 to mcr[psus]. mcr[ehv] must be set to a 1 before clearing mcr[psus] to resume operation. when the operation resumes, the flash module continues the program sequence from one of a set of predefined points. this may extend the time required for the program operation. 12.4.6 flash erase erase changes the value stored in all bits of the selected block(s) to logic 1. an erase sequence operates on any combination of blocks in the low, mid or high address space, or the shadow block. the erase sequence is fully automated within the flash. the user only needs to select the blocks to be erased and initiate the erase sequence. locked/disabled blocks cannot be erased. if multiple blocks are selected for erase during an erase sequence, the blocks are erased sequentially starting with the lowest numbered block and terminating with the highest. the erase sequence consists of the following sequence of events: the erase sequence consists of the following sequence of events: 1. change the value in the mcr[ers] bit from 0 to a 1. 2. select the block, or blocks, to be erased by writing 1s to the appropriate bits in lmsr or hsr. if the shadow row is to be erased, this step may be skipped, and lmsr and hsr are ignored. for shadow row erase, see section 12.4.7, flash shadow block for more information. note: lock and select are independent. if a block is selected and locked, no erase will occur. see section , low/mid-address space block lock register (lmlr), section , high-address space block lock register (hlr) and section , secondary low/mid-address space block lock register (slmlr) for more information. flash memory RM0029 290/1740 doc id 15177 rev 8 3. write to any address in flash. this is referred to as an erase interlock write. the interlock write causes the values of soc specific shadow enable to be captured and causing mcr[peas] to be set/cleared. 4. write a logic 1 to the mcr[ehv] bit to start an internal erase sequence or skip to step 9 to terminate. 5. wait until the mcr[done] bit goes high. 6. confirm mcr[peg] = 1. 7. write a logic 0 to the mcr[ehv] bit. 8. if more blocks are to be erased, return to step 2. 9. write a logic 0 to the mcr[ers] bit to terminate the erase. the erase sequence is presented graphically in figure 76 . the erase suspend operation detailed in figure 76 is discussed in section , flash erase suspend/resume . after setting mcr[ers], one write, referred to as an interlock write, must be performed before mcr[ehv] can be set to a 1. this interlock causes the values of soc specific shadow enable to be captured. data words written during erase sequence interlock writes are ignored. the user may terminate the erase sequence by clearing mcr[ers] before setting mcr[ehv]. an erase operation may be aborted by clearing mcr[ehv] assuming mcr[done] is low, mcr[ehv] is high, and mcr[esus] is low. an erase abort forces the module to step 8 of the erase sequence. an aborted erase results in mcr[peg] being set low, indicating a failed operation. the blocks being operated on before the abort contain indeterminate data. the user may not abort an erase sequence while in erase suspend. warning: aborting an erase operation will leave the flash core blocks being erased in an indeterminate data state. this may be recovered by executing an erase on the affected blocks. flash erase suspend/resume the erase sequence may be suspended to allow read access to the fc. the erase sequence may also be suspended to program (erase-suspended program) the fc. a program started during erase suspend can in turn be suspended. only one erase suspend and one program suspend are allowed at a time during an operation. it is not possible to erase during an erase suspend, or program during a program suspend. during suspend, all reads to fc locations targeted for program and blocks targeted for erase return indeterminate data. programming locations in blocks targeted for erase during erase- suspended program may result in corrupted data. read while write may also be used to read the array during an erase sequence providing the read is to a partition not selected for erase. an erase suspend can be initiated by changing the value of the mcr[esus] bit from a 0 to a 1. mcr[esus] can be set to a 1 at any time when mcr[ers] and mcr[ehv] are high and mcr[pgm] is low. a 0 to 1 transition of mcr[esus] causes the module to start the sequence which places it in erase suspend. the user must wait until mcr[done] = 1 before the module is suspended and further actions are attempted. mcr[done] goes high no more than t esus after mcr[esus] is set to a 1. once suspended, the array may be read RM0029 flash memory doc id 15177 rev 8 291/1740 or a program sequence may be initiated (erase-suspended program). before initiating a program sequence the user must first clear mcr[ehv]. if a program sequence is initiated the values of soc specific shadow enable is recaptured. once the erase-suspended program is completed, the value of peas is returned to its ?erase? value. fc reads while mcr[esus] = 1 from the blocks being erased return indeterminate data. the erase sequence is resumed by writing a logic 0 to mcr[esus]. mcr[ehv] must be set to a 1 and mcr[pgm] must be cleared (in the event of an erase suspended program) before mcr[esus] can be cleared to resume the operation. the module continues the erase sequence from one of a set of predefined points. this may extend the time required for the erase operation. warning: repeated suspends at a high frequency may result in the operation timing out, and the flash module will respond by completing the operation with a fail code (mcr[peg] = 0), or the operation not able to finish (mcr[done] = 1 during erase operation). the minimum time between erase suspends to ensure this does not occur is t esrt . warning: in an erase-suspended program, programming flash locations in blocks which were being operated on in the erase may corrupt flash core data. flash memory RM0029 292/1740 doc id 15177 rev 8 figure 76. erase sequence 12.4.7 flash shadow block the flash shadow block is a memory-mapped block in the flash memory map. program and erase of the shadow block are enabled when mcr[peas] = 1 only. after the user has begun an erase operation on the shadow block, the operation cannot be suspended to user mode read state write mcr ers = 1 select blocks erase interlock write step 1 step 2 step 3 write mcr ehv = 1 high voltage active access mcr done ? step 4 write esus = 1 read mcr done = 1 erase suspend ers = 0 user mode read state peg = 0 read mcr done = 1 done = 0 write mcr esus = 0 ehv = 1 abort write ehv = 0 step 5 step 6 peg ? success peg = 1 write mcr failure peg = 0 step 7 ehv = 0 erase more blocks step 8 ? no yes write mcr ers = 0 user mode read state step 9 ehv = 0 write mcr pgm = 1 program, step 2 go to step 2 note: peg will remain valid under this condition until ehv is set high or ers is cleared. note: esus cannot be cleared while ehv = 0. esus and ehv cannot be changed in a single write operation. peg valid period RM0029 flash memory doc id 15177 rev 8 293/1740 program the main address space and vice-versa. the user must terminate the shadow erase operation to program or erase the main address space. note: if an erase of user space is requested, and a suspend is done with attempts to erase suspend program shadow space, this attempted program will be directed to user space as dictated by the state of mcr[peas]. likewise an attempted erase suspended program of user space, while the shadow space is being erased, will be directed to shadow space as dictated by the state of mcr[peas]. the shadow block cannot use the rww feature. after an operation is started in the shadow block, a read cannot be done to the shadow block, or any other block. likewise, after an operation is started in a block in low-/mid-/high-address space, a read cannot be done in the shadow block. the shadow block contains information about how the lock registers are reset. the first and second words can be used for reset configuration words. all other words can be used for user-defined functions or other configuration words. the shadow block may be locked/unlocked against program or erase by using the lmlr or slmlr discussed in section 12.3.2, register descriptions . programming the shadow row has similar restrictions to programming the array in terms of how ecc is calculated. see section 12.4.5, flash programming for more information. only one program is allowed per 64-bit ecc segment between erases. erase of the shadow row is done similarly as an array erase. see section 12.4.6, flash erase for more information. 12.4.8 flash reset a reset is the highest priority operation for the flash and terminates all other operations. the flash uses reset to initialize register and status bits to their default reset values. if the flash is executing a program or erase operation and a reset is issued, the operation will be aborted and the flash will disable the high voltage logic without damage to the high-voltage circuits. reset aborts all operations and forces the flash into user mode ready to receive accesses. after reset is negated, register accesses can be performed, although it should be noted that registers that require updating from shadow information, or other inputs, cannot read updated values until flash exits reset. 12.4.9 dma requests the flash has no dma requests. 12.4.10 interrupt requests the flash has no interrupt requests. memory protection unit (mpu) RM0029 294/1740 doc id 15177 rev 8 13 memory protection unit (mpu) 13.1 introduction the memory protection unit (mpu) provides hardware access control for all memory references generated in a device. using preprogrammed region descriptors that define memory spaces and their associated access rights, the mpu concurrently monitors all system bus transactions and evaluates the appropriateness of each transfer. memory references with sufficient access control rights are allowed to complete, but references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. the mpu implements a set of program-visible region descriptors that monitor all system bus addresses. the result is a hardware structure with a two-dimensional connection matrix, where the region descriptors represent one dimension and the individual system bus addresses and attributes are the second dimension. 13.1.1 features the mpu has these major features: support for 16 memory region descriptors, each 128 bits in size ? specification of start and end addresses provide granularity for region sizes from 32 bytes to 4 gb ? mpu is invalid at reset, thus no access restrictions are enforced ? 2 types of access control definitions: processor core bus master supports the traditional {read, write, execute} permissions with independent definitions for supervisor and user mode accesses; the remaining non-core bus masters (edma, flexray, and ebi (f) ) support {read, write} attributes ? automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a coherent image of the descriptor ? alternate memory view of the access control word for each descriptor provides an efficient mechanism to dynamically alter the access rights of a descriptor only ? for overlapping region descriptors, priority is given to permission granting over access denying as this approach provides more flexibility to system software support for two xbar slave port connections (sram and pbridge) ? for each connected xbar slave port (sram and pbridge), mpu hardware monitors every port access using the preprogrammed memory region descriptors ? an access protection error is detected if a memory reference does not hit in any memory region or the reference is flagged as illegal in all memory regions where it does hit. in the event of an access error, the xbar reference is terminated with an error response and the mpu inhibits the bus cycle being sent to the targeted slave device ? 64-bit error registers, one for each xbar slave port, capture the last faulting address, attributes, and detail information f. ebi not available on all packages and is not available, as a master, for customer. RM0029 memory protection unit (mpu) doc id 15177 rev 8 295/1740 13.1.2 modes of operation the mpu does not support any special modes of operation. 13.2 mpu-to-xbar slave port mapping in some of the register field descriptions, references are made to ?slave ports?. this is not referring to the slave ports of the xbar?it refers instead to the slave ports of the mpu. the mapping is as follows: 13.3 signal description the mpu does not include any external signals. 13.4 memory map and registers this section provides a detailed description of all mpu registers. 13.4.1 module memory map the mpu memory map is shown in table 81 . the address of each register is given as an offset to the mpu base address. registers are listed in address order, identified by complete name and mnemonic, and list the type of accesses allowed. the mpu registers can be referenced using 32-bit (word) accesses only. attempted references using different access sizes, to undefined (reserved) addresses, or with a non- supported access type (for example, a write to a read-only register or a read of a write-only register) generate an error termination. table 80. mpu-to-xbar slave port mapping mpu slave port xbar slave port description 0 2 device sram 1 7 device peripheral bridge (pbridge) table 81. mpu memory map offset from mpu_base (0xfff1_0000) register location 0x0000 mpu_cesr ? mpu control/error status register on page 13- 298 0x0004?0x000f reserved 0x0010 mpu_ear0 ? mpu error address register, slave port 0 on page 13- 299 0x0014 mpu_edr0 ? mpu error detail register, slave port 0 on page 13- 300 memory protection unit (mpu) RM0029 296/1740 doc id 15177 rev 8 0x0018 mpu_ear1 ? mpu error address register, slave port 1 on page 13- 299 0x001c mpu_edr1 ? mpu error detail register, slave port 1 on page 13- 300 0x0020 reserved 0x0024 reserved 0x0028?0x03ff reserved 0x0400 mpu_rgd0 ? mpu region descriptor 0 on page 13- 301 0x0410 mpu_rgd1 ? mpu region descriptor 1 on page 13- 301 0x0420 mpu_rgd2 ? mpu region descriptor 2 on page 13- 301 0x0430 mpu_rgd3 ? mpu region descriptor 3 on page 13- 301 0x0440 mpu_rgd4 ? mpu region descriptor 4 on page 13- 301 0x0450 mpu_rgd5 ? mpu region descriptor 5 on page 13- 301 0x0460 mpu_rgd6 ? mpu region descriptor 6 on page 13- 301 0x0470 mpu_rgd7 ? mpu region descriptor 7 on page 13- 301 0x0480 mpu_rgd8 ? mpu region descriptor 8 on page 13- 301 0x0490 mpu_rgd9 ? mpu region descriptor 9 on page 13- 301 0x04a0 mpu_rgd10 ? mpu region descriptor 10 on page 13- 301 0x04b0 mpu_rgd11 ? mpu region descriptor 11 on page 13- 301 0x04c0 mpu_rgd12 ? mpu region descriptor 12 on page 13- 301 0x04d0 mpu_rgd13 ? mpu region descriptor 13 on page 13- 301 0x04e0 mpu_rgd14 ? mpu region descriptor 14 on page 13- 301 0x04f0 mpu_rgd15 ? mpu region descriptor 15 on page 13- 301 0x00500?0x07ff reserved table 81. mpu memory map (continued) offset from mpu_base (0xfff1_0000) register location RM0029 memory protection unit (mpu) doc id 15177 rev 8 297/1740 13.4.2 register descriptions this section lists the mpu registers in address order and describes the registers and their bitfields. note: the programming model can only be referenced using 32-bit (word) accesses. attempted references using different access sizes, to undefined (reserved) addresses, or with a non- 0x0800 mpu_rgdaac0 ? mpu rgd alternate access control 0 on page 13- 306 0x0804 mpu_rgdaac1 ? mpu rgd alternate access control 1 on page 13- 306 0x0808 mpu_rgdaac2 ? mpu rgd alternate access control 2 on page 13- 306 0x080c mpu_rgdaac3 ? mpu rgd alternate access control 3 on page 13- 306 0x0810 mpu_rgdaac4 ? mpu rgd alternate access control 4 on page 13- 306 0x0814 mpu_rgdaac5 ? mpu rgd alternate access control 5 on page 13- 306 0x0818 mpu_rgdaac6 ? mpu rgd alternate access control 6 on page 13- 306 0x081c mpu_rgdaac7 ? mpu rgd alternate access control 7 on page 13- 306 0x0820 mpu_rgdaac8 ? mpu rgd alternate access control 8 on page 13- 306 0x0824 mpu_rgdaac9 ? mpu rgd alternate access control 9 on page 13- 306 0x0828 mpu_rgdaac10 ? mpu rgd alternate access control 10 on page 13- 306 0x082c mpu_rgdaac11 ? mpu rgd alternate access control 11 on page 13- 306 0x0830 mpu_rgdaac12 ? mpu rgd alternate access control 12 on page 13- 306 0x0834 mpu_rgdaac13 ? mpu rgd alternate access control 13 on page 13- 306 0x0838 mpu_rgdaac14 ? mpu rgd alternate access control 14 on page 13- 306 0x083c mpu_rgdaac15 ? mpu rgd alternate access control 15 on page 13- 306 0x0840?0x3fff reserved table 81. mpu memory map (continued) offset from mpu_base (0xfff1_0000) register location memory protection unit (mpu) RM0029 298/1740 doc id 15177 rev 8 supported access type (for example, a write to a read-only register or a read of a write-only register) generate a bus error termination. mpu control/error status register (mpu_cesr) the mpu_cesr provides one byte of error status and three bytes of configuration information. a global mpu enable/disable bit is also included in this register. figure 77. mpu control/error status register (mpu_cesr) address: mpu_base (0xfff1_0000) + 0x0000 access: supervisor 0 1 23456789101112131415 r sperr[0:7] (1) hrl w reset0 0 00000010000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r nsp nrgd vld w reset0 0 10001000000000 = not implemented 1. each sperr bit can be cleared by writing a one to the bit location. table 82. mpu_cesr field descriptions field description 0?7 sperr slave port n (1) error, where the slave port number matches the bit number each bit in this read-only field represents a flag maintained by the mpu for signaling the presence of a captured error contained in the mpu_ear n and mpu_edr n registers. the individual bit is set when the hardware detects an error and records the faulting address and attributes. it is cleared when the corresponding bit is written to a logical one. if another error is captured at the exact same cycle as a write of a logical one, this flag remains set. a find-first-one instruction (or equivalent) can be used to detect the presence of a captured error. 0 the corresponding mpu_ear n /mpu_edr n registers do not contain an unread captured error 1 the corresponding mpu_ear n /mpu_edr n registers do contain an unread captured error bit 0 indicates an sram access protection error and bit 1 a peripheral bridge protection error. 12?15 hrl hardware revision level this 4-bit read-only field specifies the mpu?s hardware and definition revision level. it can be read by software to determine the functional definition of the module. this field reads as 0 on spc564a74xx, spc564a80xx. 16?19 nsp number of slave ports this 4-bit read-only field specifies the number of slave ports [1?8] connected to the mpu. this field reads as 0b0010 on the spc564a74xx, spc564a80xx at reset, indicating two slaves. RM0029 memory protection unit (mpu) doc id 15177 rev 8 299/1740 mpu error address register, slave port 0 to 1 (mpu_ear n ) when the mpu detects an access error on slave port n (g) , the 32-bit reference address is captured in this read-only register and the corresponding bit in the mpu_cesr[sperr] field is set. additional information about the faulting access is captured in the corresponding mpu_edr n register at the same time. 20?23 nrgd number of region descriptors this 4-bit read-only field specifies the number of region descriptors implemented in the mpu. the defined encodings include: 0000 8 region descriptors 0010 16 region descriptors this field reads as 0b0010 on the spc564a74xx, spc564a80xx 31 vld valid this bit provides a global enable/disable for the mpu. 0 the mpu is disabled 1 the mpu is enabled while the mpu is disabled, all accesses from all bus masters are allowed. 1. see table 80 in section 13.2, mpu-to-xbar slave port mapping , for mpu slave port details. table 82. mpu_cesr field descriptions (continued) field description g. see table 80 in section 13.2, mpu-to-xbar slave port mapping , for mpu slave port details. figure 78. mpu error address register, slave port n (mpu_ear n ) address: mpu_base (0xfff1_0000) + 0x0010 (mpu_ear0) mpu_base (0xfff1_0000) + 0x0018 (mpu_ear1) access: user read only 0 1 23456789101112131415 r eaddr[31:16] w reset? ? ?????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eaddr[16:0] w reset? ? ?????????????? = not implemented memory protection unit (mpu) RM0029 300/1740 doc id 15177 rev 8 mpu error detail register, slave port 0 to 1 (mpu_edr n ) when the mpu detects an access error on slave port n (h) , 32 bits of error detail are captured in this read-only register and the corresponding bit in the mpu_cesr[sperr] field is set. information on the faulting address is captured in the corresponding mpu_ear n register at the same time. a read of the mpu_edr n register clears the corresponding bit in the mpu_cesr[sperr] field. table 83. mpu_ear n field descriptions field description 0?31 eaddr error address this read-only field is the reference address from slave port n that generated the access error. h. see table 80 in section 13.2, mpu-to-xbar slave port mapping , for mpu slave port details. figure 79. mpu error detail register, slave port n (mpu_edr n ) address: mpu_base (0xfff1_0000) + 0x00014 (mpu_edr0) mpu_base (0xfff1_0000) + 0x001c (mpu_edr1) access: user read only 0 1 23456789101112131415 r eacd w reset? ? ?????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r epid emn eattr erw w reset? ? ?????????????? = not implemented table 84. mpu_edr n field descriptions field description 0?15 eacd error access control detail this 16-bit read-only field implements one bit per region descriptor and is an indication of the region descriptor hit logically-anded with the access error indication. the mpu performs a reference-by- reference evaluation to determine the presence/absence of an access error. when an error is detected, the hit-qualified access control vector is captured in this field. if the mpu_edr n register contains a captured error and the eacd field is all zeroes, this signals an access that did not hit in any region descriptor. all non-zero eacd values signal references that hit in a region descriptor(s), but failed due to a protection error as defined by the specific set bits. RM0029 memory protection unit (mpu) doc id 15177 rev 8 301/1740 mpu region descriptor n (mpu_rgd n ) each 128-bit (16-byte) region descriptor specifies a given memory space and the access attributes associated with that space. the descriptor definition is fundamental to the operation of the mpu. the region descriptors are organized sequentially in the mpu?s programming model and each of the four 32-bit words are detailed in the subsequent sections. mpu region descriptor n , word 0 (mpu_rgd n .word0) the first word of the mpu region descriptor defines the 0-modulo-32 byte start address of the memory region. writes to this word clear the region descriptor?s valid bit. 16?23 epid error process identification this 8-bit read-only field records the process identifier of the faulting reference. the process identifier is typically driven by processor cores only; for other bus masters, this field is cleared. 24?27 emn error master number this 4-bit read-only field records the logical master number of the faulting reference. this field is used to determine the bus master that generated the access error. 28?30 eattr error attributes this 3-bit read-only field records attribute information about the faulting reference. the supported encodings are defined as: 000 user mode, instruction access 001 user mode, data access 010 supervisor mode, instruction access 011 supervisor mode, data access all other encodings are reserved. for non-core bus masters, the access attribute information is typically wired to supervisor, data (0b011). 31 erw error read/write this 1-bit read-only field signals the access type (read, write) of the faulting reference. 0read 1write table 84. mpu_edr n field descriptions (continued) field description memory protection unit (mpu) RM0029 302/1740 doc id 15177 rev 8 mpu region descriptor n , word 1 (mpu_rgd n .word1) the second word of the mpu region descriptor defines the 31-modulo-32 byte end address of the memory region. writes to this word clear the region descriptor?s valid bit. figure 80. mpu region descriptor n , word 0 register (mpu_rgd n .word0) address: mpu_base (0xfff1_0000) + (16* n ) + 0x0 (mpu_rgd n .word0) access: user read/write 0123456789101112131415 r srtaddr[26:11] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r srtaddr[10:0] w reset???????????00000 = not implemented table 85. mpu_rgd n word 0 field description field description 0?26 srtaddr start address this field defines the most significant bits of the 0-modulo-32 byte start address of the memory region. figure 81. mpu region descriptor n , word 1 register (mpu_rgd n .word1) address: mpu_base (0xfff1_0000) + (16* n ) + 0x4 (mpu_rgd n .word1) access: user read/write 0123456789101112131415 r endaddr[26:11] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r endaddr[10:0] w reset???????????11111 = not implemented RM0029 memory protection unit (mpu) doc id 15177 rev 8 303/1740 mpu region descriptor n , word 2 (mpu_rgd n .word2) the third word of the mpu region descriptor defines the access control rights of the memory region. the access control privileges are dependent on two broad classifications of bus masters. bus masters 0?3 are typically reserved for processor cores. the corresponding access control is a 6-bit field defining separate privilege rights for user and supervisor mode accesses as well as the optional inclusion of a process identification field within the definition. bus masters 4?7 are typically reserved for data movement engines and their capabilities are limited to separate read and write permissions. for these fields, the bus master number refers to the physical master id defined in tab le 4 9 in chapter 9: multi-layer ahb crossbar switch (xbar) . note: for the processor privilege rights, there are three flags associated with this function: {read, write, execute}. in this context, these flags follow the traditional definition: read (r) permission refers to the ability to access the referenced memory address using an operand (data) fetch. write (w) permission refers to the ability to update the referenced memory address using a store (data) instruction. execute (x) permission refers to the ability to read the referenced memory address using an instruction fetch. writes to this word clear the region descriptor?s valid bit. because it is also expected that system software may adjust only the access controls within a region descriptor (mpu_rgd n .word2) as different tasks execute, an alternate programming view of this 32- bit entity is provided. if only the access controls are being updated, this operation should be performed by writing to mpu_rgdaac n (alternate access control n ) as stores to these locations do not affect the descriptor?s valid bit. the mpu operates on the following masters: m0: e200z4 core m4: edma m6: flexray m7: ebi table 86. mpu_rgd n word 1 field description field description 0?26 endaddr end address this field defines the most significant bits of the 31-modulo-32 byte end address of the memory region. there are no hardware checks to verify that endaddr > srtaddr; the software must properly load these region descriptor fields. memory protection unit (mpu) RM0029 304/1740 doc id 15177 rev 8 figure 82. mpu region descriptor n , word 2 register (mpu_rgd n .word2) address: mpu_base (0xfff1_0000) + 0x400 + (16* n ) + 0x8 (mpu_rgd n .word2) access: user read/write 0123456789101112131415 r m7re m7we m6re m6we m4re m4we w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m0pe m0sm m0um w rwx reset???????????????? = not implemented refer to table 49 , in the xbar chapter, to see the master id assignments. table 87. mpu_rgd n word 2 field description field description 6 m7re bus master id 7 (ebi) read enable if set, this flag allows bus master id 7 to perform read operations. if cleared, any attempted read by bus master id 4 terminates with an access error and the read is not performed. bus master 7 (ebi) is available for factory test only. 7 m7we bus master id 7 (ebi) write enable if set, this flag allows bus master id 7 to perform write operations. if cleared, any attempted write by bus master id 7 terminates with an access error and the write is not performed. bus master 7 (ebi) is available for factory test only. 6 m6re bus master id 6 (flexray) read enable if set, this flag allows bus master id 6 to perform read operations. if cleared, any attempted read by bus master id 6 terminates with an access error and the read is not performed. 7 m6we bus master id 6 (flexray) write enable if set, this flag allows bus master id 6 to perform write operations. if cleared, any attempted write by bus master id 6 terminates with an access error and the write is not performed. 6 m4re bus master id 4 (edma) read enable if set, this flag allows bus master id 4 to perform read operations. if cleared, any attempted read by bus master id 4 terminates with an access error and the read is not performed. 7 m4we bus master id 4 (edma) write enable if set, this flag allows bus master id 4 to perform write operations. if cleared, any attempted write by bus master id 4 terminates with an access error and the write is not performed. bits 8?25 reserved RM0029 memory protection unit (mpu) doc id 15177 rev 8 305/1740 mpu region descriptor n , word 3 (mpu_rgd n .word3) the fourth word of the mpu region descriptor contains the optional process identifier and mask, plus the region descriptor?s valid bit. because the region descriptor is a 128-bit entity, there are potential coherency issues as this structure is being updated because multiple writes are required to update the entire descriptor. accordingly, the mpu hardware assists in the operation of the descriptor valid bit to prevent incoherent region descriptors from generating spurious access errors. in particular, it is expected that a complete update of a region descriptor is typically done with sequential writes to mpu_rgd n .word0, then mpu_rgd n .word1, ... and mpu_rgd n .word3. the mpu hardware automatically clears the valid bit on any writes to words {0,1,2} of the descriptor. writes to this word set/clear the valid bit in a normal manner. because it is also expected that system software may adjust the access controls within a region descriptor (mpu_rgdn.word2) only as different tasks execute, an alternate programming view of this 32-bit entity is provided. if only the access controls are being updated, this operation must be performed by writing to mpu_rgdaac n (alternate access control n ) as stores to these locations do not affect the descriptor?s valid bit. 26 m0pe bus master id 0 (core) process identifier enable. if set, this flag specifies that the process identifier and mask defined in mpu_rgd n .word3 are to be included in the region hit evaluation. if cleared, the region hit evaluation does not include the process identifier. 27?28 m0sm bus master id 0 (core) supervisor mode access control this 2-bit field defines the access controls for bus master id 0 when operating in supervisor mode. the m0sm field is defined as: 00 r, w, x = read, write and execute allowed 01 r, ?, x = read and execute allowed, but no write 10 r, w, ? = read and write allowed, but no execute 11 same access controls as that defined by m0um for user mode 29?31 m0um bus master id 0 (core) user mode access control this 3-bit field defines the access controls for bus master id 0 when operating in user mode. the m0um field consists of three independent bits, enabling read, write, and execute permissions: {r, w, x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. table 87. mpu_rgd n word 2 field description (continued) field description memory protection unit (mpu) RM0029 306/1740 doc id 15177 rev 8 mpu region descriptor alternate access control n (mpu_rgdaac n ) as noted in section , mpu region descriptor n, word 2 (mpu_rgdn.word2) , it is expected that because system software may adjust the access controls within a region descriptor (mpu_rgd n .word2) only as different tasks execute, an alternate programming view of this 32-bit entity is desired. if only the access controls are being updated, this operation should be performed by writing to mpu_rgdaac n (alternate access control n ) as stores to these locations do not affect the descriptor?s valid bit. the memory address therefore provides an alternate location for updating mpu_rgd n .word2. figure 83. mpu region descriptor n , word 3 register (mpu_rgd n .word3) address: mpu_base (0xfff1_0000) + 0x400 + (16* n ) + 0xc (mpu_rgd n .word3) access: user read/write 0123456789101112131415 r pid pidmask w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 00000000 00 0 0 0 vld w reset0000000000000000 = not implemented table 88. mpu_rgd n word 3 field description field description 0?7 pid process identifier this 8-bit field specifies that the optional process identifier is to be included in the determination of whether the current access hits in the region descriptor. this field is combined with the pidmask and included in the region hit determination if mpu_rgd n .word2[mxpe] is set. 8?15 pidmas k process identifier mask this 8-bit field provides a masking capability so that multiple process identifiers can be included as part of the region hit determination. if a bit in the pidmask is set, the corresponding bit of the pid is ignored in the comparison. this field is combined with the pid and included in the region hit determination if mpu_rgd n .word2[mxpe] is set. for more information on the handling of the pid and pidmask, see section , access evaluation?hit determination . 31 vld valid this bit signals the region descriptor is valid. any write to mpu_rgd n .word{0,1,2} clears this bit, but a write to mpu_rgd n .word3 sets or clears this bit depending on bit 31 of the write operand. 0 region descriptor is invalid 1 region descriptor is valid RM0029 memory protection unit (mpu) doc id 15177 rev 8 307/1740 because the mpu_rgdaac n register is another memory mapping for mpu_rgd n .word2, the field definitions shown in ta ble 89 are identical to those presented in tab le 87 . figure 84. mpu rgd alternate access control n (mpu_rgdaac n ) address: mpu_base (0xfff1_0000) + 0x800 + (4* n ) (mpu_rgdaac n ) access: user read/write 0123456789101112131415 r m7re m7we m6re m6we 00 m4re m4we 00000000 w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000 m0pe m0sm m0um w rwx reset???????????????? = not implemented table 89. mpu_rgdaac n field descriptions field description 6 m7re bus master id 7 (ebi) read enable if set, this flag allows bus master id 7 to perform read operations. if cleared, any attempted read by bus master id 4 terminates with an access error and the read is not performed. bus master 7 (ebi) is available for factory test only. 7 m7we bus master id 7 (ebi) write enable if set, this flag allows bus master id 7 to perform write operations. if cleared, any attempted write by bus master id 7 terminates with an access error and the write is not performed. bus master 7 (ebi) is available for factory test only. 6 m6re bus master id 6 (flexray) read enable if set, this flag allows bus master id 6 to perform read operations. if cleared, any attempted read by bus master id 6 terminates with an access error and the read is not performed. 7 m6we bus master id 6 (flexray) write enable if set, this flag allows bus master id 6 to perform write operations. if cleared, any attempted write by bus master id 6 terminates with an access error and the write is not performed. bits 4?5 reserved these bits must never be set. 6 m4re bus master id 4 read enable if set, this flag allows bus master id 4 to perform read operations. if cleared, any attempted read by bus master id 4 terminates with an access error and the read is not performed. memory protection unit (mpu) RM0029 308/1740 doc id 15177 rev 8 13.5 functional description in this section, the functional operation of the mpu is detailed. in particular, subsequent sections discuss the operation of the access evaluation macro as well as the handling of error-terminated xbar bus cycles. 13.5.1 access evaluation as discussed, the basic operation of the mpu is performed in the access evaluation macro, a hardware structure replicated in the two-dimensional connection matrix. the access evaluation macro inputs the xbar system bus address and the contents of a region descriptor (rgd n ) and performs two major functions: region hit determination and detection of an access protection violation. access evaluation?hit determination to determine if the current xbar reference hits in the given region, two magnitude comparators are used with the region?s start and end addresses. there are no hardware checks to verify that the region end address is greater than or equal to the region start address. the software must properly load appropriate values into these fields of the region descriptor. in addition to the comparison of the xbar reference address versus the region descriptor?s start and end addresses, the optional process identifier is examined against the region descriptor?s pid and pidmask fields. for xbar bus masters that do not output a process identifier, the mpu forces the pid term to be asserted. 7 m4we bus master 4 write enable if set, this flag allows bus master 4 to perform write operations. if cleared, any attempted write by bus master 4 terminates with an access error and the write is not performed. bits 8?25 reserved 26 m0pe bus master 0 process identifier enable if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 27?28 m0sm bus master 0 supervisor mode access control this 2-bit field defines the access controls for bus master 0 when operating in supervisor mode. the m0sm field is defined as: 00 r, w, x = read, write and execute allowed 01 r, ?, x = read and execute allowed, but no write 10 r, w, ? = read and write allowed, but no execute 11 same access controls as that defined by m0um for user mode 29?31 m0um bus master 0 user mode access control this 3-bit field defines the access controls for bus master 0 when operating in user mode. the m0um field consists of three independent bits, enabling read, write, and execute permissions: {r, w, x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. table 89. mpu_rgdaac n field descriptions (continued) field description RM0029 memory protection unit (mpu) doc id 15177 rev 8 309/1740 access evaluation?privilege violation determination while the access evaluation macro is making the region hit determination, the logic is also evaluating if the current access is allowed by the permissions defined in the region descriptor. using the xbar supervisor/user mode signals, a set of permissions is generated from the appropriate fields in the region descriptor. the protection violation logic evaluates the access against the effective permissions. the access evaluation macro then uses the hit and permission signals to determine if the current access is allowed and the mpu_edr n (error detail register) is updated in the event of an error. 13.5.2 xbar error terminations for each xbar slave port being monitored, the mpu tests any access for permission violations as above. if a violation occurs, the mpu terminates the bus cycle and reports a protection error for three conditions: 1. if the access does not hit in any region descriptor, a protection error is reported. 2. if the access hits in a single region descriptor and that region signals a protection violation, a protection error is reported. 3. if the access hits in multiple (overlapping) regions and all regions signal protection violations, then a protection error is reported. the third condition reflects that priority is given to permission granting over access denying for overlapping regions as this approach provides more flexibility to system software in region descriptor assignments. for an example of the use of overlapping region descriptors, see section 13.7, application information . when the mpu causes a termination error to occur, the effect on the system depends on the bus master requesting the access. if the error was caused by a core access, a machine check is taken. if the error was caused by an edma access, an edma source or destination error occurs in the edma controller, which can be enabled to provide an interrupt request through the intc. if the error was caused by a flexray access, a controller host interface (chi) illegal system memory access error occurs in the flexray controller, which can be enabled to provide an interrupt request to the intc. 13.6 initialization information the reset state of mpu_cesr[vld] disables the entire module. while the mpu is disabled, all accesses from all bus masters are allowed. this state also minimizes the power dissipation of the mpu. the power dissipation of each access evaluation macro is minimized when the associated region descriptor is marked as invalid or when mpu_cesr[vld] = 0. typically the appropriate number of region descriptors (mpu_rgd n ) are loaded at system startup, including the setting of the mpu_rgd n .word3[vld] bits, before mpu_cesr[vld] is set, enabling the module. this approach allows all the loaded region descriptors to be enabled simultaneously. once the mpu is enabled, if a memory reference does not hit in any region descriptor, the attempted access is terminated with an error. memory protection unit (mpu) RM0029 310/1740 doc id 15177 rev 8 13.7 application information in an application?s system, interfacing with the mpu can generally be classified into the following activities: 1. creation of a new memory region requires loading the appropriate region descriptor into an available register location. when a new descriptor is loaded into a rgd n , it would typically be performed using four 32-bit word writes. as discussed in section , mpu region descriptor n, word 3 (mpu_rgdn.word3) , the hardware assists in the maintenance of the valid bit, so if this approach is followed, there are no coherency issues associated with the multi-cycle descriptor writes. deletion/removal of an existing memory region is performed by clearing mpu_rgd n .word3[vld]. 2. if only the access rights for an existing region descriptor need to change, a 32-bit write to the alternate version of the access control word (mpu_rgdaac n ) would typically be performed. writes to the region descriptor using this alternate access control location do not affect the valid bit, so there are, by definition, no coherency issues involved with the update. the access rights associated with the memory region switch instantaneously to the new value as the ips write completes. 3. if the region?s start and end addresses are to be changed, this would typically be performed by writing a minimum of three words of the region descriptor: mpu_rgd n .word{0,1,3}, where the writes to word0 and word1 redefine the start and end addresses respectively and the write to word3 re-enables the region descriptor valid bit. in many situations, all four words of the region descriptor would be rewritten. 4. typically, references to the mpu?s programming model would be restricted to supervisor mode accesses from a specific processor(s), so a region descriptor would be specifically allocated for this purpose with attempted accesses from other masters or while in user mode terminated with an error. 5. when the mpu detects an access error, the current xbar bus cycle is terminated with an error response and information on the faulting reference captured in the mpu_ear n and mpu_edr n registers. the error-terminated xbar bus cycle typically initiates some type of error response in the originating bus master. for example, a processor core may respond with a bus error exception, while a data movement bus master may respond with an error interrupt. in any event, the processor can retrieve the captured error address and detail information simply be reading the mpu_e{a,d}r n registers. information on which error registers contain captured fault data is signaled by mpu_cesr[sperr]. 6. finally, consider the use of overlapping region descriptors. application of overlapping regions can reduce the number of descriptors required for a given set of access controls. in the overlapping memory space, the protection rights of the corresponding region descriptors are logically summed together (the boolean or operator). in the following example of a dual-core system, there are four bus masters: the two processors (cp0, cp1) and two dma engines (edma, a traditional data movement engine transferring data between ram and peripherals, and flexray, a second engine transferring data to/from the ram only). consider the region descriptor assignments shown in ta ble 90 : RM0029 memory protection unit (mpu) doc id 15177 rev 8 311/1740 in this example, there are eight descriptors used to span nine regions in the three main spaces of the system memory map (flash, ram, and ips peripheral space). each region indicates the specific permissions for each of the four bus masters and this definition provides an appropriate set of shared, private and executable memory spaces. of particular interest are the two overlapping spaces: region descriptors 2 and 3, and 3 and 4. the space defined by rgd2 with no overlap is a private data and stack area that provides read/write access to cp0 only. the overlapping space between rgd2 and rgd3 defines a shared data space for passing data from cp0 to cp1 and the access controls are defined by the logical or of the two region descriptors. thus, cp0 has (r w ? | r ? ?) = (r w ?) permissions, while cp1 has (? ? ? | r ? ?) = (r ? ?) permission in this space. both dma engines are excluded from this shared processor data region. the overlapping spaces between rgd3 and rgd4 defines another shared data space, this one for passing data from cp1 to cp0. for this overlapping space, cp0 has (r ? ? | ? ? ?) = (r ? ?) permission, while cp1 has (r w ? | r ? ?) = (r w ?) permission. the non-overlapped space of rgd4 defines a private data and stack area for cp1 only. the space defined by rgd5 is a shared data region, accessible by all four bus masters. finally, the slave peripheral space mapped onto the peripheral bus is partitioned into two regions: one (rgd6) containing the mpu?s programming model accessible only to the two processor cores, and the remaining peripheral region (rgd7) accessible to both processors and the traditional edma master. this example is intended to show one possible application of the capabilities of the memory protection unit in a typical system. warning: program code occupies the end of the mpu region (#0) in which core instruction accesses are allowed. the address region immediately afterwards is protected by the mpu table 90. overlapping region descriptor example region description rgd n cp0 cp1 edma flexray memory map space cp0 code 0 r w x r ? ? ? ? ? ? flash cp1 code 1 r ? ? r w x ? ? ? ? cp0 data & stack 2 r w ? ? ? ? ? ? ? ? ram cp0 ?> cp1 shared data 3 r ? ? r ? ? ? ? ? ? cp1 ?> cp0 shared data cp0 data & stack 4 ? ? ? r w ? ? ? ?? shared dma data 5 r w ? r w ? r w r w mpu 6 r w ? r w ? ? ? ? ? ips peripherals 7 r w ? r w ? r w ? ? memory protection unit (mpu) RM0029 312/1740 doc id 15177 rev 8 (region #1) from instruction fetches by the core (or any pid=1 access). if the last instruction in the mpu region #0 space is a branch which the core takes while the core attempts to fetch instructions via instruction cache line fill from the mpu region #1 the mpu asserts a bus error (a pid=1 executable access into a region which only allows read/write accesses from pid=2). the core immediately takes the exception as a 'machine check'. in this case, modify the 'machine check' exception handler to expect this behavior. RM0029 external bus interface (ebi) doc id 15177 rev 8 313/1740 14 external bus interface (ebi) 14.1 information specific to this device this section presents device-specific parameterization and customization information not specifically referenced in the remainder of this chapter. 14.1.1 device-specific features 3.3 v operation 24-bit address bus (2 most significant signals multiplexed with 2 chip selects) the spc564a74xx, spc564a80xx mcu has only 16 data bus signals pinned out. the data bus can be multiplexed with the address bus to have a 32-bit data width mode. memory controller with support for various memory types: ? asynchronous/legacy flash and sram bus monitor ? user selectable ? programmable timeout period (with 8 external bus clock resolution) configurable wait states (via chip selects) three chip-select (cal_cs[0], cal_cs[2:3]) signals (multiplexed with 2 most significant address signals) for the calibration bus. 4 chip selects for ebi configurable bus speed modes ? system frequency ? 1/2 of system frequency ? 1/4 of system frequency optional automatic clkout gating to save power and reduce emi selectable drive strengths; 10 pf, 20 pf, 30 pf, 50 pf note that the spc564a74xx, spc564a80xx ebi implementation doesn?t support external arbitration burst is supported in spc564a74xx, spc564a80xx mcu only by the external bus interface (not by the calibration interface) 14.1.2 unsupported features external arbitration 14.2 introduction the external bus interface (ebi) provides an on-board interface for mapping external memory to the spc564a74xx, spc564a80xx microcontroller. the ebi includes a memory controller that generates interface signals to support a variety of external memory types, including single data rate (sdr) burst mode flash, sram, and asynchronous memories. external bus interface (ebi) RM0029 314/1740 doc id 15177 rev 8 14.2.1 overview on the spc564a74xx, spc564a80xx microcontroller, the ebi supports two sets of external signals: the ebi bus signals and the calibration bus signals. they are very similar in function but have different purposes. the calibration bus is a powerful development feature that enables system designers to interface dual-port sram with a system under development. this gives the system the capability of loading engine calibration data into sram instead of flash memory, making reprogramming the calibration data considerably faster and avoids the necessity of having to reconfigure pins each time calibration data is changed. note: the calibration signals are only available on the calibration package. it is a very useful development feature but not used in production systems. figure 85 shows an overview of the ebi, including the calibration signals. each external memory component used is mapped to its own addressing region. each region is separately programmable with region address and bus configuration information. available bus configurations include 16-bit, 16-bit multiplexed and 32-bit multiplexed. in the multiplexed modes. address and data signals are multiplexed on the same pins. RM0029 external bus interface (ebi) doc id 15177 rev 8 315/1740 figure 85. external bus interface with calibration bus calibration ebi controls region 0 controls external memory 0 region 2 controls external memory 2 region 3 controls external memory 3 cal_addr[13:30] cal_data[0:31] clkout cal_we[2:3]/ be [2:3] cal_ts cal_we[0:1] cal_rd_ wr cal_oe cal_cs0 cal_cs3 cal_cs2 cs0 cs2 cs1 cs3 external memory 1 external memory 2 external memory 3 external memory 0 addr[13:30] data[0:31] clkout we[0:1]/be [0:1] ts we[0:3] rd_wr oe bdip region 0 controls region 2 controls region 3 controls region 0 controls system ebi controls ale ale ta external bus interface (ebi) RM0029 316/1740 doc id 15177 rev 8 14.2.2 features note: this list is a superset list of all possible features the ebi supports. refer to section 14.1, information specific to this device , for details on specifics for a particular device due to package limitations. 32-bit address bus with transfer size indication (only 24-29 available on pins) 32-bit data bus (16-bit data bus mode also supported) multiplexed address on data pins (single master) memory controller with support for various memory types: ? synchronous burst sdr flash and sram ? asynchronous/legacy flash and sram burst support (wrapped only) bus monitor port size configuration per chip select (16 or 32 bits) configurable wait states configurable internal or external transfer acknowledge (ta ) per chip select support for dynamic calibration with up to 4 chip-selects four write/byte enable (we [0:3]/be [0:3]) signals slower-speed clock modes stop and module disable modes for power savings optional automatic clkout gating to save power and reduce emi misaligned access support (for chip-select accesses only) 14.2.3 modes of operation the mode of the ebi is determined by the mdis, extm, and ad_mux bits in the ebi_mcr. see section , ebi module configuration register (ebi_mcr) for details. slower-speed modes, debug mode, stop mode, and factory test mode are modes that the mcu may enter, in parallel to the ebi being configured in one of its block-specific modes. single master mode in single master mode, the ebi responds to internal requests matching one of its regions, but ignores all externally-initiated bus requests. the mcu is the only master allowed to initiate transactions on the external bus in this mode; therefore, it acts as a parked master and does not have to arbitrate for the bus before starting each cycle. single master mode is entered when extm=0 and mdis=0 in the ebi_mcr. module disable mode the module disable mode is used for mcu power management. the clock to the non- memory mapped logic in the ebi can be stopped while in module disable mode. internal master requests made to the external bus in module disable mode are terminated with transfer error. module disable mode is entered when mdis=1 in the ebi_mcr. stop mode when a request is made to enter stop mode (controlled in device logic outside ebi), the ebi block completes any pending bus transactions and acknowledges the stop request. after the acknowledgement, the system clock input may be shut off by the clock driver on the RM0029 external bus interface (ebi) doc id 15177 rev 8 317/1740 mcu. while the clocks are shut off, the ebi is not accessible. while in stop mode, accesses to the ebi from the internal master will terminate with transfer error. slower-speed modes in slower-speed modes, the external clkout frequency is divided (by 2, 3, etc.) compared with that of the internal system bus. the ebi behavior remains dictated by the mode of the ebi, except that it drives and samples signals at the clkout frequency rather than the internal system frequency. this mode is selected by writing a clock control register in a block outside of the ebi. refer to the device-specific documentation to see which slower-speed modes are available for a particular mcu (1/2, 1/3, etc.). 16-bit data bus mode for mcus that have only 16 data bus signals pinned out, or for systems where the use of a different multiplexed function (e.g. gpio) is desired on 16 of the 32 data pins, the ebi supports a 16-bit data bus mode. in this mode, only 16 data signals are used by the ebi. the user can select which 16 data signals are used (data[0:15] or data[16:31]) by writing the d16_31 bit in the ebi_mcr. for ebi-mastered accesses, the operation in 16-bit data bus mode (dbm=1, ps=x) is similar to a chip-select access to a 16-bit port in 32-bit data bus mode (dbm=0, ps=1), except for the case of a non-chip-select access of exactly 32-bit size. ebi-mastered non-chip-select accesses of exactly 32-bit size are supported via a two (16- bit) beat burst for both reads and writes. see section , non-chip-select burst in 16-bit data bus mode . non-chip-select transfers of non-32-bit size are supported in standard non-burst fashion. 16-bit data bus mode is entered when dbm=1 in the ebi_mcr. some mcus may have dbm=1 by default out of reset. see the device-specific documentation for the dbm and d16_31 reset values. multiplexed address on data bus mode this mode covers several cases aimed at reducing pin count on mcu and external components. in this mode, the data pins will drive (for internal master cycles) the address value on the first clock of the cycle (while ts is asserted).the memory controller supports per-chip-select selection of multiplexing address/data through the brx[ad_mux] bit. address on data bus multiplexing also supports the 16-bit data bus mode (mcr[dbm]=1) and 16-bit memories (orx[ps]=1). the user can select which 16 data signals are used (data[0:15] or data[16:31]) by writing the d16_31 bit in the ebi_mcr. for either setting of d16_31, the 16 lsbs of external address (a ddr[16:31]) are driven onto the selected 16 data pins. if additional address lines are required to interface to the memory, then non- muxed address pins are sometimes (see note below) required to complete the address space (e.g. addr[8:15] are commonly present as non-muxed address pins). note: the ebi also drives the unused 16 data signals with the msbs of the external address, zero-padded in front (e.g. when d16_31 bit is set for a device with 24 addr pins, the ebi drives (0b00000000,addr[8:15]) on data[0:15]. this allows the device to optionally use data[8:15] for the upper 8 external address lines instead of requiring separate non-muxed addr[8:15] pins. this is relevant primarily for devices that support both 32-bit and 16-bit a/d muxed operation, so therefore have data[0:31] pins present on the device, and in that case are not required to have separate addr pins. for more details (e.g. timing diagrams), see section , address data multiplexing . external bus interface (ebi) RM0029 318/1740 doc id 15177 rev 8 debug mode when the mcu is in debug mode, the ebi behavior is unaffected and remains dictated by the mode of the ebi. mode summary table ta ble 91 summarizes pin usage by ebi mode. table 91. typical pin usage across supported ebi modes pin ebi usage mode 16-bit non- muxed (1) pcr[pa] 16-bit muxed (2) pcr[pa] 32-bit muxed (3) pcr[pa] 0:3 cs[0:3], addr[8:11] or gpio[0:3] as rqd. (4) ? cs[0:3], addr[8:11] or gpio[0:3] as rqd. (4) ? cs[0:3] or gpio[0:3] as rqd. (4) ? 8 addr[12] 0b001 addr[12] 0b001 gpio[8] (5) 0b000 9:10 addr[13:14] 0b001 addr[13:14] 0b001 we[2:3] 0b100 11 addr[15] 0b001 addr[15] 0b001 gpio[11] (5) 0b000 12:27 addr[16:31] 0b001 gpio[12:27] or flexray usage (5) 0b000 / 0b010 data[16:31] / addr[16:31] (6) 0b100 28:43 data[0:15] 0b001 data[0:15] / addr[16:31] 0b001 data[0:15] / addr[0:15] (6) 0b001 62 rd_wr 0b001 rd_wr 00b01 rd_wr 0b001 63 bdip 0b001 bdip 0b001 bdip 0b001 64 we[0]/be[0] 0b001 we[0]/be[0] 0b001 we[0]/be[0] 0b001 65 we[1]/be[1] 0b001 we[1]/be[1] 0b001 we[1]/be[1] 0b001 68 oe 0b001 oe 0b001 oe 0b001 69 ts 0b001 ale 0b010 ale 0b010 70 ta 0b001 ts 0b010 ts 0b010 1. 16-bit non-multiplexed mode supported for ebi configured with ebi_mcr[d16_31]=0, and respective brx/cal_brx[ad_mux]=0. pin multiplexing does not support 16-bit non multiplexed mode for ebi configured with ebi_mcr[d16_31]=1. 2. 16 bit multiplexed mode shown for ebi configured with ebi_mcr[d16_31]=0, and respective brx/cal_brx[ad_mux]=1. this is the optimal 16 bit mux mode, as it allows access to flexray signals on unused ebi signals. operation also possible with ebi_mcr[d16_31]=1, using data[16:31] signals for ebi and leaving data[0:15] balls available for gpio use. 3. 32-bit multiplexed mode shown for ebi configured with ebi_mcr[d16_31]=0, and respective brx/cal_brx[ad_mux]=1. 4. pin functionality chosen dependent on required addressing range and chip select availability. 5. pin function/s not required to support ebi in this usage mode. 6. data/address dynamically multiplexed in ternally by ebi, not siu pin muxing. RM0029 external bus interface (ebi) doc id 15177 rev 8 319/1740 14.3 external signal description 14.3.1 overview ta ble 92 lists the external pins used by the ebi. not all signals listed here are available external to the chip. 14.3.2 detailed signal descriptions note: this section lists the superset of signals for the ebi. refer to section 14.1, information specific to this device , for device-specific package limitations and possible signal renaming. addr [3:31] ? address lines 3-31 the addr[3:31] signals specify the physical address of the bus transaction. the 29 address lines correspond to bits 3-31 of the ebi?s 32-bit internal address bus. bdip ? burst data in progress bdip is asserted to indicate that the master is requesting another data beat following the current one. this signal is driven by the ebi on all ebi-mastered external burst cycles, but is only sampled by burst mode memories that have a corresponding pin. see section , burst transfer . table 92. signal properties name i/o type function pull (1) 1. this column shows which signals require a weak pullup or pulldown. the ebi block does not contain these pullup/pulldown devices within the block. they are assumed to be in another module of the mcu (e.g. pads module). addr[3:31] i/o address bus ? bdip output burst data in progress up clkout (2) 2. the clkout signal is driven by the system clock block outside the ebi. output clockout ? cal_cs[0:3] output calibration chip selects up data[0:31] i/o data bus (3) 3. in address/data multiplexing modes, data w ill also show the address during the address phase. ? oe output output enable up rd_wr i/o read_write up ta i/o transfer acknowledge up ts i/o transfer start up we [0:3]/be [0:3] output write/byte enables up external bus interface (ebi) RM0029 320/1740 doc id 15177 rev 8 clkout ? clockout clkout is a general-purpose clock output signal to connect to the clock input of sdr external memories and in some cases to the input clock of another mcu in multi-master configurations. cal_cs [0:3] ? calibration chip selects 0-3 cal_cs x is asserted by the master to indicate that this transaction is targeted for a particular memory bank on the calibration external bus. the calibration chip selects are driven only by the ebi. external master accesses on the calibration bus are not supported. in all other aspects, the calibration chip-selects behave exactly as the primary chip-selects. see section , memory controller with support for various memory types for details on chip-select operation. data [0:31] ? data lines 0-31 the data[0:31] signals contain the data to be transferred for the current transaction. data[0:31] is driven by the ebi when it owns the external bus and it initiates a write transaction to an external device.data[0:31] is driven by an external device during a read transaction from the ebi.for 8-bit and 16-bit transactions, the byte lanes not selected for the transfer do not supply valid data. data[0:31] is driven by the ebi in the addr ess phase with the addr value if the address on data multiplexing mode is enabled. see section , multiplexed address on data bus mode, for details. in 16-bit data bus mode, (or for chip-select accesses to a 16-bit port), only data[0:15] or data[16:31] are used by the ebi, depending on the setting of the d16_31 bit in the ebi_mcr. see section , 16-bit data bus mode . oe ? output enable oe is used to indicate when an external memory is permitted to drive back read data. external memories must have their data output buffers off when oe is negated. oe is only asserted for chip-select accesses. for read cycles, oe is asserted one clock after ts assertion and held until the termination of the transfer. for write cycles, oe is negated throughout the cycle. rd_wr ? read / write rd_wr indicates whether the current transaction is a read access or a write access. rd_wr is driven in the same clock as the assertion of ts and valid address, and is kept valid until the cycle is terminated. ta ? transfer acknowledge ta is asserted to indicate that the slave has received the data (and completed the access) for a write cycle, or returned data for a read cycle. if the transaction is a burst read, ta is asserted for each one of the transaction beats. for write transactions, ta is only asserted once at access completion, even if more than one write data beat is transferred. ta is driven by the ebi when the access is controlled by the chip selects (and seta=0). otherwise, ta is driven by the slave device to which the current transaction was addressed. RM0029 external bus interface (ebi) doc id 15177 rev 8 321/1740 see section , termination signals protocol for more details. ts ? transfer start ts is asserted by the current bus owner to indicate the start of a transaction on the external bus. ts is only asserted for the first clock cycle of the transaction, and is negated in the successive clock cycles until the end of the transaction. we [0:3] / be [0:3] ? write/byte enables 0-3 write enables are used to enable program operations to a particular memory. these signals can also be used as byte enables for read and write operation by setting the webs bit in the appropriate base register. we [0:3]/be[0:3] are only asserted for chip-select accesses. for chip-select accesses to a 16-bit port, only we [0:1]/be [0:1] are used by the ebi, regardless of which half of the data bus is selected via the d16_31 bit in the ebi_mcr. see section , four write/byte enable (we/be) signals for more details on we [0:3]/be [0:3] functionality. 14.3.3 signal output buffer enable logic by mode ta ble 93 describes how the ebi drives its output buffer enable (obe) signals. these are internal signals from the ebi to device logic outside the ebi, that determine when the ebi strongly drives values on pins. when the obe for an ebi signal is asserted (1), the ebi strongly drives the value on that pin. when the obe is negated (0), the ebi does not drive the signal, and the value is determined by internal or external pullups/pulldowns, and/or device logic outside ebi block. the logic in ta ble 93 can be overwritten by device logic, so see the device-specific documentation for any exceptions to the logic below. table 93. signal output buffer enable logic by mode (1) signal obe value by mode (1=strongly driven, 0=not driven by ebi) module disable mode (2) (extm=x, mdis=1) single master mode (extm=0, mdis=0) addr[3:31] 0 1 bdip 0 1 cal_cs [0:3] 0 1 data[0:31] 0 only 1 during write access or on address phase when addr/data muxing is enabled. oe 01 rd_wr 01 ta 0 only 1 during chip-select (or cal-chip- select) seta=0 access ts 01 we [0:3]/be [0:3] 0 1 1. the values in this table only indicate when signals are strongly driven, not the logic value on the pin itself. external bus interface (ebi) RM0029 322/1740 doc id 15177 rev 8 14.4 memory map/register definition ta ble 94 shows the ebi registers. 14.4.1 register descriptions note: other than the exceptions noted below, ebi registers must not be written while a transaction to the ebi (from internal master) is in progress (or within 2 clkout cycles after a transaction has just completed, to allow internal state machines to go idle). in those cases, the behavior is undefined. exceptions that can be written while an ebi transaction is in progress: - all bits in ebi_tesr 2. this assumes that the clock to the ebi is shut off when mdis=1. this is an optional device feature. if the clocks are left running to ebi even when mdis=1, then the ebi obe behavior is as if in single master mode (though ebi accesses are not supported in this scenario). table 94. ebi address map address use ebi_base (0xc3f8_4000) ebi module configuration register (ebi_mcr) ebi_base+0x4 reserved ebi_base+0x8 ebi transfer error status register (ebi_tesr) ebi_base+0xc ebi bus monitor control register (ebi_bmcr) ebi_base+0x10 ebi base register bank 0 (ebi_br0) ebi_base+0x14 ebi option register bank 0 (ebi_or0) ebi_base+0x18 ebi base register bank 1 (ebi_br1) ebi_base+0x1c ebi option register bank 1 (ebi_or1) ebi_base+0x20 ebi base register bank 2 (ebi_br2) ebi_base+0x24 ebi option register bank 2 (ebi_or2) ebi_base+0x28 ebi base register bank 3 (ebi_br3) ebi_base+0x2c ebi option register bank 3 (ebi_or3) ebi_base+0x30 ? ebi_base+0x3c reserved ebi_base+0x40 ebi calibration base register bank 0 (ebi_cal_br0) ebi_base+0x44 ebi calibration option register bank 0 (ebi_cal_or0) ebi_base+0x48 ebi calibration base register bank 1 (ebi_cal_br1) ebi_base+0x4c ebi calibration option register bank 1 (ebi_cal_or1) ebi_base+0x50 ebi calibration base register bank 2 (ebi_cal_br2) ebi_base+0x54 ebi calibration option register bank 2 (ebi_cal_or2) ebi_base+0x58 ebi calibration base register bank 3 (ebi_cal_br3) ebi_base+0x5c ebi calibration option register bank 3 (ebi_cal_or3) RM0029 external bus interface (ebi) doc id 15177 rev 8 323/1740 see section 14.6.1, booting from external memory for related application information. ebi module configuration register (ebi_mcr) figure 86. ebi module configuration register (ebi_mcr) the ebi module configuration register contains bits which configure various attributes associated with ebi operation. ebi_base+0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r acge 0 0 0 0 0 0 0 0 mdis 0 0 0 d16_31 ad_mux dbm w reset: 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 = unimplemented or reserved table 95. ebi module configuration re gister (ebi_mcr) field descriptions name description 16 acge acge - automatic clkout gating enable the acge bit enables the ebi feature of turning off clkout (holding it high) during idle periods in-between external bus accesses. 1: automatic clkout gating is enabled 0: automatic clkout gating is disabled 25 mdis mdis ? module disable mode the mdis bit controls an internal ebi ?enable clk? signal which can be used (if mcu logic supports) to control the clocks to the ebi. the mdis bit allows the clock to be stopped to the non-memory mapped logic in the ebi, effectively putting the ebi in a software controlled power-saving state. see section , module disable mode for more information. no external bus accesses can be performed when the ebi is in module disable mode (mdis=1). 1: module disable mode is active (negate ?enable clk? signal) 0: module disable mode is inactive (assert ?enable clk? signal) external bus interface (ebi) RM0029 324/1740 doc id 15177 rev 8 29 d16_31 d16_31 ? data bus 16_31 select the d16_31 bit controls whether the ebi uses the data[0:15] or data[16:31] signals, when in 16- bit data bus mode (dbm=1) or for chip-select accesses to a 16-bit port (ps=1). for systems using a/d muxing with a 16-bit port, it is recommended to set d16_31 to 1. 1: data[16:31] signals are used for 16-bit port accesses 0: data[0:15] signals are used for 16-bit port accesses 30 ad_mux ad_mux ? address on data bus multiplexing mode the ad_mux bit controls whether non-chip-select accesses have the address driven on the data bus in the address phase of a cycle. 1: address on data multiplexing mode is used for non-cs accesses. 0: only data on data pins for non-cs accesses. 31 dbm dbm ? data bus mode the dbm bit controls whether the ebi is in 32-bit or 16-bit data bus mode. 1: 16-bit data bus mode is used 0: 32-bit data bus mode is used table 95. ebi module configuration re gister (ebi_mcr) field descriptions name description RM0029 external bus interface (ebi) doc id 15177 rev 8 325/1740 ebi transfer error status register (ebi_tesr) figure 87. ebi transfer error status register (ebi_tesr) the ebi transfer error status register contains a bit for each type of transfer error on the external bus. a bit set to logic 1 indicates what type of transfer error occurred since the last time the bits were cleared. each bit can be cleared by reset or by writing a 1 to it. writing a 0 has no effect. this register may not be writable in module disable mode due to the use of power saving clock modes, e.g., a bus error can be generated on a timeout. ebi_base+0x8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bmtf w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 96. ebi transfer error status re gister (ebi_tesr) field descriptions name description 31 bmtf bmtf ? bus monitor timeout flag this bit is set if the cycle was terminated by a bus monitor timeout. 1: bus monitor timeout occurred 0: no error external bus interface (ebi) RM0029 326/1740 doc id 15177 rev 8 ebi bus monitor control register (ebi_bmcr) the ebi bus monitor control register controls the timeout period of the bus monitor and whether it is enabled or disabled. figure 88. ebi bus monitor control register (ebi_bmcr) ebi_base+0xc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bmt bme 0 0 0 0 0 0 0 w reset: 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 = unimplemented or reserved table 97. ebi bus monitor control regi ster (ebi_bmcr) field descriptions name description 16-23 bmt bmt ?bus monitor timing this field defines the timeout period, in 8 external bus clock resolution, for the bus monitor. see section , bus monitor for more details on bus monitor operation. timeout period = (2 + (8 * bmt)) / external bus clock frequency. 24 bme bme ?bus monitor enable this bit controls whether the bus monitor is enabled for internal to external bus cycles. the bme bit is ignored (treated as 0) for chip-select accesses with internal ta (seta=0). 1: enable bus monitor (for external ta accesses only) 0: disable bus monitor RM0029 external bus interface (ebi) doc id 15177 rev 8 327/1740 ebi base registers (ebi_br0-ebi_br3, ebi_cal_br0-3) the ebi base registers are used to define the base address and other attributes for the corresponding chip select. figure 89. ebi base registers (ebi_br0-ebi_br3, ebi_cal_br0-3) ebi_base+0x10, ebi_base+0x18, ebi_base+0x20, ebi_base+0x28, ebi_base+0x40, ebi_base+0x48, ebi_base+0x50, ebi_base+0x58 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ba w reset: (1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ba 0 0 0 ps 0 0 0 ad_mux bl webs tbdip 0 seta bi v w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 = unimplemented or reserved 1. some upper bits of the ba field may be tied to a fixed value, in which case the reset value is this fixed value and not zero. refer to section 14.1, information specific to this device , to see which bits this applies to, if any. table 98. ebi base registers (ebi_br0-ebi_br3, ebi_cal_br0-3) field descriptions name description 0-16 ba ba ? base address these bits are compared to the corresponding unmasked address signals among addr[0:16] of the internal address bus to determine if a memory bank controlled by the memory controller is being accessed by an internal bus master. an mcu may have some of the upper bits of the ba field tied to a fixed value internally in order to restrict the address range of the ebi for that mcu. refer to the device-specific docu mentation to see which bits are tied off, if any, for a particular mcu. tied- off bits can be read but not written. these bits are ignored by the ebi during the chip-select address com parison. however, the internal bridge of the mcu most likely requires that the chip-select banks be located in memory regions corresponding to the fixed values chosen. 20 ps ps ? the ps bit determines the data bus width of transactions to this chip-select bank. in the case where the dbm bit in ebi_mcr is set for 16-bit data bus mode, the ps bit value is ignored and is always treated as a ?1? (16-bit port). 1: 16-bit port 0: 32-bit port external bus interface (ebi) RM0029 328/1740 doc id 15177 rev 8 24 ad_mux ad_mux ? address on data bus multiplexing the ad_mux bit controls whether accesses for this chip select have the address driven on the data bus in the address phase of a cycle 1: address on data multiplexing mode is enabled for this chip select. 0: address on data multiplexing mode is disabled for this chip select. 25 bl bl ? burst length (1) the bl bit determines the amount of data transferred in a burst for this chip select, measured in 32-bit words. the number of beats in a burst is automatically determined by the ebi to be 4, 8, or 16 according to the port size (ps bit) so that the burst fetches the number of words chosen by bl. for internal amba data bus width of 32-bits, the bl bit is ignored (treated as 1). the ebi does not support a 2-word external burst length. this means that neither a 4-beat burst to a 16- bit external memory (nor a 2-beat burst to 32-bit external memory) are supported. 26 webs webs ? write enable / byte select this bit controls the functionality of the we [0:3]/be [0:3] signals. 1: the we [0:3]/be [0:3] signals function as be [0:3] 0: the we [0:3]/be [0:3] signals function as we [0:3] 27 tbdip tbdip ? toggle burst data in progress this bit determines how long the bdip signal is asserted for each data beat in a burst cycle. see section , tbdip effect on burst transfer for details. 1: only assert bdip (bscy+1) external cycles before expecting subsequent burst data beats 0: assert bdip throughout the burst cycle, regardless of wait state configuration table 98. ebi base registers (ebi_br0-ebi_br3, ebi_cal_br0-3) field descriptions (continued) name description value burst length (1) 1. total amount of data fetched in a burst transfer. ps # beats in burst (2) 2. number of external data beats used in external burst transfer. the size of each beat is determined by ps value. 0 (3) 3. an 8-word burst length is only supported for device?s using 64-bit amba data bus width to ebi. 8-word (4) 4. a word always refers to 32-bits of data, regardless of ps. 0 (32-bit) 8 1 (16-bit) 16 14-word 0 (32-bit) 4 1 (16-bit) 8 RM0029 external bus interface (ebi) doc id 15177 rev 8 329/1740 29 seta seta ? select external transfer acknowledge the seta bit controls whether accesses for this chip select will terminate (end transfer without error) based on externally asserted ta or internally asserted ta . seta should only be set when the bi bit is 1 as well, since burst accesses with seta=1 are not supported. setting seta=1 causes the bi bit to be ignored (treated as 1, burst inhibited). 1: transfer acknowledge (ta ) is an input to the ebi, data phase will be terminated by an external device 0: transfer acknowledge (ta ) is an output from the ebi, data phase will be terminated by the ebi 30 bi bi ? burst inhibit 1 this bit determines whether or not burst read accesses are allowed for this chip-select bank. the bi bit is ignored (treated as 1) for chip-select accesses with external ta (seta=1). 1: disable burst accesses for this bank. this is the default value out of reset (or when seta=1). 0: enable burst accesses for this bank 31 v v ? valid bit the user writes this bit to indicate that the contents of this base register and option register pair are valid. the appropriate cs signal does not assert unless the corresponding v-bit is set. 1: this bank is valid 0: this bank is not valid 1. cal_br0-3 registers do not support burst operation. table 98. ebi base registers (ebi_br0-ebi_br3, ebi_cal_br0-3) field descriptions (continued) name description external bus interface (ebi) RM0029 330/1740 doc id 15177 rev 8 ebi option registers (ebi_or0-ebi_or3, ebi_cal_or0-3) the ebi option registers are used to define the address mask and other attributes for the corresponding chip select. figure 90. ebi option registers (e bi_or0-ebi_or3, ebi_cal_or0-3) ebi_base+0x14, ebi_base+0x1c, ebi_base+0x24, ebi_base+0x2c, ebi_base+0x44, ebi_base+0x4c, ebi_base+0x54, ebi_base+0x5c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r am w reset: (1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r am 0 0 0 0 0 0 0 scy 0 bscy 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. some upper bits of the am field may be tied to a fixed value, in which case the reset value is this fixed value and not zero. refer to section 14.1, information specific to this device , to see which bits this applies to, if any. table 99. ebi option registers (ebi_or0-ebi_or3, ebi_cal_or0-3) field descriptions name description 0-16 am am ? address mask this field allows masking of any corresponding bits in the associated base register. masking the address independently allows external devices of different size address ranges to be used. any clear bit masks the corresponding address bit. any set bit causes the corresponding address bit to be used in comparison with the address pins. address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. this field can be read or written at any time. an mcu may have some of the upper bits of the am field tied to a fixed value internally in order to restrict the address range of the ebi for that mcu. see the corresponding note for the base register ba field for more details. refer to the devic e-specific documentation to see whic h bits are tied off, if any, for a particular mcu. tied-off bits can be read but not written. RM0029 external bus interface (ebi) doc id 15177 rev 8 331/1740 24-27 scy scy ? cycle length in clocks this field represents the number of wait states (external cycles) inserted after the address phase in the single transfer case, or in the first beat of a burst, when the memory controller handles the external memory access. values range from 0 to 15. this is the main parameter for determining the length of the cycle. these bits are ignored when seta=1. the total cycle length for the first beat (including the ts cycle) = (2+scy) external clock cycles. see section , example wait state calculation for related application information. 29-30 bscy bscy ? burst beats length in clocks (1) this field determines the number of wait states (external cycles) inserted in all burst beats except the first, when the memory controller starts handling the external memory access and thus is using scy[0:3] to determine the length of the first beat. these bits are ignored when seta=1. the total memory access length for each beat is (1 + bscy) external clock cycles. the total cycle length (including the ts cycle) = (2+scy) + (#beats (2) -1) * (bscy+1). 1. cal_br0-3 registers do not support burst operation. 2. #beats is the number of beats (4,8,16) determined by bl and ps bits in base register. table 99. ebi option registers (ebi_or0-ebi_or3, ebi_cal_or0-3) field descriptions (continued) name description value meaning 00 0-clock cycle wait states (1 clock per data beat) 01 1-clock cycle wait states (2 clocks per data beat) 10 2-clock cycle wait states (3 clocks per data beat) 11 3-clock cycle wait states (4 clocks per data beat) external bus interface (ebi) RM0029 332/1740 doc id 15177 rev 8 14.5 functional description 14.5.1 external bus interface features 32-bit data bus (16-bit data bus mode also supported) the entire 32-bit data bus is available for external memory accesses. there is also a 16-bit data bus mode available via the dbm bit in ebi_mcr. see section , 16-bit data bus mode . multiplexed address on data pins (single master) when this mode is enabled, the address shows up on the data pins during the address phase of the cycle. this mode can be enabled separately for non-chip-select accesses and per chip-select access. see section , multiplexed address on data bus mode . memory controller with support for various memory types the ebi contains a memory controller that supports a variety of memory types, including synchronous burst mode flash and sram, and asynchronous/legacy flash and sram with a compatible interface. each cs bank is configured via its own pair of base and option registers. each time an internal to external bus cycle access is requested, the internal address is compared with the base address of each valid base register (with 17 bits having mask). see figure 91 . if a match is found, the attributes defined for this bank in its br and or are used to control the memory access. if a match is found in more than one bank, the lowest bank matched handles the memory access (e.g., bank 0 is selected over bank 1). a match on a valid calibration chip-select register overrides a match on any non-calibration chip-select register, with cal_cs0 having the highest priority. thus the full priority of the chip-selects is: cal_cs0,...,cal_cs3,cs0,...,cs3. figure 91. bank base address & match structure am [0] am [1] am [2] am [3] am [4] am [5] [16] [15] [1] [4] [3] [2] ba [0] comp comp comp comp comp comp comp am[0:16] a[0:16] base address address mask match ba ba ba ba ba ba am am [6] [16] RM0029 external bus interface (ebi) doc id 15177 rev 8 333/1740 when a match is found on one of the chip-select banks, all its attributes (from the appropriate base and option registers) are selected for the functional operation of the external memory access, such as: number of wait states for a single memory access, and for any beat in a burst access burst enable port size for the external accessed device see section , ebi base registers (ebi_br0-ebi_br3, ebi_cal_br0-3) and section , ebi option registers (ebi_or0-ebi_or3, ebi_cal_or0-3) for a full description of all chip- select attributes. when no match is found on any of the chip-select banks, the default transfer attributes shown in table 100 are used. burst support (wrapped only) the ebi supports burst read accesses of external burstable memory. to enable bursts to a particular memory region, clear the bi (burst inhibit) bit in the appropriate base register. external burst lengths of 4 and 8 words are supported. burst length is configured for each chip select by using the bl bit in the appropriate base register. see section , burst transfer for more details on burst operation. in 16-bit data bus mode (dbm=1 in ebi_mcr), a special 2-beat burst case is supported for reads and writes for 32-bit non-chip-select accesses only. this is to allow 32-bit coherent accesses to another mcu. see section , non-chip-select burst in 16-bit data bus mode . bursting of accesses that are not controlled by the chip selects is not supported for any other case besides the special case of 32-bit accesses in 16-bit data bus mode. burst writes are not supported for any other case besides the special case of 32-bit non- chip-select writes in 16-bit data bus mode. internal requests to write >32 bits (such as a cache line) externally are broken up into separate 32-bit or 16-bit external transactions according to the port size. see section , small accesses (small port size and short burst length) for more detail on these cases. table 100. default attributes for non-chip-select transfers cs attribute default value comment ps 0 32-bit port size bl 0 burst length is don?t care since burst is disabled webs 0 write enables tbdip 0 don?t care since burst is disabled bi 1 burst inhibited scy 0 don?t care since external ta is used bscy 0 don?t care since external ta is used ad_mux 0 address on data multiplexing seta 1 select external ta to terminate access external bus interface (ebi) RM0029 334/1740 doc id 15177 rev 8 bus monitor when enabled (via the bme bit in the ebi_bmcr), the bus monitor detects when no ta assertion is received within a maximum timeout period for external ta accesses. the timeout for the bus monitor is specified by the bmt field in the ebi_bmcr. each time a timeout error occurs, the bmtf bit is set in the ebi_tesr. the timeout period is measured in external bus (clkout) cycles. thus the effective real-time period is multiplied (by 2, 3, etc.) when a slower-speed mode is used, even though the bmt field itself is unchanged. port size configuration per chip select (16 or 32 bits) the ebi supports memories with data widths of 16 or 32 bits. the port size for a particular chip select is configured by writing the ps bit in the corresponding base register. configurable wait states from 0 to 15 wait states can be programmed for any cycle that the memory controller generates, via the scy bits in the appropriate option register. from 0 to 3 wait states between burst beats can be programmed using the bscy bits in the appropriate option register. configurable internal or external ta per chip select each chip select can be configured (via the seta bit) to have ta driven internally (by the ebi), or externally (by an external device). see section , ebi base registers (ebi_br0- ebi_br3, ebi_cal_br0-3) for more details on seta bit usage. support for dynamic calibration with up to 4 chip-selects the ebi contains 4 calibration chip select signals, controlling 4 independent memory banks on an optional 2nd external bus for calibration. see section , calibration bus operation for more details on using the calibration bus. four write/byte enable (we /be ) signals the functionality of the we [0:3]/be [0:3] signals depends on the value of the webs bit in the corresponding base register. setting webs to 1 configures these pins as be [0:3], while resetting it to 0 configures them as we [0:3]. we [0:3] are asserted only during write accesses, while be [0:3] is asserted for both read and write accesses. the timing of the we [0:3]/be [0:3] signals remains the same in either case. the upper write/byte enable (we0 /be0 ) indicates that the upper eight bits of the data bus (data[0:7]) contain valid data during a write/read cycle. the upper middle write/byte enable (we1 /be1 ) indicates that the upper middle eight bits of the data bus (data[8:15]) contain valid data during a write/read cycle. the lower middle write/byte enable (we2 /be2 ) indicates that the lower middle eight bits of the data bus (data[16:23]) contain valid data during a write/read cycle. the lower write/byte enable (we3 /be3 ) indicates that the lower eight bits of the data bus (data[24:31]) contain valid data during a write/read cycle. note: the exception to the preceding we /be description is that for 16-bit port transfers (dbm=1 or ps=1), only the we [0:1]/be [0:1] signals are used, regardless of whether data[0:15] or data[16:31] are selected (via the d16_31 bit in the ebi_mcr). this means for the case where data[16:31] are selected, that we0 indicates that data[16:23] contains valid data, and we1 indicates that data[24:31] contains valid data. the write/byte enable lines affected in a transaction for a 32-bit port (ps = 0) and a 16-bit port (ps=1) are shown in table 101 . only big endian byte ordering is supported by the ebi. RM0029 external bus interface (ebi) doc id 15177 rev 8 335/1740 slower-speed clock modes for memories that cannot run with a full-speed external bus, the ebi supports slower-speed clock modes. refer to section , slower-speed modes for more details on this feature. the timing diagrams for slower-speed modes are identical to those for full-speed mode, except that the frequency of clkout is reduced. stop and module disable modes for power savings see section 14.2.3, modes of operation for a description of the power saving modes. optional automatic clkout gating the ebi has the ability to hold the external clkout pin high when the ebi?s internal master state machine is idle and no requests are pending. the ebi outputs a signal to the pads logic in the mcu to disable clkout. this feature is disabled out of reset, and can be enabled or disabled by the acge bit in the ebi_mcr. note: this feature must be disabled for multi-master systems. in those cases, one master is getting its clock source from the other master and needs it to stay valid continuously. misaligned access support the ebi has limited misaligned access support. misaligned non-burst chip-select transfers from internal masters are supported. the ebi aligns the accesses when it sends them out to the external bus (splitting them into multiple aligned accesses if necessary), so that external devices are not required to support misaligned accesses. burst accesses (internal master) table 101. write/byte enable signals function (1) 1. this table applies to aligned internal master transfers only. in the case of a misaligned internal master transfer that is split into multiple ali gned external transfers, not all of the write enables x?d in the table will necessarily assert. see section , misaligned access support . transfer size address 32-bit port size 16-bit port size (2) 2. also applies when dbm=1 for 16-bit data bus mode. a30 a31 we0 / be0 we1 / be1 we2 / be2 we3 / be3 we0 / be0 we1 / be1 we2 / be2 we3 / be3 byte 00 x x 01 x x 10 x x 11 x x 16-bit 00xx xx 10 xxxx 32-bit00xxxxx (3) 3. this case consists of two 16-bit exter nal transactions, but for both transactions the we [0:1]/be [0:1] signals are the only we /be signals affected. x (3) burst00xxxxxx external bus interface (ebi) RM0029 336/1740 doc id 15177 rev 8 must match the internal bus size (64-bit aligned). see section , misaligned access support for more details. 14.5.2 external bus operations the following sections provide a functional description of the external bus, the bus cycles provided for data transfer operations, and error conditions. external clocking the clkout signal sets the frequency of operation for the bus interface directly. internally, the mcu uses a phase-locked loop (pll) circuit to generate a master clock for all of the mcu circuitry (including the ebi) which is phase-locked to the clkout signal. in general, all signals for the ebi are specified with respect to the rising-edge of the clkout signal, and they are guaranteed to be sampled as inputs or changed as outputs with respect to that edge. reset upon detection of internal reset assertion, the ebi immediately ends all transactions (abruptly, not through normal termination protocol), and ignores any transaction requests that take place while reset is asserted. basic transfer protocol the basic transfer protocol defines the sequence of actions that must occur on the external bus to perform a complete bus transaction. a simplified scheme of the basic transfer protocol is shown in figure 92 . figure 92. basic transfer protocol the arbitration phase is where bus ownership is requested and granted. this phase is not needed in single master mode because the ebi is the permanent bus owner in this mode. the address transfer phase specifies the address for the transaction and the transfer attributes that describe the transaction. the signals related to the address transfer phase are ts , addr (or data if address/data multiplexing is used), cs [0:3], rd_wr , and bdip . the address and its related signals (with the exception of ts , bdip ) are driven on the bus with the assertion of the ts signal, and kept valid until the bus master receives ta asserted (the ebi holds them one cycle beyond ta for writes and external ta accesses). note that for writes with internal ta , rd_wr is not held one cycle past ta . the data transfer phase performs the transfer of data, from master to slave (in write cycles) or from slave to master (on read cycles), if any is to be transferred. the data phase may transfer a single beat of data (1-4 bytes) for non-burst operations or a 2-beat (special dbm=1 case only), 4-beat, 8-beat, or 16-beat burst of data (2 or 4 bytes per beat depending on port size) when burst is enabled. on a write cycle, the master must not drive write data until after the address transfer phase is complete. this is to avoid electrical contentions when switching between drivers. the master must start driving write data one cycle after the arbitration address transfer data transfer termination RM0029 external bus interface (ebi) doc id 15177 rev 8 337/1740 address transfer cycle. the master can stop driving the data bus as soon as it samples the ta line asserted on the rising edge of clkout. to facilitate asynchronous write support, the ebi keeps driving valid write data on the data bus until 1 clock after the rising edge where rd_wr and we are negated (for chip-select accesses only). see figure 98 for an example of write timing. on a read cycle, the master accepts the data bus contents as valid on the rising edge of the clkout in which the ta signal is sampled asserted. see figure 94 for an example of read timing. the termination phase is where the cycle is terminated by the assertion of either ta (normal termination) or tea (termination with error). termination is discussed in detail in section , termination signals protocol . note: in the timing diagrams in this document, asynchronous relationships between signals that switch in the same clkout cycle are not guaranteed. for example, in figure 98 , we and write data change during the same clkout cycle. there is no guarantee that data will be stable before we assertion. external devices should not be latching write data on we assertion, but instead must use a signal edge that takes place in a later clkout cycle, such as we negation. single beat transfer the flow and timing diagrams in this section assume that the ebi is configured in single master mode. therefore, arbitration is not needed and is not shown in these diagrams. single beat read flow the handshakes for a single beat read cycle are illustrated in the following flow and timing diagrams. external bus interface (ebi) RM0029 338/1740 doc id 15177 rev 8 figure 93. basic flow diagram of a single beat read cycle master (ebi) slave asserts transfer start (ts ) drives address and attributes receives address drives data asserts transfer acknowledge (ta ) receives data cs access & !seta? yes no asserts transfer acknowledge (ta ) RM0029 external bus interface (ebi) doc id 15177 rev 8 339/1740 figure 94. single beat 32-bit read cycle, cs access, zero wait states figure 95. single beat 32-bit read cycle, cs access, one wait state data is valid clkout addr[3:31] ts ta rd_wr bdip oe cs [ n ] data[0:31] wait state data is valid clkout addr[3:31] ts ta rd_wr bdip oe cs [ n ] data[0:31] external bus interface (ebi) RM0029 340/1740 doc id 15177 rev 8 figure 96. single beat 32-bit read cycle, non-cs access, zero wait states single beat write flow the handshakes for a single beat write cycle are illustrated in the following flow and timing diagrams. data is valid the ebi drives address and control signals an extra cycle because it uses a latched version of the external ta (1 cycle delayed) to terminate the cycle. * * clkout addr[3:31] ts ta (input) rd_wr bdip oe cs [ n ] data[0:31] RM0029 external bus interface (ebi) doc id 15177 rev 8 341/1740 figure 97. basic flow diagram of a single beat write cycle master slave asserts transfer start (ts ) drives address and attributes receives address drives data asserts transfer acknowledge (ta ) stops driving data cs access & ! seta? yes no asserts transfer acknowledge (ta ) receives data waits 1 clock external bus interface (ebi) RM0029 342/1740 doc id 15177 rev 8 figure 98. single beat 32-bit write cycle, cs access, zero wait states figure 99. single beat 32-bit write cycle, cs access, one wait state data is valid clkout addr[3:31] ts ta rd_wr bdip cs [ n ] data[0:31] we [0:3] wait state data is valid clkout addr[3:31] ts ta rd_wr bdip cs [ n ] data[0:31] we [0:3] RM0029 external bus interface (ebi) doc id 15177 rev 8 343/1740 figure 100. single beat 32-bit write cycle, non-cs access, zero wait states back-to-back accesses due to internal bus protocol, one dead cycle is necessary between back-to-back external bus accesses that are not part of a set of small accesses (see section , small accesses (small port size and short burst length) for small access timing). a dead cycle refers to a cycle between the ta of a previous transfer and the ts of the next transfer. note: in some cases, cs remains asserted during this dead cycle, such as the cases of back-to- back writes or read-after-write to the same chip-select. see figure 104 and figure 105 . besides this dead cycle, in most cases, back-to-back accesses on the external bus do not cause any change in the timing from that shown in the previous diagrams, and the two transactions are independent of each other. the only exceptions to this are listed below: back-to-back accesses where the first access ends with an externally-driven ta or tea . in these cases, an extra cycle is required between the end of the first access and the ts assertion of the second access. see section , termination signals protocol for more details. the following diagrams show a few examples of back-to-back accesses on the external bus. data is valid clkout addr[3:31] ts ta (input) rd_wr bdip cs [ n ] data is valid the ebi drives address and control signals an extra cycle because it uses a latched version of the external ta (1 cycle delayed) to terminate the cycle. * * data[0:31] we [0:3] external bus interface (ebi) RM0029 344/1740 doc id 15177 rev 8 figure 101. back-to-back 32-bit reads to the same cs bank figure 102. back-to-back 32-bit reads to different cs banks data is valid data is valid clkout addr[3:31] ts ta rd_wr bdip oe cs [ n ] data[0:31] data is valid clkout addr[3:31] ts ta rd_wr bdip oe cs [ y ] data is valid cs [ n ] data[0:31] RM0029 external bus interface (ebi) doc id 15177 rev 8 345/1740 figure 103. write after read to the same cs bank addr[3:31] ts data[0:31] ta rd_wr data is valid bdip we csx data is valid clkout external bus interface (ebi) RM0029 346/1740 doc id 15177 rev 8 figure 104. back-to-back 32-bit writes to the same cs bank clkout addr[3:31] ts ta rd_wr bdip we cs [ n ] data is valid data is valid data[0:31] RM0029 external bus interface (ebi) doc id 15177 rev 8 347/1740 figure 105. read after write to the same cs bank burst transfer the ebi supports wrapping 32-byte critical-doubleword-first burst transfers. bursting is supported only for internally-requested cache-line size (32-byte) read accesses to external devices that use the chip selects (i) . addr[3:31] ts data[0:31] ta rd_wr data is valid bdip we csx data is valid clkout external bus interface (ebi) RM0029 348/1740 doc id 15177 rev 8 accesses to devices operating without a chip select are always single beat. if an internal request to the ebi indicates a size of less than 32 bytes, the request is fulfilled by running one or more single-beat external transfers, not by an external burst transfer. an 8-word wrapping burst reads eight 32-bit words by supplying a starting address that points to one of the words (doubleword aligned) and requiring the memory device to sequentially drive each word on the data bus. the selected slave device must internally increment addr[27:29] (also addr30 in the case of a 16-bit port size device) of the supplied address for each transfer, until the address reaches an 8-word boundary, and then wrap the address to the beginning of the 8-word boundary. the address and transfer attributes supplied by the ebi remain stable during the transfers. termination of each beat transfer occurs by the ebi asserting ta (seta=1 is not supported for burst transfers). the ebi requires that addresses be aligned to a doubleword boundary on all burst cycles. ta ble 10 2 shows the burst order of beats returned for an 8-word burst to a 32-bit port. the general case of burst transfers assumes that the external memory has 32-bit port size and 8-word burst length. the ebi can also burst from 16-bit port size memories, taking twice as many external beats to fetch the data as compared to a 32-bit port with the same burst length. the ebi can also burst from 16-bit or 32-bit memories that have a 4-word burst length (bl=1 in the appropriate base register). in this case, two external 4-word burst transfers (wrapping on 4-word boundary) are performed to fulfill the internal 8-word request (j) . this operation is considered atomic by the ebi, so the ebi does not allow other unrelated master accesses or bus arbitration to intervene between the transfers. for more details and a timing diagram, see section , small access example #3: 32-byte read to 32-bit port with bl=1 . during burst cycles, the bdip (burst data in progress) signal is used to indicate the duration of the burst data. during the data phase of a burst read cycle, the ebi receives data from the addressed slave. if the ebi needs more than one data, it asserts the bdip signal. upon receiving the data prior to the last data, the ebi negates bdip . thus, the slave stops driving new data after it receives the negation of bdip on the rising edge of the clock. some slave devices have their burst length and timing configurable internally and thus may not support connecting to a bdip pin. in this case, bdip is driven by the ebi normally, but the output is ignored by the memory and the burst data behavior is determined by the internal configuration of the ebi and slave device. when the tbdip bit is set in the appropriate base register, the timing for bdip is altered. see section , tbdip effect on burst transfer for this timing. i. except for the special case of a 32-bit non-ch ip-select access in 16-bit data bus mode. see section , non-chip- select burst in 16-bit data bus mode . table 102. wrap bursts order burst starting address addr[27:28] burst order (assuming 32-bit port size) 00 word0 word1 word2 word3 word4 word5 word6 word7 01 word2 word3 word4 word5 word6 word7 word0 word1 10 word4 word5 word6 word7 word0 word1 word2 word3 11 word6 word7 word0 word1 word2 word3 word4 word5 j. this case (of 2 external burst transfers being requir ed) applies only to amba data bus width of 64 bits. RM0029 external bus interface (ebi) doc id 15177 rev 8 349/1740 since burst writes are not supported by the ebi (k) , the ebi negates bdip during write cycles. k. except for the special case of a 32-bit non-ch ip-select access in 16-bit data bus mode. see section , non-chip- select burst in 16-bit data bus mode . external bus interface (ebi) RM0029 350/1740 doc id 15177 rev 8 figure 106. basic flow diagram of a burst read cycle master slave asserts transfer start (ts ) drives address and attributes receives address drives data asserts transfer acknowledge (ta ) next to last data beat? yes no negate bdip receive last data drives last data receives data assert bdip asserts transfer acknowledge (ta ) RM0029 external bus interface (ebi) doc id 15177 rev 8 351/1740 figure 107. burst 32-bit read cycle, zero wait states figure 108. burst 32-bit read cycle, one initial wait state tbdip effect on burst transfer some memories require different timing on the bdip signal than the default to run burst cycles. using the default value of tbdip=0 in the appropriate ebi base register results in bdip being asserted (scy+1) cycles after the address transfer phase, and being held clkout addr[3:31] bdip ta rd_wr ts oe cs [ n ] expects more data addr[29:31] = 000 data is valid data[0:31] wait state clkout addr[3:31] bdip ta rd_wr ts oe cs [ n ] expects more data addr[29:31] = 000 data is valid data[0:31] external bus interface (ebi) RM0029 352/1740 doc id 15177 rev 8 asserted throughout the cycle regardless of the wait states between beats (bscy). figure 109 shows an example of the tbdip=0 timing for a 4-beat burst with bscy=1. figure 109. burst 32-bit read cycle, one wait state between beats, tbdip=0 when using tbdip=1, the bdip behavior changes to toggle between every beat when bscy is a non-zero value. figure 110 shows an example of the tbdip=1 timing for the same 4-beat burst shown in figure 109 . clkout ts data[0:31] bdip wait state csx oe data is valid expects more data addr[3:31] rd_wr tsiz[0:1] 00 addr[29:31] = 000 wait state wait state wait state ta RM0029 external bus interface (ebi) doc id 15177 rev 8 353/1740 figure 110. burst 32-bit read cycle, one wait state between beats, tbdip=1 small accesses (small port size and short burst length) in this context, a small access refers to an access whose burst length and port size (bl, ps bits in base register for chip-select access or default burst disabled, 32-bit port for non- chip-select access) are such that the number of bytes requested by the internal master cannot all be fetched (or written) in one external transaction. if this is the case, the ebi initiates multiple transactions until all the requested data is transferred. it should be noted that all the transactions initiated to complete the data transfer are considered as an atomic transaction, so the ebi does not allow other unrelated master accesses to intervene between the transfers. ta ble 10 3 shows all the combinations of burst length, port size, and requested byte count that cause the ebi to run multiple external transactions to fulfill the request. data is valid wait state wait state clkout addr[3:31] bdip ta rd_wr ts oe cs [ n ] expects more data addr[29:31] = 000 wait state wait state data[0:31] table 103. small access cases byte count requested by internal master burst length port size # external accesses to fulfill request non-burstable chip-select banks (bi=1) or non-chip-select access 4 1 beat 16-bit 2/1 (1) 8 1 beat 32-bit 2 8 1 beat 16-bit 4 16 (2) 1 beat 32-bit 4 16 (2) 1 beat 16-bit 8 32 (3) 1 beat 32-bit 8 32 (3) 1 beat 16-bit 16 external bus interface (ebi) RM0029 354/1740 doc id 15177 rev 8 in most cases, the timing for small accesses is the same as for normal single-beat and burst accesses, except that multiple back-to-back external transfers are executed for each internal request. these transfers have no additional dead cycles in-between that are not present for back-to-back stand-alone transfers except for the case of writes with an internal request size of > 64 bits, discussed in section , small access example #2: 32-byte write with external ta . the following sections show a few examples of small accesses. the timing for the remaining cases in table 103 can be extrapolated from these and the other timing diagrams in this document. small access example #1: 32-bit write to 16-bit port figure 111 shows an example of a 32-bit write to a 16-bit port, requiring two 16-bit external transactions. figure 111. single beat 32-bit write cycle, 16-bit port size, basic timing burstable chip-select banks (bi=0) 32 (3) 4 words 16-bit (8 beats), 32-bit (4 beats) 2 1. in 32-bit data bus mode (dbm=0 in ebi_mcr), tw o accesses are performed. in 16-bit data bus mode (dbm=1), one 2-beat burst access is performed and th is is not considered a ?small access? case. see section , non-chip-select burst in 16-bit data bus mode for this special dbm=1 case. 2. only supported for case of 32-bit internal amba data bus. 3. only supported for case of 64-bit internal amba data bus. table 103. small access cases (continued) byte count requested by internal master burst length port size # external accesses to fulfill request data is valid data is valid clkout addr[3:31] ts ta rd_wr bdip we cs [ n ] aa + 2 abcdxxxx efghxxxx data[0:31] RM0029 external bus interface (ebi) doc id 15177 rev 8 355/1740 small access example #2: 32-byte write with external ta figure 112 shows an example of a 32-byte write to a non-chip-select device using external ta , requiring eight 32-bit external transactions. note that due to the use of external ta , rd_wr does not toggle between the accesses unless that access is the end of a 64-bit boundary. in this case, an extra cycle is required between ta and the next ts in order to get the next 64-bits of write data internally and rd_wr negates during this extra cycle. figure 112. 32-byte write cycle with external ta , basic timing small access example #3: 32-byte read to 32-bit port with bl=1 figure 113 shows an example of a 32-byte read to a 32-bit burst enabled port with burst length of 4 words, requiring two 16-byte external transactions. for this case, the address for the 2nd 4-word burst access is calculated by adding 0x10 to the lower 5 bits of the 1st address (no carry), and then masking out the lower 4 bits to fix them at zero. data is valid data is valid clkout addr[3:31] ts ta rd_wr bdip we cs [ n ] aa + 4 a + 8 a + 0xc data is valid this extra cycle is required after accesses 2, 4, and 6 to get the next 64-bits of internal write data. * four more external accesses (not shown) are required to complete the internal 32-byte request. the timing of these is the same as accesses 1-4 shown in this diagram. ** 12 34** * data[0:31 table 104. examples of 4-word burst addresses 1st address lower 5 bits of 1st address + 0x10 (no carry) final 2nd address (after masking lower 4 bits) 0x000 0x10 0x10 0x008 0x18 0x10 0x010 0x00 0x00 0x018 0x08 0x00 0x020 0x30 0x30 external bus interface (ebi) RM0029 356/1740 doc id 15177 rev 8 figure 113. 32-byte read with b-t-b 16-byte bursts to 32-bit port, zero wait states small access example #4: 64-bit read to 16-bit port figure 114 shows an example of a 64-bit read to a 16-bit port, requiring four 16-bit external transactions. 0x028 0x38 0x30 0x030 0x20 0x20 0x038 0x28 0x20 table 104. examples of 4-word burst addresses (continued) 1st address lower 5 bits of 1st address + 0x10 (no carry) final 2nd address (after masking lower 4 bits) expects more data clkout addr[3:31] bdip ta rd_wr ts oe cs [ n ] addr[29:31] = 000 data is valid addr[28:31] = 0000 data is valid data[0:31] RM0029 external bus interface (ebi) doc id 15177 rev 8 357/1740 figure 114. single beat 64-bit read cycle, 16-bit port size, basic timing size, alignment and packaging on transfers ta ble 10 5 shows the allowed sizes that an internal master can request from the ebi. the behavior of the ebi for request sizes not shown below is undefined. no error signal is asserted for these erroneous cases. addr[3:31] ts *data[0:15] ta rd_wr bdip we csx clkout a a+2 abcd data is valid * or data[16:31], based on d16_31 bit in ebi_mcr. a+4 a+6 efgh ijkl mnop data is valid data is valid data is valid external bus interface (ebi) RM0029 358/1740 doc id 15177 rev 8 even though misaligned non-burst transfers from internal masters are supported, the ebi naturally aligns the accesses when it sends them out to the external bus, splitting them into multiple aligned accesses if necessary. see section , misaligned access support , for these cases. natural alignment for the ebi means: byte access can have any address 16-bit access, address bit 31 must be 0 32-bit access, address bits 30?31 must be 0 for burst accesses of any size, address bits 29?31 must be 0 the ebi never generates a misaligned external access. in the erroneous case that an externally-initiated misaligned access does occur, the ebi errors the access (by asserting tea externally) and does not initiate the access on the internal bus. the ebi requires that the portion of the data bus used for a transfer to/from a particular port size be fixed. a 32-bit port must reside on data bus bits 0?31,and a 16-bit port must reside on bits 0?15. in the following figures and tables the following convention is adopted: the most significant byte of a 32-bit operand is op0, and op3 is the least significant byte. the two bytes of a 16-bit operand are op0 (most significant) and op1, or op2 (most significant) and op3, depending on the address of the access. the single byte of a byte-length operand is op0, op1, op2, or op3, depending on the address of the access. this can be seen in figure 115 . table 105. transaction sizes supported by ebi # bytes (internal master) # bytes (external master) 11 22 44 3 (1) 1. some misaligned access cases may result in 3-byte writes. these cases are treated as power-of-2 sized requests by the ebi, using we_be [0:3] to make sure only the appropriate 3 bytes get written. 8 32 (2) 2. only supported for case of 64-bit internal amba data bus. RM0029 external bus interface (ebi) doc id 15177 rev 8 359/1740 figure 115. internal operand representation figure 116 shows the device connections on the data[0:31] bus. figure 116. interface to different port size devices ta ble 10 6 lists the bytes required on the data bus for read cycles. the bytes indicated as ?? ? are not required during that read cycle. ta ble 10 7 lists the patterns of the data transfer for write cycles when accesses are initiated by the mcu. the bytes indicated as ??? are not driven during that write cycle. op0 op1 op2 031 32-bit 16-bit byte op0 op1 op2 op3 op0 op1 op2 op3 op3 031 32-bit port size op0 op1 op2 op3 op0 op1 op2 op3 op0 op1 op2 op3 16-bit port size data[0:7] data[8:15] data[16:23] data[24:31] interface output register external bus interface (ebi) RM0029 360/1740 doc id 15177 rev 8 termination signals protocol the termination signals protocol was defined in order to avoid electrical contention on lines that can be driven by various sources. in order to do that, a slave must not drive signals associated with the data transfer until the address phase is completed and it recognizes the address as its own. the slave must disconnect from signals immediately after it acknowledges the cycle and not later than the termination of the next address phase cycle. for ebi-mastered non-chip-select accesses, the ebi requires assertion of ta from an external device to signal that the bus cycle is complete. the ebi uses a latched version of ta (1 cycle delayed) for these accesses to help make timing at high frequencies. this results in the ebi driving the address and control signals 1 cycle longer than required, as seen in figure 117 . however, the data does not need to be held 1 cycle longer by the slave, because the ebi latches data every cycle during non-chip-select accesses. during these accesses, the ebi does not drive the ta signal, leaving it up to an external device (or weak internal pullup) to drive ta . table 106. data bus requirements for read cycles transfer size address 32-bit port size 16-bit port size (1) a30 a31 d0:d7 d8:d15 d16:d23 d24:d31 d0:d7 (2) d8:d15 (3) byte 0 0 op0 ? ? ? op0 ? 0 1 ? op1 ? ? ? op1 10 ? ? op2 ? op2 ? 1 1 ? ? ? op3 ? op3 16-bit 0 0 op0 op1 ? ? op0 op1 1 0 ? ? op2 op3 op2 op3 32-bit 0 0 op0 op1 op2 op3 op0/op2 (4) op1/op3 1. also applies when dbm=1 for 16-bit data bus mode. 2. for address/data muxed transfers, data[16: 23] are used externally, not data[0:7]. 3. for address/data muxed transfers, data[24:31] are used externally, not data[8:15]. 4. this case consists of two 16-bi t external transactions, the first fe tching op0 and op1, the second fetching op2 and op3. table 107. data bus contents for write cycles transfer size address 32-bit port size 16-bit port size (1) a30 a31 d0:d7 d8:d15 d16:d23 d24:d31 d0:d7 (2) d8:d15 (3) byte 0 0 op0 ? ? ? op0 ? 0 1 ? op1 - ? ? op1 1 0 ? ? op2 ? op2 ? 1 1 ? ? ? op3 ? op3 16-bit 0 0 op0 op1 ? ? op0 op1 1 0 ? ? op2 op3 op2 op3 32-bit 0 0 op0 op1 op2 op3 op0/op2 (4) op1/op3 1. also applies when dbm=1 for 16-bit data bus mode. 2. for address/data muxed transfers, data[16: 23] are used externally, not data[0:7]. 3. for address/data muxed transfers, data[24:31] are used externally, not data[8:15]. 4. this case consists of two 16-bit external transacti ons, the first writing op0 and op1, the second writing op2 and op3. RM0029 external bus interface (ebi) doc id 15177 rev 8 361/1740 for ebi-mastered chip-select accesses, when the seta bit is 0, the ebi drives ta the entire cycle, asserting according to internal wait state counters to terminate the cycle. when the seta bit is 1, the ebi samples the ta for the entire cycle. during idle periods on the external bus, the ebi drives ta negated as long as it is granted the bus; when it no longer owns the bus, it lets go of ta . if no device responds by asserting ta within the programmed timeout period (bmt in ebi_bmcr) after the ebi initiates the bus cycle, the internal bus monitor (if enabled) asserts tea to terminate the cycle. an external device may also drive tea when it detects an error on an external transaction. tea assertion causes the cycle to terminate and the processor to enter exception processing for the error condition. to properly control termination of a bus cycle for a bus error with external circuitry, tea must be asserted at the same time or before (external) ta is asserted. tea must be negated before the second rising edge after it was sampled asserted in order to avoid the detection of an error for the following bus cycle initiated. tea is only driven by the ebi during the cycle where the ebi is asserting tea and the cycle immediately following this assertion (for fast negation). during all other cycles, the ebi relies on a weak internal pullup to hold tea negated. this allows an external device to assert tea when it needs to indicate an error. external devices must follow the same protocol as the ebi, only driving tea during the assertion cycle and 1 cycle afterwards for negation. when tea is asserted from an external source, the ebi uses a latched version of tea (1 cycle delayed) to help make timing at high frequencies. this means that for any accesses where the ebi drives ta (chip-select accesses with seta=0), a tea assertion that occurs 1 cycle before or during the last ta of the access could be ignored by the ebi, since it will have completed the access internally before it detects the latched tea assertion. this means that non-burst chip-select accesses with no wait states (scy=0) cannot be reliably terminated by external tea . if external error termination is required for such a device, the ebi must be configured for scy>=1. note: for the cases discussed above where tea ?could be ignored?, this is not guaranteed. for some small access cases (which always use chip-select and internally-driven ta ), a tea that occurs 1 cycle before or during the ta cycle or for scy=0 may in fact lead to terminating the cycle with error. however, proper error termination is not guaranteed for these cases, so tea must always be asserted at least 2 cycles before an internally-driven ta cycle for proper error termination. external tea assertion that occurs during the same cycle that ts is asserted by the ebi is always treated as an error (terminating the access) regardless of scy. ta ble 10 8 summarizes how the ebi recognizes the termination signals provided from an external device. table 108. termination signals protocol tea (1) 1. latched version (1 cycle delayed) used for externally driven tea and ta . ta (1) action negated negated no termination asserted x transfer error termination negated asserted normal transfer termination external bus interface (ebi) RM0029 362/1740 doc id 15177 rev 8 figure 117 shows an example of the termination signals protocol for back-to-back reads to two different slave devices who properly ?take turns? driving the termination signals. this assumes a system using slave devices that drive termination signals. figure 117. termination signals protocol timing diagram non-chip-select burst in 16-bit data bus mode the timing diagrams in this section apply only to the special case of a non-chip-select 32-bit access in 16-bit data bus mode (dbm=1 in ebi_mcr). for this case, a special 2-beat burst protocol is used for reads and writes, so that a slave device (using the same ebi) can internally generate one 32-bit read or write access (thus 32-bit coherent), as opposed to two separate 16-bit accesses. note: if the device does not support multi-master systems, the original intent of this protocol does not apply. however, this 2-beat burst protocol can also occur in a single-master system, if a non-chip-select 32-bit access to a 16-bit port is performed. figure 118 shows a 32-bit (and non-chip-select in a single-master system) read from an external master in 16-bit data bus mode. figure 119 shows a 32-bit (and non-chip-select in a single-master system) write from an external master in 16-bit data bus mode. the ebi drives address and control signals an extra cycle because it uses a latched version of ta * this is the earliest that the ebi can start another transfer, in the case of continuing a set of small accesses. for all other cases, an extra cycle is needed before the ebi can start another ts . ** clkout bb ts data[0:31] ta , tea addr[3:31] rd_wr slave 1 slave 2 ** ** (1 cycle delayed) to terminate the cycle. an external master is not required to do this. slave 1 negates acknowledge signals and turns off slave 2 negates acknowledge signals and turns off slave 2 allowed to drive acknowledge signals slave 1 allowed to drive acknowledge signals RM0029 external bus interface (ebi) doc id 15177 rev 8 363/1740 figure 118. 32-bit read from mcu with dbm=1 figure 119. 32-bit write to mcu with dbm=1 calibration bus operation some devices with this ebi have a second external bus, intended for calibration use. this bus consists of a second set of the same signals present on the primary external bus, except that arbitration, (and optionally other signals also) are excluded. both busses can be supported with one ebi block, by using the calibration chip-selects to steer accesses to the calibration bus instead of the primary external bus. clkout rd_wr bdip addr[3:31] data[0:15] ts (output) minimum 2 wait states data is valid ta (input) data is valid data is valid clkout rd_wr bdip addr[3:31] data[0:15] ts (output) minimum 3 wait states ta (input) data is valid external bus interface (ebi) RM0029 364/1740 doc id 15177 rev 8 since the calibration bus has no arbitration signals, the arbitration on the primary bus controls accesses on the calibration bus as well, and no external master accesses can be performed on the calibration bus. accesses cannot be performed in parallel on both external busses. however, back-to-back accesses can switch from one bus to the other, as determined by the type of chip-select each address matches. the timing diagrams and protocol for the calibration bus is identical to the primary bus, except that some signals are missing on the calibration bus. see the device-specific documentation for the calibration bus signal list for a particular mcu. there is an inherent dead cycle between a calibration chip-select access and a non- calibration access (chip-select or non-chip-select), just like the one between accesses to two different non-calibration chip-selects (described in section , back-to-back accesses ). figure 120 shows an example of a non-calibration chip-select read access followed by a calibration chip-select read access. note that this figure is identical to figure 102 , except the csy is replaced by cal_csy. timing for other cases on calibration bus can similarly be derived from other figures in this document (by replacing cs with cal_cs ). RM0029 external bus interface (ebi) doc id 15177 rev 8 365/1740 figure 120. back-to-back 32-bit reads to cs , cal_cs banks misaligned access support this section describes all the misaligned cases supported by the ebi. these cases are a subset of the full set of cases allowed by the amba ahb v6 specification. the ebi works under the assumption that all internal masters on the device do not produce any misaligned access cases (to the ebi) other than the ones below. clkout addr[3:31] ts data[0:31] ta rd_wr data is valid bdip oe csx data is valid cal_csy external bus interface (ebi) RM0029 366/1740 doc id 15177 rev 8 misaligned access support (64 bit amba) ta ble 10 9 shows all the misaligned access cases supported by the ebi (using a 64-bit amba implementation), as seen on the internal master amba bus. all other misaligned cases are not supported. if an unsupported misaligned access to the ebi is attempted (such as non-chip-select or burst misaligned access), the ebi errors the access on the internal bus and does not start the access (nor assert tea ) externally. table 109. misalignment cases supported by a 64 bit amba ebi (internal bus) no. (1) program size and byte offset address [29:31] (2) data bus byte strobes (3) hsize (4) hunalign (5) 1 half @0x1,0x9 001 0110_0000 10 1 2 half @0x3,0xb 011 0001_1000 11 1 3 half @0x5,0xd 101 0000_0110 10 1 4 - half @0x7, 0xf (2 ahb transfers) 111 000 0000_0001 1000_0000 01 (6) 00 1 0 5 word @0x1,0x9 001 0111_1000 11 1 6 word @0x2,0xa 010 0011_1100 11 1 7 word @0x3,0xb 011 0001_1110 11 1 8 - word @0x5,0xd (2 ahb transfers) 101 000 0000_0111 1000_0000 10 00 1 0 9 - word @0x6, 0xe (2 ahb transfers) 110 000 0000_0011 1100_0000 10 (7) 01 1 0 10 11 word @0x7,0xf (2 ahb transfers) 111 000 0000_0001 1110_0000 10 (6) 10 1 1 12 - doubleword @0x4,0x8 (2 ahb transfers) 100 000 0000_1111 1111_0000 11 (8) 10 1 0 13 - doubleword @0x2,0xa (2 ahb transfers) 010 000 0011_1111 1100_0000 11 01 1 0 14 15 doubleword 0x6,0xe (2 ahb transfers) 110 000 0000_0011 1111_1100 11 (7) 11 1 1 1. misaligned case number. only transfers where hunalign=1 are numbered as misaligned cases. 2. address on internal master ahb bus, not necessarily address on external addr pins. 3. internal byte strobe signals on ahb bus. shown with big-endi an byte ordering in this table, even though internal master ahb bus uses little-endian byte-order ing (ebi flips order internally). 4. internal signal on ahb bus; 00=8-bits, 01=16 bits, 10=32 bits , 11=64-bits. hsize is driven according to the smallest aligned container that contains all the requested bytes. this results in extra ebi external transfers in some cases. 5. internal signal on ahb bus that indicates that this transfer is misaligned (when 1). 6. for this case, the ebi internally treats hsize as 00 (1-byte access). 7. for this case, the ebi internally treats hsize as 01 (2-byte access). 8. for this case, the ebi internally treats hsize as 10 (4-byte access). RM0029 external bus interface (ebi) doc id 15177 rev 8 367/1740 ta ble 11 0 shows which external transfers are generated by the ebi for the misaligned access cases in table 109 , for each port size. the number of external transfers for each internal ahb master request is determined by the hsize value for that request relative to the port size. for example, a half-word write to @011 (misaligned case #2) with 16-bit port size results in 4 external 16-bit transfers because the hsize is 64-bits. for cases where two or more external transfers are required for one internal transfer request, these external accesses are considered part of a ?small access? set, as described in section , small accesses (small port size and short burst length) . since all transfers are aligned on the external bus, normal timing diagrams and protocol apply. table 110. misalignment cases supported by a 64 bit amba ebi (external bus) no. (1) ps (2) program size and byte offset addr[29:31] (3) we_be [0:3] (4) 1 0 half @0x1,0x9 000 1001 1 000 010 1011 0111 2 0 half @0x3,0xb 000 100 1110 0111 1 010 100 1011 0111 3 0 half @0x5,0xd 100 1001 1 100 110 1011 0111 4 0 half @0x7,0xf (2 ahb transfers) 111 (5) 1110 - 000 0111 4 1 110 1011 - 000 0111 5 0 word @0x1,0x9 000 100 1000 0111 1 000 010 100 1011 0011 0111 6 0 word @0x2,0xa 000 100 1100 0011 1 010 100 0011 0011 7 0 word @0x3,0xb 000 100 1110 0001 1 010 100 110 1011 0011 0111 external bus interface (ebi) RM0029 368/1740 doc id 15177 rev 8 8 0 word @0x5,0xd (2 ahb transfers) 100 1000 - 000 0111 8 1 100 110 1011 0011 - 000 0111 9 0 word @0x6,0xe (2 ahb transfers) 110 (6) 1100 - 000 0011 9 1 110 (6) 0011 - 000 0011 10 0 word @0x7,0xf (2 ahb transfers) 111 (5) 1110 11 000 0001 10 1 111 (5) 1011 11 000 010 0011 0111 12 0 doubleword @0x4,0xc (2 ahb transfers) 100 (7) 0000 - 000 0000 12 1 100 (7) 110 0011 0011 - 000 010 0011 0011 13 0 doubleword @0x2,0xa (2 ahb transfers) 000 100 1100 0000 - 000 0011 13 1 010 100 110 0011 0011 0011 - 000 0011 14 0 doubleword @0x6,0xe (2 ahb transfers) 110 (6) 1100 15 000 100 0000 0011 14 1 110 (6) 0011 15 000 010 100 0011 0011 0011 1. misaligned case number, from table 109 . 2. port size; 0=32 bits, 1=16 bits. 3. external addr pins, not necessarily t he address on internal master ahb bus. table 110. misalignment cases supported by a 64 bit amba ebi (external bus) no. (1) ps (2) program size and byte offset addr[29:31] (3) we_be [0:3] (4) RM0029 external bus interface (ebi) doc id 15177 rev 8 369/1740 address data multiplexing address/data multiplexing enables the design of a system with reduced pin count. in such a system, multiplexed address/data functions (on data pins) are used, instead of having separate address and data pins. compared to the normal ebi specification (e.g. 24 address pins+32 data pins), only 32 data pins are required. compared to a 16-bit bus implementation, only 24 pins are required (e.g. addr[8:15] + addr[16:31]/data[16:31]). when performing a small access read, as described in section , small accesses (small port size and short burst length) , with a/d multiplexing enabled for this access, the ebi inserts an idle clock cycle with oe negated and cs asserted, to allow for the memory to three-state the bus prior to the ebi driving the address on the next clock. this clock gap already exists (for other reasons) for non-small-access transfers, so no additional clock gap is inserted for those cases. see figure 121 for an example of a small access read with a/d multiplexing enabled. in general, timing diagrams in a/d multiplexing mode are very similar to other diagrams in this document (including support for burst accesses), except for the behavior of the addr and data busses, which can be seen in figure 121 . 4. external we_be pins. note that these pins have negative polarity, opposite of t he internal byte strobes in table 109 . 5. treated as 1-byte access. 6. treated as 2-byte access. 7. treated as 4-byte access. external bus interface (ebi) RM0029 370/1740 doc id 15177 rev 8 figure 121. small access (32-bit read to 16-bit port) on address/data multiplexed bus 14.6 initialization/application information 14.6.1 booting from external memory the ebi block does not support booting directly to external memory (i.e. fetching the first instruction after reset externally). one common method for an mcu to resemble an external boot with this ebi is to use an internal boot assist module on the mcu, which fetches the clkout *addr[3:31] ts **data[16:31] ta rd_wr data is valid bdip oe csx data is valid addr addr+0x2 addr addr+0x2 clock gap * while the ebi drives all of addr[3:31] to valid addres s, typically only addr[3:15] (or less) are used in the system, as data[16:31] (or data[0:15]) would be used for address and data on an external muxed device. ** or data[0:15], based on d16_31 bit in ebi_mcr. RM0029 external bus interface (ebi) doc id 15177 rev 8 371/1740 first instruction internally and configures ebi registers before branching to an external address to ?boot? externally. refer to the device-specific documentation to see how/if external boot is supported for a particular mcu. if code in external memory needs to write ebi registers, this must be done in a way that avoids modifying ebi registers while external accesses are being performed, such as the following method: copy the code that is doing the register writes (plus a return branch) to internal sram branch to internal sram to run this code, ending with a branch back to external flash 14.6.2 running with sdr (single data rate) burst memories this includes flash and sram memories with a compatible burst interface. bdip is required only for some sdr memories. figure 122 shows a block diagram of an mcu connected to a 32-bit sdr burst memory. figure 122. mcu connected to sdr burst memory refer to figure 107 for an example of the timing of a typical burst read operation to an sdr burst memory. refer to figure 98 for an example of the timing of a typical single write operation to sdr memory. 14.6.3 running with asynchronous memories the ebi also supports asychronous memories. in this case, the clkout, ts , and bdip pins are not used by the memory and bursting is not supported. however, the ebi still drives these outputs, and always drives and latches all signals at posedge clkout (i.e., there is no ?asynchronous mode? for the ebi). the data timing is controlled by setting the scy bits in the appropriate option register to the proper number of wait states to work with the access time of the asynchronous memory, just as done for a synchronous memory. clkout ck addr[3:29] a[0:21] ce cs0 data[0:31] d[0:31] ts bdip we0 /be0 adv baa * we ** oe oe mcu * may or may not be connected, depending on the memory used. sdr burstable flash or sram ** flash memories typically use one we signal as shown, rams use 2 or 4 (16-bit or 32-bit) external bus interface (ebi) RM0029 372/1740 doc id 15177 rev 8 example wait state calculation this example applies to any chip-select memory, synchronous or asynchronous. as an example, say we have a memory with 50ns access time, and we are running the external bus at 66 mhz (clkout period: 15.2 ns). assume the input data spec for the mcu is 4 ns. number of wait states = (access time) / (clkout period) + (0 or 1) (depending on setup time) 50/15.2 = 3 with 4.4 ns remaining (so we need at least 3 wait states, now check setup time) 15.2-4.4=10.8 ns (this is the achieved input data setup time) since actual input setup (10.8 ns) is greater than the input setup spec (4.0ns), 3 wait states is sufficient. if the actual input setup was less than 4.0ns, we would have to use 4 wait states instead. timing and connections for asynchronous memories the connections to an asynchronous memory are the same as for a synchronous memory, except that the clkout, ts , and bdip signals are not used. figure 123 shows a block diagram of an mcu connected to an asynchronous memory. figure 123. mcu connected to asynchronous memory figure 124 shows a timing diagram of a read operation to a 16-bit asynchronous memory using 3 wait states. figure 125 shows a timing diagram of a write operation to a 16-bit asynchronous memory using 3 wait states. addr[9:30] a[0:21] asynchronous ce cs0 memory data[0:15] d[0:15] we * oe oe mcu we0 /be0 * flash memories typically use one we signal as shown, rams use 2 or 4 (16-bit or 32-bit) RM0029 external bus interface (ebi) doc id 15177 rev 8 373/1740 figure 124. read operation to asynchronous memory, three initial wait states clkout addr[3:31] ts data[0:31] ta 3 wait states csx oe we [0:1] data is valid external bus interface (ebi) RM0029 374/1740 doc id 15177 rev 8 figure 125. write operation to asynchronous memory, three initial wait states 14.6.4 connecting an mcu to multiple memories the mcu can be connected to more than one memory at a time. figure 126 shows an example of how two memories could be connected to one mcu. clkout addr[3:31] ts data[0:31] ta 3 wait states csx we [0:1] oe data is valid RM0029 external bus interface (ebi) doc id 15177 rev 8 375/1740 figure 126. mcu connected to multiple memories 14.6.5 ebi operation with reduced pinout mcus some mcus with this ebi may not have all the pins described in this document pinned out for a particular package. some of the most common pins to be removed are data[16:31] addr[3:29] cs0 data[0:31] ts oe mcu cs1 ck a[0:21] ce sdr memory d[0:31] adv we ** oe ck a[0:21] sdr memory ce d[0:31] adv we ** oe clkout we0 /be0 bdip baa * * may or may not be connected, depending on the memory used. we1 /be1 baa * ** flash memories typically use one we signal as shown, rams use 2 or 4 (16-bit or 32-bit) external bus interface (ebi) RM0029 376/1740 doc id 15177 rev 8 and arbitration pins (bb , bg , br ). this section describes how to configure dual-mcu systems for each of those scenarios, as well as describing limitations to ebi operation when other pins are missing (ta , tea , bdip ). more than one section may apply if the applicable pins are not present on one or both mcus. connecting 16-bit mcu to 32-bit mcu (master/master or master/slave) this scenario is straightforward. simply connect data[0:15] between both mcus, and configure both for 16-bit data bus mode operation (dbm=1 in ebi_mcr). note that 32-bit external memories are not supported in this scenario. transfer size with no tsiz pins (master/master or master/slave) since there are no tsiz pins to communicate transfer size from master mcu to slave mcu, the internal size field of the ebi_mcr must be used on the slave mcu (by setting sizen=1 in slave?s ebi_mcr). anytime the master mcu needs to read or write the slave mcu with a different transfer size than the current value of the slave?s size field, the master mcu must first write the slave?s size field with the correct size for the subsequent transaction. no transfer acknowledge (ta ) pin if an mcu has no ta pin available, this restricts the mcu to chip-select accesses only (no mcu->mcu transfers are possible). non-chip-select accesses have no way for the ebi to know which cycle to latch the data. the ebi has no built-in protection to prevent non-chip- select accesses in this scenario; it is up to the user to make certain they set up chip-selects and external memories correctly to ensure all external accesses fall in a valid chip-select region. no transfer error (tea ) pin if an mcu has no tea pin available, this eliminates the feature of terminating an access with tea . this means if an access times out in the ebi bus monitor, the ebi (master) will still terminate the access early, but there will be no external visibility of this termination, so the slave device might end up driving data much later, when a subsequent access is already underway. therefore, the ebi bus monitor should be disabled when no tea pin exists. no burst data in progress (bdip ) pin if an mcu has no bdip pin available, this eliminates burst support only if the burstable memory being used requires bdip to burst. many external memories use a self-timed configurable burst mechanism that does not require a dynamic burst indicator. check the applicable external memory specification to see if bdip is required in your system. RM0029 interrupt controller (intc) doc id 15177 rev 8 377/1740 15 interrupt controller (intc) 15.1 information specific to this device this section presents device-specific parameterization and customization information not specifically referenced in the remainder of this chapter. 15.1.1 device-specific features 279 peripheral interrupts 199 reserved interrupts 8 software interrupts 15.2 introduction this chapter describes the interrupt controller (intc), which schedules interrupt requests (irqs) from software and internal peripherals to the e200z4 core. the intc provides interrupt prioritization and preemption, interrupt masking, interrupt priority elevation, and protocol support. interrupts implemented by the mcu are defined in the e200z4 power architecture ? core reference manual . 15.2.1 block diagram figure 127 shows the details of the interrupt controller. interrupt controller (intc) RM0029 378/1740 doc id 15177 rev 8 figure 127. intc block diagram 15.2.2 overview interrupt functionality for the device is handled between the e200z4 core and the interrupt controller. the cpu core has 19 exception sources, each of which can interrupt the core. one exception source is from the interrupt controller (intc). the intc provides priority- based scheduling of interrupt requests and supports programmable preemption. this scheduling scheme is suitable for statically scheduled hard real-time systems. the intc is optimized for a large number of interrupt requests. table 111 displays the interrupt sources and the number of interrupts available for each module; figure 128 shows a general diagram of intc software vector mode. end-of- interrupt register software set clear interrupt registers flag bits priority select registers 8 peripheral interrupt requests 1 n 1 priority arbitrator n 1 highest priority interrupt requests n 1 request selector lowest vector interrupt request n 1 vector encoder interrupt vector 9 x 4-bits interrupt acknowledge register interrupt vector 9 hardware vector enable vector table entry size 1 module configuration register 1 highest priority 4 priority comparator new 4 current 4 priority current priority register priority 4 popped 4 priority pushed priority priority lifo slave interface for reads and writes 1 push/update/acknowledge 1 pop slave bus signals 1 interrupt acknowledge 1 update interrupt vector 1 interrupt request to processor memory-mapped registers logic not memory-mapped 1 although n (largest addressable irq vector number) = 485, this does not indicate the total number of interrupts available on this device. the total number of available interrupts on this device is 486: 279 peripheral irqs, 8 software-configurable irqs, and 199 reserved. table 111. interrupt sources available interrupt source (irqs) number of interrupts available software 8 watchdog 0 sram error correction 1 flash error correction 1 RM0029 interrupt controller (intc) doc id 15177 rev 8 379/1740 figure 128. intc software vector mode two modes are available to determine the vector for the interrupt request source: software vector mode hardware vector mode in software vector mode, as shown in figure 128 , the e200z4 branches to a common interrupt exception handler whose location is determined by an address derived from special purpose registers ivpr and ivor4. the interrupt exception handler reads the intc_iackr to determine the vector of the interrupt request source. typical program flow for software vector mode is shown in figure 129 . edma 66 fmpll 2 external irq input pins (siu) 6 emios 24 etpu engine a 33 eqadc 31 dspi 15 esci 3 flexcan 63 flexray 8 stm 5 decimation filter 3 system (pit, rti, pmc, etc) 6 table 111. interrupt sources available (continued) interrupt source (irqs) number of interrupts available irqs interrupt controller (intc) external interrupt exception request e200z4 core interrupt controller (intc) RM0029 380/1740 doc id 15177 rev 8 figure 129. program flow?software vector mode n is the largest vector number (485) with the greatest hexadecimal address (ivpr + 0x1d90) that is available in the interrupt memory map for this device. as memory blocks throughout the total memory map are used for other purposes, the maximum vector number does not indicate the total number of available interrupt sources for this device. the total number of entries in the interrupt memory map on this device is 486: 279 peripheral irqs, 8 software configurable irqs, and 199 reserved. in hardware vector mode, the core branches to an interrupt exception handler unique for each interrupt request source. typical program flow for hardware vector mode is shown in figure 130 . figure 130. program flow?hardware vector mode the intc supports a hardware vector mode that reduces the time between assertion of an interrupt and execution of the service routine. it also provides 16 priorities so that lower priority isrs do not delay the execution of higher priority isrs. the priority assigned to each interrupt source is programmable in the range 0 to 15, with 0 being the lowest and 15 being the highest priority. isr isr 0 address isr 0 isr isr 1 ? ? ? isr isr n ? ? ? isr isr n isr n address isr n address isr 1 address ? ? ? ? ? ? prolog (including using iackr to get vector then bl isr_n epilog ivpr + ivor4 irq [n] taken iackr data table address instructions address vtba of addresses prolog b handler 0 handler 0 isr ? ? ? ? ? ? isr ? ? ? ? ? ? instructions note: ?b isr_n? is technically epilog prolog epilog isr prolog epilog handler n handler n b handler 1 ? ? ? b handler 2 ? ? ? b handler n b handler n ivpr + 0x0000 ivpr + 0x0010 ivpr + 0x0020 ivpr + n [0x0010] refer to definition of n irq [n] taken address part of the handler. RM0029 interrupt controller (intc) doc id 15177 rev 8 381/1740 when multiple tasks share a resource, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol (pcp) for coherent accesses. by providing a modifiable priority mask, the priority level can be raised temporarily so that no task can preempt another task that shares the same resource. multiple processors can assert interrupt requests to each other through software configurable interrupt requests, i.e., by using application software to assert an interrupt request. these same software configurable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. the high priority portion is initiated by a peripheral interrupt request, but the isr can assert a software configurable interrupt request to finish the servicing in a low priority isr. 15.2.3 features features include the following: total number of interrupt vectors is 486, of which: ? 279 are peripheral interrupt vectors ? 8 are software configurable sources ? 199 are reserved sources 9-bit unique vector for each interrupt request source in hardware vector mode. each interrupt source can be programmed to one of 16 priorities. preemption. ? preemptive prioritized interrupt requests to processor. ? isr at a higher priority preempts isrs or tasks at lower priorities. ? automatic pushing or popping of preempted priority to or from a lifo. ? ability to modify the isr or task priority. modifying the priority can be used to implement the pcp for accessing shared resources. low latency?three clocks from receipt of interrupt request from peripheral to interrupt request to processor. 15.2.4 modes of operation the interrupt controller has two handshaking modes with the processor: software vector mode and hardware vector mode. the state of the hardware vector enable bit, intc_mcr[hven], determines which mode is used. in debug mode, the interrupt controller operation is identical to its normal operation of software vector mode or hardware vector mode. software vector mode in the software vector mode, there is a common interrupt exception handler address that is calculated by hardware as shown in figure 131 . the upper half of the interrupt vector prefix register (ivpr) is added to the offset contained in the external input interrupt vector offset register (ivor4). note: since bits ivor4[28:31] are not part of the offset value, the vector offset must be located on a quad-word (16-byte) aligned location in memory. in the software vector mode, the interrupt exception handler software must read the intc interrupt acknowledge register (intc_iackr) to obtain the vector number and base address of the handler associated with the corresponding peripheral or software interrupt interrupt controller (intc) RM0029 382/1740 doc id 15177 rev 8 request. the intc_iackr register contains a 21-bit or 20-bit address for a vector table base address (vtba). the address is then used to branch to the corresponding routine for that peripheral or software interrupt source. figure 131. software vector mode: interrupt exception handler address calculation reading the intc_iackr acknowledges the intc?s interrupt request and negates the interrupt request to the processor. the interrupt request to the processor does not clear if a higher priority interrupt request arrives. even in this case, intvec does not update to the higher priority request until the lower priority interrupt request is acknowledged by reading the intc_iackr. the reading also pushes the pri value in the intc current priority register (intc_cpr) to the lifo and updates pri in the intc_cpr with the priority of the interrupt request. the intc_cpr masks any peripheral or software configurable interrupt request at the same or lower priority of the current value of the pri field in intc_cpr from generating an interrupt request to the processor. the interrupt exception handler must write to the end-of-interrupt register (intc_eoir) to complete the operation (assuming the source of the interrupt has been cleared). writing to the intc_eoir ends the servicing of the interrupt request. the intc?s lifo is popped into the intc_cpr's pri field by writing to the intc_eoir, and the size of a write does not affect the operation of the write. those values and sizes written to this register neither update the intc_eoir contents nor affect whether the lifo pops. for possible future compatibility, write four bytes of all 0s to the intc_eoir. the timing relationship between popping the lifo and disabling recognition of external input has no restriction. the writes can happen in either order. however, disabling recognition of the external input before popping the lifo eases the calculation of the maximum stack depth at the cost of postponing the servicing of the next interrupt request. hardware vector mode in hardware vector mode, the interrupt exception handler address is specific to the peripheral or software configurable interrupt source rather than being common to all of them. no ivor is used. the interrupt exception handler address is calculated by hardware as shown in figure 132 . the upper half of the interrupt vector prefix register (ivpr) is added to an offset, which corresponds to the peripheral or software interrupt source that caused the interrupt request. the offset matches the value in the interrupt vector field, intc_iackr[intvec]. each interrupt exception handler address is aligned on a four-word 31 16 15 0 ivpr 31 28 27 16 15 0 + ivor4 31 28 27 16 15 0 0x00 0x00 offset offset prefix 0x0000 prefix = interrupt exception 0x0000 handler address RM0029 interrupt controller (intc) doc id 15177 rev 8 383/1740 (16-byte) boundary. ivor4 is not used in this mode, and software does not need to read intc_iackr to get the interrupt vector number. figure 132. hardware vector mode: interrupt exception handler address calculation the processor negates intc?s interrupt request when automatically acknowledging the interrupt request. however, the interrupt request to the processor do not negate if a higher priority interrupt request arrives. even in this case, the interrupt vector number does not update to the higher priority request until the lower priority request is acknowledged by the processor. the assertion of the interrupt acknowledge signal pushes the pri value in the intc_cpr onto the lifo and updates pri in the intc_cpr with the new priority. 15.3 external signal description the intc does not have any direct external mcu signals. however, there are 15 external pins that can be configured in the siu as external interrupt request input pins. when configured for an external interrupt request function, an interrupt on that pin sets an external interrupt flag. these flags cause one of five peripheral interrupt requests to the interrupt controller. for more information on external interrupts, the pins used, and how to configure them: refer to the signals chapter for a list and number of the external interrupt pins. refer to the siu chapter for more information on how to configure these pins. 15.4 memory map and register definition ta ble 11 2 is the intc memory map. 31 16 15 0 ivpr 31 28 27 16 15 0 0 + hardware vector 15 0 0b0000 intc_iackr[intvec] prefix 0x0000 prefix 18 0b000 19 0x0000 31 28 27 16 0b0000 irq specific offset 18 0b000 19 16 = interrupt exception handler address mode offset table 112. intc memory map address register name register description bits base (0xfff4_8000) intc_mcr intc module configuration register 32 base + 0x0004 ? reserved ? interrupt controller (intc) RM0029 384/1740 doc id 15177 rev 8 15.4.1 register descriptions except intc_ssci n and intc_psr n registers, all registers are 32-bits wide. any combination of accessing the 4 bytes of a register with a single access is supported, provided that the access does not cross the register boundary. these supported accesses include types and sizes of 8 bits, aligned 16 bits, and aligned 32 bits. although intc_ssci n and intc_psr n are 8-bits wide, they can be accessed with a single 16-bit or 32-bit access, provided that the access does not cross a 32-bit boundary. in the software vector mode, the side effects of a read of the intc interrupt acknowledge register (intc_iackr) are the same regardless of the size of the read. in either software or hardware vector mode, the size of a write to the intc end-of-interrupt register (intc_eoir) does not affect the operation of the write. intc module configuration register (intc_mcr) the intc_mcr is used to configure options of the intc. base + 0x0008 intc_cpr intc current priority register 32 base + 0x000c ? reserved ? base + 0x0010 intc_iackr intc interrupt acknowledge register (1) 32 base + 0x0014 ? reserved ? base + 0x0018 intc_eoir intc end-of-interrupt register 32 base + 0x001c ? reserved ? base + 0x0020 intc_sscir0 intc software set/clear interrupt register 0 8 base + 0x0021 intc_sscir1 intc software set/clear interrupt register 1 8 base + 0x0022 intc_sscir2 intc software set/clear interrupt register 2 8 base + 0x0023 intc_sscir3 intc software set/clear interrupt register 3 8 base + 0x0024 intc_sscir4 intc software set/clear interrupt register 4 8 base + 0x0025 intc_sscir5 intc software set/clear interrupt register 5 8 base + 0x0026 intc_sscir6 intc software set/clear interrupt register 6 8 base + 0x0027 intc_sscir7 intc software set/clear interrupt register 7 8 base + (0x0028?0x003f) ? reserved ? base + (0x0040?0x01a7) intc_psr n intc priority select registers (2) 0 ? 485 8 1. when the hven bit in the intc_mcr is asserted, a read of the intc_iackr has no side effects. 2. the pri fields are ?reserved? fo r peripheral interrupt requests whose vectors are labeled as reserved in table 117 . table 112. intc memory map (continued) address register name register description bits RM0029 interrupt controller (intc) doc id 15177 rev 8 385/1740 figure 133. intc module configuration register (intc_mcr) intc current priority register (intc_cpr) the intc_cpr masks any peripheral or software configurable interrupt request set at the same or lower priority as the current value of the intc_cpr[pri] field from generating an interrupt request to the processor. when the intc interrupt acknowledge register (intc_iackr) is read in the software vector mode or the interrupt acknowledge signal from the processor is asserted in the hardware vector mode, the value of pri is pushed onto the lifo, and pri is updated with the priority of the preempting interrupt request. when the intc end-of-interrupt register (intc_eoir) is written, the lifo is popped into the intc_cpr?s pri field. the masking priority can be raised or lowered by writing to the pri field, supporting the pcp. refer to section 15.6.5, priority ceiling protocol . note: on some power architecture mcus, a store to raise the pri field which closely precedes an access to a shared resource can result in a non-coherent access to that resource unless an mbar or msync followed by an isync sequence of instructions is executed between the address: base + 0x0000 (intc_mcr access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 vtes 0 0 0 0 hven w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 113. intc_mcr field descriptions field description 0?25 reserved, must be cleared. 26 vtes vector table entry size. controls the number of ?0?s to the right of intvec in section , intc interrupt acknowledge register (intc_iackr) . if the contents of intc_iackr are used as an address of an entry in a vector table as in software vector mode, th en the number of rightmost ?0?s determines the size of each vector table entry. vtes impacts software vector mode operation bu t also affects the intc_iackr[intvec] position in both hardware vector mode and software vector mode. 0 4 bytes (normal expected use) 1 8 bytes 27?30 reserved, must be cleared. 31 hven hardware vector enable. controls whether the intc is in hardware vector mode or software vector mode. refer to section 15.2.4, modes of operation , for the details of the handshaking with the processor in each mode. 0 software vector mode 1 hardware vector mode interrupt controller (intc) RM0029 386/1740 doc id 15177 rev 8 accesses. an mbar or msync instruction is also necessary after accessing the resource but before lowering the pri field. refer to section , ensuring coherency . figure 134. intc current priority register (intc_cpr) intc interrupt acknowledge register (intc_iackr) the intc_iackr provides a value that can be used to load the address of an isr from a vector table. the vector table can be composed of addresses of the isrs specific to their respective interrupt vectors. in software vector mode, reading the intc_iackr acknowledges the intc's interrupt request. refer to section , software vector mode , for a detailed description of the effect on the interrupt request to the processor. the reading also pushes the pri value in the intc current priority register (intc_cpr) onto the lifo and updates pri in the intc_cpr with the priority of the interrupt request. the side effect from the reads in software vector mode, that is, the effect on the interrupt request to the processor, the current priority, and the lifo, are the same regardless of the size of the read reading the intc_iackr does not have side effects in hardware vector mode. note: the intc_iackr must not be read speculatively while in software vector mode. therefore, for future compatibility, the tlb entry covering the intc_iackr must be configured to be guarded. in software vector mode, the intc_iackr must be read before setting msr[ee]. no synchronization instruction is needed after reading the intc_iackr and before setting msr[ee]. address: base + 0x0008 (intc_cpr) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 pri w reset: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 = unimplemented or reserved table 114. intc_cpr field descriptions field description 0?27 reserved, must be cleared. 28?31 pri priority. pri is the priority of the currently executing isr according to the field values defined below. 1111 priority 15 (highest) 1110 priority 14 ... 0001 priority 1 0000 priority 0 (lowest) RM0029 interrupt controller (intc) doc id 15177 rev 8 387/1740 however, the time for the processor to recognize the assertion or negation of the external input to it is not defined by the book e architecture and can be greater than 0. therefore, insert instructions between the reading of the intc_iackr and the setting of msr[ee] that consumes at least two processor clock cycles. this length of time allows the interrupt request negation to propagate through the processor before msr[ee] is set. figure 135. intc interrupt acknowledge register (intc_iackr)? intc_mcr[vtes] = 0 figure 136. intc interrupt acknowledge register (intc_iackr)? intc_mcr[vtes] = 1 address: base + 0x0010 (intc_iackr) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vtba (most significant 16 bits) w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r vtba (least significant 5 bits) intvec (1) 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. when the vtes bit in the intc module configuration register (intc_mcr) is asserted, intvec is shifted to the left one bit. bit 29 is read as a ?0?. vtba is narrowed to 20 bits in width. address: base + 0x0010 (intc_iackr) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vtba (most significant 16 bits) w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r vtba (least significant 4 bits) intvec (1) 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. when the vtes bit in the intc module configuration register (intc_mcr) is asserted, intvec is shifted to the left one bit. bit 29 is read as a ?0?. vtba1 is narrowed to 20 bits in width. interrupt controller (intc) RM0029 388/1740 doc id 15177 rev 8 intc end-of-interrupt register (intc_eoir) writing to the intc_eoir signals the end of the servicing of the interrupt request. when the intc_eoir is written, the priority last pushed on the lifo is popped into intc_cpr. the values and size of data written to the intc_eoir are ignored. the values and sizes written to this register neither update the intc_eoir contents nor affect whether the lifo pops. for possible future compatibility, write four bytes of all 0?s to the intc_eoir. reading the intc_eoir has no effect on the lifo. figure 137. intc end-of-interrupt register (intc_eoir) intc software set/clear interrupt registers intc_sscir0_3 ? intc_sscir4_7) the intc_sscir n supports the setting or clearing of software configurable interrupt requests. these registers contain eight independent sets of bits to set and clear a corresponding flag bit by software. with the exception of being set by software, this flag bit behaves the same as a flag bit set within a peripheral. this flag bit generates an interrupt request within the intc just like a peripheral interrupt request. writing a 1 to set n leaves set n unchanged at 0 but sets clr n . writing a 0 to set n has no effect. clr n is the flag bit. writing a 1 to clr n clears it. writing a 0 to clr n has no effect. if a 1 is written to a pair set n and clr n bits at the same time, clr n is asserted, regardless of whether clr n was asserted before the write. table 115. intc_iackr field descriptions field description 0?20 or 0?19 vtba vector table base address. can be the base address of a vector table of addresses of isrs. the vtba only uses the left-most 20 bits when the vtes bit in intc_mcr is asserted. 21?29 or 20?28 intvec interrupt vector. vector of peripheral or software-co nfigurable interrupt requests that caused the interrupt request to the processor. when the interrupt request to the processor asserts, the intvec is updated, whether the intc is in software or hardware vector mode. if intc_mcr[vtes] = 1, then the intvec field is shifted left one position to bits 20?28. vtba is then shortened by one bit to bits 0?19. 30?31 or 29?31 reserved, must be cleared. address: base + 0x0018 (intc_eoir) access: w/o 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved RM0029 interrupt controller (intc) doc id 15177 rev 8 389/1740 although intc_ssci n is 8 bits wide, it can be accessed with a single 16-bit or 32-bit access, provided that the access does not cross a 32-bit boundary. figure 138. intc software set/clear interrupt register (intc_sscir n ) intc priority select registers (intc_psr0?485) the intc_psr n allows you to select a priority for each interrupt request source (peripheral irqs or software configurable irqs). each priority select register (intc_psr n) is assigned to the irq source vector with the same number. for example, the software configurable irqs 0?7 are assigned vectors 0?7, and their priorities are configured in intc_psr0? intc_psr7, respectively. the peripheral interrupt requests are assigned vectors 8?485 and their priorities are configured in priority select registers intc_psr8 through intc_psr485, respectively. although intc_psr n is 8-bits wide, you can use a single 16-bit or 32-bit access, provided that it does not cross a 32-bit boundary. note: do not modify the pri n field in intc_psr n when the irq is asserted. address: base + 0x0020 + n (intc_sscir n ); n =0?7 access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 clr0 0 0 0 0 0 0 0 clr1 w set0 set1 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 clr2 0 0 0 0 0 0 0 clr3 w set2 set3 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 116. intc_sscir n field descriptions field description 0?5 reserved, must be cleared. 6 set n set flag bits. writing a 1 sets the corresponding clr n bit. writing a 0 has no effect. each set n is always read as a 0. 7 clr n clear flag bits. clr n is the flag bit. writing a 1 to clr n clears it provided that a 1 is not written simultaneously to its corresponding set n bit. writing a 0 to clr n has no effect. 0 interrupt request not pending within intc. 1 interrupt request pending within intc. interrupt controller (intc) RM0029 390/1740 doc id 15177 rev 8 figure 139. intc priority select register 0?3 (intc_psr0_3) figure 140. intc priority select register 482?485 (intc_psr482_485) 15.5 functional description 15.5.1 interrupt request sources the intc has two types of interrupt requests, peripheral and software configurable. the assignments between the interrupt requests from the modules to the vectors for input to the e200z4 are shown in tab le 118 . the hardware vector mode offset column lists the irq- specific offsets when using hardware vector mode. the source column shows the c address: base + 0x0010 (intc_iackr) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pri0 0 0 0 0 pri1 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 pri2 0 0 0 0 pri3 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved address: base + 0x0040 + n (intc_psr n ); n = 0?485 access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pri482 0 0 0 0 pri483 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 pri484 0 0 0 0 pri485 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 117. intc_psr n field descriptions field description 0?3 reserved, must be cleared. 4?7 pri n priority select. selects the priority for corresponding interrupt request. 1111 priority 15 (highest) 1110 priority 14 ... 0001 priority 1 0000 priority 0 (lowest) RM0029 interrupt controller (intc) doc id 15177 rev 8 391/1740 language syntax for the register bit label: module_register[bit]. interrupt requests from the same module location are ored together. the individual interrupt priorities are selected in intc_psr n , where the priority select register is assigned according to the vector number. table 118. interrupt request sources hardware vector mode offset vector number (1) source (2) description software 0x0000 0 intc_sscir0[clr0] intc software settable clear flag 0 0x0010 1 intc_sscir1[clr1] intc software settable clear flag 1 0x0020 2 intc_sscir2[clr2] intc software settable clear flag 2 0x0030 3 intc_sscir3[clr3] intc software settable clear flag 3 0x0040 4 intc_sscir4[clr4] intc software settable clear flag 4 0x0050 5 intc_sscir5[clr5] intc software settable clear flag 5 0x0060 6 intc_sscir6[clr6] intc software settable clear flag 6 0x0070 7 intc_sscir7[clr7] intc software settable clear flag 7 ecc 0x0080 8 reserved ? 0x0090 9 ecsm_esr[rnce] ecsm_esr[fnce] ecsm combined interrupt requests: internal sram non-correctable error and flash non-correctable error edmac 0x00a0 10 edma_erl[err31:err0] edma channel error flags 31?0 0x00b0 11 edma_irqrl[int00] edma channel interrupt 0 0x00c0 12 edma_irqrl[int01] edma channel interrupt 1 0x00d0 13 edma_irqrl[int02] edma channel interrupt 2 0x00e0 14 edma_irqrl[int03] edma channel interrupt 3 0x00f0 15 edma_irqrl[int04] edma channel interrupt 4 0x0100 16 edma_irqrl[int05] edma channel interrupt 5 0x0110 17 edma_irqrl[int06] edma channel interrupt 6 0x0120 18 edma_irqrl[int07] edma channel interrupt 7 0x0130 19 edma_irqrl[int08] edma channel interrupt 8 0x0140 20 edma_irqrl[int09] edma channel interrupt 9 0x0150 21 edma_irqrl[int10] edma channel interrupt 10 0x0160 22 edma_irqrl[int11] edma channel interrupt 11 0x0170 23 edma_irqrl[int12] edma channel interrupt 12 0x0180 24 edma_irqrl[int13] edma channel interrupt 13 0x0190 25 edma_irqrl[int14] edma channel interrupt 14 interrupt controller (intc) RM0029 392/1740 doc id 15177 rev 8 0x01a0 26 edma_irqrl[int15] edma channel interrupt 15 0x01b0 27 edma_irqrl[int16] edma channel interrupt 16 0x01c0 28 edma_irqrl[int17] edma channel interrupt 17 0x01d0 29 edma_irqrl[int18] edma channel interrupt 18 0x01e0 30 edma_irqrl[int19] edma channel interrupt 19 0x01f0 31 edma_irqrl[int20] edma channel interrupt 20 0x0200 32 edma_irqrl[int21] edma channel interrupt 21 0x0210 33 edma_irqrl[int22] edma channel interrupt 22 0x0220 34 edma_irqrl[int23] edma channel interrupt 23 0x0230 35 edma_irqrl[int24] edma channel interrupt 24 0x0240 36 edma_irqrl[int25] edma channel interrupt 25 0x0250 37 edma_irqrl[int26] edma channel interrupt 26 0x0260 38 edma_irqrl[int27] edma channel interrupt 27 0x0270 39 edma_irqrl[int28] edma channel interrupt 28 0x0280 40 edma_irqrl[int29] edma channel interrupt 29 0x0290 41 edma_irqrl[int30] edma channel interrupt 30 0x02a0 42 edma_irqrl[int31] edma channel interrupt 31 pll 0x02b0 43 fmpll_synsr[locf] fmpll loss of clock flag 0x02c0 44 fmpll_synsr[lolf] fmpll loss of lock flag siu 0x02d0 45 siu_osr[ovf15:ovf0] siu combined overrun interrupt requests of the external interrupt overrun flags 0x02e0 46 siu_eiisr[eif0] siu external interrupt flag 0 0x02f0 47 siu_eiisr[eif1] siu external interrupt flag 1 0x0300 48 siu_eiisr[eif2] siu external interrupt flag 2 0x0310 49 siu_eiisr[eif3] siu external interrupt flag 3 0x0320 50 siu_eiisr[eif15:eif4] siu external interrupt flags 15?4 emios 0x0330 51 emios_gfr[f0] emios channel 0 flag 0x0340 52 emios_gfr[f1] emios channel 1 flag 0x0350 53 emios_gfr[f2] emios channel 2 flag 0x0360 54 emios_gfr[f3] emios channel 3 flag table 118. interrupt request sources (continued) hardware vector mode offset vector number (1) source (2) description RM0029 interrupt controller (intc) doc id 15177 rev 8 393/1740 0x0370 55 emios_gfr[f4] emios channel 4 flag 0x0380 56 emios_gfr[f5] emios channel 5 flag 0x0390 57 emios_gfr[f6] emios channel 6 flag 0x03a0 58 emios_gfr[f7] emios channel 7 flag 0x03b0 59 emios_gfr[f8] emios channel 8 flag 0x03c0 60 emios_gfr[f9] emios channel 9 flag 0x03d0 61 emios_gfr[f10] emios channel 10 flag 0x03e0 62 emios_gfr[f11] emios channel 11 flag 0x03f0 63 emios_gfr[f12] emios channel 12 flag 0x0400 64 emios_gfr[f13] emios channel 13 flag 0x0410 65 emios_gfr[f14] emios channel 14 flag 0x0420 66 emios_gfr[f15] emios channel 15 flag etpu_a 0x0430 67 etpu_mcr[mgea] etpu_mcr[mgeb] etpu_mcr[ilfa] etpu_mcr[ilfb] etpu_mcr[scmmisf] etpu global exception 0x0440 68 etpu_cisr_a[cis0] etpu engine a channel 0 interrupt status 0x0450 69 etpu_cisr_a[cis1] etpu engine a channel 1 interrupt status 0x0460 70 etpu_cisr_a[cis2] etpu engine a channel 2 interrupt status 0x0470 71 etpu_cisr_a[cis3] etpu engine a channel 3 interrupt status 0x0480 72 etpu_cisr_a[cis4] etpu engine a channel 4 interrupt status 0x0490 73 etpu_cisr_a[cis5] etpu engine a channel 5 interrupt status 0x04a0 74 etpu_cisr_a[cis6] etpu engine a channel 6 interrupt status 0x04b0 75 etpu_cisr_a[cis7] etpu engine a channel 7 interrupt status 0x04c0 76 etpu_cisr_a[cis8] etpu engine a channel 8 interrupt status 0x04d0 77 etpu_cisr_a[cis9] etpu engine a channel 9 interrupt status 0x04e0 78 etpu_cisr_a[cis10] etpu engine a channel 10 interrupt status 0x04f0 79 etpu_cisr_a[cis11] etpu engine a channel 11 interrupt status 0x0500 80 etpu_cisr_a[cis12] etpu engine a channel 12 interrupt status 0x0510 81 etpu_cisr_a[cis13] etpu engine a channel 13 interrupt status 0x0520 82 etpu_cisr_a[cis14] etpu engine a channel 14 interrupt status 0x0530 83 etpu_cisr_a[cis15] etpu engine a channel 15 interrupt status table 118. interrupt request sources (continued) hardware vector mode offset vector number (1) source (2) description interrupt controller (intc) RM0029 394/1740 doc id 15177 rev 8 0x0540 84 etpu_cisr_a[cis16] etpu engine a channel 16 interrupt status 0x0550 85 etpu_cisr_a[cis17] etpu engine a channel 17 interrupt status 0x0560 86 etpu_cisr_a[cis18] etpu engine a channel 18 interrupt status 0x0570 87 etpu_cisr_a[cis19] etpu engine a channel 19 interrupt status 0x0580 88 etpu_cisr_a[cis20] etpu engine a channel 20 interrupt status 0x0590 89 etpu_cisr_a[cis21] etpu engine a channel 21 interrupt status 0x05a0 90 etpu_cisr_a[cis22] etpu engine a channel 22 interrupt status 0x05b0 91 etpu_cisr_a[cis23] etpu engine a channel 23 interrupt status 0x05c0 92 etpu_cisr_a[cis24] etpu engine a channel 24 interrupt status 0x05d0 93 etpu_cisr_a[cis25] etpu engine a channel 25 interrupt status 0x05e0 94 etpu_cisr_a[cis26] etpu engine a channel 26 interrupt status 0x05f0 95 etpu_cisr_a[cis27] etpu engine a channel 27 interrupt status 0x0600 96 etpu_cisr_a[cis28] etpu engine a channel 28 interrupt status 0x0610 97 etpu_cisr_a[cis29] etpu engine a channel 29 interrupt status 0x0620 98 etpu_cisr_a[cis30] etpu engine a channel 30 interrupt status 0x0630 99 etpu_cisr_a[cis31] etpu engine a channel 31 interrupt status eqadc 0x0640 100 eqadc_fisr x [torf] eqadc_fisr x [rfof] eqadc_fisr x [cfuf] eqadc combined overrun interrupt request s from all of the fifos: trigger overrun, receive fifo overflow, and command fifo underflow 0x0650 101 eqadc_fisr0[ncf] eqadc command fifo 0 non-coherency flag 0x0660 102 eqadc_fisr0[pf] eqadc command fifo 0 pause flag 0x0670 103 eqadc_fisr0[eoqf] eqadc command fifo 0 command queue end of queue flag 0x0680 104 eqadc_fisr0[cfff] eqadc command fifo 0 fill flag 0x0690 105 eqadc_fisr0[rfdf] eqadc receive fifo 0 drain flag 0x06a0 106 eqadc_fisr1[ncf] eqadc command fifo 1 non-coherency flag 0x06b0 107 eqadc_fisr1[pf] eqadc command fifo 1 pause flag 0x06c0 108 eqadc_fisr1[eoqf] eqadc command fifo 1 command queue end of queue flag 0x06d0 109 eqadc_fisr1[cfff] eqadc command fifo 1 fill flag 0x06e0 110 eqadc_fisr1[rfdf] eqadc receive fifo 1 drain flag table 118. interrupt request sources (continued) hardware vector mode offset vector number (1) source (2) description RM0029 interrupt controller (intc) doc id 15177 rev 8 395/1740 0x06f0 111 eqadc_fisr2[ncf] eqadc command fifo 2 non-coherency flag 0x0700 112 eqadc_fisr2[pf] eqadc command fifo 2 pause flag 0x0710 113 eqadc_fisr2[eoqf] eqadc command fifo 2 command queue end of queue flag 0x0720 114 eqadc_fisr2[cfff] eqadc command fifo 2 fill flag 0x0730 115 eqadc_fisr2[rfdf] eqadc receive fifo 2 drain flag 0x0740 116 eqadc_fisr3[ncf] eqadc command fifo 3 non-coherency flag 0x0750 117 eqadc_fisr3[pf] eqadc command fifo 3 pause flag 0x0760 118 eqadc_fisr3[eoqf] eqadc command fifo 3 command queue end of queue flag 0x0770 119 eqadc_fisr3[cfff] eqadc command fifo 3 fill flag 0x0780 120 eqadc_fisr3[rfdf] eqadc receive fifo 3 drain flag 0x0790 121 eqadc_fisr4[ncf] eqadc command fifo 4 non-coherency flag 0x07a0 122 eqadc_fisr4[pf] eqadc command fifo 4 pause flag 0x07b0 123 eqadc_fisr4[eoqf] eqadc command fifo 4 command queue end of queue flag 0x07c0 124 eqadc_fisr4[cfff] eqadc command fifo 4 fill flag 0x07d0 125 eqadc_fisr4[rfdf] eqadc receive fifo 4 drain flag 0x07e0 126 eqadc_fisr5[ncf] eqadc command fifo 5 non-coherency flag 0x07f0 127 eqadc_fisr5[pf] eqadc command fifo 5 pause flag 0x0800 128 eqadc_fisr5[eoqf] eqadc command fifo 5 command queue end of queue flag 0x0810 129 eqadc_fisr5[cfff] eqadc command fifo 5 fill flag 0x0820 130 eqadc_fisr5[rfdf] eqadc receive fifo 5 drain flag dspi 0x0830 131 dspi_bsr[tfuf] dspi_bsr[rfof] dspi_bsr[spef] dspi_bsr[dpef] dspi_b combined overrun interrupt requests: transmit fifo underflow and receive fifo overflow, spi and dsi parity error 0x0840 132 dspi_bsr[eoqf] dspi_b transmit fifo end of queue flag 0x0850 133 dspi_bsr[tfff] dspi_b transmit fifo fill flag 0x0860 134 dspi_bsr[tcf] dspi_b transfer complete flag table 118. interrupt request sources (continued) hardware vector mode offset vector number (1) source (2) description interrupt controller (intc) RM0029 396/1740 doc id 15177 rev 8 0x0870 135 dspi_bsr[rfdf] dspi_bsr[ddif] dspi_b receive fifo drain flag dspi_b dsi data interrupt 0x0880 136 dspi_csr[tfuf] dspi_csr[rfof] dspi_csr[spef] dspi_csr[dpef] dspi_c combined overrun interrupt requests: transmit fifo underflow and receive fifo overflow , spi and dsi parity error 0x0890 137 dspi_csr[eoqf] dspi_c transmit fifo end of queue flag 0x08a0 138 dspi_csr[tfff] dspi_c transmit fifo fill flag 0x08b0 139 dspi_csr[tcf] dspi_c transfer complete flag 0x08c0 140 dspi_csr[rfdf] dspi_csr[ddif] dspi_c receive fifo drain flag 0x08d0 141 dspi_dsr[tfuf] dspi_dsr[rfof] dspi_dsr[spef] dspi_dsr[dpef] dspi_d combined overrun interrupt requests: transmit fifo underflow and receive fifo overflow, spi and dsi parity error 0x08e0 142 dspi_dsr[eoqf] dspi_d transmit fifo end of queue flag 0x08f0 143 dspi_dsr[tfff] dspi_d transmit fifo fill flag 0x0900 144 dspi_dsr[tcf] dspi_d transfer complete flag 0x0910 145 dspi_dsr[rfdf] dspi_dsr[ddif] dspi_d receive fifo drain flag esci 0x0920 146 escia_sr[tdre] escia_sr[tc] escia_sr[rdrf] escia_sr[idle] escia_sr[or] escia_sr[nf] escia_sr[fe] escia_sr[pf] escia_sr[berr] escia_sr[rxrdy] escia_sr[txrdy] escia_sr[lwake] escia_sr[sto] escia_sr[pberr] escia_sr[cerr] escia_sr[ckerr] ? transmit data register empty, transmit complete, receive data register full, idle line, overrun, noise flag, framing error flag, and parity error flag interrupt requests, sci status register 2 bit error interrupt request, lin status register 1 receive data ready, transmit data ready, received lin wakeup signal, slave timeout, physical bus error, crc error, checksum error, frame complete interrupts requests, and lin status register 2 receive register overflow ? combined interrupt requests of esci module a table 118. interrupt request sources (continued) hardware vector mode offset vector number (1) source (2) description RM0029 interrupt controller (intc) doc id 15177 rev 8 397/1740 0x0930 147 gifer[lrne] gifer[drne] flexray lram non corrected error flexray dram non corrected error 0x0940 148 gifer[lrce] gifer[drce] flexray lram corrected error flexray dram corrected error 0x0950 149 escib_sr[tdre] escib_sr[tc] escib_sr[rdrf] escib_sr[idle] escib_sr[or] escib_sr[nf] escib_sr[fe] escib_sr[pf] escib_sr[berr] escib_sr[rxrdy] escib_sr[txrdy] escib_sr[lwake] escib_sr[sto] escib_sr[pberr] escib_sr[cerr] escib_sr[ckerr] combined interrupt requests of esci module b: transmit data register empty, transmit complete, receive data register full, idle line, overrun, noise flag, framing error flag, and parity error flag interrupt requests, sci status register 2 bit error interrupt request, lin status register 1 receive data ready, transmit data ready, received lin wakeup signal, slave timeout, physical bus error, crc error, checksum error, frame complete interrupts requests, and lin status register 2 receive register overflow 0x0960 150 reserved reserved 0x0970 151 reserved reserved flexcan_a and flexcan_c 0x0980 152 cana_esr[boff_int] flexcan_a bus off interrupt 0x0990 153 cana_esr[err_int] flexcan_a error interrupt 0x09a0 154 can_a.ipi_int_wakein flexcan_a wake up interrupt 0x09b0 155 cana_ifrl[buf0] flexcan_a buffer 0 interrupt 0x09c0 156 cana_ifrl[buf1] flexcan_a buffer 1 interrupt 0x09d0 157 cana_ifrl[buf2] flexcan_a buffer 2 interrupt 0x09e0 158 cana_ifrl[buf3] flexcan_a buffer 3 interrupt 0x09f0 159 cana_ifrl[buf4] flexcan_a buffer 4 interrupt 0x0a00 160 cana_ifrl[buf5] flexcan_a buffer 5 interrupt 0x0a10 161 cana_ifrl[buf6] flexcan_a buffer 6 interrupt 0x0a20 162 cana_ifrl[buf7] flexcan_a buffer 7 interrupt 0x0a30 163 cana_ifrl[buf8] flexcan_a buffer 8 interrupt 0x0a40 164 cana_ifrl[buf9] flexcan_a buffer 9 interrupt 0x0a50 165 cana_ifrl[buf10] flexcan_a buffer 10 interrupt table 118. interrupt request sources (continued) hardware vector mode offset vector number (1) source (2) description interrupt controller (intc) RM0029 398/1740 doc id 15177 rev 8 0x0a60 166 cana_ifrl[buf11] flexcan_a buffer 11 interrupt 0x0a70 167 cana_ifrl[buf12] flexcan_a buffer 12 interrupt 0x0a80 168 cana_ifrl[buf13] flexcan_a buffer 13 interrupt 0x0a90 169 cana_ifrl[buf14] flexcan_a buffer 14 interrupt 0x0aa0 170 cana_ifrl[buf15] flexcan_a buffer 15 interrupt 0x0ab0 171 cana_ifrl[buf31i:buf16] flexcan_a buffers 31 ? 16 interrupts 0x0ac0 172 cana_ifrh[buf63i:buf32] flexcan_a buffers 63 ? 32 interrupts 0x0ad0 173 canc_esr[boff_int] flexcan_c bus off interrupt 0x0ae0 174 canc_esr[err_int] flexcan_c error interrupt 0x0af0 175 can_c.ipi_int_wakein flexcan_c wake up interrupt 0x0b00 176 canc_ifrl[buf0] flexcan_c buffer 0 interrupt 0x0b10 177 canc_ifrl[buf1] flexcan_c buffer 1 interrupt 0x0b20 178 canc_ifrl[buf2] flexcan_c buffer 2 interrupt 0x0b30 179 canc_ifrl[buf3] flexcan_c buffer 3 interrupt 0x0b40 180 canc_ifrl[buf4] flexcan_c buffer 4 interrupt 0x0b50 181 canc_ifrl[buf5] flexcan_c buffer 5 interrupt 0x0b60 182 canc_ifrl[buf6] flexcan_c buffer 6 interrupt 0x0b70 183 canc_ifrl[buf7] flexcan_c buffer 7 interrupt 0x0b80 184 canc_ifrl[buf8] flexcan_c buffer 8 interrupt 0x0b90 185 canc_ifrl[buf9] flexcan_c buffer 9 interrupt 0x0ba0 186 canc_ifrl[buf10] flexcan_c buffer 10 interrupt 0x0bb0 187 canc_ifrl[buf11] flexcan_c buffer 11 interrupt 0x0bc0 188 canc_ifrl[buf12] flexcan_c buffer 12 interrupt 0x0bd0 189 canc_ifrl[buf13] flexcan_c buffer 13 interrupt 0x0be0 190 canc_ifrl[buf14] flexcan_c buffer 14 interrupt 0x0bf0 191 canc_ifrl[buf15] flexcan_c buffer 15 interrupt 0x0c00 192 canc_ifrl[buf31:buf16] flexcan_c buffers 31 ? 16 interrupts 0x0c10 193 canc_ifrh[buf63:buf32] flexcan_c buffers 63 ? 32 interrupts 0x0c20 194? 196 reserved reserved 0x0c50 197 decfil_a_in decimation a input (fill) 0x0c60 198 decfil_a_out decimation a output (drain) 0x0c70 199 decfil_a_err decimation a error table 118. interrupt request sources (continued) hardware vector mode offset vector number (1) source (2) description RM0029 interrupt controller (intc) doc id 15177 rev 8 399/1740 0x0c80 200 stm0 stm[0] 0x0c90 201 stm1_or_stm2_or_stm3 stm[1:3] emios 0x0ca0 202 emios_gfr[f16] emios channel 16 flag 0x0cb0 203 emios_gfr[f17] emios channel 17 flag 0x0cc0 204 emios_gfr[f18] emios channel 18 flag 0x0cd0 205 emios_gfr[f19] emios channel 19 flag 0x0ce0 206 emios_gfr[f20] emios channel 20 flag 0x0cf0 207 emios_gfr[f21] emios channel 21 flag 0x0d00 208 emios_gfr[f22] emios channel 22 flag 0x0d10 209 emios_gfr[f23] emios channel 23 flag edma 0x0d20 210 edma_errh[err63:err32] edma channel error flags 63 ? 32 0x0d30 211 edma_irqrh[int32] edma channel interrupt 32 0x0d40 212 edma_irqrh[int33] edma channel interrupt 33 0x0d50 213 edma_irqrh[int34] edma channel interrupt 34 0x0d60 214 edma_irqrh[int35] edma channel interrupt 35 0x0d70 215 edma_irqrh[int36] edma channel interrupt 36 0x0d80 216 edma_irqrh[int37] edma channel interrupt 37 0x0d90 217 edma_irqrh[int38] edma channel interrupt 38 0x0da0 218 edma_irqrh[int39] edma channel interrupt 39 0x0db0 219 edma_irqrh[int40] edma channel interrupt 40 0x0dc0 220 edma_irqrh[int41] edma channel interrupt 41 0x0dd0 221 edma_irqrh[int42] edma channel interrupt 42 0x0de0 222 edma_irqrh[int43] edma channel interrupt 43 0x0df0 223 edma_irqrh[int44] edma channel interrupt 44 0x0e00 224 edma_irqrh[int45] edma channel interrupt 45 0x0e10 225 edma_irqrh[int46] edma channel interrupt 46 0x0e20 226 edma_irqrh[int47] edma channel interrupt 47 0x0e30 227 edma_irqrh[int48] edma channel interrupt 48 0x0e40 228 edma_irqrh[int49] edma channel interrupt 49 0x0e50 229 edma_irqrh[int50] edma channel interrupt 50 0x0e60 230 edma_irqrh[int51] edma channel interrupt 51 table 118. interrupt request sources (continued) hardware vector mode offset vector number (1) source (2) description interrupt controller (intc) RM0029 400/1740 doc id 15177 rev 8 0x0e70 231 edma_irqrh[int52] edma channel interrupt 52 0x0e80 232 edma_irqrh[int53] edma channel interrupt 53 0x0e90 233 edma_irqrh[int54] edma channel interrupt 54 0x0ea0 234 edma_irqrh[int55] edma channel interrupt 55 0x0eb0 235 edma_irqrh[int56] edma channel interrupt 56 0x0ec0 236 edma_irqrh[int57] edma channel interrupt 57 0x0ed0 237 edma_irqrh[int58] edma channel interrupt 58 0x0ee0 238 edma_irqrh[int59] edma channel interrupt 59 0x0ef0 239 edma_irqrh[int60] edma channel interrupt 60 0x0f00 240 edma_irqrh[int61] edma channel interrupt 61 0x0f10 241 edma_irqrh[int62] edma channel interrupt 62 0x0f20 242 edma_irqrh[int63] edma channel interrupt 63 0x0f30 243?279 reserved reserved flexcan_b 0x1180 280 canb_esr[boff_int] flexcan_b bus off interrupt 0x1190 281 canb_esr[err_int] flexcan_b error interrupt 0x11a0 282 canb.ipi_int_wakein flexcan_b wake up interrupt 0x11b0 283 canb_ifrl[buf0] flexcan_b buffer 0 interrupt 0x11c0 284 canb_ifrl[buf1] flexcan_b buffer 1 interrupt 0x11d0 285 canb_ifrl[buf2] flexcan_b buffer 2 interrupt 0x11e0 286 canb_ifrl[buf3] flexcan_b buffer 3 interrupt 0x11f0 287 canb_ifrl[buf4] flexcan_b buffer 4 interrupt 0x1200 288 canb_ifrl[buf5] flexcan_b buffer 5 interrupt 0x1210 289 canb_ifrl[buf6] flexcan_b buffer 6 interrupt 0x1220 290 canb_ifrl[buf7] flexcan_b buffer 7 interrupt 0x1230 291 canb_ifrl[buf8] flexcan_b buffer 8 interrupt 0x1240 292 canb_ifrl[buf9] flexcan_b buffer 9 interrupt 0x1250 293 canb_ifrl[buf10] flexcan_b buffer 10 interrupt 0x1260 294 canb_ifrl[buf11] flexcan_b buffer 11 interrupt 0x1270 295 canb_ifrl[buf12] flexcan_b buffer 12 interrupt 0x1280 296 canb_ifrl[buf13] flexcan_b buffer 13 interrupt 0x1290 297 canb_ifrl[buf14] flexcan_b buffer 14 interrupt 0x12a0 298 canb_ifrl[buf15] flexcan_b buffer 15 interrupt table 118. interrupt request sources (continued) hardware vector mode offset vector number (1) source (2) description RM0029 interrupt controller (intc) doc id 15177 rev 8 401/1740 0x12b0 299 canb_ifrl[buf31:bu f16] flexcan_b buffers 31 ? 16 interrupts 0x12c0 300 canb_ifrh[buf63:buf32] flexcan_b buffers 63 ? 32 interrupts 0x12d0 301 pit0 pit[0] 0x12e0 302 pit1 pit[1] 0x12f0 303 pit2 pit[2] 0x1300 304 pit3 pit[3] 0x1310 305 rti rti 0x1320 306 pmc pmc 0x1330 307 ecsm_esr[r1bc] ecsm_esr[f1bc] flash and sram single-bit ecc error correction 0x1340 308 ? 349 reserved reserved flexray 0x15e0 350 gifer[mif] flexray mif 0x15f0 351 gifer[prif] flexray prif 0x1600 352 gifer[chif] flexray chif 0x1610 353 gifer[wup_if] flexray wup_if 0x1620 354 gifer[fbne_f] flexray fbne_f 0x1630 355 gifer[fane_f] flexray fane_f 0x1640 356 gifer[rbif] flexray rbif 0x1650 357 gifer[tbif] flexray tbif 0x1660 358 stm1 stm[1] 0x1670 359 stm2 stm[2] 0x1680 360 stm3 stm[3] 0x1690 361 ? 365 reacm_ge reacm[0] reacm[1] reacm[2] reacm[3] reaction channel global error reaction channel 0 ? 3 interrupt 0x16e0 366 decfil_b_in decimation b input (fill) 0x16f0 367 decfil_b_out decimation b output (drain) 0x1700 368 decfil_b_err decimation b error 0x1710 369? 472 reserved reserved reaction module table 118. interrupt request sources (continued) hardware vector mode offset vector number (1) source (2) description interrupt controller (intc) RM0029 402/1740 doc id 15177 rev 8 the peripheral or software configurable interrupt request asserts when the prin value in the interrupt priority select register (intc_psrn) is greater than the prin value in interrupt current priority register (intc_cpr). if an asserted peripheral or software configurable interrupt request negates before the processor acknowledges its request, the interrupt request can reassert and remain asserted. if this occurs, the processor uses the intc_psrn value to locate the irq vector, and updates the prin value in the intc_cpr with the prin value in intc_psrn. clearing the peripheral interrupt request enable bit for the peripheral initiating the request, or setting the irq mask bit has the same consequences as clearing its flag bit. setting its enable bit or clearing its mask bit while its flag bit is asserted has the same effect on the intc as an interrupt event setting the flag bit. 0x1690 361 ? 365 reacm_ge reacm[0] reacm[1] reacm[2] reacm[3] reaction channel global error reaction channel 0 ? 3interrupt 0x1d90 473 escic_sr[tdre] escic_sr[tc] escic_sr[rdrf] escic_sr[idle] escic_sr[or] escic_sr[nf] escic_sr[fe] escic_sr[pf] escic_sr[berr] escic_sr[rxrdy] escic_sr[txrdy] escic_sr[lwake] escic_sr[sto] escic_sr[pberr] escic_sr[cerr] escic_sr[ckerr] combined interrupt requests of esci module c: transmit data register empty, transmit complete, receive data register full, idle line, overrun, noise flag, framing error flag, and parity error flag interrupt requests, sci status register 2 bit error interrupt request, lin status register 1 receive data ready, transmit data ready, received lin wakeup signal, slave timeout, physical bus error, crc error, checksum error, frame complete interrupts requests, and lin status register 2 receive register overflow 0x1da0 474? 483 reserved reserved 0x1e40 484? 485 reacm[4] reacm[5] reaction channel 4 ? 5 interrupts 1. the maximum vector number (485) is used to identify t he location of the last available interrupt vector in memory for this device. because blocks of memory throughout the total memory map are used for other purposes, the maximum vector number does not indicate the total number of available interrupt sources for this device. 2. interrupt requests from the same module location are ored together. table 118. interrupt request sources (continued) hardware vector mode offset vector number (1) source (2) description RM0029 interrupt controller (intc) doc id 15177 rev 8 403/1740 peripheral interrupt requests an interrupt event in a peripheral?s hardware sets a flag bit, which resides in that peripheral. the interrupt request from the peripheral is driven by that flag bit. the time from when the peripheral starts to drive its peripheral interrupt request to the intc to the time that the intc starts to drive the interrupt request to the processor is three clocks. software configurable interrupt requests the software set/clear interrupt registers (intc_sscir x_x ) support the setting or clearing of software-configurable interrupt requests. these registers contain eight independent sets of bits to set and clear a corresponding flag bit by software. with the exception of being set by software, this flag bit behaves the same as a flag bit set within a peripheral. this flag bit generates an interrupt request within the intc just like a peripheral interrupt request. an interrupt request is triggered by software writing a 1 to the set n bit in intc software set/clear interrupt registers (intc_sscir0?intc_sscir7). this write sets a clr n flag bit that generates an interrupt request. the interrupt request is cleared by writing a 1 to the clr n bit. specific behavior includes the following: writing a 1 to set n leaves set n unchanged at 0 but sets the flag bit (clr n bit). writing a 0 to set n has no effect. writing a 1 to clr n clears the flag (clr n ) bit. writing a 0 to clr n has no effect. if a 1 is written to a pair of set n and clr n bits at the same time, the flag (clr n ) is set, regardless of whether clr n was asserted before the write. the time from the write to the set n bit to the time that the intc starts to drive the interrupt request to the processor is four clocks. unique vector for each interrupt request source each peripheral and software configurable interrupt request is assigned a hardwired unique 9-bit vector. software configurable interrupts 0?7 are assigned vectors 0?7, respectively. the peripheral interrupt requests are assigned vectors 8 to as high as needed to cover all of the peripheral interrupt requests. 15.5.2 priority management the asserted interrupt requests are compared to each other based on their pri n values in intc priority select registers (intc_psr0?intc_psr485). the result of the comparison also is compared to pri in intc current priority register (intc_cpr). the results of those comparisons are used to manage the priority of the isr being executed by the processor. the lifo also assists in managing the priority. current priority and preemption the priority arbitrator, selector, encoder, and comparator submodules shown in figure 127 are used to compare the priority of the asserted interrupt requests to the current priority. if the priority of any asserted peripheral or software configurable interrupt request is higher than the current priority, then the interrupt request to the processor is asserted. also, a unique vector for the preempting peripheral or software configurable interrupt request is generated for intc interrupt acknowledge register (intc_iackr), and if in hardware vector mode, for the interrupt vector provided to the processor. interrupt controller (intc) RM0029 404/1740 doc id 15177 rev 8 priority arbitrator submodule the priority arbitrator submodule compares all the priorities of all of the asserted interrupt requests, both peripheral and software configurable. the output of the priority arbitrator submodule is the highest of those priorities. also, any interrupt requests which have this highest priority are output as asserted interrupt requests to the request selector submodule. request selector submodule if only one interrupt request from the priority arbitrator submodule is asserted, then it is passed as asserted to the vector encoder submodule. if multiple interrupt requests from the priority arbitrator submodule are asserted, then only the one with the lowest vector is passed as asserted to the vector encoder submodule. the lower vector is chosen regardless of the time order of the assertions of the peripheral or software configurable interrupt requests. vector encoder submodule the vector encoder submodule generates the unique 9-bit vector for the asserted interrupt request from the request selector submodule. priority comparator submodule the priority comparator submodule compares the highest priority output from the priority arbitrator submodule with pri in intc_cpr. if the priority comparator submodule detects that this highest priority is higher than the current priority, then it asserts the interrupt request to the processor. this interrupt request to the processor asserts whether this highest priority is raised above the value of pri in intc_cpr or the pri value in intc_cpr is lowered below this highest priority. this highest priority then becomes the new priority which is written to pri in intc_cpr when the interrupt request to the processor is acknowledged. interrupt requests whose pri n in intc_psr n are zero does not cause a preemption because their pri n is not higher than pri in intc_cpr. lifo the lifo stores the preempted pri values from the intc_cpr. therefore, because these priorities are stacked within the intc, if interrupts need to be enabled during the isr, at the beginning of the interrupt exception handler the pri value in the intc_cpr does not need to be loaded from the intc_cpr and stored onto the context stack. likewise at the end of the interrupt exception handler, the priority does not need to be loaded from the context stack and stored into the intc_cpr. the pri value in the intc_cpr is pushed onto the lifo when the intc_iackr is read in software vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode. the priority is popped into pri in the intc_cpr whenever the intc_eoir is written. although the intc supports 16 priorities, an isr executing with pri in the intc_cpr equal to 15 is not preempted. therefore, the lifo supports the stacking of 15 priorities. however, the lifo is only 14 entries deep. an entry for a priority of 0 is not needed because of how pushing onto a full lifo and popping an empty lifo are treated. if the lifo is pushed 15 or more times than it is popped, the priorities first pushed are overwritten. a priority of 0 is an overwritten priority. however, the lifo pop zeros if it is popped more times than it is pushed. therefore, although a priority of 0 was overwritten, it is regenerated with the popping of an empty lifo. RM0029 interrupt controller (intc) doc id 15177 rev 8 405/1740 the lifo is not memory mapped. 15.5.3 details on handshaking with processor software vector mode handshaking acknowledging interrupt request to processor a timing diagram of the interrupt request and acknowledge handshaking in software vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in figure 141 . the intc examines the peripheral and software configurable interrupt requests. when it finds an asserted peripheral or software configurable interrupt request with a higher priority than pri in intc current priority register (intc_cpr), it asserts the interrupt request to the processor. the intvec field in intc interrupt acknowledge register (intc_iackr) is updated with the preempting interrupt request?s vector when the interrupt request to the processor is asserted. the intvec field retains that value until the next time the interrupt request to the processor is asserted. the rest of the handshaking is described in section , software vector mode . end-of-interrupt exception handler before the interrupt exception handling completes, intc end-of-interrupt register (intc_eoir) must be written. when it is written, the lifo is popped so that the preempted priority is restored into pri of the intc_cpr. before it is written, the peripheral or software configurable flag bit must be cleared so that the peripheral or software configurable interrupt request is negated. note: to ensure proper operation across all power architecture mcus, execute an mbar or msync instruction between the access to clear the flag bit and the write to the intc_eoir. when returning from the preemption, the intc does not search for the peripheral or software configurable interrupt request whose isr was preempted. depending on how much the isr progressed, that interrupt request can no longer be asserted. when pri in intc_cpr is lowered to the priority of the preempted isr, the interrupt request for the preempted isr or any other asserted peripheral or software configurable interrupt request at or below that priority does not cause a preemption. instead, after the restoration of the preempted context, the processor returns to the instruction address that it was to next execute before it was preempted. this next instruction is part of the preempted isr or the interrupt exception handler?s prolog or epilog. interrupt controller (intc) RM0029 406/1740 doc id 15177 rev 8 figure 141. software vector mode handshaking timing diagram hardware vector mode handshaking a timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in figure 142 . as in software vector mode, the intc examines the peripheral and software configurable interrupt requests, and when it finds an asserted one with a higher priority than pri in intc_cpr, it asserts the interrupt request to the processor. the intvec field in the intc_iackr is updated with the preempting peripheral or software configurable interrupt request?s vector when the interrupt request to the processor is asserted. the intvec field retains that value until the next time the interrupt request to the processor is asserted. in addition, the value of the interrupt vector to the processor matches the value of the intvec field in the intc_iackr. the rest of the handshaking is described in section , hardware vector mode . the handshaking near the end of the interrupt exception handler, that is the writing to the intc_eoir, is the same as in software vector mode. refer to section , end-of-interrupt exception handler . clock interrupt request to processor hardware vector enable interrupt acknowledge interrupt vector read intc_iackr write intc_eoir intvec in intc_iackr pri in intc_cpr peripheral interrupt request 100 0 0 0 108 10 RM0029 interrupt controller (intc) doc id 15177 rev 8 407/1740 figure 142. hardware vector mode handshaking timing diagram 15.6 initialization and application information 15.6.1 initialization flow after exiting reset, all of the pri n fields in intc priority select registers (intc_psr0? intc_psr485) is zero, and pri in intc current priority register (intc_cpr) is 15. these reset values prevent the intc from asserting the interrupt request to the processor. the enable or mask bits in the peripherals are reset such that the peripheral interrupt requests are negated. an initialization sequence that allows the peripheral and software configurable interrupt requests to generate an interrupt request to the processor is: interrupt_request_initialization: configure vtes and hven in intc_mcr configure vtba in intc_iackr raise the pri n fields in intc_psr n set the enable bits or clear the mask bits for the peripheral interrupt requests lower pri in intc_cpr to zero enable processor recognition of interrupts 15.6.2 interrupt exception handler these example interrupt exception handlers use power architecture assembly code. software vector mode interrupt_exception_handler: code to create stack frame, save working register, and save srr0 and srr1 clock interrupt request to processor hardware vector enable interrupt acknowledge interrupt vector read intc_iackr write intc_eoir intvec in intc_iackr pri in intc_cpr peripheral interrupt request 100 0 0108 0 108 01 interrupt controller (intc) RM0029 408/1740 doc id 15177 rev 8 lis r3,intc_iackr@ha# form adjusted upper half of intc_iackr address lwz r3,intc_iackr@l(r3)# load intc_iackr, which clears request to processor lwz r3,0x0(r3) # load address of isr from vector table wrteei1 # enable processor recognition of interrupts code to save rest of context required by e500 eabi mtlr r3 # move the intc_iackr address into the link register blrl # branch to isr; link register updated with epilog # address epilog: code to restore most of context required by e500 eabi # popping the lifo after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,intc_eoir@ha # form adjusted upper half of intc_eoir address li r4,0x0 # form 0 to write to intc_eoir wrteei0 # disable processor recognition of interrupts stw r4,intc_eoir@l(r3) # store to intc_eoir, informing intc to lower priority code to restore srr0 and srr1, restore working registers, and delete stack frame rfi vector_table_base_address: address of isr for interrupt with vector 0 address of isr for interrupt with vector 1 . . . address of isr for interrupt with vector 510 address of isr for interrupt with vector 511 isr x : code to service the interrupt event code to clear flag bit which drives interrupt request to intc blr # return to epilog hardware vector mode this interrupt exception handler is useful with processor and system bus implementations that support a hardware vector. in this example, each interrupt_exception_handler x has space for only four instructions, and therefore a branch to interrupt_ exception_handler_continued x is needed. interrupt_exception_handler x : b interrupt_exception_handler_continued x # 4 instructions available, branch to continue RM0029 interrupt controller (intc) doc id 15177 rev 8 409/1740 interrupt_exception_handler_continued x : code to create stack frame, save working register, and save srr0 and srr1 wrteei1 # enable processor recognition of interrupts code to save rest of context required by e500 eabi bl isr x # branch to isr for interrupt with vector x epilog: code to restore most of context required by e500 eabi # popping the lifo after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,intc_eoir@ha # form adjusted upper half of intc_eoir address li r4,0x0 # form 0 to write to intc_eoir wrteei0 # disable processor recognition of interrupts stw r4,intc_eoir@l(r3)# store to intc_eoir, informing intc to lower priority code to restore srr0 and srr1, restore working registers, and delete stack frame rfi isr x : code to service the interrupt event code to clear flag bit which drives interrupt request to intc blr # branch to epilog 15.6.3 isr, rtos, and task hierarchy the rtos and all of the tasks under its control typically execute with pri in intc current priority register (intc_cpr) having a value of 0. the rtos execute the tasks according to whatever priority scheme that it has, but that priority scheme is independent and has a lower priority of execution than the priority scheme of the intc. in other words, the isrs execute above intc_cpr priority 0 and outside the control of the rtos, the rtos executes at intc_cpr priority 0, and while the tasks execute at different priorities under the control of the rtos, they also execute at intc_cpr priority 0. if a task shares a resource with an isr and the pcp is being used to manage that shared resource, then the task?s priority can be elevated in the intc_cpr while the shared resource is being accessed. an isr whose pri n in intc priority select registers (intc_psr0?intc_psr485) has a value of 0 does not cause an interrupt request to the processor, even if its peripheral or software configurable interrupt request is asserted. for a peripheral interrupt request, not interrupt controller (intc) RM0029 410/1740 doc id 15177 rev 8 setting its enable bit or disabling the mask bit causes it to remain negated, which consequently also does not cause an interrupt request to the processor. since the isrs are outside the control of the rtos, this isr does not run unless called by another isr or the interrupt exception handler, perhaps after executing another isr. 15.6.4 order of execution an isr with a higher priority can preempt an isr with a lower priority, regardless of the unique vectors associated with each of their peripheral or software configurable interrupt requests. however, if multiple peripheral or software configurable interrupt requests are asserted, more than one has the highest priority, and that priority is high enough to cause preemption, the intc selects the one with the lowest unique vector regardless of the order in time that they asserted. however, the ability to meet deadlines with this scheduling scheme is no less than if the isrs execute in the time order that their peripheral or software configurable interrupt requests asserted. the example in tab le 119 shows the order of execution of both isrs with different priorities, and with the same priority. table 119. order of isr execution example step step description code executing at end of step pri in intc_cpr at end of step rtos isr108 (1) isr208 isr308 isr408 interrupt exception handler 1 rtos at priority 0 is executing. x 0 2 peripheral interrupt request 100 at priority 1 asserts. interrupt taken. x1 3 peripheral interrupt request 400 at priority 4 asserts. interrupt taken. x4 4 peripheral interrupt request 300 at priority 3 asserts. x4 5 peripheral interrupt request 200 at priority 3 asserts. x4 6 isr408 completes. interrupt exception handler writes to intc_eoir. x1 7 interrupt taken. isr208 starts to execute, even though peripheral interrupt request 300 asserted first. x3 8 isr208 completes. interrupt exception handler writes to intc_eoir. x1 9 interrupt taken. isr308 starts to execute. x3 10 isr308 completes. interrupt exception handler writes to intc_eoir. x1 RM0029 interrupt controller (intc) doc id 15177 rev 8 411/1740 15.6.5 priority ceiling protocol elevating priority the pri field in intc current priority register (intc_cpr) is elevated in the osek pcp to the ceiling of all of the priorities of the isrs that share a resource. this protocol therefore allows coherent accesses of the isrs to that shared resource. for example, isr1 has a priority of 1, isr2 has a priority of 2, and isr3 has a priority of 3. they all share the same resource. before isr1 or isr2 can access that resource, they must raise the pri value in intc_cpr to 3, the ceiling of all of the isr priorities. after they release the resource, the pri value in intc_cpr can be lowered. if they do not raise their priority, then isr2 can preempt isr1, and isr3 can preempt isr1 or isr2, possibly corrupting the shared resource. another possible failure mechanism is deadlock. if the higher priority isr needs the lower priority isr to release the resource before it can continue, but the lower priority isr cannot release the resource until the higher priority isr completes and execution returns to the lower priority isr. using the pcp instead of disabling processor recognition of all interrupts eliminates the time when accessing a shared resource that all higher priority interrupts are blocked. for example, while isr3 cannot preempt isr1 while it is accessing the shared resource, all of the isrs with a priority higher than 3 can preempt isr1. ensuring coherency non-coherent accesses to a shared resource can occur. as an example, isr1 and isr2 both share a resource. isr1 has a lower priority, therefore it executes and then writes the new pri value in the current priority register (intc_cpr). the next instruction writes a value to a shared coherent data block. if intc asserts the isr2 interrupt request to the processor just before or at the same time as the first isr1 write, it is possible for both the isr1 and isr2 writes to execute while the processor responds to the intc request, discards the transactions, and flushes the processing pipeline. however, isr2 cannot access the data block coherently because the data block is now corrupted. osek uses the getresource and releaseresource system services to manage access to a shared resource. to prevent corrupting a coherent data block, use the following code to modify the pri in intc_cpr. interrupts must be enabled before executing the following getresource code sequence: 11 isr108 completes. interrupt exception handler writes to intc_eoir. x0 12 rtos continues execution. x 0 1. isr108 executes for peripheral interrupt request 100 because the first eight isrs ar e for software configurable interrupt requests. table 119. order of isr execution example (continued) step step description code executing at end of step pri in intc_cpr at end of step rtos isr108 (1) isr208 isr308 isr408 interrupt exception handler interrupt controller (intc) RM0029 412/1740 doc id 15177 rev 8 getresource: raise pri mbar isync releaseresource: mbar lower pri 15.6.6 selecting priorities according to request rates and deadlines the selection of the priorities for the isrs can be made using rate monotonic scheduling (rms) or a superset of it, deadline monotonic scheduling (dms). in rms, the isrs that have higher request rates have higher priorities. in dms, if the deadline is before the next time the isr is requested, then the isr is assigned a priority according to the time from the request for the isr to the deadline, not from the time of the request for the isr to the next request for it. for example, isr1 executes every 100 s, isr2 executes every 200 s, and isr3 executes every 300 s. isr1 has a higher priority than isr2, which has a higher priority than isr3. however, if isr3 has a deadline of 150 s, then it has a higher priority than isr2. the intc has 16 priorities, which can be considerably less than the number of isrs. in this case, group the isrs with other isrs that have similar deadlines. for example, when a priority is allocated for every time, the request rate doubles isrs with request rates around 1 ms share a priority; isrs with request rates around 500 s share a priority; isrs with request rates around 250 s share a priority, etc. with this approach, a range of isr request rates of 2 16 can be covered, regardless of the number of isrs. reducing the number of priorities reduces the processor's ability to meet its deadlines. however, it also allows easier management of isrs with similar deadlines that share a resource. they do not need to use the pcp to access the shared resource. 15.6.7 software configurable interrupt requests the software configurable interrupt requests can be used in two ways. they can be used to schedule a lower priority portion of an isr and for processors to interrupt other processors in a multiple processor system. scheduling a lower priority portion of an isr a portion of an isr needs to be executed at the pri n value in intc priority select registers (intc_psr0?intc_psr485), which becomes the pri value in intc current priority register (intc_cpr) with the interrupt acknowledgement. the isr, however, can have a portion of it that does not need to be executed at this higher priority. therefore, executing this later portion that does not need to be executed at this higher priority can prevent the execution of isrs, which do not have a higher priority than the earlier portion of the isr but do have a higher priority than what the later portion of the isr needs. this preemptive scheduling inefficiency reduces the processor's ability to meet its deadlines. one option is for the isr to complete the earlier higher priority portion, but then schedule through the rtos a task to execute the later lower priority portion. however, some rtoss can require a large amount of time for an isr to schedule a task. therefore, a second option for the isr is, after completing the higher priority portion, to set a set n bit in intc software RM0029 interrupt controller (intc) doc id 15177 rev 8 413/1740 set/clear interrupt registers (intc_sscir0?intc_sscir7). writing a 1 to set n causes a software configurable interrupt request. this software configurable interrupt request, which usually has a lower pri n value in the intc_psr n , does not cause preemptive scheduling inefficiencies. after generating a software configurable interrupt request, the higher priority isr completes. the lower priority isr is scheduled according to its priority. execution of the higher priority isr is not resumed after the completion of the lower priority isr. scheduling an isr on another processor since the set n bits in the intc_sscir n are memory mapped, processors in multiple processor systems can schedule isrs on the other processors. one application is that one processor simply wants to command another processor to perform a piece of work, and the initiating processor does not need to use the results of that work. if the initiating processor is concerned that processor executing the software configurable isr has not completed the work before asking it to again execute that isr, it can check if the corresponding clr n bit in intc_sscir n is asserted before again writing a 1 to the set n bit. another application is the sharing of a block of data. for example, a first processor has completed accessing a block of data and wants a second processor to then access it. furthermore, after the second processor has completed accessing the block of data, the first processor again wants to access it. the accesses to the block of data must be done coherently. the procedure is that the first processor writes a 1 to a set n bit on the second processor. the second processor, after accessing the block of data, clears the corresponding clr n bit and then writes 1 to a set n bit on the first processor, informing it that it now can access the block of data. 15.6.8 lowering priority within an isr in implementations without the software-configurable interrupt requests in the intc software set/clear interrupt registers (intc_sscir0?intc_sscir7), a way ? besides scheduling a task through an rtos ? to prevent preemptive scheduling inefficiencies with an isr whose work spans multiple priorities (as described in section , scheduling a lower priority portion of an isr ) is to lower the current priority. however, the intc has a lifo whose depth is determined by the number of priorities. note: lowering the pri value in intc current priority register (intc_cpr) within an isr to below the isr?s corresponding pri value in intc priority select registers (intc_psr0? intc_psr485) allows more preemptions than the depth of the lifo can support. therefore, through its use of the lifo the intc does not support lowering the current priority within an isr as a way to avoid preemptive scheduling inefficiencies. 15.6.9 negating an interrupt request outside of its isr negating an interrupt request as a side effect of an isr some peripherals have flag bits which can be cleared as a side effect of servicing a peripheral interrupt request. for example, reading a specific register can clear the flag bits, and consequently their corresponding interrupt requests, too. this clearing as a side effect of servicing a peripheral interrupt request can cause the negation of other peripheral interrupt requests besides the peripheral interrupt request whose isr presently is executing. this negating of a peripheral interrupt request outside of its isr can be a desired effect. interrupt controller (intc) RM0029 414/1740 doc id 15177 rev 8 negating multiple interrupt requests in one isr an isr can clear other flag bits besides its own flag bit. one reason that an isr clears multiple flag bits is because it serviced those other flag bits, and therefore the isrs for these other flag bits do not need to be executed. proper setting of interrupt request priority whether an interrupt request negates outside of its own isr due to the side effect of an isr execution or the intentional clearing a flag bit, the priorities of the peripheral or software configurable interrupt requests for these other flag bits must be selected properly. their pri n values in intc priority select registers (intc_psr0?intc_psr485) must be selected to be at or lower than the priority of the isr that cleared their flag bits. otherwise, those flag bits still can cause the interrupt request to the processor to assert. furthermore, the clearing of these other flag bits also has the same timing relationship to the writing to intc end-of-interrupt register (intc_eoir) as the clearing of the flag bit that caused the present isr to be executed. refer to section , end-of-interrupt exception handler , for more information. a flag bit whose enable bit or mask bit is negating its peripheral interrupt request can be cleared at any time, regardless of the peripheral interrupt request?s pri n value in intc_psr n . 15.6.10 examining lifo contents normally you do not need to know the contents of the lifo, or even how deep the lifo is nested. although the lifo contents are not memory mapped, you can read the contents by popping the lifo and reading the pri field in the intc current priority register (intc_cpr). disabling processor recognition of interrupts while examining the lifo contents provides a coherent view of the preempted priorities. the code sequence is: pop_lifo: store to intc_eoir load intc_cpr, examine pri, and store onto stack if pri is not zero or value when interrupts were enabled, branch to pop_lifo when you are finished examining the lifo contents, you can restore it in software vector mode using the following code sequence. in hardware vector mode, reading the intc_iackr does not push the intc_cpr[pri] onto the lifo, therefore the lifo contents cannot be restored in hardware vector mode. push_lifo: load stacked pri value and store to intc_cpr load intc_iackr if stacked pri values are not depleted, branch to push_lifo note: reading the intc_iackr acknowledges the interrupt request to the processor and updates the intc_cpr[pri] with the priority of the preempting interrupt request. if the processor recognition of interrupts is disabled during the lifo restoration, interrupt requests to the processor can go undetected. however, since the peripheral or software configurable interrupt requests are not cleared, the peripheral interrupt request to the processor re- asserts when intc_cpr[pri] is lower than the priorities of those peripheral or software configurable interrupt requests. RM0029 system integration unit (siu) doc id 15177 rev 8 415/1740 16 system integration unit (siu) 16.1 overview the system integration unit (siu) controls this device?s reset configuration, pad configuration, external interrupt, general purpose i/o (gpio), internal peripheral multiplexing, and the system reset operation. the reset configuration block contains the external pin boot configuration logic. the pad configuration block controls the static electrical characteristics of i/o pins. the gpio block provides uniform and discrete input/output control of the mcu i/o pins. the reset controller performs reset monitoring of internal and external reset sources, and drives the rstout pin. the siu is accessed by the core through the peripheral bus. 16.2 features system configuration ? mcu reset configuration via external pins ? pad configuration control system reset monitoring and generation ? power-on reset support ? reset status register provides last reset source to software ? glitch detection on reset input ? software controlled reset assertion external interrupt ? 15 interrupt requests ? 1 non-maskable/critical interrupt request (nmi) ? rising or falling edge event detection ? programmable digital filter for glitch rejection gpio ? gpio function on 163 i/o pins ? dedicated input and output registers for each gpio pin internal multiplexing ? allows serial and parallel chaining of dspis ? allows flexible selection of eqadc trigger inputs ? allows selection of interrupt requests between external pins and dspi ? allows selection of some etpu inputs from external etpu pins or deserialized output from the dspi module ? allows selection of serialized data source for the dspi system integration unit (siu) RM0029 416/1740 doc id 15177 rev 8 16.3 modes of operation 16.3.1 normal mode in normal mode, the siu provides the register interface and logic that controls system configuration, the reset controller, and gpio. 16.3.2 debug mode siu operation in debug mode is identical to operation in normal mode. 16.4 block diagram figure 143 is a block diagram of the siu. the signals shown are external pins to the device. the siu registers are accessed through the crossbar switch. note that the power-on reset detection block, pad interface/pad ring block, and peripheral i/o channels are external to the siu. RM0029 system integration unit (siu) doc id 15177 rev 8 417/1740 figure 143. siu block diagram 16.5 signal description ta ble 12 0 lists the external pins used by the siu. reset controller reset siu registers detection gpio rstout pad configuration power-on reset peripheral i/o channels pad interface/pad ring config reset edge external irq / imux dspi signals, & irq inputs, eqadc triggers bootcfg1_ irq[7:15] irq[4:5] irq[0:3] irq[3]_ gpio[212] wkpcfg_ nmi_ gpio[213] detects bootcfg0_ irq[2]_ gpio[211] etrig[3] system integration unit (siu) RM0029 418/1740 doc id 15177 rev 8 16.6 memory map and register descriptions 16.6.1 memory map ta ble 12 1 is the address map for the siu registers. table 120. siu signal properties name i/o type pad type function pull up/down (1) resets reset input ? reset input up rstout output slow reset output up system configuration bootcfg0 input slow boot configuration input down bootcfg1 input slow boot configuration input down wkpcfg_ nmi_ gpio[213] input input i/o slow weak pull configuration pin / non-maskable interrupt / general purpose i/o up ? up/down gpio configuration gpio[0:245] i/o slow general purpose i/o up/down external interrupt irq[0:5,7:15] input slow external interrupt request input ? (2) 1. internal weak pull up/down. the reset weak pull up/down st ate is given by the pull up/down state for the primary pin function. for example, the reset weak pull up/down state of the bootcfg1 pin is weak pull down enabled. 2. see table 5 in section 3.1, signal properties for more information. table 121. siu address map address use bits per register location siu_base mcu id register 2 (siu_midr2) 32 on page 16- 420 siu_base+0x4 mcu id register (siu_midr) 32 on page 16- 422 siu_base+0x8 reserved siu_base+0xc reset status register (siu_rsr) 32 on page 16- 423 siu_base+0x10 system reset control register (siu_srcr) 32 on page 16- 425 siu_base+0x14 siu external interrupt status register (siu_eisr) 32 on page 16- 426 siu_base+0x18 dma/interrupt request enable register (siu_direr) 32 on page 16- 427 RM0029 system integration unit (siu) doc id 15177 rev 8 419/1740 siu_base+0x1c dma/interrupt request select register (siu_dirsr) 32 on page 16- 428 siu_base+0x20 overrun status register (siu_osr) 32 on page 16- 429 siu_base+0x24 overrun request enable register (siu_orer) 32 on page 16- 430 siu_base+0x28 external irq rising-edge event enable register (siu_ireer) 32 on page 16- 430 siu_base+0x2c external irq falling-edge event enable register (siu_ifeer) 32 on page 16- 431 siu_base+0x30 external irq digital filter register (siu_idfr) 32 on page 16- 432 siu_base+0x34 ? siu_base+0x3f reserved siu_base+0x40 ? siu_base+0x37b pad configuration register 0 (siu_pcr0) ? pad configuration register 413 (siu_pcr413) (1) 16 on page 16- 434 siu_base+0x37c ? siu_base+0x5ff reserved siu_base+0x600 ? siu_base+0x79d gpio pin data output register 0 ? 3 (siu_gpdo0_3) ? gpio pin data output register 412 ? 413 (siu_gpdo412_413) 1 8 on page 16- 551 siu_base+0x79e ? siu_base+0x7ff reserved siu_base+0x800 ? siu_base+0x8e9 gpio pin data input register 0 ? 3 (siu_gpdi0_3) ? gpio pin data input register 232 ? 233 (siu_gpdi232_233) 1 8 on page 16- 552 siu_base+0x8ea ? siu_base+0x8ff reserved siu_base+0x900 eqadc trigger imux select register (etisr) (2) 32 on page 16- 553 siu_base+0x904 external interrupt imux select register (eiisr) (3) 32 on page 16- 555 siu_base+0x908 dspi imux select register (disr) (4) 32 on page 16- 558 siu_base+0x90c imux select register 3 (siu_isel3) 32 on page 16- 560 siu_base+0x910 ? siu_base+0x91f reserved siu_base+0x920 imux select register 8 (siu_isel8) 32 on page 16- 566 table 121. siu address map (continued) address use bits per register location system integration unit (siu) RM0029 420/1740 doc id 15177 rev 8 16.6.2 mcu id register 2 (siu_midr2) the mcu id register 2 contains additional configuration information about the device. siu_base+0x924 imux select register 9 (siu_isel9) 32 on page 16- 568 siu_base+0x928 imux select register 10 (siu_isel10) 32 on page 16- 569 siu_base+0x92c ? siu_base+0x97f reserved siu_base+0x980 chip configuration register (siu_ccr) 32 on page 16- 571 siu_base+0x984 external clock control register (siu_eccr) 32 on page 16- 572 siu_base+0x988 compare a high register (siu_carh) 32 on page 16- 573 siu_base+0x98c compare a low register (siu_carl) 32 on page 16- 573 siu_base+0x990 compare b high register (siu_cbrh) 32 on page 16- 574 siu_base+0x994 compare b low register (siu_cbrl) 32 on page 16- 574 siu_base+0x998 reserved siu_base+0x9a0 system clock register (siu_sysdiv) 32 on page 16- 575 siu_base+0x9a4 halt register (siu_hlt) 32 on page 16- 576 siu_base+0x9a8 halt acknowledge register (siu_hltack) 32 on page 16- 579 siu_base+0x9ac ? siu_base+0x9b3 reserved siu_base+0x9b4 core mmu pid control register (siu_empcr0) 32 on page 16- 581 siu_base+0x9b8 ? siu_base+0x9ff reserved 1. gaps exist in this memory s pace where i/o pins are not available in the specified package. 2. the etisr is sometimes referred to as isel0 3. the eiisr is sometimes referred to as isel1 4. the disr is sometimes referred to as isel2 table 121. siu address map (continued) address use bits per register location RM0029 system integration unit (siu) doc id 15177 rev 8 421/1740 figure 144. mcu id register 2 (siu_midr2) siu_base + 0x0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 function s_f flash_size_1 flash_size_2 temp_ range res. max_ freq res. sup ply s_f (1) 1 0 0 0 0 0 0 0 1 1 0 1 1 0 0 8 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 function part_number (ascii character) res. ee res. fr 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 a = 0x41 1. s_f set with metal option table 122. siu_midr2 field description bit name description 0s_f identifies the manufacturer 1: st 1?4 flash_size_1 define major flash memory size (see table 123 for details) 5?8 flash_size_2 define flash memory size, small granularity (see table 124 for details) 19?10 temp_range define maximum operating range 11 ? reserved for future enhancements 12?13 max_freq define maximum device speed 14 ? reserved for future enhancements 15 supply defines if the part is 5 v or 3 v 1: 3 v 0: 5 v 16?23 part_number contain the ascii representation of the character that indicates the product family. 24?26 ? reserved for future enhancements 27 ee indicates if data flash is present 1: data flash present 0: data flash not present 28?30 ? reserved for future enhancements 31 fr indicates if data flexray is present 1: flexray present 0: flexray not present system integration unit (siu) RM0029 422/1740 doc id 15177 rev 8 16.6.3 mcu id register (siu_midr) the mcu id register contains the part number and the package id of the device. table 123. flash memory size flash_size_1 field size 0h 16 kb 1h 32 kb 2h 64 kb 3h 128 kb 4h 256 kb 5h 512 kb 6h 1024 kb 7h 2048 kb ... n2 4+n kb table 124. flash memory size detailed (1) 1. total flash memory size = (flash size 1) + (flash size 2) flash_size_2 field size 0h 0x(flash size 1)/8 1h 1x(flash size 1)/8 2h 2x(flash size 1)/8 ... ... n nx(flash size 1)/8 RM0029 system integration unit (siu) doc id 15177 rev 8 423/1740 figure 145. mcu id register (siu_midr) 16.6.4 reset status register (siu_rsr) the reset status register (siu_rsr) reflects the most recent source, or sources, of reset. this register contains one bit for each reset source, except jtag reset. a bit set to logic one indicates the type of reset that occurred. simultaneous reset requests cause more than one bit to set at the same time. once set, the reset source bits in the siu_rsr remain set until another reset occurs. a software external reset causes the serf bit to be set, but no previously set bits in the siu_rsr will be cleared. the unidirectional mode of reset operation is implemented, all registers named mode 1 are implemented. siu_base + 0x4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r partnum [0?15] (4 digits) w reset0101011001000000 5 6 4 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r csp pkg [0?4] reserved masknum [0?3] - major masknum [0?3] - minor w reset ? (1) ? (2) ???? 0000000000 1. values corresponding to device packaging; see table 125 . 2. values for these bits vary according to the package. see table 125 for details. table 125. siu_midr field description bit name description 0?15 partnum [0?15] 0x5640 16 csp csp configuration: 1:calibration tool package 0: standard qfp package or bga208 package 17?21 pkg [0?4] indicate the package the die is mounted in 10001: 176-pin qfp 10000: 208-ball bga 10100: 324-ball bga 22?23 ? reserved 24?27 major masknum [0?3] mcu major mask number; the current value applies to revision 0 and will be updated for each complete resynthesis 28?31 minor masknum [0?3] mcu minor mask number; the current value applies to revision 0 and will be updated for each mask revision system integration unit (siu) RM0029 424/1740 doc id 15177 rev 8 figure 146. reset status register (siu_rsr) siu_base + 0xc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r porsersllrslcrswdrs0swtrs000000 0ssrsserf w reset (1) 1 0 0 0 0 0 0 000000 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r wkpcfg 0 0 0 0 0 0 00000abrbootcfg [0?1] rgf w reset (1) u (2) 0 0 0 0 0 0 00000u (3) 000 = unimplemented or reserved 1. the reset values for this register are defined for power-on reset only. 2. the reset value of this bit is determined by the value latched on the associated pin at the negation of the last reset. 3. the reset value of this bit is determined by the inverse of the value latched on the associated evto pin. table 126. siu_rsr field description bits name description 0pors power-on reset status 1: a power-on reset has occurred. 0: no power-on reset has occurred. 1ers external reset status 1: an external reset has occurred. 0: no external reset has occurred. 2llrs loss of lock reset status 1: a loss of lock reset has occurred. 0: no loss of lock reset has occurred. 3 lcrs loss of clock reset status 1: a loss of clock reset has occurred due to a loss of the reference or failure of the fmpll. 0: no loss of clock reset has occurred. 4 wdrs watchdog timer/debug reset status 1: a watchdog timer or debug reset has occurred. 0: no watchdog timer or debug reset has occurred. 5 ? reserved 6swtrs software watchdog timer reset status 1: an enabled swt reset has occurred. 0: no enabled swt reset has occurred. RM0029 system integration unit (siu) doc id 15177 rev 8 425/1740 16.6.5 system reset control register (siu_srcr) the system reset control register (siu_srcr) allows software to generate either a software system reset or software external reset. the software system reset causes an internal reset sequence, while the software external reset only causes the external rstout pin to be asserted for the predetermined number of clock cycles (refer to section 4.3.2, rstout ). when written to one, the ser bit automatically clears after the clock count expires. if the value of the ser bit is one and a zero is written to the bit, the bit is cleared and the rstout pin is negated regardless if the clock count has expired. 7?13 ? reserved 14 ssrs software system reset status 1: a software system reset has occurred. 0: no software system reset has occurred. 15 serf software external reset flag 1: a software external reset has occurred. 0: no software external reset has occurred. 16 wkpcfg weak pull configuration pin status 1: wkpcfg pin latched during the last reset was logical one and weak pull up is the default setting. 0: wkpcfg pin latched during the last reset was logical zero and weak pull down is the default setting. 17?27 ? reserved 28 abr auto baud rate 1: auto baud rate enabled. 0: auto baud rate disabled. 29?30 bootcfg[0:1] reset configuration pin status the bootcfg field holds the value of the bootcfg[1] pin that was latched on the last negation of the rstout pin. the bootcfg field is used by the bam program to determine the location of the reset configuration word. see table 10 in section , rchw overview for a translation of the reset configuration half word location from the bootcfg field value. 0b00: boot from internal flash memory (default) 0b01: flexcan / esci boot 0b10: boot from external memory (no arbitration) 0b11: reserved 31 rgf reset glitch flag this bit is set by the mcu when the reset pin is asserted for more than 2 clock cycles, but less than the minimum reset assertion time of 10 consecutive clock cycles to cause a reset. this bit is cleared by the reset controller for a valid assertion of the reset pin or a power-on reset or a write of one to the bit. 1: a glitch was detected on the reset pin. 0: no glitch was detected on the reset pin. table 126. siu_rsr field description (continued) bits name description system integration unit (siu) RM0029 426/1740 doc id 15177 rev 8 figure 147. system reset control register (siu_srcr) 16.6.6 external interrupt status register (siu_eisr) the external interrupt status register is used to record edge triggered events on the irq0 ? irq15 inputs to the siu. it also records the critical interrupts nmi and swt. siu_base + 0xe 0123456789101112131415 r ssrser00000000000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r res.000000000000000 w reset 1 (1) 000000000000000 = unimplemented or reserved 1. this bit in the spc564a74xx, spc564a80xx mcu has no effect as checkstop reset is not supported. table 127. siu_srcr field description field description ssr software system reset writing a one to this bit causes an internal reset and assertion of the rstout pin. the bit is automatically cleared by all reset sources except the software external reset. 1: generate a software system reset. 0: do not generate a software system reset. ser software external reset writing a one to this bit causes a software external reset. the rstout pin is asserted for the predetermined number of clock cycles (refer to section 4.3.2, rstout ), but the mcu is not reset. the bit is automatically cleared when the software external reset completes. 1: generate a software external reset. 0: do not generate a software external reset. RM0029 system integration unit (siu) doc id 15177 rev 8 427/1740 figure 148. external irq status register (siu_eisr) 16.6.7 dma/interrupt request enable register (siu_direr) the dma/interrupt request enable register allows the assertion of a dma or interrupt request if the corresponding flag bit is set in section 16.6.6, external interrupt status register (siu_eisr) . the external interrupt request enable bits enable the interrupt or dma request. there is only one interrupt request from the siu to the interrupt controller. the eire bits allow selection of which external interrupt request flag bits cause assertion of the one interrupt request signal. siu_base + 0x14 0123456789101112131415 r nmi0000000swt0000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eif15 eif14 eif13 eif12 eif11 eif10 eif9 eif8 eif7 eif6 eif5 eif4 eif3 eif2 eif1 eif0 w reset 0000000000000000 = unimplemented or reserved table 128. siu_eisr field description field description nmi non-maskable interrupt flag this bit is set when a nmi interrupt occurs on the nmi input pin. 1: an nmi event has occurred on the nmi input 0: no nmi event has occurred on the nmi input swt software watch dog timer interrupt flag, from platform this bit is set when a swt interrupt occurs on the platform. 1: an swt event has occurred 0: no swt event has occurred eif x external interrupt request flag x this bit is set when an edge triggered event occurs on the corresponding irq x input. 1: an edge triggered event has occurred on the corresponding irq x input 0: no edge triggered event has occurred on the corresponding irq x input system integration unit (siu) RM0029 428/1740 doc id 15177 rev 8 figure 149. dma/interrupt request enable register (siu_direr) 16.6.8 dma/interrupt request select register (siu_dirsr) the dma/interrupt request select register allows selection between a dma or interrupt request for events on the irq[0:3] inputs. siu_base + 0x18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r nmi_sel (1) 0000000 nmi_sel0 (1) 0000000 w reset0 0000000 0 0000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eire15 eire14 eire13 eire12 eire11 eire10 eire9 eire8 eire7 0 eire5 eire4 eire3 eire2 eire1 eire0 w reset0 0000000 0 0000000 = unimplemented or reserved 1. this bit is cleared only by a reset. table 129. siu_direr field description field description nmi_sel non-maskable interrupt / critical interrupt selection x the siu generates two specific sources of interrupt to the core. one of them is defined as the critical interrupt (ivor0 core exception) and the other is defined as the non-maskable interrupt (nmi) (ivor1 core exception). the nmi_sel bit selects which exception will be generated by the external nmi pin. this bit is cleared only by a reset. 1: critical interrupt (ivor0) is enabled 0: nmi (ivor1) is enabled nmi_sel0 non-maskable interrupt / critical interrupt selection x the siu generates two specific sources of interrupt to the core. one of them is defined as the critical interrupt (ivor0 core exception) and the other is defined as the non-maskable interrupt (nmi) (ivor1 core exception). the nmi_sel0 bit selects which exception will be generated by the swt interrupt. this bit is cleared only by a reset. 1: critical interrupt (ivor0) is enabled 0: nmi (ivor1) is enabled eire x external dma/interrupt request enable x this bit enables the assertion of a dma or the interrupt request from the siu to the interrupt controller when an edge triggered event occurs on the irq x inputs. 1: external interrupt request is enabled 0: external interrupt request is disabled RM0029 system integration unit (siu) doc id 15177 rev 8 429/1740 figure 150. dma/interrupt request select register (siu_dirsr) 16.6.9 overrun status register (siu_osr) the overrun status register contains flag bits that record an overrun. figure 151. overrun status register (siu_osr) siu_base + 0x1c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 dirs3 dirs2 dirs1 dirs0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 130. siu_dirsr field description field description dirs x dma/interrupt request select x this bit selects between a dma or interrupt request when an edge triggered event occurs on the corresponding irq x input. 1: dma request is selected (on this device these dma connections do not exist, causing the interrupt to be inhibit) 0: interrupt request is selected siu_base + 0x20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ovf15 ovf14 ovf13 ovf12 ovf11 ovf10 ovf9 ovf8 ovf7 ovf6 ovf5 ovf4 ovf3 ovf2 ovf1 ovf0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved system integration unit (siu) RM0029 430/1740 doc id 15177 rev 8 16.6.10 overrun request enable register (siu_orer) the overrun request enable register contains bits to enable an overrun if the corresponding flag bit is set in the siu_osr. if any overrun request enable bit and the corresponding flag bit is set, the single combined overrun request from the siu to the interrupt controller is asserted. figure 152. overrun request enable register (siu_orer) 16.6.11 irq rising-edge event enable register (siu_ireer) the irq rising-edge event enable register allows rising edge triggered events to be enabled on the corresponding irq x inputs. rising and falling edge events can be enabled by setting the corresponding bits in both the siu_ireer and siu_ifeer. table 131. siu_osr field description field description ovf x overrun flag x this bit is set when an overrun occurs on the corresponding irq x input. 1: an overrun has occurred on the corresponding irq x input 0: no overrun has occurred on the corresponding irq x input siu_base + 0x24 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ore15 ore14 ore13 ore12 ore11 ore10 ore9 ore8 ore7 ore6 ore5 ore4 ore3 ore2 ore1 ore0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 132. siu_orer field description field description ore x overrun request enable x this bit enables the corresponding overrun request when an overrun occurs on the corresponding irq x input. 1: overrun request is enabled 0: overrun request is disabled RM0029 system integration unit (siu) doc id 15177 rev 8 431/1740 figure 153. irq rising-edge event enable register (siu_ireer) 16.6.12 external irq falling-edge event enable register (siu_ifeer) the external irq falling-edge event enable register allows falling edge triggered events to be enabled on the corresponding irq x inputs. rising and falling edge events can be enabled by setting the corresponding bits in both the siu_ireer and siu_ifeer. siu_base + 0x28 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r nmire (1) 0 0 0 0 0 0 0 nmire0 (1) 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r iree15 iree14 iree13 iree12 iree11 iree10 iree9 iree8 iree7 iree6 iree5 iree4 iree3 iree2 iree1 iree0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. this bit is cleared only by a reset. table 133. siu_ireer field description field description nmire nmi rising-edge event enable (nmi input) this write once bit enables rising-edge triggered events on the nmi input. this bit is cleared only by a reset. 1: rising edge event is enabled 0: rising edge event is disabled nmire0 nmi rising-edge event enable (swt) this write once bit enables rising-edge triggered events by swt. this bit is cleared only by a reset. 1: rising edge event is enabled 0: rising edge event is disabled iree x irq rising-edge event enable x this bit enables rising-edge triggered events on the corresponding irq x input. 1: rising edge event is enabled 0: rising edge event is disabled system integration unit (siu) RM0029 432/1740 doc id 15177 rev 8 figure 154. external irq falling-edge event enable register (siu_ifeer) 16.6.13 external irq digital filter register (siu_idfr) the external irq digital filter register specifies the amount of digital filtering on the irq0 ? irq15 inputs. the digital filter length field specifies the number of system clocks that define the period of the digital filter. siu_base + 0x2c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r nmife (1) 0 0 0 0 0 0 0 nmife0 (1) 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ifee15 ifee14 ifee13 ifee12 ifee11 ifee10 ifee9 ifee8 ifee7 ifee6 ifee5 ifee4 ifee3 ifee2 ifee1 ifee0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. this bit is cleared only by a reset. table 134. siu_ifeer field description field description nmife nmi falling-edge event enable (nmi input) this write once bit enables falling-edge triggered events on the nmi input. this bit is cleared only by a reset. 1: falling edge event is enabled 0: falling edge event is disabled nmife0 nmi falling-edge event enable (swt) this write once bit enables falling-edge triggered events by swt. this bit is cleared only by a reset. 1: falling edge event is enabled 0: falling edge event is disabled ifee x irq falling-edge event enable x this bit enables falling-edge triggered events on the corresponding irq x input. 1: falling edge event is enabled 0: falling edge event is disabled RM0029 system integration unit (siu) doc id 15177 rev 8 433/1740 figure 155. irq digital filter register (siu_idfr) 16.6.14 irq filtered input register (siu_ifir) the siu_ifir is a read-only register used to capture the filtered values of the irq0?31 pins. this feature is enabled with a parameter at the top level of the module. the msb positions of the register correspond to nmi pins and the number of nmi pins are defined by a parameter. the lsb positions of the register corresponds to the irq pins and the number of irq pins is defined by a parameter. siu_base + 0x30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 dfl[0?3] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 135. siu_idfr field description field description dfl[0?3] digital filter length this field defines the digital filter period on the irq x inputs according to equation 1 : equation 1 for a 100 mhz system clock, this gives a range of 20 ns to 328 s. the minimum time of two clocks accounts for synchronization of the irq input pins with the system clock. using the same calculation, for a 150 mhz system clock, this gives a range of 13.3 ns to 218 s. filter period s ( ystemclockperiod 2 dfl ) 1s ( ystemclockperiod ) + = system integration unit (siu) RM0029 434/1740 doc id 15177 rev 8 figure 156. irq filtered input register (siu_ifir) 16.6.15 pad configuration registers (siu_pcr) the pad configuration registers (pcrs) select function, i/o direction and some electrical characteristics for configurable device pins. not all device pins are configurable. pcrs are 16-bit registers but may be read or written as 32-bit values aligned on 32-bit address boundaries. they are based on a common set of fields, but only the pertinent fields appear in each register. the information in the following sections pertains to the bits and fields that are active for a given pin or group of pins, and the reset state of the register. the reset state given for each pcr is the state prior to execution of the bam program. the bam program may change certain pcrs based on the reset configuration. see chapter 21: boot assist module (bam) for more details. the device is available in the packages listed in chapter 1: introduction . some of the i/o functions controlled by the siu pcrs are not available in the smaller packages. the port enable logic for these pcrs is the same for pcrs that control i/o functions that are available in all packages. for the smaller packages where some of the i/o functions are not available, the pad drivers are disabled in the pad interface logic. the user should take care not to select the unavailable functions via the pa field. see section 3.1, signal properties , for a definition of which i/o functions are available in each package. ta ble 13 6 lists and describes the fields contained in the pcrs. not all fields appear in each pcr but each field has an identical function in each register where it resides. siu_base + 0x2c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r nmife (1) 0 0 0 0 0 0 0 nmife0 (1) 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ifee15 ifee14 ifee13 ifee12 ifee11 ifee10 ifee9 ifee8 ifee7 ifee6 ifee5 ifee4 ifee3 ifee2 ifee1 ifee0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. this bit is cleared only by a reset. RM0029 system integration unit (siu) doc id 15177 rev 8 435/1740 table 136. siu_pcr field description field description ? reserved fields are indicated by shading in the register maps. pa pin assignment selects the function of a multiplexed pad. obe (1),(2) output buffer enable enables the pad as an output and drives the output buffer enable signal. 0 disable output buffer for the pad. 1 enable output buffer for the pad is enabled. ibe (1),(2) input buffer enable enables the pad as an input and drives the input buffer enable signal. 0 disable input buffer for the pad. 1 enable input buffer for the pad is enabled. for all pcrs where gpio function is available on the pin, if the pin is configured as an output and the ibe bit is set, the actual value of the pin will be reflected in the corresponding gpdi x _ x register. negating the ibe bit when the pin is configured as an output will reduce noise and power consumption. dsc (3) drive strength control controls the pad drive strength. drive strength control pertains to pins with the fast i/o pad type. 00 10 pf drive strength 01 20 pf drive strength 10 30 pf drive strength 11 50 pf drive strength ode (3) open drain output enable controls output driver configuration for the pads. either open drain or push/pull driver configurations can be selected. this feature applies to output pins only. 0 disable open drain for the pad (push/pull driver enabled). 1 enable open drain for the pad. pa value (1) 1. depending on the register, the pa field size can vary in length. for pa fields having fewer than four bits, remove the appropriate number of leading ze roes from these values. pin function 0b0001 p primary function 0b0010 a1 alternate function 1 0b0100 a2 alternate function 2 0b1000 a3 alternate function 3 0b0000 g gpio system integration unit (siu) RM0029 436/1740 doc id 15177 rev 8 the following sections describe pcr functions using maps that show the fields contained in each register. refer to table 136 for the details of each field. figure 157 shows a sample pcr map. please note the following: the register bit numbering order follows the power architecture standard of the most significant bit being bit 0. field bit ranges are the opposite?the least significant bit is referred to as bit 0. bit 0 is an example of a reserved field. it is read-only and always returns a value of 0. hys (4) input hysteresis controls whether hysteresis is enabled for the pad. 0 disable hysteresis for the pad. 1 enable hysteresis for the pad. src (3) slew rate control controls slew rate for the pad. slew rate control pertains to pins with slow or medium i/o pad types, and the output signals are driven according to the value of this field. actual slew rate depends on the pad type and load. refer to the electrical specifications for this information. 00 minimum slew rate 01 medium slew rate 10 invalid value 11 maximum slew rate wpe (5) weak pullup/down enable controls whether the weak pullup/down devices are enabled/disabled for the pad. pullup/down devices are enabled by default. 0 disable weak pull device for the pad. 1 enable weak pull device for the pad. wps (5) weak pullup/down select controls whether weak pullup or weak pulldown devices are used for the pad when weak pullup/down devices are enabled. the wkpcfg pin determines whether pullup or pulldown devices are enabled during reset. the wps bit determines whether weak pullup or pulldown devices are used after reset, or for pads in which the wkpcfg pin does not determine the reset weak pullup/down state. 0 pulldown is enabled for the pad. 1 pullup is enabled for the pad. 1. in cases where an i/o function is either input-only or output-only the ibe and obe bits do not need to be set to enable pin i/o. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. 3. if a pin is configured as an input, the ode, src, and dsc bits do not apply. 4. if a pin is configured as an output, the hys bit does not apply. 5. when a pin is configured as an output, the weak internal pull up/down is disabled regardless of the wpe or wps settings in the pcr. table 136. siu_pcr field description (continued) field description RM0029 system integration unit (siu) doc id 15177 rev 8 437/1740 figure 157. sample pcr map f siu_base+0x40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) 1. obe bit is significant in gpio ibe (2) 2. ibe bit is significant in gpio dsc ode hys 0 0 wpe wps w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary cs[0] ebi chip select o 0b01 alt1 addr[8] ebi address bus i/o 0b10 gpio gpio[0] ebi gpio i/o 0b00 read values write values reset values register address footnote bit number field name register bit range = [4:5] field bit range = [1:0] ?signal? refers to position in muxing order?primary, alt1, alt2, alt3 or gpio. signal i/o direction. i - input o - output i/o - input or output pa field value required to select a signal for the pin controlled by this pcr. system integration unit (siu) RM0029 438/1740 doc id 15177 rev 8 pad configuration register 0 (siu_pcr0) figure 158. pad configuration register (siu_pcr0) pad configuration register 1 (siu_pcr1) figure 159. pad configuration register (siu_pcr1) siu_base+0x40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as cs[0] or addr[8] the obe bit has no effect. when configured as gpo, set the obe bit to one. 2. when configured as cs[0] or gpo, set the ibe bit to one to reflect the pin state in the gpdi register. when configured as gpi, set the ibe bit to one. 3. when configured as cs[0] or addr[8], set the ode bit to zero. 4. see the ebi section for weak pull up settings when configured as cs[0]. table 137. siu_pcr0 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa primary cs[0] ebi chip select o 0b01 alt1 addr[8] ebi address bus i/o 0b10 gpio gpio[0] ebi gpio i/o 0b00 siu_base+0x42 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as cs[1] or addr[9] the obe bit has no effect. when configured as gpo, set the obe bit to one. 2. when configured as cs[1] or gpo, set the ibe bit to one to reflect the pin state in the gpdi register. when configured as gpi, set the ibe bit to one. 3. when configured as cs[1] or addr[9], set the ode bit to zero. 4. see the ebi section for weak pull up settings when configured as cs[1]. RM0029 system integration unit (siu) doc id 15177 rev 8 439/1740 pad configuration register 2 (siu_pcr2) figure 160. pad configuration register (siu_pcr2) table 138. siu_pcr1 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa primary cs[1] ebi chip select o 0b01 alt1 addr[9] ebi address bus i/o 0b10 gpio gpio[1] siu gpio i/o 0b00 siu_base+0x44 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as cs[2] or addr[10] the obe bit has no effect. when configured as gpo, set the obe bit to one. 2. when configured as cs[2] or gpo, set the ibe bit to one to reflect the pin state in the gpdi register. when configured as gpi, set the ibe bit to one. 3. when configured as cs[2] or addr[10], set the ode bit to zero. 4. see the ebi section for weak pull up settings when configured as cs[0]. table 139. siu_pcr2 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa primary cs[2] ebi chip select o 0b0001 alt1 addr[10] ebi address bus i/o 0b0010 alt2 we[2]/be[2] ebi write/byte enable o 0b0100 alt3 cal_we[2]/be[2] cal bus write/byte enable o 0b1000 gpio gpio[2] siu gpio i/o 0b0000 system integration unit (siu) RM0029 440/1740 doc id 15177 rev 8 pad configuration register 3 (siu_pcr3) figure 161. pad configuration register (siu_pcr3) pad configuration register 8 (siu_pcr8) figure 162. pad configuration register (siu_pcr8) siu_base+0x46 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps 4 w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as cs[3] or addr[11] the obe bit has no effect. when configured as gpo, set the obe bit to one. 2. when configured as cs[3] or gpo, set the ibe bit to one to reflect the pin state in the gpdi register. when configured as gpi, set the ibe bit to one. 3. when configured as cs[3] or addr[11], set the ode bit to zero. 4. see the ebi section for weak pull up settings when configured as cs[0]. table 140. siu_pcr3 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa primary cs[3] ebi chip select o 0b0001 alt1 addr[11] ebi address bus i/o 0b0010 alt2 we[3]/be[3] ebi write/byte enable o 0b0100 alt3 cal_we[3]/be[3] cal bus write/byte enable o 0b1000 gpio gpio[3] siu gpio i/o 0b0000 siu_base+0x50 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[12] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[12] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumpt ion. when configured as gpi, the ibe bit should be set to one. 3. when configured as addr[12], the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as addr[12] RM0029 system integration unit (siu) doc id 15177 rev 8 441/1740 pad configuration register 9 (siu_pcr9) figure 163. pad configuration register (siu_pcr9) pad configuration register 10 (siu_pcr10) table 141. siu_pcr8 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary addr[12] ebi address bus i/o 0b1 gpio gpio[8] siu gpio i/o 0b0 siu_base+0x52 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[13] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[13], we [2] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as addr[13], the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as addr[13] table 142. siu_pcr9 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary addr[13] ebi address bus i/o 0b001 alt2 we [2] ebi write enable o 0b100 gpio gpio[9] siu gpio i/o 0b000 siu_base+0x54 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[14] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. system integration unit (siu) RM0029 442/1740 doc id 15177 rev 8 figure 164. pad configuration register (siu_pcr10) pad configuration register 11 (siu_pcr11) figure 165. pad configuration register (siu_pcr11) 2. when configured as addr[14], we [2] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as addr[14], the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as addr[14] table 143. siu_pcr10 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary addr[14] ebi address bus i/o 0b001 alt2 we [3] ebi write enable o 0b100 gpio gpio[10] siu gpio i/o 0b000 siu_base+0x56 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[15] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[15] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumpt ion. when configured as gpi, the ibe bit should be set to one. 3. when configured as addr[15], the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as addr[15] table 144. siu_pcr11 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary addr[15] ebi address bus i/o 0b1 gpio gpio[11] siu gpio i/o 0b0 RM0029 system integration unit (siu) doc id 15177 rev 8 443/1740 pad configuration register 12 (siu_pcr12) figure 166. pad configuration register (siu_pcr12) pad configuration register 13 (siu_pcr13) figure 167. pad configuration register (siu_pcr13) siu_base+0x58 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[16] or data[16] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[16], fr_a_tx or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as addr[16], the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as addr[16] table 145. siu_pcr12 pa values signal name module description i/o (1),(2) pa value primary addr[16] ebi address bus i/o 0b001 alt1 fr_a_tx ebi flexray transmit o 0b010 alt2 data[16] ebi data bus i/o 0b100 gpio gpio[12] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x5a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[17] or data[17], the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[17], fr_a_tx_en or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as addr[17], the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as addr[17] system integration unit (siu) RM0029 444/1740 doc id 15177 rev 8 pad configuration register 14 (siu_pcr14) figure 168. pad configuration register (siu_pcr14) table 146. siu_pcr13 pa values signal name module description i/o (1),(2) pa value primary addr[17] ebi address bus i/o 0b001 alt1 fr_a_tx_en ebi flexray transmit enable o 0b010 alt2 data[17] ebi data bus i/o 0b100 gpio gpio[13] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x5c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[18], fr_a_rx or data[18] the o be bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[18] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumpt ion. when configured as gpi, the ibe bit should be set to one. 3. when configured as addr[18], the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as addr[18] table 147. siu_pcr14 pa values signal name module description i/o (1),(2) pa value primary addr[18] ebi address bus i/o 0b001 alt1 fr_a_rx flexray flexray receive i 0b010 alt2 data[18] ebi data bus i/o 0b100 gpio gpio[14] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 445/1740 pad configuration register 15 (siu_pcr15) figure 169. pad configuration register (siu_pcr15) pad configuration register 16 (siu_pcr16) figure 170. pad configuration register (siu_pcr16) siu_base+0x5e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[19] or data[19] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[19], fr_b_tx or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as addr[19], the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as addr[19] table 148. siu_pcr15 pa values signal name module description i/o (1),(2) pa value primary addr[19] ebi address bus i/o 0b001 alt1 fr_b_tx flexray flexray transmit o 0b010 alt2 data[19] ebi data bus i/o 0b100 gpio gpio[15] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x60 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[20] or data[20] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[20], data[20], fr_b_tx_en or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. w hen configured as gpi, the ibe bit should be set to one. 3. when configured as addr[20] or data[20], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as addr[20] or data[20]. system integration unit (siu) RM0029 446/1740 doc id 15177 rev 8 pad configuration register 17 (siu_pcr17) figure 171. pad configuration register (siu_pcr17) table 149. siu_pcr16 pa values signal name module description i/o (1),(2) pa value primary addr[20] ebi address bus i/o 0b001 alt1 fr_b_tx_en flexray flexray transmit enable o 0b010 alt2 data[20] ebi data bus i/o 0b100 gpio gpio[16] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x62 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[21], fr_b_rx or data[21] the o be bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[21], data[21] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as addr[21] or data[21], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as addr[21] or data[21]. table 150. siu_pcr17 pa values signal name module description i/o (1),(2) pa value primary addr[21] ebi address bus i/o 0b001 alt1 fr_b_rx flexray flexray receive i 0b010 alt2 data[21] ebi data bus i/o 0b100 gpio gpio[17] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 447/1740 pad configuration register 18 (siu_pcr18) figure 172. pad configuration register (siu_pcr18) pad configuration register 19 (siu_pcr19) figure 173. pad configuration register (siu_pcr19) siu_base+0x64 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[22] or data[22] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[22] data[22] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as addr[22] or data[22], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as addr[22] or data[22]. table 151. siu_pcr18 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary addr[22] ebi address bus i/o 0b001 alt2 data[22] ebi data bus i/o 0b100 gpio gpio[18] siu gpio i/o 0b000 siu_base+0x66 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[23] or data[23] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[23], data[23] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as addr[23] or data[23], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as addr[23] or data[23]. system integration unit (siu) RM0029 448/1740 doc id 15177 rev 8 pad configuration register 20 (siu_pcr20) figure 174. pad configuration register (siu_pcr20) pad configuration register 21 (siu_pcr21) table 152. siu_pcr19 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary addr[23] ebi address bus i/o 0b001 alt2 data[23] ebi data bus i/o 0b100 gpio gpio[19] siu gpio i/o 0b000 siu_base+0x68 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[24] or data[24] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[24], data[24] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as addr[24] or data[24], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as addr[24] or data[24]. table 153. siu_pcr20 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary addr[24] ebi address bus i/o 0b001 alt2 data[24] ebi data bus i/o 0b100 gpio gpio[20] siu gpio i/o 0b000 RM0029 system integration unit (siu) doc id 15177 rev 8 449/1740 figure 175. pad configuration register (siu_pcr21) pad configuration register 22 (siu_pcr22) figure 176. pad configuration register (siu_pcr22) siu_base+0x6a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[25] or data[25] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[25], data[25] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as addr[25] data[25], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as addr[25] or data[25]. table 154. siu_pcr21 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary addr[25] ebi address bus i/o 0b001 alt2 data[25] ebi data bus i/o 0b100 gpio gpio[21] siu gpio i/o 0b000 siu_base+0x6c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[26] or data[26] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[26], data[26] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as addr[26] or data[26], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as addr[26] or data[26]. system integration unit (siu) RM0029 450/1740 doc id 15177 rev 8 pad configuration register 23 (siu_pcr23) figure 177. pad configuration register (siu_pcr23) pad configuration register 24 (siu_pcr24) table 155. siu_pcr22 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary addr[26] ebi address bus i/o 0b001 alt2 data[26] ebi data bus i/o 0b100 gpio gpio[22] siu gpio i/o 0b000 siu_base+0x6e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[27] or data[27] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[27], data[27] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as addr[27] or data[27], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as addr[27] or data[27]. table 156. siu_pcr23 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary addr[27] ebi address bus i/o 0b001 alt2 data[27] ebi data bus i/o 0b100 gpio gpio[23] siu gpio i/o 0b000 RM0029 system integration unit (siu) doc id 15177 rev 8 451/1740 figure 178. pad configuration register (siu_pcr24) pad configuration register 25 (siu_pcr25) figure 179. pad configuration register (siu_pcr25) siu_base+0x70 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[28] or data[28] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[28], data[28] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as addr[28] or data[28], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as addr[28] or data[28]. table 157. siu_pcr24 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary addr[28] ebi address bus i/o 0b001 alt2 data[28] ebi data bus i/o 0b100 gpio gpio[24] siu gpio i/o 0b000 siu_base+0x72 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[29] or data[29] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[29], data[29] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as addr[29] or data[29], the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as addr[29] system integration unit (siu) RM0029 452/1740 doc id 15177 rev 8 pad configuration register 26 (siu_pcr26) figure 180. pad configuration register (siu_pcr26) table 158. siu_pcr25 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary addr[29] ebi address bus i/o 0b001 alt2 data[29] ebi data bus i/o 0b100 gpio gpio[25] siu gpio i/o 0b000 siu_base+0x74 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[30] or data[30], the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[30], addr[6], data[30] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as addr[30], addr[6] or data[30], the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as addr[30], addr[6] or data[30]. table 159. siu_pcr26 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary addr[30] ebi address bus i/o 0b001 alt1 addr[6] ebi address bus o 0b010 alt2 data[30] ebi data bus i/o 0b100 gpio gpio[26] siu gpio i/o 0b000 RM0029 system integration unit (siu) doc id 15177 rev 8 453/1740 pad configuration register 27 (siu_pcr27) figure 181. pad configuration register (siu_pcr27) pad configuration register 28 (siu_pcr28) figure 182. pad configuration register (siu_pcr28) siu_base+0x76 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode (3) hys src wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as addr[31] or data[31] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as addr[31], addr[7], data[31] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as addr[31], addr[7] or data[31], the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as addr[31], addr[7] or data[31]. table 160. siu_pcr27 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary addr[31] ebi address bus i/o 0b001 alt1 addr[7] ebi address bus o 0b010 alt2 data[31] ebi data bus i/o 0b100 gpio gpio[27] siu gpio i/o 0b000 siu_base+0x78 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[0] or addr[16] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[0], addr[16] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as data[0] or addr[16], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[0] or addr[16]. system integration unit (siu) RM0029 454/1740 doc id 15177 rev 8 pad configuration register 29 (siu_pcr29) figure 183. pad configuration register (siu_pcr29) pad configuration register 30 (siu_pcr30) table 161. siu_pcr28 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[0] ebi data bus i/o 0b01 alt1 addr[16] ebi address bus i/o 0b10 gpio gpio[28] siu gpio i/o 0b00 siu_base+0x7a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[1] or addr[17] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[1], addr[17] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as data[1] or addr[17], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[1] or addr[17]. table 162. siu_pcr29 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[1] ebi data bus i/o 0b01 alt1 addr[17] ebi address bus i/o 0b10 gpio gpio[29] siu gpio i/o 0b00 RM0029 system integration unit (siu) doc id 15177 rev 8 455/1740 figure 184. pad configuration register (siu_pcr30) pad configuration register 31 (siu_pcr31) figure 185. pad configuration register (siu_pcr31) siu_base+0x7c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[2] or addr[18] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[2], addr[18] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as data[2] or addr[18], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[2] or addr[18]. table 163. siu_pcr30 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[2] ebi data bus i/o 0b01 alt1 addr[18] ebi address bus i/o 0b10 gpio gpio[30] siu gpio i/o 0b00 siu_base+0x7e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[3] or addr[19] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[3], addr[19] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as data[3] or addr[19], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[3] or addr[19]. system integration unit (siu) RM0029 456/1740 doc id 15177 rev 8 pad configuration register 32 (siu_pcr32) figure 186. pad configuration register (siu_pcr32) pad configuration register 33 (siu_pcr33) table 164. siu_pcr31 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[3] ebi data bus i/o 0b01 alt1 addr[19] ebi address bus i/o 0b10 gpio gpio[31] siu gpio i/o 0b00 siu_base+0x80 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[4] or addr[20] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[4], addr[20] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as data[4] or addr[20], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[4] or addr[20]. table 165. siu_pcr32 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[4] ebi data bus i/o 0b01 alt1 addr[20] ebi address bus i/o 0b10 gpio gpio[32] siu gpio i/o 0b00 RM0029 system integration unit (siu) doc id 15177 rev 8 457/1740 figure 187. pad configuration register (siu_pcr33) pad configuration register 34 (siu_pcr34) figure 188. pad configuration register (siu_pcr34) siu_base+0x82 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[5] or addr[21] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[5], addr[21] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as data[5] or addr[21], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[5] or addr[21]. table 166. siu_pcr33 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[5] ebi data bus i/o 0b01 alt1 addr[21] ebi address bus i/o 0b10 gpio gpio[33] siu gpio i/o 0b00 siu_base+0x84 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[6] or addr[22] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[6], addr[22] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as data[6] or addr[22], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[6] or addr[22]. system integration unit (siu) RM0029 458/1740 doc id 15177 rev 8 pad configuration register 35 (siu_pcr35) figure 189. pad configuration register (siu_pcr35) pad configuration register 36 (siu_pcr36) table 167. siu_pcr34 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[6] ebi data bus i/o 0b01 alt1 addr[22] ebi address bus i/o 0b10 gpio gpio[34] siu gpio i/o 0b00 siu_base+0x86 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[7] or addr[23] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[7], addr[23] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as data[7] or addr[23], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[7] or addr[23]. table 168. siu_pcr35 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[7] ebi data bus i/o 0b01 alt1 addr[23] ebi address bus i/o 0b10 gpio gpio[35] siu gpio i/o 0b00 RM0029 system integration unit (siu) doc id 15177 rev 8 459/1740 figure 190. pad configuration register (siu_pcr36) pad configuration register 37 (siu_pcr37) figure 191. pad configuration register (siu_pcr37) siu_base+0x88 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[8] or addr[24] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[8], addr[24] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as data[8] or addr[24], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[8] or addr[24]. table 169. siu_pcr36 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[8] ebi data bus i/o 0b01 alt1 addr[24] ebi address bus i/o 0b10 gpio gpio[36] siu gpio i/o 0b00 siu_base+0x8a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[9] or addr[25] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[9], addr[25] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as data[9] or addr[25], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[9] or addr[25]. system integration unit (siu) RM0029 460/1740 doc id 15177 rev 8 pad configuration register 38 (siu_pcr38) figure 192. pad configuration register (siu_pcr38) pad configuration register 39 (siu_pcr39) table 170. siu_pcr37 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[9] ebi data bus i/o 0b01 alt1 addr[25] ebi address bus i/o 0b10 gpio gpio[37] siu gpio i/o 0b00 siu_base+0x8c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[10] or addr[26] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[10], addr[26] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as data[10] or addr[26], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[10] or addr[26]. table 171. siu_pcr38 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[10] ebi data bus i/o 0b01 alt1 addr[26] ebi address bus i/o 0b10 gpio gpio[38] siu gpio i/o 0b00 RM0029 system integration unit (siu) doc id 15177 rev 8 461/1740 figure 193. pad configuration register (siu_pcr39) pad configuration register 40 (siu_pcr40) figure 194. pad configuration register (siu_pcr40) siu_base+0x8e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[11] or addr[27] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[11], addr[27] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as data[11] or addr[27], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[11] or addr[27]. table 172. siu_pcr39 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[11] ebi data bus i/o 0b01 alt1 addr[27] ebi address bus i/o 0b10 gpio gpio[39] siu gpio i/o 0b00 siu_base+0x90 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[12] or addr[28] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[12], addr[28] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as data[12] or addr[28], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[12] or addr[28]. system integration unit (siu) RM0029 462/1740 doc id 15177 rev 8 pad configuration register 41 (siu_pcr41) figure 195. pad configuration register (siu_pcr41) pad configuration register 42 (siu_pcr42) table 173. siu_pcr40 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[12] ebi data bus i/o 0b01 alt1 addr[28] ebi address bus i/o 0b10 gpio gpio[40] siu gpio i/o 0b00 siu_base+0x92 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[13] or addr[29] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[13], addr[29] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as data[13] or addr[29], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[13] or addr[29]. table 174. siu_pcr41 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[13] ebi data bus i/o 0b01 alt1 addr[29] ebi address bus i/o 0b10 gpio gpio[41] siu gpio i/o 0b00 RM0029 system integration unit (siu) doc id 15177 rev 8 463/1740 figure 196. pad configuration register (siu_pcr42) pad configuration register 43 (siu_pcr43) figure 197. pad configuration register (siu_pcr43) siu_base+0x94 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[14] or addr[30] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[14], addr[30] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as data[14] or addr[30], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[14] or addr[30]. table 175. siu_pcr42 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[14] ebi data bus i/o 0b01 alt1 addr[30] ebi address bus i/o 0b10 gpio gpio[42] siu gpio i/o 0b00 siu_base+0x96 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as data[15] or addr[31] the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as data[15], addr[31] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. 3. when configured as data[15] or addr[31], the ode bit should be set to zero. 4. see the ebi section for weak pull up setti ngs when configured as data[15] or addr[31]. system integration unit (siu) RM0029 464/1740 doc id 15177 rev 8 pad configuration register 62 (siu_pcr62) figure 198. pad configuration register (siu_pcr62) pad configuration register 63 (siu_pcr63) table 176. siu_pcr43 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary data[15] ebi data bus i/o 0b01 alt1 addr[31] ebi address bus i/o 0b10 gpio gpio[43] siu gpio i/o 0b00 siu_base+0xbc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as rd_wr , the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as rd_wr or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumpt ion. when configured as gpi, the ibe bit should be set to one. 3. when configured as rd_wr , the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as rd_wr . table 177. siu_pcr62 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary rd_wr ebi read/write i/o 0b1 gpio gpio[62] siu gpio i/o 0b0 siu_base+0xbe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps 4 w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. RM0029 system integration unit (siu) doc id 15177 rev 8 465/1740 figure 199. pad configuration register (siu_pcr63) pad configuration register 64 (siu_pcr 64) figure 200. pad configuration register (siu_pcr64) 2. when configured as bdip or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as bdip , the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as bdip . table 178. siu_pcr63pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary bdip ebi burst data in progress o0b1 gpio gpio[63] siu gpio i/o 0b0 siu_base+0xc0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as we [0]/be [0] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumpt ion. when configured as gpi, the ibe bit should be set to one. 3. when configured as we [0]/be [0], the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as we [0]/be [0]. table 179. siu_pcr64 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary we [0]/be [0] ebi write enable / byte enable o0b1 gpio gpio[64] siu gpio i/o 0b0 system integration unit (siu) RM0029 466/1740 doc id 15177 rev 8 pad configuration register 65 (siu_pcr 65) figure 201. pad configuration register (siu_pcr65) pad configuration register 68 (siu_pcr68) figure 202. pad configuration register (siu_pcr68) siu_base+0xc2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as we [1]/be [1] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumpt ion. when configured as gpi, the ibe bit should be set to one. 3. when configured as we [1]/be [1], the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as we [1]/be [1]. table 180. siu_pcr65 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary we [1]/be [1] ebi write enable / byte enable o0b1 gpio gpio[65] siu gpio i/o 0b0 siu_base+0xc8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as oe or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as oe , the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as oe . RM0029 system integration unit (siu) doc id 15177 rev 8 467/1740 pad configuration register 69 (siu_pcr69) figure 203. pad configuration register (siu_pcr69) pad configuration register 70 (siu_pcr70) table 181. siu_pcr68 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary oe ebi output enable o 0b1 gpio gpio[68] siu gpio i/o 0b0 siu_base+0xca 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as ts , the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as ts or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as ts , the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as ts . table 182. siu_pcr69 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary ts ebi transfer start i/o 0b01 alt1 ale ebi address latch enable o 0b10 gpio gpio[69] siu gpio i/o 0b00 siu_base+0xcc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0pa obe (1) ibe (2) dsc ode (3) hys 0 0 wpe (4) wps (4) w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as ta , the obe bit has no effect. when configured as gpo, the obe bit should be set to one. system integration unit (siu) RM0029 468/1740 doc id 15177 rev 8 figure 204. pad configuration register (siu_pcr70) pad configuration registers 75?82 (siu_pcr75?siu_pcr82) the siu_pcr75?siu_pcr82 registers control the pin function, direction, and static electrical attributes of the mdo[4:11]_gpio[75:82] pins. gpio is the default function at reset for these pins. note: the full port mode (fpm) and nexcfg bits in the nexus port controller (npc) port configuration register control whether these pins function as mdo[4:11] or gpio[75:82]. when the fpm and nexcfg bits are set, the npc enables the mdo port enable, and disables gpio. when the fpm or nexcfg bit is cleared, the npc disables the mdo port enable, and enables gpio. pad configuration register 75 (siu_pcr75) figure 205. pad configuration register (siu_pcr75) 2. when configured as ta , or gpio, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as ta and external master operation is enabled, the ode bit should be set to zero. 4. see the ebi section for weak pull up settings when configured as ta . table 183. siu_pcr70 pa values signal name module description i/o (1),(2) 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. set ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically , such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. pa value primary ta ebi transfer acknowledge i/o 0b001 alt1 ts ebi transfer start o 0b010 gpio gpio[70] siu gpio i/o 0b000 siu_base+0xd6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe 1 0 0 ode (2) hys (3) src wpe (4) wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. this bit applies only to gpio operation. 2. the ode bit should be set to zero for mdo operation. 3. the hys bit has no effect on mdo operation. 4. the wpe bit should be set to zero for mdo operation. RM0029 system integration unit (siu) doc id 15177 rev 8 469/1740 pad configuration register 76 (siu_pcr76) figure 206. pad configuration register (siu_pcr76) table 184. siu_pcr75 pa values signal name module description i/o (1),(2) pa value primary mdo[4] nexus message data out o 0b01 alt1 etpu_a[2] etpu etpu channel o 0b10 gpio gpio[75] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0xd8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe 1 0 0 ode (2) hys (3) src wpe (4) wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. this bit applies only to gpio operation. 2. the ode bit should be set to zero for mdo operation. 3. the hys bit has no effect on mdo operation. 4. the wpe bit should be set to zero for mdo operation. table 185. siu_pcr76 pa values signal name module description i/o (1),(2) pa value primary mdo[5] nexus message data out o 0b01 alt1 etpu_a[4] etpu etpu channel o 0b10 gpio gpio[76] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. system integration unit (siu) RM0029 470/1740 doc id 15177 rev 8 pad configuration register 77 (siu_pcr77) figure 207. pad configuration register (siu_pcr77) pad configuration register 78 (siu_pcr78) figure 208. pad configuration register (siu_pcr78) siu_base+0xda 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe 1 0 0 ode (2) hys (3) src wpe (4) wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. this bit applies only to gpio operation. 2. the ode bit should be set to zero for mdo operation. 3. the hys bit has no effect on mdo operation. 4. the wpe bit should be set to zero for mdo operation. table 186. siu_pcr77 pa values signal name module description i/o (1),(2) pa value primary mdo[6] nexus message data out o 0b01 alt1 etpu_a[13] etpu etpu channel o 0b10 gpio gpio[77] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0xdc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe 1 0 0 ode (2) hys (3) src wpe (4) wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. this bit applies only to gpio operation. 2. the ode bit should be set to zero for mdo operation. 3. the hys bit has no effect on mdo operation. 4. the wpe bit should be set to zero for mdo operation. RM0029 system integration unit (siu) doc id 15177 rev 8 471/1740 pad configuration register 79 (siu_pcr79) figure 209. pad configuration register (siu_pcr79) table 187. siu_pcr78 pa values signal name module description i/o (1),(2) pa value primary mdo[7] nexus message data out o 0b01 alt1 etpu_a[19] etpu etpu channel o 0b10 gpio gpio[78] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0xde 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe 1 0 0 ode (2) hys (3) src wpe (4) wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. this bit applies only to gpio operation. 2. the ode bit should be set to zero for mdo operation. 3. the hys bit has no effect on mdo operation. 4. the wpe bit should be set to zero for mdo operation. table 188. siu_pcr79 pa values signal name module description i/o (1),(2) pa value primary mdo[8] nexus message data out o 0b01 alt1 etpu_a[21] etpu etpu channel o 0b10 gpio gpio[79] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. system integration unit (siu) RM0029 472/1740 doc id 15177 rev 8 pad configuration register 80 (siu_pcr80) figure 210. pad configuration register (siu_pcr80) pad configuration register 81 (siu_pcr81) figure 211. pad configuration register (siu_pcr81) siu_base+0xe0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe 1 0 0 ode (2) hys (3) src wpe (4) wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. this bit applies only to gpio operation. 2. the ode bit should be set to zero for mdo operation. 3. the hys bit has no effect on mdo operation. 4. the wpe bit should be set to zero for mdo operation. table 189. siu_pcr80 pa values signal name module description i/o (1),(2) pa value primary mdo[9] nexus message data out o 0b01 alt1 etpu_a[25] etpu etpu channel o 0b10 gpio gpio[80] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0xe2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe 1 0 0 ode (2) hys (3) src wpe (4) wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. this bit applies only to gpio operation. 2. the ode bit should be set to zero for mdo operation. 3. the hys bit has no effect on mdo operation. 4. the wpe bit should be set to zero for mdo operation. RM0029 system integration unit (siu) doc id 15177 rev 8 473/1740 pad configuration register 82 (siu_pcr82) figure 212. pad configuration register (siu_pcr82) pad configuration register 83 (siu_pcr83) table 190. siu_pcr81 pa values signal name module description i/o (1),(2) pa value primary mdo[10] nexus message data out o 0b01 alt1 etpu_a[27] etpu etpu channel o 0b10 gpio gpio[81] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0xe4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe 1 0 0 ode (2) hys (3) src wpe (4) wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. this bit applies only to gpio operation. 2. the ode bit should be set to zero for mdo operation. 3. the hys bit has no effect on mdo operation. 4. the wpe bit should be set to zero for mdo operation. table 191. siu_pcr82 pa values signal name module description i/o (1),(2) pa value primary mdo[11] nexus message data out o 0b01 alt1 etpu_a[29] etpu etpu channel o 0b10 gpio gpio[82] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0xe6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. system integration unit (siu) RM0029 474/1740 doc id 15177 rev 8 figure 213. pad configuration register (siu_pcr83) pad configuration register 84 (siu_pcr84) figure 214. pad configuration register (siu_pcr84) 2. when configured as can_a_tx or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. when configured as sci_a_tx both obe and ibe are set to one automatically. setting the ibe bit to zero reduces power consumption. when configured as gpi, the ibe bit should be set to one. table 192. siu_pcr83 pa values signal name module description i/o (1),(2) pa value primary can_a_tx flexcan flexcan transmit o 0b01 alt1 sci_a_tx esci esci transmit o 0b10 gpio gpio[83] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0xe8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as can_a_rx or sci_a_rx, the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. w hen configured as gpi, the ibe bit should be set to one. table 193. siu_pcr84 pa values signal name module description i/o (1),(2) pa value primary can_a_rx flexcan flexcan receive i 0b01 alt1 sci_a_rx esci esci receive i 0b10 gpio gpio[84] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 475/1740 pad configuration register 85 (siu_pcr85) figure 215. pad configuration register (siu_pcr85) pad configuration register 86 (siu_pcr86) figure 216. pad configuration register (siu_pcr86) siu_base+0xea 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as can_b_tx, dspi_c_pcs[3], sci_c_tx or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to ze ro reduces power consumption. when configured as gpi, the ibe bit should be set to one. table 194. siu_pcr85 pa values signal name module description i/o (1),(2) pa value primary can_b_tx flexcan flexcan transmit o 0b001 alt1 dspi_c_pcs[3] dspi chip select o 0b010 alt2 sci_c_tx esci esci transmit o 0b100 gpio gpio[85] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0xec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as can_b_rx or sci_c_rx, the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as dspi_c_pcs[4] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. table 195. siu_pcr86 pa values signal name module description i/o (1),(2) pa value primary can_b_rx flexcan flexcan receive i 0b001 alt1 dspi_c_pcs[4] dspi chip select o 0b010 system integration unit (siu) RM0029 476/1740 doc id 15177 rev 8 pad configuration register 87 (siu_pcr87) figure 217. pad configuration register (siu_pcr87) pad configuration register 88 (siu_pcr88) alt2 sci_c_rx esci esci receive i 0b100 gpio gpio[86] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. table 195. siu_pcr86 pa values signal name module description i/o (1),(2) pa value siu_base+0xee 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as can_c_tx, dspi_d_pcs[3] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. table 196. siu_pcr87 pa values signal name module description i/o (1),(2) pa value primary can_c_tx flexcan flexcan transmit o 0b01 alt1 dspi_d_pcs[3] dspi chip select o 0b10 gpio gpio[87] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 477/1740 figure 218. pad configuration register (siu_pcr88) pad configuration register 89 (siu_pcr89) figure 219. pad configuration register (siu_pcr89) siu_base+0xf0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as can_c_rx, the obe bit has no effect . when configured as gpo, the obe bit should be set to one. 2. when configured as can_c_rx, dspi_d_pcs[4] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. table 197. siu_pcr88 pa values signal name module description i/o (1),(2) pa value primary can_c_rx flexcan flexcan receive i 0b01 alt1 dspi_d_pcs[4] dspi chip select o 0b10 gpio gpio[88] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0xf2 0123456789101112131415 r 0000 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0000000000000011 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as sci_a_tx, emios[13] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. for sci loop back operation the ibe bit must be set to one. setting the ibe bit to zero reduces power consumption. when configured as gpi, the ibe bit should be set to one. system integration unit (siu) RM0029 478/1740 doc id 15177 rev 8 pad configuration register 90 (siu_pcr90) figure 220. pad configuration register (siu_pcr90) pad configuration register 91 (siu_pcr91) table 198. siu_pcr89 pa values signal name module description i/o (1),(2) pa value primary sci_a_tx esci esci transmit o 0b01 alt1 emios[13] emios emios channel o 0b10 gpio gpio[89] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0xf4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as sci_a_rx the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as emios[15] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. for sci loop back operation the ibe bit must be set to one. setting the ibe bit to zero reduces power consumption. when configured as gpi, the ibe bit should be set to one. table 199. siu_pcr90 pa values signal name module description i/o (1),(2) pa value primary sci_a_rx esci esci receive i 0b01 alt1 emios[15] emios emios channel o 0b10 gpio gpio[90] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 479/1740 figure 221. pad configuration register (siu_pcr91) pad configuration register 92 (siu_pcr92) figure 222. pad configuration register (siu_pcr92) siu_base+0xf6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as sci_b_tx, dspi_d_pcs[1] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. for sci loop back operation the ibe bit must be set to one. setting the ibe bit to zero reduces power consumption. when configured as gpi, the ibe bit should be set to one. table 200. siu_pcr91 pa values signal name module description i/o (1),(2) pa value primary sci_b_tx esci esci transmit o 0b01 alt1 dspi_d_pcs[1] dspi chip select o 0b10 gpio gpio[91] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0xf8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as sci_b_rx, the obe bit has no effect . when configured as gpo, the obe bit should be set to one. 2. when configured as dspi_d_pcs[5] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. for sci loop back operation the ibe bit must be set to one. setting the ibe bit to zero reduces power consumption. when configured as gpi, the ibe bit should be set to one. table 201. siu_pcr92 pa values signal name module description i/o (1),(2) pa value primary sci_b_rx esci esci receive i 0b01 alt1 dspi_d_pcs[5] dspi chip select o 0b10 gpio gpio[92] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. system integration unit (siu) RM0029 480/1740 doc id 15177 rev 8 pad configuration register 93 (siu_pcr93) figure 223. pad configuration register (siu_pcr93) pad configuration register 94 (siu_pcr94) figure 224. pad configuration register (siu_pcr94) 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0xfa 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the scka function is not available on the spc564a74xx, spc564a80xx. do not select 0b01 or 0b11 for the pa field. 2. when configured as gpo, the obe bit should be set to one. 3. when configured as dspi_c_pcs[1] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. table 202. siu_pcr93 pa values signal name module description i/o (1),(2) pa value scka (3) alt1 dspi_c_pcs[1] dspi chip select o 0b10 gpio gpio[93] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. 3. this signal name is us ed to support legacy naming. siu_base+0xfc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the sina function is not available on the spc564a74xx, spc564a80xx. do not select 0b01 or 0b11 for the pa field. 2. when configured as gpo, the obe bit should be set to one. 3. when configured as dspi_c_pcs[2] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. RM0029 system integration unit (siu) doc id 15177 rev 8 481/1740 pad configuration register 95 (siu_pcr95) figure 225. pad configuration register (siu_pcr95) table 203. siu_pcr94 pa values signal name module description i/o (1),(2) pa value sina (3) alt1 dspi_c_pcs[2] dspi chip select o 0b10 gpio gpio[94] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. 3. this signal name is us ed to support legacy naming. siu_base+0xfe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the souta function is not available on the spc564a74xx, spc564a80xx. do not select 0b01 or 0b11 for the pa field. 2. when configured as gpo, the obe bit should be set to one. 3. when configured as dspi_c_pcs[5] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. table 204. siu_pcr95 pa values signal name module description i/o (1),(2) pa value souta (3) alt1 dspi_c_pcs[5] dspi chip select o 0b10 gpio gpio[95] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. 3. this signal name is us ed to support legacy naming. system integration unit (siu) RM0029 482/1740 doc id 15177 rev 8 pad configuration register 96 (siu_pcr96) figure 226. pad configuration register (siu_pcr96) pad configuration register 97 (siu_pcr97) figure 227. pad configuration register (siu_pcr97) siu_base+0x100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the pcsa[0] function is not available on the spc564a74xx, spc564a80xx. do not select 0b01 or 0b11 for the pa field. 2. when configured as gpo, the obe bit should be set to one. 3. when configured as dspi_d_pcs[2] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. table 205. siu_pcr96 pa values signal name module description i/o (1),(2) pa value pcsa0 (3) alt1 dspi_d_pcs[2] dspi chip select o 0b10 gpio gpio[96] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. 3. this signal name is us ed to support legacy naming. siu_base+0x102 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the pcsa[1] function is not available on the spc564a74xx, spc564a80xx mcu. do not select 0b01 or 0b11 for the pa field. 2. when configured as gpo, the obe bit should be set to one. 3. when configured as dspi_b_pcs[2] or gpo, the ibe bit ma y be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. RM0029 system integration unit (siu) doc id 15177 rev 8 483/1740 pad configuration register 98 (siu_pcr98) figure 228. pad configuration register (siu_pcr98) pad configuration register 99 (siu_pcr99) table 206. siu_pcr97 pa values signal name module description i/o (1),(2) pa value pcsa1 (3) alt1 dspi_b_pcs[2] dspi chip select o 0b10 gpio gpio[97] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. 3. this signal name is us ed to support legacy naming. siu_base+0x104 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the pcsa[2] function is not available on the spc564a74xx, spc564a80xx. do not select 0b01 or 0b11 for the pa field. 2. when configured as dspi_d_sck, the obe bit should be se t to one for master operation, and set to zero for slave operation. when configured as gpo, the obe bit should be set to one. 3. when configured as dspi_d_sck in sl ave operation, the ibe bit should be set to one. when configured as dspi_d_sck in master operation or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. when configured as gpi, the ibe bit should be set to one. table 207. siu_pcr98 pa values signal name module description i/o (1),(2) pa value alt1 dspi_d_sck dspi clock i/o 0b10 gpio gpio[98] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x106 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the pcsa[3] function is not available on the spc564a74xx, spc564a80xx. do not select 0b01 or 0b11 for the pa field. system integration unit (siu) RM0029 484/1740 doc id 15177 rev 8 figure 229. pad configuration register (siu_pcr99) pad configuration register 100 (siu_pcr100) figure 230. pad configuration register (siu_pcr100) 2. when configured as gpo, the obe bit should be set to one. 3. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. w hen configured as gpi, the ibe bit should be set to one. table 208. siu_pcr99 pa values signal name module description i/o (1),(2) pa value alt1 dspi_d_sin dspi input i 0b10 gpio gpio[99] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x108 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the pcsa[4] function is not available on the spc564a74xx, spc564a80xx. do not select 0b01 or 0b11 for the pa field. 2. when configured as dspi_d_sout, the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 3. when configured as dspi_d_sout or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. table 209. siu_pcr100 pa values signal name module description i/o (1),(2) pa value pcsa4 (3) alt1 dspi_d_sout dspi output o 0b10 gpio gpio[100] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. 3. this signal name is us ed to support legacy naming. RM0029 system integration unit (siu) doc id 15177 rev 8 485/1740 pad configuration register 101 (siu_pcr101) figure 231. pad configuration register (siu_pcr101) pad configuration register 102 (siu_pcr102) figure 232. pad configuration register (siu_pcr102) siu_base+0x10a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the pcsa[5] function is not available on the spc564a74xx, spc564a80xx. do not select 0b01 or 0b11 for the pa field. 2. when configured as gpo, the obe bit should be set to one. 3. when configured as dspi_b_pcs[3] or gpo, the ibe bit ma y be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. table 210. siu_pcr101 pa values signal name module description i/o (1),(2) pa value pcsa5 (3) alt1 dspi_b_pcs[3] dspi chip select o 0b10 gpio gpio[101] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. 3. this signal name is us ed to support legacy naming. siu_base+0x10c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as dspi_b_sck, the obe bit should be set to one for master operation, and set to zero for slave operation. when configured as gpo, the obe bit should be set to one. 2. when configured as dspi_b_sck in slav e operation the ibe bit should be set to one. when configured as dspi_b_sck in master operation or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. w hen configured as gpi, the ibe bit should be set to one. system integration unit (siu) RM0029 486/1740 doc id 15177 rev 8 pad configuration register 103 (siu_pcr103) figure 233. pad configuration register (siu_pcr103) pad configuration register 104 (siu_pcr104) table 211. siu_pcr102 pa values signal name module description i/o (1),(2) pa value primary dspi_b_sck dspi clock i/o 0b01 alt1 dspi_c_pcs[1] dspi chip select o 0b10 gpio gpio[102] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x10e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as dspi_b_sin, the obe bit should be set to zero. when configured as pcs, the obe bit should be set to one. 2. when configured as dspi_b_sin or dspi_c_pcs[2], the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. table 212. siu_pcr103 pa values signal name module description i/o (1),(2) pa value primary dspi_b_sin dspi input i 0b01 alt1 dspi_c_pcs[2] dspi chip select o 0b10 gpio gpio[103] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. RM0029 system integration unit (siu) doc id 15177 rev 8 487/1740 figure 234. pad configuration register (siu_pcr104) pad configuration register 105 (siu_pcr105) figure 235. pad configuration register (siu_pcr105) 2. when configured as dspi_b_sout or dspi_c_pcs[5] or gpo, t he ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. table 213. siu_pcr104 pa values signal name module description i/o (1),(2) pa value primary dspi_b_sout dspi output o 0b01 alt1 dspi_c_pcs[5] dspi chip select o 0b10 gpio gpio[104] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x112 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as dspi_b_pcs[0], dspi_d _pcs[2] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. table 214. siu_pcr105 pa values signal name module description i/o (1),(2) pa value primary dspi_b_pcs[0] dspi chip select i/o 0b01 alt1 dspi_d_pcs[2] dspi chip select o 0b10 gpio gpio[105] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. system integration unit (siu) RM0029 488/1740 doc id 15177 rev 8 pad configuration register 106 (siu_pcr106) figure 236. pad configuration register (siu_pcr106) pad configuration register 107 (siu_pcr107) figure 237. pad configuration register (siu_pcr107) siu_base+0x114 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as dspi_d_pcs[0], the obe bit should be set to one for master operation, and set to zero for slave operation. when configured as gpo, the obe bit should be set to one. 2. when configured as dspi_d_pcs[0] in slave operation, t he ibe bit should be set to one. when configured as pcs in master operation or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. w hen configured as gpi, the ibe bit should be set to one. table 215. siu_pcr106 pa values signal name module description i/o (1),(2) pa value primary dspi_b_pcs[1] dspi chip select o 0b01 alt1 dspi_d_pcs[0] dspi chip select i/o 0b10 gpio gpio[106] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x116 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as dspi_b_pcs[2], dspi _c_sout or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. RM0029 system integration unit (siu) doc id 15177 rev 8 489/1740 pad configuration register 108 (siu_pcr108) figure 238. pad configuration register (siu_pcr108) pad configuration register 109 (siu_pcr109) table 216. siu_pcr107 pa values signal name module description i/o (1),(2) pa value primary dspi_b_pcs[2] dspi chip select o 0b01 alt1 dspi_c_sout dspi output o 0b10 gpio gpio[107] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x118 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as dspi_c_sin, the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as dspi_b_pcs[3] or gpo, the ibe bit ma y be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. table 217. siu_pcr108 pa values signal name module description i/o (1),(2) pa value primary dspi_b_pcs[3] dspi chip select o 0b01 alt1 dspi_c_sin dspi input i 0b10 gpio gpio[108] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x11a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as dspi_c_sck, the obe bit should be se t to one for master operation, and set to zero for slave operation. when configured as gpo, the obe bit should be set to one. system integration unit (siu) RM0029 490/1740 doc id 15177 rev 8 figure 239. pad configuration register (siu_pcr109) pad configuration register 110 (siu_pcr110) figure 240. pad configuration register (siu_pcr110) 2. when configured as dspi_c_sck in slave operation, the ibe bit should be set to one. when configured as dspi_b_pcs[4] or dspi_c_sck in master operation or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. when c onfigured as gpi, the ibe bit should be set to one. table 218. siu_pcr109 pa values signal name module description i/o (1),(2) pa value primary dspi_b_pcs[4] dspi chip select o 0b01 alt1 dspi_c_sck dspi clock i/o 0b10 gpio gpio[109] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x11c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as dspi_c_pcs[0], the obe bit should be set to one for master operation, and set to zero for slave operation. when configured as gpo, the obe bit should be set to one. 2. when configured as dspi_c_pcs[0] in slave operation, t he ibe bit should be set to one. when configured as pcs in master operation or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. w hen configured as gpi, the ibe bit should be set to one. table 219. siu_pcr110 pa values signal name module description i/o (1),(2) pa value primary dspi_b_pcs[5] dspi chip select o 0b01 alt1 dspi_c_pcs[0] dspi chip select i/o 0b10 gpio gpio[110] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 491/1740 pad configuration register 113 (siu_pcr113) figure 241. pad configuration register (siu_pcr113) pad configuration register 114?125 (siu_pcr114?siu_pcr125) the siu_pcr114 ? siu_pcr125 registers control the pin function, direction, and static electrical attributes of the etpua0 ? etpua11 pins, which host the etpu_a[0:11], etpu_a[12:23] and gpio[114:125] signals. note: only the output channels of the etpu_a[12:23] signals are connected to pins. both the input and output channels of the etpu_a[0:11] signals are connected to pins. pad configuration register 114 (siu_pcr114) siu_base+0x122 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as tcrclka or irq, the obe bit has no ef fect. when configured as gpo, the obe bit should be set to one. 2. when configured as tcrclka or irq or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. when configured as gpi, the ibe bit should be set to one. table 220. siu_pcr113 pa values signal name module description i/o (1),(2) pa value primary tcrclka etpu tcr time base input clock i 0b01 alt1 irq[7] siu external interrupt i 0b10 gpio gpio[113] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. system integration unit (siu) RM0029 492/1740 doc id 15177 rev 8 figure 242. pad configuration register (siu_pcr114) pad configuration register 115 (siu_pcr115) figure 243. pad configuration register (siu_pcr115) siu_base+0x124 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpu_a[0] and gpio[114] when configured as outputs. 2. the ibe bit must be set to one for both etpu_a[0] and gp io[114] when configured as inputs. when configured as etpu_a[12] or etpu_a[19] or when etpu_a[0] or gpio[114] are configured as outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[0] pin is determined by the wkpcfg pin. table 221. siu_pcr114 pa values signal name module description i/o (1),(2) pa value primary etpu_a[0] etpu etpu channel i/o 0b001 alt1 etpu_a[12] etpu etpu channel o 0b010 alt2 etpu_a[19] etpu etpu channel o 0b100 gpio gpio[114] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x126 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpu_a[1] and gpio[115] when configured as outputs. 2. the ibe bit must be set to one for both etpu_a[1] and gp io[113] when configured as inputs. when configured as etpu_a[13] or when etpu_a[1] or gpio[ 115] are configured as outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[1] pin is determined by the wkpcfg pin. table 222. siu_pcr115 pa values signal name module description i/o (1),(2) pa value primary etpu_a[1] etpu etpu channel i/o 0b01 RM0029 system integration unit (siu) doc id 15177 rev 8 493/1740 pad configuration register 116 (siu_pcr116) figure 244. pad configuration register (siu_pcr116) pad configuration register 117 (siu_pcr117) alt1 etpu_a[13] etpu etpu channel o 0b10 gpio gpio[115] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. table 222. siu_pcr115 pa values signal name module description i/o (1),(2) pa value siu_base+0x128 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpu_a[2] and gpio[116] when configured as outputs. 2. the ibe bit must be set to one for both etpu_a[2] and gp io[116] when configured as inputs. when configured as etpu_a[14] or when etpu_a[2] or gpio[ 116] are configured as outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[2] pin is determined by the wkpcfg pin. table 223. siu_pcr116 pa values signal name module description i/o (1),(2) pa value primary etpu_a[2] etpu etpu channel i/o 0b01 alt1 etpu_a[14] etpu etpu channel o 0b10 gpio gpio[116] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x12a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpu_a[3] and gpio[117] when configured as outputs. system integration unit (siu) RM0029 494/1740 doc id 15177 rev 8 figure 245. pad configuration register (siu_pcr117) pad configuration register 118 (siu_pcr118) figure 246. pad configuration register (siu_pcr118) 2. the ibe bit must be set to one for both etpu_a[3] and gp io[117] when configured as inputs. when configured as etpu_a[15] or when etpu_a[3] or gpio[ 117] are configured as outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[3] pin is determined by the wkpcfg pin. table 224. siu_pcr117 pa values signal name module description i/o (1),(2) pa value primary etpu_a[3] etpu etpu channel i/o 0b01 alt1 etpu_a[15] etpu etpu channel o 0b10 gpio gpio[117] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x12c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpu_a[4] and gpio[118] when configured as outputs. 2. the ibe bit must be set to one for both etpu_a[4] and gp io[118] when configured as inputs. when configured as etpu_a[16] or fr_b_tx or when etpu_a[4] or gpio[118] ar e configured as outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[4] pin is determined by the wkpcfg pin. table 225. siu_pcr118 pa values signal name module description i/o (1),(2) pa value primary etpu_a[4] etpu etpu channel i/o 0b0001 alt1 etpu_a[16] etpu etpu channel o 0b0010 alt3 fr_b_tx flexray flexray transmit o 0b1000 gpio gpio[118] siu gpio i/o 0b0000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 495/1740 pad configuration register 119 (siu_pcr119) figure 247. pad configuration register (siu_pcr119) pad configuration register 120 (siu_pcr120) figure 248. pad configuration register (siu_pcr120) siu_base+0x12e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpu_a[5] and gpio[119] when configured as outputs. 2. the ibe bit must be set to one for both etpu_a[5] and gp io[119] when configured as inputs. when configured as etpu_a[17] or when etpu_a[5] or gpio[ 119] are configured as outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[5] pin is determined by the wkpcfg pin. table 226. siu_pcr119 pa values signal name module description i/o (1),(2) pa value primary etpu_a[5] etpu etpu channel i/o 0b0001 alt1 etpu_a[17] etpu etpu channel o 0b0010 alt2 dspi_b_sck_lvds ? dspi lvds ? clock o 0b0100 alt3 fr_b_tx_en flexray flexray transmit enable o 0b1000 gpio gpio[119] siu gpio i/o 0b0000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x130 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpu_a[6] and gpio[120] when configured as outputs. 2. the ibe bit must be set to one for both etpu_a[6] and gp io[120] when configured as inputs. when configured as etpu_a[18] or when etpu_a[6] or gpio[ 119] are configured as outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[6] pin is determined by the wkpcfg pin. system integration unit (siu) RM0029 496/1740 doc id 15177 rev 8 pad configuration register 121 (siu_pcr121) figure 249. pad configuration register (siu_pcr121) table 227. siu_pcr120 pa values signal name module description i/o (1),(2) pa value primary etpu_a[6] etpu etpu channel i/o 0b0001 alt1 etpu_a[18] etpu etpu channel o 0b0010 alt2 dspi_b_sck_lvds+ dspi lvds+ clock o 0b0100 alt3 fr_b_rx flexray flexray receive i 0b1000 gpio gpio[120] siu gpio i/o 0b0000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x132 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpu_a[7] and gpio[121] when configured as outputs. 2. the ibe bit must be set to one for both etpu_a[7] and gp io[121] when configured as inputs. when configured as etpu_a[19] or when etpu_a[7] or gpio[ 119] are configured as outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[7] pin is determined by the wkpcfg pin. table 228. siu_pcr121 pa values signal name module description i/o (1),(2) pa value primary etpu_a[7] etpu etpu channel i/o 0b0001 alt1 etpu_a[19] etpu etpu channel o 0b0010 alt2 dspi_b_sout_lvds ? dspi lvds ? output o 0b0100 alt3 etpu_a[6] etpu etpu channel o 0b1000 gpio gpio[121] siu gpio i/o 0b0000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 497/1740 pad configuration register 122 (siu_pcr122) figure 250. pad configuration register (siu_pcr122) pad configuration register 123 (siu_pcr123) figure 251. pad configuration register (siu_pcr123) siu_base+0x134 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpu_a[8] and gpio[122] when configured as outputs. 2. the ibe bit must be set to one for both etpu_a[8] and gp io[122] when configured as inputs. when configured as etpu_a[20] or when etpu_a[8] or gpio[ 122] are configured as outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[8] pin is determined by the wkpcfg pin. table 229. siu_pcr122 pa values signal name module description i/o (1),(2) pa value primary etpu_a[8] etpu etpu channel i/o 0b001 alt1 etpu_a[20] etpu etpu channel o 0b010 alt2 dspi_b_sout_lvds+ dspi lvds+ output o 0b100 gpio gpio[122] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x136 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpu_a[9] and gpio[123] when configured as outputs. 2. the ibe bit must be set to one for both etpu_a[9] and gp io[123] when configured as inputs. when configured as etpu_a[21] or when etpu_a[9] or gpio[ 123] are configured as outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[9] pin is determined by the wkpcfg pin. system integration unit (siu) RM0029 498/1740 doc id 15177 rev 8 pad configuration register 124 (siu_pcr124) figure 252. pad configuration register (siu_pcr124) table 230. siu_pcr123 pa values signal name module description i/o (1),(2) pa value primary etpu_a[9] etpu etpu channel i/o 0b001 alt1 etpu_a[21] etpu etpu channel o 0b010 alt2 rch1_b reaction reaction channel o 0b100 gpio gpio[123] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x138 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpu_a[10] and gpio[124] when configured as outputs. 2. the ibe bit must be set to one for both etpu_a[10] and gpio[124] when configured as inputs. when configured as etpu_a[22] or when etpu_a[10] or gpio[124] are configured as outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[10] pin is determined by the wkpcfg pin. table 231. siu_pcr124 pa values signal name module description i/o (1),(2) pa value primary etpu_a[10] etpu etpu channel i/o 0b001 alt1 etpu_a[22] etpu etpu channel o 0b010 alt2 rch1_c reaction reaction channel o 0b100 gpio gpio[124] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 499/1740 pad configuration register 125 (siu_pcr125) figure 253. pad configuration register (siu_pcr125) pad configuration register 126 (siu_pcr126) figure 254. pad configuration register (siu_pcr126) siu_base+0x13a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpu_a[11] and gpio[125] when configured as outputs. 2. the ibe bit must be set to one for both etpu_a[11] and gpio[125] when configured as inputs. when configured as etpu_a[23] or when etpu_a[11] or gpio[125] are configured as outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[11] pin is determined by the wkpcfg pin. table 232. siu_pcr125 pa values signal name module description i/o (1),(2) pa value primary etpu_a[11] etpu etpu channel i/o 0b001 alt1 etpu_a[23] etpu etpu channel o 0b010 alt2 rch4_b reaction reaction channel o 0b100 gpio gpio[125] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x13c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. when configured as pcs, the obe bit has no effect. the obe bit must be set to one for both etpua and gpio when configured as outputs. 2. the ibe bit must be set to one for both etpua and gpio when configured as inputs. when configured as pcs, or etpua or gpo outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[12] pin is determined by the wkpcfg pin. system integration unit (siu) RM0029 500/1740 doc id 15177 rev 8 pad configuration register 127 (siu_pcr127) figure 255. pad configuration register (siu_pcr127) pad configuration register 128 (siu_pcr128) table 233. siu_pcr126 pa values signal name module description i/o (1),(2) pa value primary etpu_a[12] etpu etpu channel i/o 0b001 alt1 dspi_b_pcs[1] dspi chip select o 0b010 alt2 rch4_c reaction reaction channel o 0b100 gpio gpio[126] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x13e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpua and gpio when configured as outputs. 2. the ibe bit must be set to one for both etpua and gpio when configured as inputs. when configured as pcs, or etpua or gpo outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[13] pin is determined by the wkpcfg pin. table 234. siu_pcr127 pa values signal name module description i/o (1),(2) pa value primary etpu_a[13] etpu etpu channel i/o 0b01 alt1 dspi_b_pcs[3] dspi chip select o 0b10 gpio gpio[127] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 501/1740 figure 256. pad configuration register (siu_pcr128) pad configuration register 129 (siu_pcr129) figure 257. pad configuration register (siu_pcr129) siu_base+0x140 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpua and gpio when configured as outputs. 2. the ibe bit must be set to one for both etpua and gpio when configured as inputs. when configured as pcs, or etpua or gpo outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[14] pin is determined by the wkpcfg pin. table 235. siu_pcr128 pa values signal name module description i/o (1),(2) pa value primary etpu_a[14] etpu etpu channel i/o 0b0001 alt1 dspi_b_pcs[4] dspi chip select o 0b0010 alt2 etpu_a[9] etpu etpu channel o 0b0100 alt3 rch0_a reaction reaction channel o 0b1000 gpio gpio[128] siu gpio i/o 0b0000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x142 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpua and gpio when configured as outputs. 2. the ibe bit must be set to one for both etpua and gpio when configured as inputs. when configured as pcs, or etpua or gpo outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[15] pin is determined by the wkpcfg pin. system integration unit (siu) RM0029 502/1740 doc id 15177 rev 8 pad configuration register 130 (siu_pcr130) figure 258. pad configuration register (siu_pcr130) table 236. siu_pcr129 pa values signal name module description i/o (1),(2) pa value primary etpu_a[15] etpu etpu channel i/o 0b001 alt1 dspi_b_pcs[5] dspi chip select o 0b010 alt2 rch1_a reaction reaction channel o 0b100 gpio gpio[129] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x144 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpua and gpio when configured as outputs. 2. the ibe bit must be set to one for both etpua and gpio when configured as inputs. when configured as pcs, or etpua or gpo outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[16] pin is determined by the wkpcfg pin. table 237. siu_pcr130 pa values signal name module description i/o (1),(2) pa value primary etpu_a[16] etpu etpu channel i/o 0b001 alt1 dspi_d_pcs[1] dspi chip select o 0b010 alt2 rch2_a reaction reaction channel o 0b100 gpio gpio[130] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 503/1740 pad configuration register 131 (siu_pcr131) figure 259. pad configuration register (siu_pcr131) pad configuration register 132 (siu_pcr132) figure 260. pad configuration register (siu_pcr132) siu_base+0x146 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpua and gpio when configured as outputs. 2. the ibe bit must be set to one for both etpua and gpio when configured as inputs. when configured as pcs, or etpua or gpo outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[17] pin is determined by the wkpcfg pin. table 238. siu_pcr131 pa values signal name module description i/o (1),(2) pa value primary etpu_a[17] etpu etpu channel i/o 0b001 alt1 dspi_d_pcs[2] dspi chip select o 0b010 alt2 rch3_a reaction reaction channel o 0b100 gpio gpio[131] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x148 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpua and gpio when configured as outputs. 2. the ibe bit must be set to one for both etpua and gpio when configured as inputs. when configured as pcs, or etpua or gpo outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[18] pin is determined by the wkpcfg pin. system integration unit (siu) RM0029 504/1740 doc id 15177 rev 8 pad configuration register 133 (siu_pcr133) figure 261. pad configuration register (siu_pcr133) table 239. siu_pcr132 pa values signal name module description i/o (1),(2) pa value primary etpu_a[18] etpu etpu channel i/o 0b001 alt1 dspi_d_pcs[3] dspi chip select o 0b010 alt2 rch4_a reaction reaction channel o 0b100 gpio gpio[132] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x14a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both etpua and gpio when configured as outputs. 2. the ibe bit must be set to one for both etpua and gpio when configured as inputs. when configured as pcs, or etpua or gpo outputs, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. 3. the weak pull up/down selection at reset for the etpu_a[19] pin is determined by the wkpcfg pin. table 240. siu_pcr133 pa values signal name module description i/o (1),(2) pa value primary etpu_a[19] etpu etpu channel i/o 0b001 alt1 dspi_d_pcs[4] dspi chip select o 0b010 alt2 rch5_a reaction reaction channel o 0b100 gpio gpio[133] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 505/1740 pad configuration register 134 (siu_pcr134) figure 262. pad configuration register (siu_pcr134) pad configuration register 135 (siu_pcr135) figure 263. pad configuration register (siu_pcr135) siu_base+0x14c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. when configured as irq, the obe bit has no effect. the obe bit must be set to one for both etpu_a[20] and gpio[134] when configured as outputs. 2. when configured as fr_a_tx, irq or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. the ibe bit must be set to one for both etpu_a[20] and gpio[134] when configured as inputs. 3. the weak pull up/down selection at reset for the etpu_a[20] pin is determined by the wkpcfg pin. table 241. siu_pcr134 pa values signal name module description i/o (1),(2) pa value primary etpu_a[20] etpu etpu channel i/o 0b0001 alt1 irq[8] siu external interrupt i 0b0010 alt2 rch0_b reaction reaction channel o 0b0100 alt3 fr_a_tx flexray flexray transmit o 0b1000 gpio gpio[134] siu gpio i/o 0b0000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x14e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. when configured as irq, the obe bit has no effect. the obe bit must be set to one for both etpu_a[21] and gpio[135] when configured as outputs. 2. when configured as fr_a_rx, irq or gpo, the ibe bit ma y be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. the ibe bit must be set to one for both etpu_a[21] and gpio[135] when configured as inputs. 3. the weak pull up/down selection at reset for the etpu_a[21] pin is determined by the wkpcfg pin. system integration unit (siu) RM0029 506/1740 doc id 15177 rev 8 pad configuration register 136 (siu_pcr136) figure 264. pad configuration register (siu_pcr136) table 242. siu_pcr135 pa values signal name module description i/o (1),(2) pa value primary etpu_a[21] etpu etpu channel i/o 0b0001 alt1 irq[9] siu external interrupt i 0b0010 alt2 rch0_c reaction reaction channel o 0b0100 alt3 fr_a_rx flexray flexray receive i 0b1000 gpio gpio[135] siu gpio i/o 0b0000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x150 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. when configured as irq, the obe bit has no effect. the obe bit must be set to one for both etpu_a[22] and gpio[136] when configured as outputs. 2. when configured as etpu_a[17], irq or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power c onsumption. the ibe bit must be set to one for both etpu_a[22] and gpio[136] when configured as inputs. 3. the weak pull up/down selection at reset for the etpu_a[22] pin is determined by the wkpcfg pin. table 243. siu_pcr136 pa values signal name module description i/o (1),(2) pa value primary etpu_a[22] etpu etpu channel i/o 0b001 alt1 irq[10] siu external interrupt i 0b010 alt2 etpu_a[17] etpu etpu channel o 0b100 gpio gpio[136] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 507/1740 pad configuration register 137 (siu_pcr137) figure 265. pad configuration register (siu_pcr137) pad configuration register 138 (siu_pcr138) figure 266. pad configuration register (siu_pcr138) siu_base+0x152 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. when configured as irq, the obe bit has no effect. the obe bit must be set to one for both etpu_a[23] and gpio[137] when configured as outputs. 2. when configured as etpu_a[21], fr_a_tx_en, irq or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. the ibe bit must be set to one for both etpu_a[23] and gpio[137] when configured as inputs. 3. the weak pull up/down selection at reset for the etpu_a[23] pin is determined by the wkpcfg pin. table 244. siu_pcr137 pa values signal name module description i/o (1),(2) pa value primary etpu_a[23] etpu etpu channel i/o 0b0001 alt1 irq[11] siu external interrupt i 0b0010 alt2 etpu_a[21] etpu etpu channel o 0b0100 alt3 fr_a_tx_en flexray flexray transmit enable o 0b1000 gpio gpio[137] siu gpio i/o 0b0000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x154 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. when configured as irq, the obe bit has no effect. the obe bit must be set to one for both etpu_a[24] and gpio[138] when configured as outputs. 2. when configured as dspi_c_sck_lvds ? , irq or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. the ibe bit must be set to one for both etpu_a[24] and gpio[138] when configured as inputs. 3. the weak pull up/down selection at reset for the etpu_a[24] pin is determined by the wkpcfg pin. system integration unit (siu) RM0029 508/1740 doc id 15177 rev 8 pad configuration register 139 (siu_pcr139) figure 267. pad configuration register (siu_pcr139) table 245. siu_pcr138 pa values signal name module description i/o (1),(2) pa value primary etpu_a[24] (3) etpu etpu channel i/o 0b001 alt1 irq[12] siu external interrupt i 0b010 alt2 dspi_c_sck_lvds ? dspi lvds ? clock o 0b100 gpio gpio[138] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. 3. the etpu function controlled by this register has an additional dependency on the siu_isel8 register settings. please see section 16.6.22, imux select register 8 (siu_isel8) , for more detail. siu_base+0x156 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. when configured as irq, the obe bit has no effect. the obe bit must be set to one for both etpu_a[25] and gpio[139] when configured as outputs. 2. when configured as irq, dspi_c_sck_lv ds+ or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. the ibe bit must be set to one for both etpu_a[25] and gpio[139] when configured as inputs. 3. the weak pull up/down selection at reset for the etpu_a[25] pin is determined by the wkpcfg pin. table 246. siu_pcr139 pa values signal name module description i/o (1),(2) pa value primary etpu_a[25] (3) etpu etpu channel i/o 0b001 alt1 irq[13] siu external interrupt i 0b010 alt2 dspi_c_sck_lvds+ dspi lvds+ clock o 0b100 gpio gpio[139] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. 3. the etpu function controlled by this register has an additional dependency on the siu_isel8 register settings. please see section 16.6.22, imux select register 8 (siu_isel8) , for more detail. RM0029 system integration unit (siu) doc id 15177 rev 8 509/1740 pad configuration register 140 (siu_pcr140) figure 268. pad configuration register (siu_pcr140) pad configuration register 141 (siu_pcr141) figure 269. pad configuration register (siu_pcr141) siu_base+0x158 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. when configured as irq, the obe bit has no effect. the obe bit must be set to one for both etpu_a[26] and gpio[140] when configured as outputs. 2. when configured as irq, dspi_c_sout_lvds ? or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduc es power consumption. the ibe bit must be set to one for both etpu_a[26] and gpio[140] when configured as inputs. 3. the weak pull up/down selection at reset for the etpu_a[26] pin is determined by the wkpcfg pin. table 247. siu_pcr140 pa values signal name module description i/o (1),(2) pa value primary etpu_a[26] (3) etpu etpu channel i/o 0b001 alt1 irq[14] siu external interrupt i 0b010 alt2 dspi_c_sout_lvds ? dspi lvds ? output o 0b100 gpio gpio[140] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. 3. the etpu function controlled by this register has an additional dependency on the siu_isel8 register settings. please see section 16.6.22, imux select register 8 (siu_isel8) , for more detail. siu_base+0x15a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. when configured as irq, the obe bit has no effect. the obe bit must be set to one for both etpu_a[27] and gpio[141] when configured as outputs. 2. when configured as irq, dspi_c_sout_lvds+, soutb or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero r educes power consumption. the ibe bit must be set to one for both etpu_a[27] and gpio[141] when configured as inputs. 3. the weak pull up/down selection at reset for the etpu_a[27] pin is determined by the wkpcfg pin. system integration unit (siu) RM0029 510/1740 doc id 15177 rev 8 pad configuration register 142 (siu_pcr142) figure 270. pad configuration register (siu_pcr142) table 248. siu_pcr141 pa values signal name module description i/o (1),(2) pa value primary etpu_a[27] (3) etpu etpu channel i/o 0b0001 alt1 irq[15] siu external interrupt i 0b0010 alt2 dspi_c_sout_lvds+ dspi lvds+ output o 0b0100 alt3 dspi_b_sout dspi output o 0b1000 gpio gpio[141] siu gpio i/o 0b0000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. 3. the etpu function controlled by this register has an additional dependency on the siu_isel8 register settings. please see section 16.6.22, imux select register 8 (siu_isel8) , for more detail. siu_base+0x15c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as pcs or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ib e bit must be set to one for gpio when configured as input. 3. the weak pull up/down selection at reset for the etpu_a[28] pin is determined by the wkpcfg pin. table 249. siu_pcr142 pa values signal name module description i/o (1),(2) pa value primary etpu_a[28] (3) etpu etpu channel i/o 0b001 alt1 dspi_c_pcs[1] dspi chip select o 0b010 alt2 rch5_b reaction reaction channel o 0b100 gpio gpio[142] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. 3. the etpu function controlled by this register has an additional dependency on the siu_isel8 register settings. please see section 16.6.22, imux select register 8 (siu_isel8) , for more detail. RM0029 system integration unit (siu) doc id 15177 rev 8 511/1740 pad configuration register 143 (siu_pcr143) figure 271. pad configuration register (siu_pcr143) pad configuration register 144 (siu_pcr144) figure 272. pad configuration register (siu_pcr144) siu_base+0x15e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as pcs or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ib e bit must be set to one for gpio when configured as input. 3. the weak pull up/down selection at reset for the etpu_a[29] pin is determined by the wkpcfg pin. table 250. siu_pcr143 pa values signal name module description i/o (1),(2) pa value primary etpu_a[29] (3) etpu etpu channel i/o 0b001 alt1 dspi_c_pcs[2] dspi chip select o 0b010 alt2 rch5_c reaction reaction channel o 0b100 gpio gpio[143] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. 3. the etpu function controlled by this register has an additional dependency on the siu_isel8 register settings. please see section 16.6.22, imux select register 8 (siu_isel8) , for more detail. siu_base+0x160 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. when configured as etpua output or gpo, the obe bit should be set to one. 2. when configured as etpua output, pcs, or gpo, the ibe bit ma y be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for etpua or gpio when configured as input. 3. the weak pull up/down selection at reset for the etpu_a[30] pin is determined by the wkpcfg pin system integration unit (siu) RM0029 512/1740 doc id 15177 rev 8 pad configuration register 145 (siu_pcr145) figure 273. pad configuration register (siu_pcr145) table 251. siu_pcr144 pa values signal name module description i/o (1),(2) pa value primary etpu_a[30] etpu etpu channel i/o 0b001 alt1 dspi_c_pcs[3] dspi chip select o 0b010 alt2 etpu_a[11] etpu etpu channel o 0b100 gpio gpio[144] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x162 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. when configured as etpua output or gpo, the obe bit should be set to one. 2. when configured as etpua output, dspi_c_pcs[4], etpu_a[13] or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for etpua or gpio when configured as input. 3. the weak pull up/down selection at reset for the etpu_a[31] pin is determined by the wkpcfg pin. table 252. siu_pcr145 pa values signal name module description i/o (1),(2) pa value primary etpu_a[31] etpu etpu channel i/o 0b001 alt1 dspi_c_pcs[4] dspi chip select o 0b010 alt2 etpu_a[13] etpu etpu channel o 0b100 gpio gpio[145] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 513/1740 pad configuration register 179 (siu_pcr179) figure 274. pad configuration register (siu_pcr179) pad configuration register 180 (siu_pcr180) figure 275. pad configuration register (siu_pcr180) siu_base+0x1a6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the obe bit must be set to one for both emios[0] and gpio[179] when configured as outputs. 2. when configured as etpu, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[0] and gpio[179] when configured as inputs. table 253. siu_pcr179 pa values signal name module description i/o (1),(2) pa value primary emios[0] emios emios channel i/o 0b001 alt1 etpu_a[0] etpu etpu channel o 0b010 alt2 etpu_a[25] etpu etpu channel o 0b100 gpio gpio[179] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1a8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the obe bit must be set to one for both emios[1] and gpio[180] when configured as outputs. 2. when configured as etpu, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[1] and gpio[180] when configured as inputs. table 254. siu_pcr180 pa values signal name module description i/o (1),(2) pa value primary emios[1] emios emios channel i/o 0b01 system integration unit (siu) RM0029 514/1740 doc id 15177 rev 8 pad configuration register 181 (siu_pcr181) figure 276. pad configuration register (siu_pcr181) pad configuration register 182 (siu_pcr182) alt1 etpu_a[1] etpu etpu channel o 0b10 gpio gpio[180] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. table 254. siu_pcr180 pa values signal name module description i/o (1),(2) pa value siu_base+0x1aa 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the obe bit must be set to one for both emios[2] and gpio[181] when configured as outputs. 2. when configured as etpu, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[2] and gpio[181] when configured as inputs. table 255. siu_pcr181 pa values signal name module description i/o (1),(2) pa value primary emios[2] emios emios channel i/o 0b001 alt1 etpu_a[2] etpu etpu channel o 0b010 alt2 rch2_b reaction reaction channel o 0b100 gpio gpio[181] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1ac 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both emios[3] and gpio[182] when configured as outputs. RM0029 system integration unit (siu) doc id 15177 rev 8 515/1740 figure 277. pad configuration register (siu_pcr182) pad configuration register 183 (siu_pcr183) figure 278. pad configuration register (siu_pcr183) 2. when configured as etpu, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[3] and gpio[182] when configured as inputs. 3. the weak pull up/down selection at reset for the emios[3] pin is determined by the wkpcfg pin. table 256. siu_pcr182 pa values signal name module description i/o (1),(2) pa value primary emios[3] emios emios channel i/o 0b01 alt1 etpu_a[3] etpu etpu channel o 0b10 gpio gpio[182] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1ae 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both emios[4] and gpio[183] when configured as outputs. 2. when configured as etpu, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[4] and gpio[183] when configured as inputs. 3. the weak pull up/down selection at reset for the emios[4] pin is determined by the wkpcfg pin. table 257. siu_pcr183 pa values signal name module description i/o (1),(2) pa value primary emios[4] emios emios channel i/o 0b001 alt1 etpu_a[4] etpu etpu channel o 0b010 alt2 rch2_c reaction reaction channel o 0b100 gpio gpio[183] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. system integration unit (siu) RM0029 516/1740 doc id 15177 rev 8 pad configuration register 184 (siu_pcr184) figure 279. pad configuration register (siu_pcr184) pad configuration register 185 (siu_pcr185) figure 280. pad configuration register (siu_pcr185) siu_base+0x1b0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both emios[5] and gpio[184] when configured as outputs. 2. when configured as etpu, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[5] and gpio[184] when configured as inputs. 3. the weak pull up/down selection at reset for the emios[5] pin is determined by the wkpcfg pin. table 258. siu_pcr184 pa values signal name module description i/o (1),(2) pa value primary emios[5] emios emios channel i/o 0b01 alt1 etpu_a[5] etpu etpu channel o 0b10 gpio gpio[184] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1b2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 = unimplemented or reserved 1. the obe bit must be set to one for both emios[6] and gpio[185] when configured as outputs. 2. when configured as etpu, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[6] and gpio[185] when configured as inputs. RM0029 system integration unit (siu) doc id 15177 rev 8 517/1740 pad configuration register 186 (siu_pcr186) figure 281. pad configuration register (siu_pcr186) pad configuration register 187 (siu_pcr187) table 259. siu_pcr185 pa values signal name module description i/o (1),(2) pa value primary emios[6] emios emios channel i/o 0b01 alt1 etpu_a[6] etpu etpu channel o 0b10 gpio gpio[185] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1b4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 = unimplemented or reserved 1. the obe bit must be set to one for both emios[7] and gpio[186] when configured as outputs. 2. when configured as etpu, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[7] and gpio[186] when configured as inputs. table 260. siu_pcr186 pa values signal name module description i/o (1),(2) pa value primary emios[7] emios emios channel i/o 0b01 alt1 etpu_a[7] etpu etpu channel o 0b10 gpio gpio[186] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1b6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the obe bit must be set to one for both emios[8] and gpio[187] when configured as outputs. system integration unit (siu) RM0029 518/1740 doc id 15177 rev 8 figure 282. pad configuration register (siu_pcr187) pad configuration register 188 (siu_pcr188) figure 283. pad configuration register (siu_pcr188) 2. when configured as etpu or sci_b_tx, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[8] and gpio[187] when configured as inputs. table 261. siu_pcr187 pa values signal name module description i/o (1),(2) pa value primary emios[8] emios emios channel i/o 0b001 alt1 etpu_a[8] etpu etpu channel o 0b010 alt2 sci_b_tx esci esci transmit o 0b100 gpio gpio[187] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1b8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the obe bit must be set to one for both emios[9] and gpio[188] when configured as outputs. 2. when configured as etpu, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[9] and gpio[188] when configured as inputs. table 262. siu_pcr188 pa values signal name module description i/o (1),(2) pa value primary emios[9] emios emios channel i/o 0b001 alt1 etpu_a[9] etpu etpu channel o 0b010 alt2 sci_b_rx esci esci receive i 0b100 gpio gpio[188] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 519/1740 pad configuration register 189 (siu_pcr189) figure 284. pad configuration register (siu_pcr189) pad configuration register 190 (siu_pcr190) figure 285. pad configuration register (siu_pcr190) siu_base+0x1ba 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both emios[10] and gpio[189] when configured as outputs. 2. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[10] and gpio[189] when configured as inputs. 3. the weak pull up/down selection at reset for the emios[10] pin is determined by the wkpcfg pin. table 263. siu_pcr189 pa values signal name module description i/o (1),(2) pa value primary emios[10] emios emios channel i/o 0b001 alt1 dspi_d_pcs[3] dspi chip select o 0b010 alt2 rch3_b reaction reaction channel o 0b0100 gpio gpio[189] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1bc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both emios[11] and gpio[190] when configured as outputs. 2. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[11] and gpio[190] when configured as inputs. 3. the weak pull up/down selection at reset for the emios[11] pin is determined by the wkpcfg pin. system integration unit (siu) RM0029 520/1740 doc id 15177 rev 8 pad configuration register 191 (siu_pcr191) figure 286. pad configuration register (siu_pcr191) table 264. siu_pcr190 pa values signal name module description i/o (1),(2) pa value primary emios[11] emios emios channel i/o 0b001 alt1 dspi_d_pcs[4] dspi chip select o 0b010 alt2 rch3_c reaction reaction channel o 0b0100 gpio gpio[190] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1be 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for gpio[191] when configured as an output. 2. when configured as etpu_a[27] or gpo the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for gpio[191] when configured as an input. 3. the weak pull up/down selection at reset for the emios[12] pin is determined by the wkpcfg pin. table 265. siu_pcr191 pa values signal name module description i/o (1),(2) pa value primary emios[12] emios emios channel i/o 0b001 alt1 dspi_c_sout dspi output o 0b010 alt2 etpu_a[27] etpu etpu channel o 0b100 gpio gpio[191] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 521/1740 pad configuration register 192 (siu_pcr192) figure 287. pad configuration register (siu_pcr192) pad configuration register 193 (siu_pcr193) figure 288. pad configuration register (siu_pcr193) siu_base+0x1c0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for gpio[192] when configured as an output. 2. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bi t must be set to one for gpio[192] when configured as an input. 3. the weak pull up/down selection at reset for the emios[13] pin is determined by the wkpcfg pin. table 266. siu_pcr192 pa values signal name module description i/o (1),(2) pa value primary emios[13] emios emios channel i/o 0b01 alt1 dspi_d_sout dspi output o 0b10 gpio gpio[192] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1c2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 = unimplemented or reserved 1. the obe bit must be set to one for gpio[193] when configured as outputs. 2. when configured as irq, etpu or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for gpio[193] when configured as inputs. table 267. siu_pcr193 pa values signal name module description i/o (1),(2) pa value primary emios[14] emios emios channel i/o 0b001 alt1 irq[0] siu external interrupt i 0b010 system integration unit (siu) RM0029 522/1740 doc id 15177 rev 8 pad configuration register 194 (siu_pcr194) figure 289. pad configuration register (siu_pcr194) pad configuration register 195 (siu_pcr195) alt2 etpu_a[29] etpu etpu channel o 0b100 gpio gpio[193] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. table 267. siu_pcr193 pa values signal name module description i/o (1),(2) pa value siu_base+0x1c4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 = unimplemented or reserved 1. the obe bit must be set to one for gpio[194] when configured as outputs. 2. when configured as irq, etpu or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for gpio[194] when configured as inputs. table 268. siu_pcr194 pa values signal name module description i/o (1),(2) pa value primary emios[15] emios emios channel i/o 0b01 alt1 irq[1] siu external interrupt i 0b10 gpio gpio[194] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 523/1740 figure 290. pad configuration register (siu_pcr195) pad configuration register 196 (siu_pcr196) figure 291. pad configuration register (siu_pcr196) siu_base+0x1c6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the obe bit must be set to one for both emios[16] and gpio[195] when configured as outputs. 2. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[16] and gpio[195] when configured as inputs. table 269. siu_pcr195 pa values signal name module description i/o (1),(2) pa value primary emios[16] emios emios channel i/o 0b1 gpio gpio[195] siu gpio i/o 0b0 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1c8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the obe bit must be set to one for both emios[17] and gpio[196] when configured as outputs. 2. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[17] and gpio[196] when configured as inputs. table 270. siu_pcr196 pa values signal name module description i/o (1),(2) pa value primary emios[17] emios emios channel i/o 0b1 gpio gpio[196] siu gpio i/o 0b0 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. system integration unit (siu) RM0029 524/1740 doc id 15177 rev 8 pad configuration register 197 (siu_pcr197) figure 292. pad configuration register (siu_pcr197) pad configuration register 198 (siu_pcr198) figure 293. pad configuration register (siu_pcr198) siu_base+0x1ca 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the obe bit must be set to one for both emios[18] and gpio[197] when configured as outputs. 2. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[18] and gpio[197] when configured as inputs. table 271. siu_pcr197 pa values signal name module description i/o (1),(2) pa value primary emios[18] emios emios channel i/o 0b1 gpio gpio[197] siu gpio i/o 0b0 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1cc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both emios[19] and gpio[198] when configured as outputs. 2. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[19] and gpio[198] when configured as inputs. table 272. siu_pcr198 pa values signal name module description i/o (1),(2) pa value primary emios[19] emios emios channel i/o 0b1 gpio gpio[198] siu gpio i/o 0b0 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 525/1740 pad configuration register 199 (siu_pcr199) figure 294. pad configuration register (siu_pcr199) pad configuration register 200 (siu_pcr200) figure 295. pad configuration register (siu_pcr200) siu_base+0x1ce 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both emios[20] and gpio[199] when configured as outputs. 2. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[20] and gpio[199] when configured as inputs. 3. the weak pull up/down selection at reset for the emios[20] pin is determined by the wkpcfg pin. table 273. siu_pcr199 pa values signal name module description i/o (1),(2) pa value primary emios[20] emios emios channel i/o 0b1 gpio gpio[199] siu gpio i/o 0b0 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1d0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps (3) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 wkp = unimplemented or reserved 1. the obe bit must be set to one for both emios[21] and gpio[200] when configured as outputs. 2. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[21] and gpio[200] when configured as inputs. 3. the weak pull up/down selection at reset for the emios[21] pin is determined by the wkpcfg pin. table 274. siu_pcr200 pa values signal name module description i/o (1),(2) pa value primary emios[21] emios emios channel i/o 0b1 gpio gpio[200] siu gpio i/o 0b0 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. system integration unit (siu) RM0029 526/1740 doc id 15177 rev 8 pad configuration register 201 (siu_pcr201) figure 296. pad configuration register (siu_pcr201) pad configuration register 202 (siu_pcr202) figure 297. pad configuration register (siu_pcr202) 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1d2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 = unimplemented or reserved 1. the obe bit must be set to one for both emios[22] and gpio[201] when configured as outputs. 2. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[22] and gpio[201] when configured as inputs. table 275. siu_pcr201 pa values signal name module description i/o (1),(2) pa value primary emios[22] emios emios channel i/o 0b1 gpio gpio[201] siu gpio i/o 0b0 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1d4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 = unimplemented or reserved 1. the obe bit must be set to one for both emios[23] and gpio[202] when configured as outputs. 2. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. the ibe bit must be set to one for both emios[23] and gpio[202] when configured as inputs. RM0029 system integration unit (siu) doc id 15177 rev 8 527/1740 pad configuration register 203 (siu_pcr203) figure 298. pad configuration register (siu_pcr203) pad configuration register 204 (siu_pcr204) table 276. siu_pcr202 pa values signal name module description i/o (1),(2) pa value primary emios[23] emios emios channel i/o 0b1 gpio gpio[202] siu gpio i/o 0b0 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1d6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the pa bit should be set to one for emios and cleared to zero when used as gpio. 2. when configured as gpo, the obe bit should be set to one. 3. when configured as emios or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumpt ion. when configured as gpi, the ibe bit should be set to one. table 277. siu_pcr203 pa values signal name module description i/o (1),(2) pa value primary emios[14] emios emios channel o 0b1 gpio gpio[203] siu gpio i/o 0b0 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. system integration unit (siu) RM0029 528/1740 doc id 15177 rev 8 figure 299. pad configuration register (siu_pcr204) pad configuration register 206 (siu_pcr206) figure 300. pad configuration register (siu_pcr206) siu_base+0x1d8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. the pa bit should be set to one for emios and cleared to zero when used as gpio. 2. when configured as gpo, the obe bit should be set to one. 3. when configured as emios or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumpt ion. when configured as gpi, the ibe bit should be set to one. table 278. siu_pcr204 pa values signal name module description i/o (1),(2) pa value primary emios[15] emios emios channel o 0b1 gpio gpio[204] siu gpio i/o 0b0 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1dc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. when configured as gpi, the ibe bit should be set to one. se tting the ibe bit to zero reduces power consumption. table 279. siu_pcr206 pa values signal name module description i/o (1),(2) pa value gpio gpio[206] etrig0 siu gpio i/o 0b0 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 529/1740 pad configuration register 207 (siu_pcr207) figure 301. pad configuration register (siu_pcr207) pad configuration register 208 (siu_pcr208) figure 302. pad configuration register (siu_pcr208) siu_base+0x1de 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. when configured as gpi, the ibe bit should be set to one. se tting the ibe bit to zero reduces power consumption. table 280. siu_pcr207 pa values signal name module description i/o (1),(2) pa value gpio gpio[207] etrig1 siu gpio i/o 0b0 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1e0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys (3) src wpe wps w reset 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 1 = unimplemented or reserved 1. when configured as irq, the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as irq or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as irq, the hys bit should be set to one. table 281. siu_pcr208 pa values signal name module description i/o (1),(2) pa value primary pllref config selects fmpll mode after reset i 0b001 alt1 irq[4] siu external interrupt i 0b010 alt2 etrig2 siu triggers eqadc cfifo2 i 0b100 gpio gpio[208] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. system integration unit (siu) RM0029 530/1740 doc id 15177 rev 8 pad configuration register 209 (siu_pcr209) figure 303. pad configuration register (siu_pcr209) pad configuration register 210 (siu_pcr210) figure 304. pad configuration register (siu_pcr210) 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1e2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa obe (1) ibe (2) 0 0 ode hys (3) src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as irq, the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 2. when configured as irq or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. when configured as gpi, the ibe bit should be set to one. 3. when configured as irq, the hys bit should be set to one. table 282. siu_pcr209 pa values signal name module description i/o (1),(2) pa value pllcfg1 alt1 irq[5] siu external interrupt i 0b010 alt2 dspi_d_sout dspi output o 0b100 gpio gpio[209] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1e4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 = unimplemented or reserved 1. rstcfg function is only applicable during reset. the pa bit must be set to zero for gpio operation 2. when configured as gpo, the obe bit should be set to one. 3. when configured as gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. when configured as gpi, the ibe bit should be set to one. RM0029 system integration unit (siu) doc id 15177 rev 8 531/1740 pad configuration register 211 (siu_pcr211) figure 305. pad configuration register (siu_pcr211) pad configuration register 212 (siu_pcr212) table 283. siu_pcr210 pa values signal name module description i/o (1),(2) pa value primary rstcfg reset/config enable/disable pllref and bootcfg i 0b1 gpio gpio[210] siu gpio i/o 0b0 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1e6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys (4) src wpe wps w reset 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 = unimplemented or reserved 1. the bootcfg function applies only during reset when the rstcfg pin is asserted during reset. 2. when configured as irq, the obe bit has no effect. when configured as gpo, the obe bit should be set to one. 3. when configured as irq or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. when configured as gpi, the ibe bit should be set to one. 4. when configured as irq, the hys bit should be set to one. table 284. siu_pcr211 pa values signal name module description i/o (1),(2) pa value primary bootcfg[0] reset/config selects boot mode i 0b01 alt1 irq[2] siu external interrupt i 0b10 gpio gpio[211] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1e8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys (4) src wpe wps w reset 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 = unimplemented or reserved 1. the bootcfg function applies only during reset when the rstcfg pin is asserted during reset. 2. when configured as irq, the obe bit has no effect. when configured as gpo, the obe bit should be set to one. system integration unit (siu) RM0029 532/1740 doc id 15177 rev 8 figure 306. pad configuration register (siu_pcr212) pad configuration register 213 (siu_pcr213) figure 307. pad configuration register (siu_pcr213) 3. when configured as irq or gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. when configured as gpi, the ibe bit should be set to one. 4. when configured as irq, the hys bit should be set to one. table 285. siu_pcr212 pa values signal name module description i/o (1),(2) pa value primary bootcfg[1] reset/config selects boot mode i 0b001 alt1 irq[3] siu external interrupt i 0b010 alt2 etrig3 siu triggers eqadc cfifo3 i 0b100 gpio gpio[212] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1ea 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa (1) obe (2) ibe (3) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 1 = unimplemented or reserved 1. wkpcfg function is only applicable during reset. 2. when configured as gpo, the obe bit should be set to one. 3. when configured as gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. when configured as gpi, the ibe bit should be set to one. table 286. siu_pcr213 pa values signal name module description i/o (1),(2) pa value primary wkpcfg reset/config connects etpu and emios pins to internal weak pull-up or weak pull-down devices after reset i 0b001 alt1 nmi reset/config non-maskable interrupt i 0b010 alt2 dspi_b_sout dspi output o 0b100 gpio gpio[213] siu gpio i/o 0b000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 533/1740 pad configuration register 214 (siu_pcr214) the siu_pcr214 register controls the enabling/disabling and drive strength of the engclk pin. the engclk pin is enabled and disabled by setting and clearing the obe bit. the engclk pin is enabled during reset. figure 308. pad configuration register (siu_pcr214) pad configuration register 215 (siu_pcr215) figure 309. pad configuration register (siu_pcr215) siu_base+0x1ec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) 0 dsc ode hys 0 0 wpe wps w reset 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 = unimplemented or reserved 1. engclk is enabled/disabled by setting/clearing this bit. table 287. siu_pcr214 pa values signal name module description i/o (1),(2) pa value primary engclk clock generation engineering clock output o 0b001 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1ee 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 pa (1) 0 0 0 0 ode hys src wpe wps w reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. input and output buffers are enabled/disabled based on pa selection. both input and output buffer disabled for an[12] function. output buffer only enabled for ma[0], etpu and sds functions. table 288. siu_pcr215 pa values signal name module description i/o (1),(2) pa value primary an[12] eqadc analog input i 0b0001 alt1 ma[0] eqadc mux address o 0b0010 alt2 etpu_a[19] etpu etpu channel o 0b0100 gpio sds eqadc serial data select o 0b0000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. system integration unit (siu) RM0029 534/1740 doc id 15177 rev 8 pad configuration register 216 (siu_pcr216) figure 310. pad configuration register (siu_pcr216) pad configuration register 217 (siu_pcr217) figure 311. pad configuration register (siu_pcr217) 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1f0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 pa (1) 0 0 0 0 ode hys src wpe wps w reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. input and output buffers are enabled/disabled based on pa selection. both input and output buffer disabled for an[13] function. output buffer only enabled for ma[1], etpu and sdo functions. table 289. siu_pcr216 pa values signal name module description i/o (1),(2) pa value primary an[13] eqadc analog input i 0b0001 alt1 ma[1] eqadc mux address o 0b0010 alt2 etpu_a[21] etpu etpu channel o 0b0100 gpio sdo eqadc serial data output o 0b0000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1f2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 pa (1) 0 0 0 0 ode hys src wpe (2) wps (3) w reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. input and output buffers are enabled/disabled based on pa selection. both input and output buffer disabled for an[14] function. output buffer only enabled for ma[2] and etpu function and input buffer only enabled for sdi functions. 2. the wpe bit should be set to zero when configured as an analog input or ma[2], and set to one when configured as sdi. 3. the wps bit should be set to one when configured as sdi. RM0029 system integration unit (siu) doc id 15177 rev 8 535/1740 pad configuration register 218 (siu_pcr218) figure 312. pad configuration register (siu_pcr218) pad configuration register 219 (siu_pcr219) note: the siu_pcr219 register is unusual in that it controls pads for two separate device pins: gpio[219] and mcko. please carefully note the pin(s) affected by the bits in this register. table 290. siu_pcr217 pa values signal name module description i/o (1),(2) pa value primary an[14] eqadc analog input i 0b0001 alt1 ma[2] eqadc mux address o 0b0010 alt2 etpu_a[27] etpu etpu channel o 0b0100 gpio sdi eqadc serial data input i 0b0000 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x1f4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa (1) 0 0 0 0 ode hys src wpe wps w reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. input and output buffers are enabled/disabled based on pa selection. both input and output buffer disabled for an[15] function. output buffer only enabled for fck and etpu functions. table 291. siu_pcr218 pa values signal name module description i/o (1),(2) pa value primary an[15] eqadc analog input i 0b001 alt1 fck eqadc free-running clock o 0b010 alt2 etpu_a[29] etpu etpu channel o 0b100 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. system integration unit (siu) RM0029 536/1740 doc id 15177 rev 8 figure 313. pad configuration register (siu_pcr219) siu_base+0x1f6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 obe (1) ibe (2) dsc[1:0] ode hys src[1:0] wpe wps w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to 1. 2. when configured as gpo, the ibe bit may be set to one to reflect the pin state in the corresponding gpdi register. when configured as gpi, the ibe bit should be set to one. table 292. siu_pcr219 field descriptions field description 0?5 reserved 6 obe (1) output buffer enable enables the pad as an output and drives the output buffer enable signal. 0 disable output buffer for the pad. 1 enable output buffer for the pad is enabled. this field affects only the gpio[219] pin. 7 ibe (1) input buffer enable enables the pad as an input and drives the input buffer enable signal. 0 disable input buffer for the pad. 1 enable input buffer for the pad is enabled. for all pcrs where gpio function is available on the pin, if the pin is configured as an output and the ibe bit is set, the actual value of the pin will be reflected in the corresponding gpdi x _ x register. negating the ibe bit when the pin is configured as an output will reduce noise and power consumption. this field affects only the gpio[219] pin. 8?9 dsc[1:0] (2) drive strength control controls the pad drive strength. drive strength control pertains to pins with the fast i/o pad type. 00 10 pf drive strength 01 20 pf drive strength 10 30 pf drive strength 11 50 pf drive strength this field affects only the mcko pin. RM0029 system integration unit (siu) doc id 15177 rev 8 537/1740 10 ode (3) open drain output enable controls output driver configuration for the pads. either open drain or push/pull driver configurations can be selected. this feature applies to output pins only. 0 disable open drain for the pad (push/pull driver enabled). 1 enable open drain for the pad. this field affects both the gpio[219] and mcko pins. 11 hys (3) input hysteresis controls whether hysteresis is enabled for the pad. 0 disable hysteresis for the pad. 1 enable hysteresis for the pad. this field affects both the gpio[219] and mcko pins. 12?13 src[1:0] (3) slew rate control controls slew rate for the pad. slew rate control pertains to pins with slow or medium i/o pad types, and the output signals are driven according to the value of this field. actual slew rate depends on the pad type and load. refer to the electrical specifications for this information. 00 minimum slew rate 01 medium slew rate 10 invalid value 11 maximum slew rate this field affects only the gpio[219] pin. 14 wpe (4) weak pullup/down enable controls whether the weak pullup/down devices are enabled/disabled for the pad. pullup/down devices are enabled by default. 0 disable weak pull device for the pad. 1 enable weak pull device for the pad. this field affects both the gpio[219] and mcko pins. 15 wps (4) weak pullup/down select controls whether weak pullup or weak pulldown devices are used for the pad when weak pullup/down devices are enabled. the wkpcfg pin determines whether pullup or pulldown devices are enabled during reset. the wps bit determines whether weak pullup or pulldown devices are used after reset, or for pads in which the wkpcfg pin does not determine the reset weak pullup/down state. 0 pulldown is enabled for the pad. 1 pullup is enabled for the pad. this field affects both the gpio[219] and mcko pins. 1. in cases where an i/o function is either input-only or output-only the ibe and obe bits do not need to be set to enable pin i/o. table 292. siu_pcr219 field descriptions (continued) field description system integration unit (siu) RM0029 538/1740 doc id 15177 rev 8 pad configuration register 220 (siu_pcr220) figure 314. pad configuration register (siu_pcr220) pad configuration register 221 (siu_pcr221) figure 315. pad configuration register (siu_pcr221) pad configuration register 222 (siu_pcr222) 2. if a pin is configured as an input, the ode, src, and dsc bits do not apply. 3. if a pin is configured as an output, the hys bit does not apply. 4. when a pin is configured as an output, the weak internal pull up/down is disabled regardless of the wpe or wps settings in the pcr. siu_base+0x1f8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 dsc ode hys 0 wpe wps w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 = unimplemented or reserved table 293. siu_pcr220 pa values signal name module description i/o pa value primary mdo0 nexus nexus message data out o ? siu_base+0x1fa 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 dsc ode hys 0 wpe wps w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 = unimplemented or reserved table 294. siu_pcr221 pa values signal name module description i/o pa value primary mdo1 nexus nexus message data out o ? RM0029 system integration unit (siu) doc id 15177 rev 8 539/1740 figure 316. pad configuration register (siu_pcr222) pad configuration register 223 (siu_pcr223) figure 317. pad configuration register (siu_pcr223) pad configuration register 224 (siu_pcr224) figure 318. pad configuration register (siu_pcr224) siu_base+0x1fc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 dsc ode hys 0 wpe wps w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 = unimplemented or reserved table 295. siu_pcr222 pa values signal name module description i/o pa value primary mdo2 nexus nexus message data out o ? siu_base+0x1fe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 dsc ode hys 0 wpe wps w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 = unimplemented or reserved table 296. siu_pcr223 pa values signal name module description i/o pa value primary mdo3 nexus nexus message data out o ? siu_base+0x200 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 297. siu_pcr224 pa values signal name module description i/o pa value primary mseo0 nexus nexus message start/end out o ? system integration unit (siu) RM0029 540/1740 doc id 15177 rev 8 pad configuration register 225 (siu_pcr225) figure 319. pad configuration register (siu_pcr225) pad configuration register 226 (siu_pcr226) figure 320. pad configuration register (siu_pcr226) pad configuration register 227 (siu_pcr227) figure 321. pad configuration register (siu_pcr227) siu_base+0x202 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 298. siu_pcr225 pa values signal name module description i/o pa value primary mseo1 nexus nexus message start/end out o ? siu_base+0x204 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 299. siu_pcr226 pa values signal name module description i/o pa value primary rdy nexus read/write ready o ? siu_base+0x206 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe ibe 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 = unimplemented or reserved RM0029 system integration unit (siu) doc id 15177 rev 8 541/1740 pad configuration register 228 (siu_pcr228) figure 322. pad configuration register (siu_pcr228) pad configuration register 229 (siu_pcr229) the siu_pcr229 register controls the enabling/disabling and drive strength of the clkout pin. the clkout pin is enabled and disabled by setting and clearing the obe bit. the clkout pin is enabled during reset. figure 323. pad configuration register (siu_pcr229) pad configuration register 230 (siu_pcr230) table 300. siu_pcr227 pa values signal name module description i/o pa value primary evto nexus nexus event out o ? siu_base+0x208 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 src 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 301. siu_pcr228 pa values signal name module description i/o pa value primary tdo jtag nexus event out o 01 siu_base+0x20a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) 0 dsc ode hys 0 0 wpe wps w reset 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 = unimplemented or reserved 1. clkout pin is enabled and disabled by setting and clearing the obe bit. table 302. siu_pcr229 pa values signal name module description i/o (1),(2) pa value primary clkout clock generation system clock output o 0b001 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. system integration unit (siu) RM0029 542/1740 doc id 15177 rev 8 figure 324. pad configuration register (siu_pcr230) pad configuration register 231 (siu_pcr231) figure 325. pad configuration register (siu_pcr231) pad configuration register 232 (siu_pcr232) figure 326. pad configuration register (siu_pcr232) siu_base+0x20c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 = unimplemented or reserved table 303. siu_pcr230 pa values signal name module description i/o pa value primary rstout reset external reset output o 0b001 siu_base+0x20e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved table 304. siu_pcr231 pa values signal name module description i/o pa value primary evti nexus nexus event in i ? siu_base+0x210 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 src 0 0 w reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 305. siu_pcr232 pa values signal name module description i/o pa value primary tdi jtag nexus event in i 01 RM0029 system integration unit (siu) doc id 15177 rev 8 543/1740 pad configuration register 244 (siu_pcr244) figure 327. pad configuration register (siu_pcr244) pad configuration register 245 (siu_pcr245) figure 328. pad configuration register (siu_pcr245) siu_base+0x228 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. w hen configured as gpi, the ibe bit should be set to one. table 306. siu_pcr244 pa values signal name module description i/o (1),(2) pa value primary sci_c_tx esci esci c transmit o 0b01 gpio gpio[244] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x22a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pa obe (1) ibe (2) 0 0 ode hys src wpe wps w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 = unimplemented or reserved 1. when configured as gpo, the obe bit should be set to one. 2. when configured as gpo, the ibe bit may be set to one to refl ect the pin state in the corresponding gpdi register. setting the ibe bit to zero reduces power consumption. w hen configured as gpi, the ibe bit should be set to one. table 307. siu_pcr245 pa values signal name module description i/o (1),(2) pa value primary sci_c_rx esci esci c receive i 0b01 gpio gpio[245] siu gpio i/o 0b00 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. system integration unit (siu) RM0029 544/1740 doc id 15177 rev 8 pad configuration register 336 (siu_pcr336) figure 329. pad configuration register (siu_pcr336) pad configuration register 338 (siu_pcr338) figure 330. pad configuration register (siu_pcr338) pad configuration register 339 (siu_pcr339) siu_base+0x2e0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 dsc ode hys 0 0 wpe wps w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 = unimplemented or reserved table 308. siu_pcr336 pa values signal name module description i/o pa value primary cal_cs0 calibration bus calibration chip select o ? siu_base+0x2e4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0pa 0 0 dsc ode hys 0 0 wpe wps w reset 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 = unimplemented or reserved table 309. siu_pcr338 pa values signal name module description i/o (1),(2) pa value primary cal_cs2 calibration bus calibration chip select o 001 alt1 cal_addr[10] calibration bus calibration address bus i/o 010 alt2 cal_we[2]/be[2] calibration bus calibration write/byte enable o 100 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. RM0029 system integration unit (siu) doc id 15177 rev 8 545/1740 figure 331. pad configuration register (siu_pcr339) pad configuration register 340 (siu_pcr340) note: unlike other pad configuration registers (pcrs), which control the function and electrical characteristics of one pin, this register controls the function and electrical characteristics for a group of pins on the calibration bus. figure 332. pad configuration register (siu_pcr340) siu_base+0x2e6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0pa 0 0 dsc ode hys 0 0 wpe wps w reset 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 = unimplemented or reserved table 310. siu_pcr339 pa values signal name module description i/o (1),(2) pa value primary cal_cs3 calibration bus calibration chip select o 001 alt1 cal_addr[11] calibration bus calibration address bus i/o 010 alt2 cal_we[3]/be[3] calibration bus calibration write/byte enable o 100 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. siu_base+0x2e8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0pa 0 0 dsc ode hys 0 0 wpe wps w reset 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 = unimplemented or reserved table 311. siu_pcr340 pa values signal name module description i/o (1),(2) pa value primary cal_addr[12:15] calibration bus calibration address bus i/o 001 alt1 cal_we[2]/be[2] calibration write/byte enable o 010 cal_we3]/be[3] calibration write/byte enable o cal_data[31] calibration data bus i/o cal_ale calibration address latch enable o 1. in cases where an i/o function can be either an input or an output, i/o direction is specified using the ibe and obe bits. se t ibe = 1 for input or obe = 1 for output. 2. for i/o functions that change direction dynamically, such as the external data bus, switching between input and output is handled internally and the ibe and obe bits are ignored. system integration unit (siu) RM0029 546/1740 doc id 15177 rev 8 pad configuration register 341 (siu_pcr341) note: unlike other pad configuration registers (pcrs), which control the function and electrical characteristics of one pin, this register controls the electrical characteristics for a group of pins on the calibration bus. figure 333. pad configuration register (siu_pcr341) pad configuration register 342 (siu_pcr342) note: unlike other pad configuration registers (pcrs), which control the function and electrical characteristics of one pin, this register controls the function and electrical characteristics for a group of pins on the calibration bus. figure 334. pad configuration register (siu_pcr342) siu_base+0x2ea 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 dsc ode hys 0 0 wpe wps w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 = unimplemented or reserved table 312. siu_pcr341pa values signal name module description i/o pa value primary cal_data[0:15] calibration bus calibration data bus i/o ? siu_base+0x2ec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 dsc ode hys 0 0 wpe wps w reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 = unimplemented or reserved table 313. siu_pcr342 pa values signal name module description i/o pa value primary cal_rd_wr calibration bus calibration data bus i/o ? cal_we[0]/be[0] calibration write/byte enable cal_we[1]/be[1] calibration write/byte enable cal_oe calibration output enable RM0029 system integration unit (siu) doc id 15177 rev 8 547/1740 pad configuration register 343 (siu_pcr343) figure 335. pad configuration register (siu_pcr343) pad configuration register 345 (siu_pcr345) note: unlike other pad configuration registers (pcrs), which control the function and electrical characteristics of one pin, this register controls the function and electrical characteristics for a group of pins on the calibration bus. figure 336. pad configuration register (siu_pcr345) pad configuration register 350 ? 381 (siu_pcr350 ? siu_pcr381) the siu_pcr350 ? siu_pcr381 registers control the muxing of the signals to the dspi. pa field values are shown in table 316 . siu_base+0x2ee 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0pa 0 0 dsc ode hys 0 0 wpe wps w reset 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 = unimplemented or reserved table 314. siu_pcr343 pa values signal name module description i/o pa value primary cal_ts calibration bus calibration transfer start o 01 alt1 cal_ale calibration bus address latch enabl eo10 siu_base+0x2f2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0pa 0 0 dsc ode hys 0 0 wpe wps w reset 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 = unimplemented or reserved table 315. siu_pcr345 pa values signal name module description i/o pa value primary cal_addr[16:30] calibration bus calibration address bus i/o 01 alt1 cal_data[16:30] calibration bus calibration data bus i/o 10 system integration unit (siu) RM0029 548/1740 doc id 15177 rev 8 figure 337. pad configuration register 350 ? 381 (siu_pcr350 ? siu_pcr381) siu_base+0x2fc ? siu_base+0x33a (32) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 316. siu_pcr350 ? siu_pcr381 dspi muxing register address offset from siu_base dspi serialize signal name pa value 0b001 0b100 0b010 0b000 siu_pcr350 0x2fc dspi_b -dsi0 etpu_a_23 ? emios_11 gpio350 siu_pcr351 0x2fe dspi_b -dsi1 etpu_a_22 ? emios_10 gpio351 siu_pcr352 0x300 dspi_b -dsi2 etpu_a_21 ? emios_9 gpio352 siu_pcr353 0x302 dspi_b -dsi3 etpu_a_20 ? emios_8 gpio353 siu_pcr354 0x304 dspi_b -dsi4 etpu_a_19 ? emios_6 gpio354 siu_pcr355 0x306 dspi_b -dsi5 etpu_a_18 ? emios_5 gpio355 siu_pcr356 0x308 dspi_b -dsi6 etpu_a_17 ? emios_4 gpio356 siu_pcr357 0x30a dspi_b -dsi7 etpu_a_16 ? emios_3 gpio357 siu_pcr358 0x30c dspi_b -dsi8 etpu_a_29 ? emios_2 gpio358 siu_pcr359 0x30e dspi_b -dsi9 etpu_a_28 ? emios_1 gpio359 siu_pcr360 0x310 dspi_b -dsi10 etpu_a_27 ? emios_0 gpio360 siu_pcr361 0x312 dspi_b -dsi11 etpu_a_26 ? emios_23 gpio361 siu_pcr362 0x314 dspi_b -dsi12 etpu_a_25 ? emios_15 gpio362 siu_pcr363 0x316 dspi_b -dsi13 etpu_a_24 ? emios_14 gpio363 siu_pcr364 0x318 dspi_b -dsi14 etpu_a_31 ? emios_13 gpio364 siu_pcr365 0x31a dspi_b -dsi15 etpu_a_30 ? emios_12 gpio365 siu_pcr366 0x31c dspi_b -dsi16 etpu_a_12 ? emios_23 gpio366 siu_pcr367 0x31e dspi_b -dsi17 etpu_a_13 ? emios_15 gpio367 siu_pcr368 0x320 dspi_b -dsi18 etpu_a_14 ? emios_14 gpio368 siu_pcr369 0x322 dspi_b -dsi19 etpu_a_15 ? emios_13 gpio369 siu_pcr370 0x324 dspi_b -dsi20 etpu_a_0 ? emios_12 gpio370 siu_pcr371 0x326 dspi_b -dsi21 etpu_a_1 ? emios_11 gpio371 siu_pcr372 0x328 dspi_b -dsi22 etpu_a_2 ? emios_10 gpio372 siu_pcr373 0x32a dspi_b -dsi23 etpu_a_3 ? emios_9 gpio373 siu_pcr374 0x32c dspi_b -dsi24 etpu_a_4 ? emios_8 gpio374 siu_pcr375 0x32e dspi_b -dsi25 etpu_a_5 ? emios_6 gpio375 RM0029 system integration unit (siu) doc id 15177 rev 8 549/1740 pad configuration register 382 ? 389 (siu_pcr382 ? siu_pcr389) the siu_pcr382 ? siu_pcr389 registers control the muxing of the signals to the dspi. pa field values are shown in table 317 . figure 338. pad configuration register 382 ? 389 (siu_pcr382 ? siu_pcr389) pad configuration register 390 ? 413 (siu_pcr390 ? siu_pcr413) the siu_pcr390 ? siu_pcr413 registers control the muxing of the signals to the dspi. pa field values are shown in table 318 . siu_pcr376 0x330 dspi_b -dsi26 etpu_a_6 ? emios_5 gpio376 siu_pcr377 0x332 dspi_b -dsi27 etpu_a_7 ? emios_4 gpio377 siu_pcr378 0x334 dspi_b -dsi28 etpu_a_8 ? emios_3 gpio378 siu_pcr379 0x336 dspi_b -dsi29 etpu_a_9 ? emios_2 gpio379 siu_pcr380 0x338 dspi_b -dsi30 etpu_a_10 ? emios_1 gpio380 siu_pcr381 0x33a dspi_b -dsi31 etpu_a_11 ? emios_0 gpio381 table 316. siu_pcr350 ? siu_pcr381 dspi muxing (continued) register address offset from siu_base dspi serialize signal name pa value 0b001 0b100 0b010 0b000 siu_base+0x33c ? siu_base+0x34a (8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 pa 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 317. siu_pcr382 ? siu_pcr389 dspi muxing register address offset from siu_base dspi serialize signal name pa value 0b001 0b100 0b010 0b000 siu_pcr382 0x33c dspi_c -dsi0 etpu_a_12 emios_7 emios_12 gpio382 siu_pcr 383 0x33e dspi_c -dsi1 e tpu_a_13 emios_16 emios_13 gpio383 siu_pcr 384 0x340 dspi_c -dsi2 e tpu_a_14 emios_17 emios_14 gpio384 siu_pcr 385 0x342 dspi_c -dsi3 e tpu_a_15 emios_18 emios_15 gpio385 siu_pcr 386 0x344 dspi_c -dsi4 etpu_a_0 emios_19 emios_23 gpio386 siu_pcr 387 0x346 dspi_c -dsi5 etpu_a_1 emios_20 emios_0 gpio387 siu_pcr 388 0x348 dspi_c -dsi6 etpu_a_2 emios_21 emios_1 gpio388 siu_pcr 389 0x34a dspi_c -dsi7 etpu_a_3 emios_22 emios_2 gpio389 system integration unit (siu) RM0029 550/1740 doc id 15177 rev 8 figure 339. pad configuration register 390 ? 413 (siu_pcr390 ? siu_pcr413) siu_base+0x34c ? siu_base+0x37a (24) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pa 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 318. siu_pcr390 ? siu_pcr413 dspi muxing register address offset from siu_base dspi serialize signal name pa value 0b001 0b100 0b010 0b000 siu_pcr 390 0x34c dspi_c -dsi8 etpu_a_4 ? emios_3 gpio390 siu_pcr 391 0x34e dspi_c -dsi9 etpu_a_5 ? emios_4 gpio391 siu_pcr 392 0x350 dspi_c - dsi10 etpu_a_6 ? emios_5 gpio392 siu_pcr 393 0x352 dspi_c -dsi11 etpu_a_7 ? emios_6 gpio393 siu_pcr 394 0x354 dspi_c - dsi12 etpu_a_8 ? emios_8 gpio394 siu_pcr 395 0x356 dspi_c - dsi13 etpu_a_9 ? emios_9 gpio395 siu_pcr 396 0x358 dspi_c - dsi14 etpu_a_10 ? emios_10 gpio396 siu_pcr 397 0x35a dspi_c - dsi15 etpu_a_11 ? emios_11 gpio397 siu_pcr 398 0x35c dspi_c - dsi16 etpu_a_23 ? emios_0 gpio398 siu_pcr 399 0x35e dspi_c - dsi17 etpu_a_22 ? emios_1 gpio399 siu_pcr 400 0x360 dspi_c - dsi18 etpu_a_21 ? emios_2 gpio400 siu_pcr 401 0x362 dspi_c - dsi19 etpu_a_20 ? emios_3 gpio401 siu_pcr 402 0x364 dspi_c - dsi20 etpu_a_19 ? emios_4 gpio402 siu_pcr 403 0x366 dspi_c - dsi21 etpu_a_18 ? emios_5 gpio403 siu_pcr 404 0x368 dspi_c - dsi22 etpu_a_17 ? emios_6 gpio404 siu_pcr 405 0x36a dspi_c - dsi23 etpu_a_16 ? emios_8 gpio405 siu_pcr 406 0x36c dspi_c - dsi24 etpu_a_29 ? emios_9 gpio406 RM0029 system integration unit (siu) doc id 15177 rev 8 551/1740 16.6.16 gpio pin data output registers (siu_gpdo0_3 ? siu_gpdo412_413) the siu_gpdo x _ x registers are written to by software to drive data out on the external gpio pin. each byte of a register drives a single external gpio pin, which allows the state of the pin to be controlled independently from other gpio pins. writes to the siu_gpdo x _ x registers have no effect on pin states if the pins are configured as inputs by the associated pad configuration registers. the siu_gpdo x _ x register values are automatically driven to the gpio pins without software update if the direction of the gpio pins is changed from input to output. writes to the siu_gpdo x _ x registers have no effect on the state of the corresponding pins when the pins are configured for their primary function by the corresponding pcr. the definition of the siu_gpdo x _ x registers is given in figure 340 and figure 341 . each of the pdo bits corresponds to the pin with the same gpio pin number. for example, pdo0 is the pin data output bit for the cs [0]_addr[8]_gpio[0] pin, and pdo213 is the pin data output bit for the wkpcfg_gpio[213] pin. gaps exist in this memory space where the pin is not available in the package. siu_pcr 407 0x36e dspi_c - dsi25 etpu_a_28 ? emios_10 gpio407 siu_pcr 408 0x370 dspi_c - dsi26 etpu_a_27 ? emios_11 gpio408 siu_pcr 409 0x372 dspi_c - dsi27 etpu_a_26 ? emios_12 gpio409 siu_pcr 410 0x374 dspi_c - dsi28 etpu_a_25 ? emios_13 gpio410 siu_pcr 411 0x376 dspi_c - dsi29 etpu_a_24 ? emios_14 gpio411 siu_pcr 412 0x378 dspi_c - dsi30 etpu_a_31 ? emios_15 gpio412 siu_pcr 413 0x37a dspi_c - dsi31 etpu_a_30 ? emios_23 gpio413 table 318. siu_pcr390 ? siu_pcr413 dspi muxing (continued) register address offset from siu_base dspi serialize signal name pa value 0b001 0b100 0b010 0b000 siu_base + 0x600 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 pdo 0 0 0 0 0 0 0 0 pdo 1 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 pdo 2 0 0 0 0 0 0 0 pdo 3 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved system integration unit (siu) RM0029 552/1740 doc id 15177 rev 8 figure 340. gpio pin data out register 0 ? 3 (siu_gpdo0 ? siu_gpdo3) figure 341. gpio pin data out register 412 ? 413 (siu_gpdo410 ? siu_gpdo413) 16.6.17 gpio pin data input registers (siu_gpdi0_3 ? siu_gpdi_232) the siu_gpdi x _ x registers are read-only registers that allow software to read the input state of an external gpio pin. each byte of a register represents the input state of a single external gpio pin. if the gpio pin is configured as an output, and the input buffer enable (ibe) bit is set in the associated pad configuration register, the siu_gpdi x _ x register reflects the actual state of the output pin. the definition of the siu_gpdi x _ x registers is given in figure 342 and figure 343 . each of the gpdi bits corresponds to the pin with the same gpio pin number. for example, gpdi0 is the pin data input bit for the cs [0]_gpio[0] pin, and pdi213 is the pin data input bit for the wkpcfg_gpio[213] pin. gaps exist in this memory space where the pin is not available in the package. ssiu_base + 0x79d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 pdo 412 0 0 0 0 0 0 0 pdo 413 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 319. siu_gpdox_x field description field description pdox pin data out. this bit stores the data to be driven out on the external gpio pin associated with the register. 0 vol is driven on the external gpio pin when the pin is configured as an output. 1 voh is driven on the external gpio pin when the pin is configured as an output. RM0029 system integration unit (siu) doc id 15177 rev 8 553/1740 figure 342. gpio pin data in register 0 ? 3 (siu_gpdi0 ? siu_gpdi3) figure 343. gpio pin data in register 230 ? 232 (siu_gpdi230 ? siu_gpdi232) 16.6.18 eqadc trigger input select register (siu_etisr (l) ) the eqadc trigger input select register (siu_etisr) selects the source for the eqadc trigger inputs. the fields in this register operate in conjunction with the corresponding fields in the siu_isel3 register. each field in the siu_etisr offers direct selection of three signals to be used as a trigger to a eqadc cfifo queue. the tsel5 field is used to select the trigger source for eqadc cfifo5, the tsel4 field selects the trigger source for eqadc cfifo4, siu_base + 0x800 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 pdi 0 0 0 0 0 0 0 0 pdi 1 w reset 0 0 0 0 0 0 0 u 0 0 0 0 0 0 0 u 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 pdi 2 0 0 0 0 0 0 0 pdi 3 w reset 0 0 0 0 0 0 0 u 0 0 0 0 0 0 0 u = unimplemented or reserved siu_base + 0x8ea 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 pdi 230 0 0 0 0 0 0 0 pdi 231 w reset 0 0 0 0 0 0 0 u 0 0 0 0 0 0 0 u 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 pdi 232 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 u 0 0 0 0 0 0 0 0 = unimplemented or reserved table 320. siu_gpdix_x field description field description pdix pin data in. this bit stores the input state on the external gpio pin associated with the register. 0 signal on pin is less than or equal to vil. 1 signal on pin is greater than or equal to vih. l.the etisr is sometimes referred to as isel0 system integration unit (siu) RM0029 554/1740 doc id 15177 rev 8 and so on. additionally, each siu_etisr field offers selection among a group of signals using the corresponding field in the siu_isel3 register. figure 344 illustrates the available trigger selections for eqadc cfifo5. figure 344. trigger selection for eqadc cfifo queue 5 as shown in the above figure, the tsel5 field can be used to select the etpu_a[26], emios[12] or gpio[207] signal or, by assigning a value of 0b00 to the tsel5 field, a variety of other signals can be selected using the etsel5 field of the siu_isel3 register. figure 345. eqadc trigger input select register (siu_etisr) siu_etisr[tsel5] 00 01 10 11 e t p u _ a [ 2 6 ] e m i o s [ 1 2 ] e t r i g [ 1 ] siu_isel3[etsel5] p i t 1 t r i g g e r p i t 3 t r i g g e r e t p u [ 3 0 ] a n d p i t 1 to eqadc external trigger input 5 (affects eqadc queue 5) p i t 2 t r i g g e r e t p u 3 0 a n d p i t 0 e t p u [ 2 9 ] e t r i g 2 p in e t p u [ 2 8 ] e t p u [ 3 1 ] r t i t r i g g e r p i t 0 t r i g g e r g p i o [ 2 0 7 ] e m i o s [ 1 0 ] a n d p i t 3 e m i o s [ 2 3 ] e t p u [ 3 0 ] e m i o s [ 1 0 ] a n d p i t 2 siu_base+0x900 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r tsel5 tsel4 tsel3 tsel2 tsel1 tsel0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved RM0029 system integration unit (siu) doc id 15177 rev 8 555/1740 16.6.19 external irq input select register (siu_eiisr (m) ) the eiisr selects the source for the external interrupt/dma inputs. table 321. siu_etisr field description field description 0:1 tsel5 eqadc trigger input select 5. the eqadc trigger 5 input is as follows: 00 etsel5 (described in siu_isel3) 01 etpu_a[26] channel 10 emios[12] channel 11 etrig[1] pin 2:3 tsel4 eqadc trigger input select 4. the eqadc trigger 4 input is as follows: 00 etsel4 (described in siu_isel3) 01 etpu_a[27] channel 10 emios[13] channel 11 etrig[0] pin 4:5 tsel3 eqadc trigger input select 3. the eqadc trigger 3 input is as follows: 00 etsel3 (described in siu_isel3) 01 etpu_a[28] channel 10 emios[14] channel 11 etrig[1] pin 6:7 tsel2 eqadc trigger input select 2. the eqadc trigger 2 input is as follows: 00 etsel2 (described in siu_isel3) 01 etpu_a[29] channel 10 emios[15] channel 11 etrig[0] pin 8:9 tsel1 eqadc trigger input select 1. the eqadc trigger 1 input is as follows: 00 etsel1 (described in siu_isel3) 01 etpu_a[31] channel 10 emios[11] channel 11 etrig[1] pin 10:11 tsel0 eqadc trigger input select 0. the eqadc trigger 0 input is as follows: 00 etsel0 (described in siu_isel3) 01 etpu_a[30] channel 10 emios[10] channel 11 etrig[0] pin 12:31 reserved m. the eiisr is sometimes referred to as isel1 system integration unit (siu) RM0029 556/1740 doc id 15177 rev 8 figure 346. external irq input select register (siu_eiisr) siu_base+0x904 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r esel15 esel14 esel13 esel12 esel11 esel10 esel9 esel8 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r esel7 esel6 esel5 esel4 esel3 esel2 esel1 esel0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 322. siu_eiisr field description field description 0:1 esel15 external irq input select 15. irq[15] input is specified by esel15 as follows: 00 irq[15] pin 01 dspi_b[15] deserialized output 10 dspi_c[0] deserialized output 11 dspi_d[1] deserialized output 2:3 esel14 external irq input select 14. irq[14] input is specified by esel14 as follows: 00 irq[14] pin 01 dspi_b[14] deserialized output 10 dspi_c[15] deserialized output 11 dspi_d[0] deserialized output 4:5 esel13 external irq input select 13. irq[13] input is specified by esel13 as follows: 00 irq[13] pin 01 dspi_b[13] deserialized output 10 dspi_c[14] deserialized output 11 dspi_d[15] deserialized output 6:7 esel12 external irq input select 12. irq[12] input is specified by esel12 as follows: 00 irq[12] pin 01 dspi_b[12] deserialized output 10 dspi_c[13] deserialized output 11 dspi_d[14] deserialized output 8:9 esel11 external irq input select 11. irq[11] input is specified by esel11 as follows: 00 irq[11] pin 01 dspi_b[11] deserialized output 10 dspi_c[12] deserialized output 11 dspi_d[13] deserialized output 10:11 esel10 external irq input select 10. irq[10] input is specified by esel10 as follows: 00 irq[10] pin 01 dspi_b[10] deserialized output 10 dspi_c[11] deserialized output 11 dspi_d[12] deserialized output RM0029 system integration unit (siu) doc id 15177 rev 8 557/1740 12:13 esel9 external irq input select 9. irq[9] input is specified by esel9 as follows: 00 irq[9] pin 01 dspi_b[9] deserialized output 10 dspi_c[10] deserialized output 11 dspi_d[11] deserialized output 14:15 esel8 external irq input select 8. irq[8] input is specified by esel8 as follows: 00 irq[8] pin 01 dspi_b[8] deserialized output 10 dspi_c[9] deserialized output 11 dspi_d[10] deserialized output 16:17 esel7 external irq input select 7. irq[7] input is specified by esel7 as follows: 00 irq[7] pin 01 dspi_b[7] deserialized output 10 dspi_c[8] deserialized output 11 dspi_d[9] deserialized output 18:19 esel6 external irq input select 6. irq[6] is multiplexed on the tcrclk_b pin, which is not available in any of the spc564a74xx, spc564a80xx packages. irq[6] input is specified by esel6 as follows: 00 irq[6] pin 01 dspi_b[6] deserialized output 10 dspi_c[7] deserialized output 11 dspi_d[8] deserialized output 20:21 esel5 external irq input select 5. irq[5] input is specified by esel5 as follows: 00 irq[5] pin 01 dspi_b[5] deserialized output 10 dspi_c[6] deserialized output 11 dspi_d[7] deserialized output 22:23 esel4 external irq input select 4. irq[4] input is specified by esel4 as follows: 00 irq[4] pin 01 dspi_b[4] deserialized output 10 dspi_c[5] deserialized output 11 dspi_d[6] deserialized output 24:25 esel3 external irq input select 3. irq[3] input is specified by esel3 as follows: 00 irq[3] pin 01 dspi_b[3] deserialized output 10 dspi_c[4] deserialized output 11 dspi_d[5] deserialized output 26:27 esel2 external irq input select 2. irq[2] input is specified by esel2 as follows: 00 irq[2] pin 01 dspi_b[2] deserialized output 10 dspi_c[3] deserialized output 11 dspi_d[4] deserialized output table 322. siu_eiisr field description (continued) field description system integration unit (siu) RM0029 558/1740 doc id 15177 rev 8 16.6.20 dspi input select register (siu_disr (n) ) the disr specifies the source of each dspi data input, slave select, clock input, and trigger input to allow serial and parallel chaining of the dspi blocks. figure 347. dspi input select register (siu_disr) 28:29 esel1 external irq input select 1. irq[1] input is specified by esel1 as follows: 00 irq[1] pin 01 dspi_b[1] deserialized output 10 dspi_c[2] deserialized output 11 emios[15] 30:31 esel0 external irq input select 0. irq[0] input is specified by esel0 as follows: 00 irq[0] pin 01 dspi_b[0] deserialized output 10 dspi_c[1] deserialized output 11 emios[14] n. the disr is sometimes referred to as isel2 table 322. siu_eiisr field description (continued) field description siu_base+0x908 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 sinselb ssselb sckselb trigselb w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sinselc ssselc sckselc trigselc sinseld ssseld sckseld trigseld w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 323. siu_disr field description field description 0:7 reserved 8:9 sinselb dspi_b data input select. the source of the data input of dspi_b is specified by sinselb as follows: 00 dspi_b_sin pin 01 reserved 10 dspi_c_sout 11 dspi_d_sout RM0029 system integration unit (siu) doc id 15177 rev 8 559/1740 10:11 ssselb dspi_b slave select input select. the source of the slave select input of dspi_b is specified by ssselb as follows: 00 dspi_b_pcs[0] pin 01 reserved 10 dspi_c_pcs[0] (master) 11 dspi_d_pcs[0] (master) 12:13 sckselb dspi_b clock input select. the source of the clock input of dspi_b when in slave mode is specified by sckselb as follows: 00 dspi_b_sck pin 01 reserved 10 dspi_c_sck (master) 11 dspi_d_sck (master) 14:15 trigselb dspi_b trigger input select. the source of the trigger input of dspi_b for master or slave mode is specified by trigselb as follows: 00 reserved 01 reserved 10 dspi_c_pcs[4] 11 dspi_d_pcs[4] 16:17 sinselc dspi_c data input select. the source of the data input of dspi_c is specified by sinselc as follows: 00 dspi_c_sin pin 01 reserved 10 dspi_b_sout 11 dspi_d_sout 18:19 ssselc dspi_c slave select input select. the source of the slave select input of dspi_c is specified by ssselc as follows: 00 dspi_c_pcs[0] pin 01 reserved 10 dspi_b_pcs[0] (master) 11 dspi_d_pcs[0] (master) 20:21 sckselc dspi_c clock input select. the source of the clock input of dspi_c when in slave mode is specified by sckselc as follows: 00 dspi_c_sck pin 01 reserved 10 dspi_b_sck (master) 11 dspi_d_sck (master) 22:23 trigselc dspi_c trigger input select. the source of the trigger input of dspi_c for master or slave mode is specified by trigselc as follows: 00 reserved 01 reserved 10 dspi_b_pcs[4] 11 dspi_d_pcs[4] 24:25 sinseld dspi_d data input select. the source of the data input of dspi_d is specified by sinseld as follows: 00 dspi_d_sin pin 01 reserved 10 dspi_b_sout 11 dspi_c_sout table 323. siu_disr field description (continued) field description system integration unit (siu) RM0029 560/1740 doc id 15177 rev 8 16.6.21 imux select register 3 (siu_isel3) the siu_isel 3 register selects the source for the external eqadc trigger inputs. figure 348. imux select register 3 (siu_isel3) for options 0b01000, 0b01001, 0b10100, 0b10101 for each queue, two trigger sources are logically anded together. the intention is that the pit provides the regular cyclic trigger, while the etpu or emios channels are used to ?gate? that cyclic trigger. this way, the adc can be commanded to make regular samples but only during a given time or angle window. 26:27 ssseld dspi_d slave select input select. the source of the slave select input of dspi_d is specified by ssseld as follows: 00 dspi_d_pcs[0] pin 01 reserved 10 dspi_b_pcs[0] (master) 11 dspi_c_pcs[0] (master) 28:29 sckseld dspi_d clock input select. the source of the clock input of dspi_d when in slave mode is specified by sckseld as follows: 00 dspi_d_sck pin 01 reserved 10 dspi_b_sck (master) 11 dspi_c_sck (master) 30:31 trigseld dspi_d trigger input select. the source of the trigger input of dspi_d for master or slave mode is specified by trigseld as follows: 00 reserved 01 reserved 10 dspi_b_pcs[4] 11 dspi_c_pcs[4] table 323. siu_disr field description (continued) field description siu_base+0x90c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 etsel5 etsel4 etsel3 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r etsel 3 etsel2 etsel1 etsel0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved RM0029 system integration unit (siu) doc id 15177 rev 8 561/1740 table 324. eqadc queue0 enhanced trigger selection etsel0 eqadc enhanced trigger input 0 0 0 0 0 gpio206 (etrig0) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 0 0 1 1 0 reserved 0 0 1 1 1 bootcfg[1] (etrig3) 0 1 0 0 0 etpu30 and pit0 0 1 0 0 1 etpu30 and pit1 0 1 0 1 0 reserved 0 1 0 1 1 reserved 01100 etpu28 01101 etpu29 01110 etpu30 01111 etpu31 1 0 0 0 0 reserved 1 0 0 0 1 reserved 1 0 0 1 0 reserved 1 0 0 1 1 reserved 1 0 1 0 0 emios10 and pit2 1 0 1 0 1 emios10 and pit3 1 0 1 1 0 reserved 1 0 1 1 1 reserved 1 1 0 0 0 reserved 1 1 0 0 1 reserved 1 1 0 1 0 reserved 1 1 0 1 1 reserved 1 1 1 0 0 reserved 1 1 1 0 1 reserved 1 1 1 1 0 reserved 11111 emios23 system integration unit (siu) RM0029 562/1740 doc id 15177 rev 8 table 325. eqadc queue1 enhanced trigger selection etsel1 eqadc enhanced trigger input 0 0 0 0 0 gpio207 (etrig1) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 0 0 1 1 0 reserved 0 0 1 1 1 pllref (etrig2) 0 1 0 0 0 etpu31 and pit0 0 1 0 0 1 etpu31 and pit1 0 1 0 1 0 reserved 0 1 0 1 1 reserved 01100 etpu28 01101 etpu29 01110 etpu30 01111 etpu31 1 0 0 0 0 reserved 1 0 0 0 1 reserved 1 0 0 1 0 reserved 1 0 0 1 1 reserved 1 0 1 0 0 emios11 and pit2 1 0 1 0 1 emios11 and pit3 1 0 1 1 0 reserved 1 0 1 1 1 reserved 1 1 0 0 0 reserved 1 1 0 0 1 reserved 1 1 0 1 0 reserved 1 1 0 1 1 reserved 1 1 1 0 0 reserved 1 1 1 0 1 reserved 1 1 1 1 0 reserved 11111 emios23 RM0029 system integration unit (siu) doc id 15177 rev 8 563/1740 table 326. eqadc queue2 enhanced trigger selection etsel2 eqadc enhanced trigger input 0 0 0 0 0 gpio206 (etrig0) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 0 0 1 1 0 reserved 0 0 1 1 1 bootcfg[1] (etrig3) 0 1 0 0 0 etpu30 and pit0 0 1 0 0 1 etpu30 and pit1 0 1 0 1 0 reserved 0 1 0 1 1 reserved 01100 etpu28 01101 etpu29 01110 etpu30 01111 etpu31 1 0 0 0 0 reserved 1 0 0 0 1 reserved 1 0 0 1 0 reserved 1 0 0 1 1 reserved 1 0 1 0 0 emios10 and pit2 1 0 1 0 1 emios10 and pit3 1 0 1 1 0 reserved 1 0 1 1 1 reserved 1 1 0 0 0 reserved 1 1 0 0 1 reserved 1 1 0 1 0 reserved 1 1 0 1 1 reserved 1 1 1 0 0 reserved 1 1 1 0 1 reserved 1 1 1 1 0 reserved 11111 emios23 system integration unit (siu) RM0029 564/1740 doc id 15177 rev 8 table 327. eqadc queue3 enhanced trigger selection etsel3 eqadc enhanced trigger input 0 0 0 0 0 gpio207 (etrig1) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 0 0 1 1 0 reserved 0 0 1 1 1 pllref (etrig2) 0 1 0 0 0 etpu30 and pit0 0 1 0 0 1 etpu30 and pit1 0 1 0 1 0 reserved 0 1 0 1 1 reserved 01100 etpu28 01101 etpu29 01110 etpu30 01111 etpu31 1 0 0 0 0 reserved 1 0 0 0 1 reserved 1 0 0 1 0 reserved 1 0 0 1 1 reserved 1 0 1 0 0 emios10 and pit2 1 0 1 0 1 emios10 and pit3 1 0 1 1 0 reserved 1 0 1 1 1 reserved 1 1 0 0 0 reserved 1 1 0 0 1 reserved 1 1 0 1 0 reserved 1 1 0 1 1 reserved 1 1 1 0 0 reserved 1 1 1 0 1 reserved 1 1 1 1 0 reserved 11111 emios23 RM0029 system integration unit (siu) doc id 15177 rev 8 565/1740 table 328. eqadc queue4 enhanced trigger selection etsel4 eqadc enhanced trigger input 00000 gpio206 (etrig0) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 0 0 1 1 0 reserved 0 0 1 1 1 bootcfg[1] (etrig3) 0 1 0 0 0 etpu30 and pit0 0 1 0 0 1 etpu30 and pit1 0 1 0 1 0 reserved 0 1 0 1 1 reserved 01100 etpu28 01101 etpu29 01110 etpu30 01111 etpu31 1 0 0 0 0 reserved 1 0 0 0 1 reserved 1 0 0 1 0 reserved 1 0 0 1 1 reserved 1 0 1 0 0 emios10 and pit2 1 0 1 0 1 emios10 and pit3 1 0 1 1 0 reserved 1 0 1 1 1 reserved 1 1 0 0 0 reserved 1 1 0 0 1 reserved 1 1 0 1 0 reserved 1 1 0 1 1 reserved 1 1 1 0 0 reserved 1 1 1 0 1 reserved 1 1 1 1 0 reserved 11111 emios23 system integration unit (siu) RM0029 566/1740 doc id 15177 rev 8 16.6.22 imux select register 8 (siu_isel8) the siu_isel8 register is used to multiplex the etpu[24:29] inputs. table 329. eqadc queue5 enhanced trigger selection etsel5 eqadc enhanced trigger input 0 0 0 0 0 gpio207 (etrig1) 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 0 0 1 1 0 reserved 0 0 1 1 1 pllref (etrig2) 0 1 0 0 0 etpu30 and pit0 0 1 0 0 1 etpu30 and pit1 0 1 0 1 0 reserved 0 1 0 1 1 reserved 01100 etpu28 01101 etpu29 01110 etpu30 01111 etpu31 1 0 0 0 0 reserved 1 0 0 0 1 reserved 1 0 0 1 0 reserved 1 0 0 1 1 reserved 1 0 1 0 0 emios10 and pit2 1 0 1 0 1 emios10 and pit3 1 0 1 1 0 reserved 1 0 1 1 1 reserved 1 1 0 0 0 reserved 1 1 0 0 1 reserved 1 1 0 1 0 reserved 1 1 0 1 1 reserved 1 1 1 0 0 reserved 1 1 1 0 1 reserved 1 1 1 1 0 reserved 11111 emios23 RM0029 system integration unit (siu) doc id 15177 rev 8 567/1740 these six etpu channels can come from the output of the dspi or the corresponding pad. when siu_isel8 is in its default state, the etpu pins listed in figure 349 will not be connected to their respective output pin, irrespective of the siu_pcr[pa] field. figure 349. imux select register 8 (siu_isel8) siu_base+0x920 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 esel5 0 0 0 esel4 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 esel3 0 0 0 esel2 0 0 0 esel1 0 0 0 esel0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 330. siu_isel8 field description field description 0:10 reserved 11 esel5 etpu input channel connected as follows: 0 dspi_b[8] deserialized output 1 etpu channel 29 12:14 reserved 15 esel4 etpu input channel connected as follows: 0 dspi_b[9] deserialized output 1 etpu channel 28 16:18 reserved 19 esel3 etpu input channel connected as follows: 0 dspi_b[10] deserialized output 1 etpu channel 27 20:22 reserved 23 esel2 etpu input channel connected as follows: 0 dspi_b[11] deserialized output 1 etpu channel 26 24:26 reserved 27 esel1 etpu input channel connected as follows: 0 dspi_b[12] deserialized output 1 etpu channel 25 system integration unit (siu) RM0029 568/1740 doc id 15177 rev 8 16.6.23 imux select register 9 (siu_isel9) the eqadc has a mode of operation called ?streaming?. this mode requires a second trigger for queue 0. the source for this trigger can come from etpu, emios or pit channels. a mux select register is required to select the source of this new queue0 trigger. figure 350. imux select register 9 (siu_isel9) 28:30 reserved 31 esel0 etpu input channel connected as follows: 0 dspi_b[13] deserialized output 1 etpu channel 24 table 330. siu_isel8 field description (continued) field description siu_base+0x924 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 etsel0a w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 331. eqadc advance trigger selection etsel0a eqadc enhanced trigger input 0 0 0 0 0 reserved 0 0 0 0 1 rti trigger 0 0 0 1 0 pit0 trigger 0 0 0 1 1 pit1 trigger 0 0 1 0 0 pit2 trigger 0 0 1 0 1 pit3 trigger 0 0 1 1 0 reserved 0 0 1 1 1 reserved 0 1 0 0 0 etpu30 and pit0 0 1 0 0 1 etpu30 and pit1 0 1 0 1 0 reserved 0 1 0 1 1 reserved 01100 etpu28 RM0029 system integration unit (siu) doc id 15177 rev 8 569/1740 16.6.24 imux select register 10 (siu_isel10) the imux select register 10 (siu_isel10) register contains bit fields that specify which etpu output is connected to the decimation filter integrator halt signal (hselx) and integrator reset signal (zselx).for more details refer to section 26.3.3, integrator halt signal and section 26.3.4, integrator reset signal . 01101 etpu29 01110 etpu30 01111 etpu31 1 0 0 0 0 reserved 1 0 0 0 1 reserved 1 0 0 1 0 reserved 1 0 0 1 1 reserved 1 0 1 0 0 emios10 and pit2 1 0 1 0 1 emios10 and pit3 1 0 1 1 0 reserved 1 0 1 1 1 reserved 1 1 0 0 0 reserved 1 1 0 0 1 reserved 1 1 0 1 0 reserved 1 1 0 1 1 reserved 1 1 1 0 0 reserved 1 1 1 0 1 reserved 1 1 1 1 0 reserved 11111 emios23 table 331. eqadc advance trigger selection (continued) etsel0a eqadc enhanced trigger input system integration unit (siu) RM0029 570/1740 doc id 15177 rev 8 figure 351. imux select register 10 (siu_isel10 or siu_decfil1) siu_base+0x928 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hselb zselb hsela zsela w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 332. decimation filter control source selection field code source zsela 0001 etpu[22] 0010 etpu[23] 0011 etpu[24] 0100 etpu[25] others unused hsela 0001 etpu[22] 0010 etpu[23] 0011 etpu[24] 0100 etpu[25] others unused zselb 0001 etpu[22] 0010 etpu[23] 0011 etpu[24] 0100 etpu[25] others unused hselb 0001 etpu[22] 0010 etpu[23] 0011 etpu[24] 0100 etpu[25] others unused RM0029 system integration unit (siu) doc id 15177 rev 8 571/1740 16.6.25 chip configuration register (siu_ccr) figure 352. chip configuration register (siu_ccr) siu_base + 0x980 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 match disnex w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u (1) u (2) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crse 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved 1. during reset the comparison is performed and result is uncertain 2. the value after reset is uncertain table 333. siu_ccr field description field description 0:13 reserved 14 match compare register match. the match bit is a read only bit that holds the value of the match input signal to the siu. the match bit is asserted if the password in shadow flash memory and the contents of the siu_cbrh/siu_cbrl registers are equal. 0 match input signal is negated 1 match input signal is asserted 15 disnex disable nexus. the disnex bit is a read only bit that holds the value of the nexus disable input signal to the siu. when system reset negates, the value in this bit depends on the censorship control word and the boot configuration bits. 0 nexus disable input signal is negated 1 nexus disable input signal is asserted 16:29 reserved 30 crse calibration reflection suppression enable. the crse bit enables the suppression of reflections from the ebi?s calibration bus onto the non-calibration bus. the ebi drives some outputs to both the calibration and non-calibration busses. when crse is asserted, the values driven onto the calibration bus pins will not be reflected onto the non-calibration bus pins. when crse is negated, the values driven onto the calibration bus pins will be reflected onto the non-calibration bus pins. crse only enables reflection suppression for non-calibration bus pins which do not have a negated state to which the pins return at the end of the access. crse does not enable reflection suppression for the non-calibration bus pins which have a negated state to which the pins return at the end of an access. those reflections always are suppressed. furthermore, the suppression of reflections from the non-calibration bus onto the calibration bus is not enabled by crse. those reflections are also always suppressed. 0 calibration reflection suppression is disabled 1 calibration reflection suppression is enabled 31 reserved system integration unit (siu) RM0029 572/1740 doc id 15177 rev 8 16.6.26 external clock control register (siu_eccr) the siu_eccr controls the timing relationship between the system clock and the external clock clkout. all bits and fields in the siu_eccr are read/write and are reset by the global signals asynchronous reset signal. figure 353. external clock control register (siu_eccr) siu_base+0x984 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r engdiv engsse 0 0 0 ebts 0 ebdf w reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 = unimplemented or reserved table 334. siu_eccr field description field description 0:15 reserved 16:23 engdiv engineering clock division factor. the engdiv field specifies the frequency ratio between the system clock and the engclk. the engclk frequency is divided from the system clock frequency according to the following equation. equation 2 engdiv = 0 is reserved and results in the engclk frequency being equal to the system clock frequency. 24 engsse engineering clock (engclk) source select. 0 engclk source is system clock. 1 engclk source is crystal oscillator clock. 25:27 reserved engclk systemcloc korcrystaloscillator engdivx2 ------------------------------------------------------------------------------------ = RM0029 system integration unit (siu) doc id 15177 rev 8 573/1740 16.6.27 compare a high register (siu_carh) the siu_carh register holds the 32-bit value that is compared against the value in the siu_cbrh register. the cmpah field is read/write and is reset by the ip green-line synchronous reset signal. figure 354. compare a high register (siu_carh) 16.6.28 compare a low register (siu_carl) the siu_carl register holds the 32-bit value that is compared against the value in the siu_cbrl register. the cmpal field is read/write and is reset by the ip green-line synchronous reset signal. 28 ebts external bus tap select. the ebts bit changes the phase relationship between the system clock and clkout. changing the phase relationship so that clkout is advanced in relation to system clock increases the output hold time of the external bus signals to a non-zero value. it also increases the output delay times, increases the input hold times to non-zero values, and decreases the input setup times. the ebts bit must not be modified while an external bus transac tion is in progress. 29 reserved 30:31 ebdf external bus division factor. the ebdf field specifies the frequency ratio between the system clock and clkout. the ebdf field must not be changed during an external bus access or while an access is pending. 00 external bus division factor = 1 01 external bus division factor = 2 10 reserved 11 external bus division factor = 4 the reset value of the ebdf field is divide-by-2. afte r reset, if ebdf is changed to divided-by-1, no glitches occurs on the clkout signal, but if ebdf is changed back to divide-by-2 or divide-by-4, there is no guarantee that the switch will be glitchless. table 334. siu_eccr field description (continued) field description siu_base + 0x988 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r cmpah w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cmpah w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved system integration unit (siu) RM0029 574/1740 doc id 15177 rev 8 figure 355. compare a low register (siu_carl) 16.6.29 compare b high register (siu_cbrh) the siu_cbrh register holds the 32-bit value that is compared against the value in the siu_carh register. the cmpbh field is read/write and is reset by the ip green-line synchronous reset signal. figure 356. compare b high register (siu_cbrh) 16.6.30 compare b low register (siu_cbrl) the siu_cbrl register holds the 32-bit value that is compared against the value in the siu_carl register. the cmpbl field is read/write and is reset by the ip green-line synchronous reset signal. siu_base + 0x98c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r cmpal w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cmpal w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved siu_base + 0x990 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r cmpbh w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cmpbh w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved RM0029 system integration unit (siu) doc id 15177 rev 8 575/1740 figure 357. compare b low register (siu_cbrl) 16.6.31 system clock register (siu_sysdiv) the fields in the siu_sysdiv register are read/write and are reset by the ip green-line synchronous reset signal. figure 358. system clock register (siu_sysdiv) siu_base + 0x994 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r cmpbl w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cmpbl w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved siu_base + 0x9a0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can_src w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 bypass sysclkdiv 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 = unimplemented or reserved table 335. siu_sysdiv field description field description 0:14 reserved 15 can_src flexcan 2:1 mode 1 when can_ctrl[clk_src] = 1, flexcan runs at half the system frequency 0 when can_ctrl[clk_src] = 1, flexcan runs at the system frequency see section , support for can interface operation . 16:26 reserved system integration unit (siu) RM0029 576/1740 doc id 15177 rev 8 16.6.32 halt register (siu_hlt) the siu_hlt register is used to put various modules into stop mode to save power. each bit will drive a separate stop request signal to a different module. when the module acknowledges the stop request, the clock to that module is halted. in order to remove the module from stop mode, the corresponding bit in the siu_hlt register must be cleared. in the case of the cpu, stop mode in entered when the corresponding bit in siu_hlt is set and a wait instruction is executed. the cpu exits stop mode upon reception of any interrupt request. figure 359. halt register (siu_hlt) 27 bypass bypass bit 1 system clock divider is bypassed 0 system clock divider is not bypassed 28:29 sysclkdiv system clock divide the sysclkdiv bits select the divider value for the system clock (ipg_clk). note that the sysclkdiv divider is required in addition to the rfd to allow the other sources for the system clock (16 mhz irc and osc) to be divided down to slowest frequencies to improve power. the output of the clock divider is nominally a 50% duty cycle. 00 divide by 2 01 divide by 4 10 divide by 8 11 divide by 16 note: the above four divider values can be selected only if siu_sysdiv[bypass] value = 0. if siu_sysdiv[bypass] = 1, the system clock divider is bypassed and ?divide by 1? is selected. 30:31 reserved table 335. siu_sysdiv fiel d description (continued) field description siu_base + 0x9a4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r cpustp 0 0 0 0 tpustp npcstp ebistp adcstp reacmstp miosstp dfilstp 0 pitstp 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 cncstp cnbstp cnastp spidstp spicstp spibstp 0 0 0 0 0 0 scicstp scibstp sciastp w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved RM0029 system integration unit (siu) doc id 15177 rev 8 577/1740 table 336. siu_hlt field description field description 0 cpustp cpu stop request when asserted, a stop request is sent to the following modules: cpu, cross-bar, peripheral bridge, system ram, stm, and dma. 1: stop mode request 0: normal operation 1:2 reserved 3 reserved (unimplemented) 4 reserved 5 tpustp etpu stop request when asserted, a stop request is sent to the etpu module and the etpu nexus module. 1: stop mode request 0: normal operation 6 npcstp nexus stop request when asserted, a stop request is sent to the nexus controller. 1: stop mode request 0: normal operation 7 ebistp ebi stop request when asserted, a stop request is sent to the external bus controller which handles the calibration interface. 1: stop mode request 0: normal operation 8 adcstp eqadc stop request when asserted, a stop request is sent to the eqadc module. 1: stop mode request 0: normal operation 9 reacmstp reaction module stop request when asserted, a stop request is sent to the reaction module. 1: stop mode request 0: normal operation 10 miosstp emios stop request when asserted, a stop request is sent to the emios module. 1: stop mode request 0: normal operation 11 dfilstp decimation filter stop request when asserted, a stop request is sent to the decimation filter module. 1: stop mode request 0: normal operation 12 reserved 13 pitstp pit stop request when asserted, a stop request is sent to the periodic interrupt timer module. 1: stop mode request 0: normal operation system integration unit (siu) RM0029 578/1740 doc id 15177 rev 8 14:16 reserved 17 cncstp flexcan c stop request when asserted, a stop request is sent to the flexcan c module. 1: stop mode request 0: normal operation 18 cnbstp flexcan b stop request when asserted, a stop request is sent to the flexcan b module. 1: stop mode request 0: normal operation 19 cnastp flexcan a stop request when asserted, a stop request is sent to the flexcan a module. 1: stop mode request 0: normal operation 20 spidstp dspi d stop request when asserted, a stop request is sent to the dspi c. 1: stop mode request 0: normal operation 21 spicstp dspi c stop request when asserted, a stop request is sent to the dspi c. 1: stop mode request 0: normal operation 22 spibstp dspi b stop request when asserted, a stop request is sent to the dspi b. 1: stop mode request 0: normal operation 23:28 reserved 29 scicstp esci c stop request when asserted, a stop request is sent to the esci c module. 1: stop mode request 0: normal operation 30 scibstp esci b stop request when asserted, a stop request is sent to the esci b module. 1: stop mode request 0: normal operation 31 sciastp esci a stop request when asserted, a stop request is sent to the esci a module. 1: stop mode request 0: normal operation table 336. siu_hlt field description (continued) field description RM0029 system integration unit (siu) doc id 15177 rev 8 579/1740 16.6.33 halt acknowledge register (siu_hltack) the bits in the siu_hltack register indicate that the module requested to halt via the siu_hlt register has completed the halt process and has entered a halted state with the module clocks disabled. this register is read-only. figure 360. halt acknowledge register (siu_hltack) siu_base + 0x9a8 0 1 2 3 4 5 6 7 8 9 101112131415 r cpuack 000 nsetiack tpuack npcack ebiack adcack reacmack miosack dfilack 0 pitack 00 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 cncack cnback cnaack spidack spicack spiback 000000 scicack sciback sciaack w reset 0000000000000000 = unimplemented or reserved table 337. siu_hltack field description field description 0 cpuack cpu stop acknowledge when asserted, indicates that a stop acknowledge was received from the following modules: cpu, cross-bar, peripheral bridge, system ram, flash, stm, dma. 1: stop mode request 0: normal operation 1:3 reserved 4 nsetiack etpu nexus module (nseti) stop acknowledge when asserted, indicates that a stop acknowledge was received from the nseti module. 1: stop mode request 0: normal operation 5 tpuack etpu stop acknowledge when asserted, indicates that a stop acknowledge was received from the etpu module. 1: stop mode request 0: normal operation system integration unit (siu) RM0029 580/1740 doc id 15177 rev 8 6 npcack nexus stop acknowledge when asserted, indicates that a stop acknowledge was received from the nexus controller. 1: stop mode request 0: normal operation 7 ebiack ebi stop acknowledge when asserted, indicates that a stop acknowledge was received from the external bus controller which handles the calibration interface. 1: stop mode request 0: normal operation 8 adcack eqadc stop acknowledge when asserted, indicates that a stop acknowledge was received from the eqadc module. 1: stop mode request 0: normal operation 9 reacmack reaction module (reacm) stop acknowledge when asserted, indicates that a stop acknowledge was received from the reaction module. 1: stop mode request 0: normal operation 10 miosack emios stop acknowledge when asserted, indicates that a stop acknowledge was received from the emios module. 1: stop mode request 0: normal operation 11 dfilack decimation filter stop acknowledge when asserted, indicates that a stop acknowledge was received from the decimation filter module. 1: stop mode request 0: normal operation 12 reserved 13 pitack pit stop acknowledge when asserted, indicates that a stop acknowledge was received from the periodic interrupt timer module. 1: stop mode request 0: normal operation 14:16 reserved 17 cncack flexcan c stop acknowledge when asserted, indicates that a stop acknowledge was received from the flexcan c module. 1: stop mode request 0: normal operation 18 flexcan b stop acknowledge when asserted, indicates that a stop acknowledge was received from the flexcan b module. 1: stop mode request 0: normal operation table 337. siu_hltack field description (continued) field description RM0029 system integration unit (siu) doc id 15177 rev 8 581/1740 16.6.34 core mmu pid control register (siu_empcr0) the siu_empcr0 register is part of a mechanism that provides the capability of real-time remapping of mmu entries by software or an external tool. this capability is intended for use in calibration activities requiring real-time switching between calibration data tables. the siu_empcr0 register works in conjunction with the nexus module to enable an external calibration tool to modify the logical-to-physical address mapping of the calibration bus by replacing bits 6:7 of the mmu?s pid (process id) register with values specified in siu_empcr0 register fields. this remapping does not interrupt normal application code execution. in addition, the register provides a synchronization mechanism that enables the mapping to change when a specified instruction address is reached or a specified load/store address is 19 cnaack flexcan a stop acknowledge when asserted, indicates that a stop acknowledge was received from the flexcan a module. 1: stop mode request 0: normal operation 20 dspi d stop acknowledge when asserted, indicates that a stop acknowledge was received from the dspi d. 1: stop mode request 0: normal operation 21 spicack dspi c stop acknowledge when asserted, indicates that a stop acknowledge was received from the dspi c. 1: stop mode request 0: normal operation 22 spiback dspi b stop acknowledge when asserted, indicates that a stop acknowledge was received from the dspi b. 1: stop mode request 0: normal operation 23:28 reserved 29 esci c stop acknowledge when asserted, indicates that a stop acknowledge was received from the esci c module. 1: stop mode request 0: normal operation 30 sciback esci b stop acknowledge when asserted, indicates that a stop acknowledge was received from the esci b module. 1: stop mode request 0: normal operation 31 sciaack esci a stop acknowledge when asserted, indicates that a stop acknowledge was received from the esci a module. 1: stop mode request 0: normal operation table 337. siu_hltack field description (continued) field description system integration unit (siu) RM0029 582/1740 doc id 15177 rev 8 accessed. synchronization is implemented using watchpoint event 2 output in the processor core. the mechanism is detailed in figure 361 and ta ble 33 8 . figure 361. core mmu pid control register (siu_empcr0) siu_base + 0x9b4 0 1 2 3 4 5 6 7 8 9 101112131415 r ext_pid_en ext_pid_sync0 00000000000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000000000 ext_pid6 ext_pid7 w reset 0000000000000000 = unimplemented or reserved table 338. siu_empcr0 field description field description ext_pid_en 0 external pid selection enable 0: the contents of this register are not used to select the alternate mmu mapping. 1: the contents of this register are used to select the alternate mmu mapping defined by ext_pid6 and ext_pid7. ext_pid_sync0 1 external pid synchronization 0 0: the nexus watchpoint event 2 does not transfer the ext_pid6 and ext_pid7 values to the mmu. 1: the nexus watchpoint event 2 transfers the ext_pid6 and ext_pid7 values to the mmu. 2:29 reserved ext_pid6 30 external pid bit 6 0: when the pid remapping is enabled (ext_pid_en = 1), the processor mmu?s pid register bit 6 is logic 0. 1: when the pid remapping is enabled (ext_pid_en = 1), the processor mmu?s pid register bit 6 is logic 1. ext_pid7 31 external pid bit 7 0: when the pid remapping is enabled (ext_pid_en = 1), the processor mmu?s pid register bit 7 is logic 0. 1: when the pid remapping is enabled (ext_pid_en = 1), the processor mmu?s pid register bit 7 is logic 1. RM0029 system integration unit (siu) doc id 15177 rev 8 583/1740 16.7 functional description the following sections provide an overview of the siu operation features. 16.7.1 system configuration boot configuration two bootcfg signals are implemented in spc564a74xx, spc564a80xx mcus. the bam program uses the bootcfg0 bit to determine where to read the reset configuration word, and whether to initiate a flexcan or esci boot. see section 4.7.1, reset configuration half word (rchw) , for details on the rchw. ta ble 38 7 in section 21.5.2, bam program operation , defines the boot modes specified by the bootcfg0 and bootcfg1 pins. during the assertion of rstout, the bootcfg0 and bootcfg1 pins are used to update the rsr and the bam boot mode. this device has a second serial boot mode to support a new serial boot with can and sci baudrate auto-detection. for additional details on the bam program operation see chapter 21: boot assist module (bam) . pad configuration the pad configuration registers (pcr) in the siu allow software control of the static electrical characteristics of external pins. the multiplexed function of a pin, selection of pull up or pull down devices, the slew rate of i/o signals, open drain mode for output pins, hysteresis on input pins, and the drive strength for bus signals can be specified through the pcrs. 16.7.2 reset control the reset controller logic is located in the siu. see chapter 4: resets for details on reset operation. 16.7.3 external interrupt request input (irq) the fifteen external interrupt request inputs available on this device (irq [0:5,7:15]) connect to the siu irq inputs. the external irq input select register (eiisr) specifies the irq [0:5,7:15] signals that are input to the siu irqs. note: irq[6] can be only generated by the deserialized output of the dspi module?not the external pins. external interrupt requests are triggered by rising- and/or falling-edge events that are enabled by setting a bit in: irq rising-edge event enable register (siu_ireer) irq falling-edge event enable register (siu_ifeer) if the bit is set in both registers, both rising- and falling-edge events trigger an interrupt request. each irq has a counter that tracks the number of system clock cycles that occur between the rising- and falling-edge events. an irq counter exists for each irq rising- or falling-edge event enable bit. system integration unit (siu) RM0029 584/1740 doc id 15177 rev 8 the digital filter length field in the irq digital filter register (siu_idfr) specifies the minimum number of system clocks that the irq signal must hold a logic value to qualify the edge-triggered event as a valid state change. when the number of system clocks in the irq counter equals the value in the digital filter length field, the irq state latches and the irq counter is cleared. if the previous filtered state of the irq does not match the current state, and the rising- or falling-edge event is enabled, the irq flag bit is set to 1. for example, the irq flag bit is set if a rising-edge event occurs under the following conditions: previous filtered irq state was a logic 0 current latched irq state is a logic 1 rising-edge event is enabled for the irq when the counter for an irq is not enabled, the state of the irq is held in the current and previous state latches. the irq counter operates independently of the irq or overrun flag bit. clearing the irq flag or overrun flag bits does not clear or reload the counter. refer to the following sections for more information: section 16.6.6, external interrupt status register (siu_eisr) section 16.6.11, irq rising-edge event enable register (siu_ireer) section 16.6.12, external irq falling-edge event enable register (siu_ifeer) section 16.6.13, external irq digital filter register (siu_idfr) external interrupts the irq signals map to 15 independent interrupt requests output from the siu. the irq flag bit is set when a rising-edge and/or falling-edge event occurs for the irq. an external irq signal is asserted when all of the following occur: enable bit is set in the irq rising- and/or falling-edge event registers (siu_ireer, siu_ifeer) irq flag bit is set in the external interrupt status register (siu_eisr) enable bit is cleared in the dma/interrupt request enable register (siu_direr) select bit is cleared in the dma/interrupt select register (siu_dirsr) the nmi and swt interrupts can each generate an nmi exception or critical interrupt exception as an input to the core. this selection is controlled by the nmi_sel8 and nmi_sel0 (siu_direr) signals respectively. when wkpcfg_nmi_gpio213 is enabled as nmi, the pin will override the pcr configuration after reset. the siu_direr selects between critical and non-maskable interrupt use, the siu_eisr reports the status of nmi, and the siu_ifeer selects edge sensitivity of the nmi input. RM0029 system integration unit (siu) doc id 15177 rev 8 585/1740 figure 362. siu dma/interrupt request diagram refer to the following sections for more information: section 16.6.7, dma/interrupt request enable register (siu_direr) section 16.6.8, dma/interrupt request select register (siu_dirsr) 16.7.4 gpio operation the siu provides all gpio functionality for this device. each device pin that has gpio functionality has an associated pin configuration register in the siu where the gpio function is selected for the pin. in addition, each device pin with gpio functionality has an input data register (siu_gpdi x _ x ) and an output data register (siu_gpdo x _ x ). 16.7.5 internal multiplexing the imux select registers (siu_isel x ) provide selection of the eqadc external trigger inputs sources, the siu external interrupts, some of the etpu inputs and the dspi signals that are used in the serial and parallel chaining of dspi blocks. siu_eisr siu interrupt controller overrun siu_dirsr dma / int select siu_osr imux eirq pins or internal sources 0 1 2 0 1 15 15 request interrupt request 3 4 interrupt request 23 swt cpu nmi_sel8 (for swt) (siu_direr) nmi critical interrupt 31 nmi nmi_sel0 (for nmi) (siu_direr) system integration unit (siu) RM0029 586/1740 doc id 15177 rev 8 eqadc external trigger input multiplexing the six eqadc external trigger inputs can be connected to either an external pin, an etpu channel, an emios channel or a pit or rti trigger. the input source for each eqadc external trigger is individually specified in the etisr, siu_isel3 and siu_isel9 registers. one of these inputs is in turn specified in the imux select register 3 (siu_isel3). an example of the multiplexing of an eqadc external trigger input is given in figure 363 . as shown in the figure, the trigger[0] input of the eqadc can be connected to either the etrig[0] pin, the etpu_a[30] channel or the emios[10] channel or the output of the mux, imux3. the inputs of imux3 can be some of the etpu/emios channels or pit/rti triggers or external triggers. figure 363. eqadc trigger input multiplexing example the remaining adc trigger inputs are multiplexed in the same manner. note that if an etrig input is connected to an etpu or emios channel, the external pin used by that channel can be used by the alternate function on that pin. along with the six eqadc external trigger inputs, there is one additional trigger input to adc. the source of that trigger is specified in imux select register 9 (siu_isel9). it is similar to siu_isel3, shown in the above figure. siu external interrupt input multiplexing the fifteen siu external interrupt inputs can be connected to either external pins or to deserialized output signals from a dspi block. the input source for each siu external interrupt is individually specified in the external irq input select register (o) (eiisr). an example of the multiplexing of an siu external interrupt input is given in figure 364 . as shown in the figure, the irq[0] input of the siu can be connected to either the emios[14]_irq[0]_etpu_a[29]_gpio[193] pin, the dspi_b[0] deserialized output signal, the dspi_c[1] deserialized output signal or emios[14] channel. the remaining irq inputs are multiplexed in the same manner. only irq[0] and [1] have an emios channel as input. other irq input source is one of the dspi_d[15:4,1:0] output signal instead (as specified in the external irq input select register (eiisr)). the inputs to the irq from each dspi block are offset by one so that if more than one dspi block is connected to the same external device type, a separate interrupt can be generated for each device. this also etisr[tsel0] etrig[0] etsel0 etpu_a[30] emios[10] to adc trigger input siu_isel3 rti-trigger pit-0/1/2/3-trigger etrig-0/3 etpu_a-28/29/30/31 emios-10/23 o. the eiisr is sometimes referred to as isel1. RM0029 system integration unit (siu) doc id 15177 rev 8 587/1740 applies to dspi blocks connected to external devices of different type that have status bits in the same bit location of the deserialized information. see section 16.6.19, external irq input select register (siu_eiisr) , for more information. figure 364. siu external interrupt input multiplexing example multiplexed inputs for dspi multiple transfer operation to support multiple dspis transfer operations, an input multiplexor is required for the sin, ss , sck in, and trigger signals of each dspi. these dspi input sources can be a pin or respectively the sout, pcs[0], sck out, or pcss of any other dspi. they are individually specified in the dspi input select register (disr). see section , multiple transfer operation (mto) , for more information on multiple transfer operation. multiplexed inputs for etpu[29:24] the etpu channel input pins, etpu[29:24], are multiplexed with dspi_b[8:13] deserialized output signals and then given as input to the etpu block. these are individually specified in the imux select register 8 (siu_isel8). when siu_isel8 is in its default state, the etpu[29:24] will not be connected to their respective output pin, irrespective of the siu_pcr[pa] field. the siu_isel8 register must be modified if these signals are to be used as external inputs or outputs. eiisr[0:1] dspi_b[0] serialized output dspi_c[1] serialized output emios[14] channel irq[0] emios[14]_irq[0]_etpu_a[29]_gpio[193] frequency-modulated phase locked loop (fmpll) RM0029 588/1740 doc id 15177 rev 8 17 frequency-modulated phase locked loop (fmpll) 17.1 information specific to this device this section presents device-specific parameterization and customization information not specifically referenced in the remainder of this chapter. 17.1.1 device-specific features on-chip oscillator for external crystal: range (4?40 mhz) internal rc oscillator (rcosc): 16 mhz phase-locked loop (pll): vco range (256?512 mhz) pllref top level pin to control pll reference clock quality monitor system clock divider (sysdiv) used to further reduce the system clock frequency register to control system clock source and programming of pll parameter clock gating for individual modules controlled by either siu_hlt or module?s mdis register bit (refer to table 14 (mdis support) 5, operating modes and clocking , to see which modules implement the mdis bit.) 17.1.2 device-specific parameters ta ble 33 9 shows the reset values for several register fields on this device. 17.2 introduction this chapter describes the features and functions of the fmpll module. 17.2.1 overview the frequency modulated phase locked loop (fmpll) allows the user to generate high speed system clocks from a crystal oscillator or from an external clock generator. furthermore, the fmpll supports programmable frequency modulation of the system clock. the fmpll multiplication factor, reference clock predivider factor, output clock divider ratio, table 339. register field reset values parameter name value description fmpll_syncr[prediv] 0b111 inhibit the clock to the phase detector fmpll_syncr[mfd] 0b00100 divide-by-8 fmpll_syncr[rfd] 0b010 divide-by-4 fmpll_esyncr1[emode] 0b0 allowing legacy mode to be used fmpll_esyncr1[eprediv] 0b1111 inhibit the clock to the phase detector fmpll_esyncr1[emfd] 0b0100000 divide-by-32 fmpll_esyncr2[erfd] 0b11 divide-by-16 RM0029 frequency-modulated phase locked loop (fmpll) doc id 15177 rev 8 589/1740 modulation depth and multiplication rate are all controllable through programmable registers. figure 365 shows the block diagram of the fmpll. figure 365. fmpll block diagram xtal osc extal xtal predivider prediv phase detector charge pump low pass filter vco divider mfd out divider rfd fm controller control/status registers pll prediv rfd mfd lock clock quality monitor reference failure fmpll failure pllref rc osc frequency-modulated phase locked loop (fmpll) RM0029 590/1740 doc id 15177 rev 8 17.2.2 features the fmpll has the following features: reference clock predivider for finer frequency synthesis resolution reduced frequency divider for reducing the fmpll output clock frequency without forcing the fmpll to relock input clock frequency range from 4 mhz to 20 or 40 mhz (p) before the predivider, and from 4 mhz to 16 mhz after the predivider voltage controlled oscillator (vco) range from 256 mhz to 512 mhz vco free-running frequency range from 25 mhz to 125 mhz 4 bypass modes: crystal or external reference with pll on or off 2 normal modes: crystal or external reference programmable frequency modulation ? triangle wave modulation ? register programmable modulation frequency and depth lock detect circuitry reports when the fmpll has achieved frequency lock and continuously monitors lock status to report loss of lock conditions ? user-selectable ability to generate an interrupt request upon loss of lock ? user-selectable ability to generate a system reset upon loss of lock clock quality monitor (cqm) module provides loss-of-clock detection for the fmpll reference and output clocks ? user-selectable ability to generate an interrupt request upon loss of clock ? user-selectable ability to generate a system reset upon loss of clock ? backup clock (reference clock or fmpll free-running) can be applied to the system in case of loss of clock 17.2.3 modes of operation upon reset, the operational mode is bypass with pll running, and the source of the reference clock, either the crystal oscillator or external clock, is determined by the reset value of the clkcfg[2] bit of the fmpll_esyncr1. the reset state of this bit comes from an external signal to the module connected to a package pin called pllref. after reset, a different operational mode can be selected by writing to fmpll_esyncr1[clkcfg]. the available modes are specified in table 340 . p. see section 17.1, information specific to this device , for information on crystal frequencies supported. table 340. clock mode selection clkcfg[0] clkcfg[1] (1) clkcfg[2] (2) clock mode 0 0 0 bypass mode with external reference and pll off 0 0 1 bypass mode with crystal reference and pll off 0 1 0 bypass mode with external reference and pll running 0 1 1 bypass mode with crystal reference and pll running 1 0 0 reserved RM0029 frequency-modulated phase locked loop (fmpll) doc id 15177 rev 8 591/1740 at reset the fmpll is enabled, but the reset value of the predivider may be set by the soc integration to inhibit the clock to the pll, making the vco run within its free-running frequency range of 25 mhz to 125 mhz, unconnected from the system clock (since bypass is the default mode at reset). if using crystal reference, after power-on reset the clock quality monitor (cqm) will inhibit the system clock and keep system reset asserted while the crystal oscillator has not stabilized. the pllref input must be kept stable during the whole period while system reset is asserted. bypass mode with crystal reference in the bypass mode with crystal reference, the fmpll is completely bypassed and the system clock is driven from the crystal oscillator. the user must supply a crystal that is within the appropriate frequency range, the crystal manufacturer recommended external support circuitry, and short signal route from the mcu to the crystal. in bypass mode the pll itself may or may not be running, depending on the state of the clkcfg[1] bit of fmpll_esyncr1, but the pll output is not connected to the system clock. consequently, frequency modulation is not available. the predivider is also bypassed. bypass mode with crystal reference is the default mode at reset if the pllref input is driven high. after reset, this mode can be entered by programming fmpll_esyncr1[clkcfg] as shown in table 340 . bypass mode with external reference the bypass mode with external reference functions the same as bypass mode with crystal reference, except that the system clock is driven by an external clock generator connected to the extal pin, rather than a crystal oscillator. the input frequency range is the same and frequency modulation is not available. bypass mode with external reference is the default mode at reset if the pllref input is driven low. after reset, this mode can be entered by programming fmpll_esyncr1[pllcfg] as shown in table 340 . normal mode with crystal reference in the normal mode with crystal reference, the fmpll receives an input clock frequency from the crystal oscillator and the predivider, and multiplies the frequency to create the fmpll output clock. the user must supply a crystal that is within the appropriate frequency range, the crystal manufacturer recommended external support circuitry, and short signal route from the mcu to the crystal. in normal mode with crystal reference, the fmpll can generate a frequency modulated clock or a non-modulated clock (locked on a single frequency). the modulation rate, 1 0 1 reserved 1 1 0 normal mode with external reference 1 1 1 normal mode with crystal reference 1. clkcfg[1] is not writable to zero while clkcfg[0] = 1. 2. the reset state of this bit is determined by the logical state applied to the pllref pin. table 340. clock mode selection (continued) clkcfg[0] clkcfg[1] (1) clkcfg[2] (2) clock mode frequency-modulated phase locked loop (fmpll) RM0029 592/1740 doc id 15177 rev 8 modulation depth, output divider (rfd) and whether the fmpll is modulating or not can be programmed by writing to the fmpll registers. normal mode with external reference the normal mode with external reference functions the same as normal mode with crystal reference, except that the input clock reference to the fmpll is driven by an external clock generator connected to the extal pin, rather than a crystal oscillator. the input frequency range is the same and frequency modulation is available. 17.3 external signal description ta ble 34 1 lists external signals used by the fmpll during normal operation. 17.3.1 detailed signal descriptions ta ble 34 2 describes the external signals used by the fmpll. table 341. signal properties name function i/o pull pllref configures the fmpll clock reference at reset i/o up xtal output drive for external crystal o ? extal_extclk crystal/external clock input i/o ? vddpll analog power supply (1.2v +/ ? 10%) power ? vsspll (1) analog ground ground ? 1. this signal is internally bonded to vss. table 342. fmpll detailed signal descriptions signal i/ o description pllref i/ o pll reference?determines the reset state of the clkcfg[2] bit in fmpll_esyncr1. the pllref pin must be kept stable during system reset. after reset, this pin has no effect on the pll configuration, therefore it can be assigned to another function such as gpio. state meaning asserted?indicates that the reference clock comes from the crystal oscillator. negated?indicates that the reference clock comes from the external clock generator. timing assertion or negation?must be done at the beginning of the reset cycle and then kept stable for the whole reset duration. xtal o crystal oscillator?output for an external crystal oscillator. extal_extclk i/ o crystal oscillator/external clock input?this pin is the input for an external crystal oscillator or an external clock source. the function of this pin is determined by the clkcfg[2] bit in fmpll_esyncr1, whose reset value is determined by the pllref pin. vddpll / vsspll ? pll power supply?these are the 1.2v supply and ground for the fmpll. RM0029 frequency-modulated phase locked loop (fmpll) doc id 15177 rev 8 593/1740 17.4 memory map and register definition this section provides the memory map and detailed descriptions of all registers of the fmpll. 17.4.1 memory map ta ble 34 3 shows the memory map. addresses are given as offsets of the module base address. 17.4.2 register descriptions this section contains the register descriptions in ascending address order. two different programming models are selectable through fmpll_esyncr1[emode]: legacy model?the fmpll is controlled by the synthesizer control register (syncr). in this model, the fmpll operating mode changes automatically to normal mode when the register is written in the first time. there is no way to switch back to bypass mode once the operating mode has switched to normal. enhanced model?the pll is controlled by the enhanced synthesizer control registers 1?2 (esyncr1/esyncr2). in this model, it is possible to change the fmpll operating mode back and forth between bypass and normal modes by programming fmpll_esyncr1[clkcfg]. the reset value of fmpll_esyncr1[emode] is determined by the soc integration. this bit is write once. after it is set to ?1?, further write attempts to this bit will have no effect. synthesizer control register (syncr) this register is provided for backwards compatibility with previous devices. new applications should use esyncr1/esyncr2 instead of syncr. table 343. fmpll memory map offset register location 0x0000 synthesizer control register (syncr) on page 17-593 0x0004 synthesizer status register (synsr) on page 17-596 0x0008 enhanced synthesizer control register 1 (esyncr1) on page 17-598 0x000c enhanced synthesizer control register 2 (esyncr2) on page 17-600 0x0010 reserved ? 0x0014 reserved ? 0x0018 synthesizer fm modulation register (synfmmr) on page 17-601 frequency-modulated phase locked loop (fmpll) RM0029 594/1740 doc id 15177 rev 8 figure 366. synthesizer control register (syncr) offset 0x0000 access: user read/write 0123456789101112131415 r 0 prediv mfd 0 rfd loc en lol re loc re w reset 0 ? (1) ? (1) ? (1) ? (1) ? (1) ? (1) ? (1) ? (1) 0? (1) ? (1) ? (1) 000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 lol irq loc irq 000000 0 00 0000 w reset0000000000000000 1. reset value is determined by the soc integration. table 344. syncr field descriptions field description 0 reserved, should be cleared. 1?3 prediv predivider this 3-bit field controls the value of the divider on the input clock. the output of the predivider circuit generates the reference clock to the fmpll analog loop. the value 111 causes the input clock to be inhibited. 000 divide by 1 001 divide by 2 010 divide by 3 011 divide by 4 100 divide by 5 101 divide by 6 110 divide by 7 111 clock inhibit 4?8 mfd multiplication factor divider this 5-bit field controls the value of the divider in the fmpll feedback loop. the value specified by the mfd bits establishes the multiplication factor applied to the reference frequency. 000xx invalid 00100 divide by 8 00101 divide by 9 00110 divide by 10 ... 10011 divide by 23 10100 divide by 24 10101 invalid 1011x invalid 11xxx invalid 9 reserved, should be cleared. RM0029 frequency-modulated phase locked loop (fmpll) doc id 15177 rev 8 595/1740 10?12 rfd reduced frequency divider this 3-bit field controls a divider at the output of the fmpll. the value specified by the rfd bits establishes the division factor applied to the fmpll frequency. 000 divide by 1 001 divide by 2 010 divide by 4 011 invalid 1xx invalid 13 locen loss-of-clock enable the locen bit determines if the loss-of-clock function is operational. this bit only has effect in normal mode. in bypass mode, the loss-of-clock function is always enabled, regardless of the state of the locen bit. furthermore, the locen bit has no effect on the loss-of-lock detection circuitry. 0 loss of clock disabled 1 loss of clock enabled 14 lolre loss-of-lock reset enable the lolre bit determines whether system reset is asserted or not upon a loss-of-lock indication. when operating in normal mode, the fmpll must be locked before setting the lolre bit, otherwise reset is immediately asserted. note that once reset is asserted, the operating mode is switched to bypass mode, and once in bypass, a loss-of-lock condition does not generate reset, regardless of the value of the lolre bit. see section 17.5.3, lock detection . 0 ignore loss-of-lock. reset not asserted. 1 assert reset on loss-of-lock when operating in normal mode. 15 locre loss-of-clock reset enable the locre bit determines whether system reset is asserted or not upon a loss-of-clock condition when locen = 1. locre has no effect when locen = 0. if the locf bit in the synsr indicates a loss-of-clock condition, setting the locre bit causes immediate reset. in bypass mode with crystal reference, reset will occur if the reference clock fails, even if locre = 0 or even if locen = 0. the locre bit has no effect in bypass mode with external reference. in this mode, the reference clock is not monitored at all. see section , loss-of-clock reset . 0 ignore loss-of-clock. reset not asserted. 1 assert reset on loss-of-clock. 16 reserved, should be cleared. 17 lolirq loss-of-lock interrupt request the lolirq bit enables a loss-of-lock interrupt request when the lolf flag is set. if either lolf or lolirq is negated, the interrupt request is negated. when operating in normal mode, the fmpll must be locked before setting the lolirq bit, otherwise an interrupt is immediately asserted. the interrupt request only happens in normal mode, therefore t he lolirq bit has no effect in bypass mode. see section 17.5.3, lock detection . 0 ignore loss-of-lock. interrupt not requested. 1 enable interrupt request upon loss-of-lock. table 344. syncr field descriptions (continued) field description frequency-modulated phase locked loop (fmpll) RM0029 596/1740 doc id 15177 rev 8 synthesizer status register (synsr) 18 locirq loss-of-clock interrupt request the locirq bit enables a loss-of-clock interrupt request when the locf flag is set. if either locf or locirq is negated, the interrupt request is negated. if loss-of-clock is detected while in bypass mode, a system reset is generated. therefore, locirq has no effect in bypass mode. see section , loss-of- clock interrupt request . 0 ignore loss-of-clock. interrupt not requested. 1 enable interrupt request upon loss-of-clock. 19?31 reserved, should be cleared. table 344. syncr field descriptions (continued) field description figure 367. synthesizer status register (synsr) offset 0x0004 access: user read/write 01234567 8 9101112131415 r 0 0 0 0 0 000 0 00 0 0000 w reset00000000 0 00 0 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000lolflocmode pll sel pll ref locks lock locf 0 0 w w1c w1c reset00000000 0 0? (1) 0 0000 1. reset value is determined by the state of the pllref pin. table 345. synsr field descriptions field description 0?21 reserved, should be cleared. 22 lolf loss-of-lock flag this bit provides the interrupt request flag for the loss-of-lock. to clear the flag, software must write a 1 to the bit. writing 0 has no effect. this flag bit is sticky in the sense that if lock is reacquired, the bit will remain set until cleared by either writing 1 or asserting reset. it will not be asserted when lock is lost due to system reset, write to the fmpll_syncr in legacy mode which modifies the prediv or mfd fields, or write to fmpll_esyncr1 in enhanced mode which modifies the emode, eprediv, emfd or clkcfg[1:0] fields. furthermore, it is not asserted if the loss-of-lock condition was detected while the fmpll is in bypass mode. nevertheless, going from normal to bypass will not automatically clear the flag if it was asserted while the fmpll was in normal mode. see section 17.5.3, lock detection . 0 no loss of lock detected. interrupt service not requested. 1 loss of lock detected. interrupt service requested. RM0029 frequency-modulated phase locked loop (fmpll) doc id 15177 rev 8 597/1740 23 loc loss-of-clock this bit is an indication of whether a loss-of-clock condition is present. if loc = 0, the system clocks are operating normally. if loc = 1, the system clocks have failed due to a reference or vco failure. if a loss- of-clock condition occurs which sets this bit and the clocks later return to normal, this bit will be cleared. a loss-of-clock condition can only be detected if locen = 1. furthermore, the loc bit is not asserted when the fmpll is in bypass mode (because, in bypass, the vco clock is not monitored and a loss-of- clock on the reference clock causes reset). see section 17.5.4, loss-of-clock detection . 0 no loss-of-clock detected. clocks are operating normally. 1 loss-of-clock detected. clocks are not operating normally. 24 mode mode of operation this bit indicates whether the fmpll is working in bypass mode or normal mode. the reset value indicates bypass mode. in legacy mode (fmpll_esyncr1[emode] negated), the mode bit will change to normal mode at the first time the fmpll_syncr is written. in enhanced mode (fmpll_esyncr1[emode] asserted), the mode bit reflects the value of the clkcfg[0] bit of the fmpll_esyncr1. 0 bypass mode 1 normal mode 25 pllsel mode select dual controller mode is not supported, therefore in legacy mode this bit resets to ?0? (bypass), but changes to ?1? (normal mode) at the first time the fmpll_syncr is written. in enhanced mode, the mode bit reflects the value of the clkcfg[1] bit of the fmpll_esyncr1. 0 legacy mode: bypass or dual controller; enhanced mode: pll off 1 legacy mode: normal; enhanced mode: pll on 26 pllref fmpll reference source this bit indicates whether the fmpll reference is from a crystal oscillator or from an external clock generator. the reset value is determined by the state of the pllref pin. in legacy mode, the reset value captured from the pllref pin cannot be changed anymore after reset. in enhanced mode, the pllref bit reflects the value of the clkcfg[2] bit of the fmpll_esyncr1. 0 external clock reference 1 crystal oscillator reference 27 locks sticky fmpll lock status bit this bit is set by the lock detect circuitry when the fmplll acquires lock after one of the following: ? a system reset ? a write to the fmpll_syncr in legacy mode which changes the prediv or mfd fields ? a write to the fmpll_esyncr1 in enhanced mode which changes the emode, eprediv, emfd or clkcfg[1:2] fields whenever the fmpll loses lock, locks is cleared. locks remains cleared even after the fmpll relocks, until one of the three previously stated conditions occurs. coming in bypass mode from system reset, locks is asserted as soon as the fmpll has locked, even if normal mode was not entered yet. if the fmpll is locked, going from normal to bypass mode does not clear the locks bit. 0 fmpll has lost lock since last system reset or last write to pll registers which affect the lock status. 1 fmpll has not lost lock. table 345. synsr field descriptions (continued) field description frequency-modulated phase locked loop (fmpll) RM0029 598/1740 doc id 15177 rev 8 enhanced synthesizer control register 1 (esyncr1) figure 368. enhanced synthesizer control register 1 (esyncr1) 28 lock fmpll lock status bit indicates whether the fmpll has acquired lock. fmpll lock occurs when the synthesized frequency matches to within approximately 4% of the programmed frequency. the fmpll loses lock when a frequency deviation of greater than approximately 16% occurs. the flag is also immediately negated when the prediv or mfd fields of the syncr are changed in legacy mode, or when emode, eprediv, emfd or clkcfg[1:2] are changed in enhanced mode, and then asserted again when the pll regains lock. if operating in bypass mode, the lock bit is still asserted or negated when the fmpll acquires or loses lock. 0 fmpll is unlocked. 1 fmpll is locked. 29 locf loss-of-clock flag this bit provides the interrupt request flag for the loss-of-clock. to clear the flag, software must write a 1 to the bit. writing 0 has no effect. this flag bit is sticky in the sense that if clocks return to normal, the bit will remain set until cleared by either writing 1 or asserting reset. the locf flag is not asserted while the fmpll is in bypass mode. see section 17.5.4, loss-of-clock detection , for information on which operating modes and conditions can this flag be asserted. 0 no loss of clock detected. interrupt service not requested. 1 loss of clock detected. interrupt service requested. 30?31 reserved, should be cleared. table 345. synsr field descriptions (continued) field description offset 0x0008 access: user read/write 0123456789101112131415 r emode clkcfg 00000000 eprediv w reset 0 0 1 ? (1) 000000001111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 emfd w reset0000000000100000 1. reset value determined by the pllref pin. RM0029 frequency-modulated phase locked loop (fmpll) doc id 15177 rev 8 599/1740 table 346. esyncr1 field descriptions field description 0 emode enhanced mode enable this bit determines whether th e fmpll will be controlled by syncr or esyncr1/esyncr2. at soc integration, a signal tie will dictate the default state that the pll operates. if the soc integration ties the fmpll to run in enhanced mode, the emode bit will reflect this by reading a logic 1. additionally, software writes to this bit to revert to legacy mode will not be allowed. if the signal is tied to select legacy mode as the default state, the emode bit will reflect this by reading a logic 0. in this case, software writes to this bit to enable enhanced mode is allowed, but it is a write once operation. after written to ?1?, further write attempts to this bit will have no effect. 0 legacy mode. fmpll controlled by syncr. 1 enhanced mode. fmpll controlled by esyncr1/esyncr2. 1?3 clkcfg clock configuration this 3-bit field is used to change the operating mode of the fmpll. bit 2 is not writable to ?0? while bit 1 is ?1?. the reset state of bit 3 is determined by the state of the pllref pin. 000 bypass mode with external reference and pll off 001 bypass mode with crystal reference and pll off 010 bypass mode with external reference and pll running 011 bypass mode with crystal reference and pll running 100 reserved 101 reserved 110 normal mode with external reference 111 normal mode with crystal reference 4?11 reserved, should be cleared. 12?15 eprediv enhanced predivider this 4-bit field controls the value of the divider on the input clock. the output of the predivider circuit generates the reference clock to the pll analog loop. the prediv value 1111 causes the input clock to be inhibited. 0000 divide by 1 0001 divide by 2 0010 divide by 3 0011 divide by 4 0100 divide by 5 0101 divide by 6 0110 divide by 7 0111 divide by 8 1000 divide by 9 1001 divide by 10 1010 divide by 11 1011 divide by 12 1100 divide by 13 1101 divide by 14 1110 divide by 15 1111 clock inhibit frequency-modulated phase locked loop (fmpll) RM0029 600/1740 doc id 15177 rev 8 enhanced synthesizer control register 2 (esyncr2) 16?24 reserved, should be cleared. 25?31 emfd enhanced multiplication factor divider this 7-bit field controls the value of the divider in the fmpll feedback loop. the value specified by the emfd bits establishes the multiplication factor applied to the reference frequency. the valid range of multiplication factors is 32 (010_0000) to 96 (110_0000). values outside this range are invalid and will cause the fmpll to produce unpredictable clock output. 00x_xxxx invalid 010_0000 divide by 32 010_0001 divide by 33 ... 101_1111 divide by 95 110_0000 divide by 96 110_0001 invalid ... 111_1111 invalid table 346. esyncr1 field descriptions (continued) field description figure 369. enhanced synthesizer control register 2 (esyncr2) offset 0x000c access: user read/write 0123456789101112131415 r0 00 00 00 0 locen lolre locre lolirq locirq 0 0 0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 00 00 00 00 00 00 0 erfd w reset0000000000000011 table 347. esyncr2 field descriptions field description 0?7 reserved, should be cleared. 8 locen loss-of-clock enable the locen bit determines if the loss-of-clock function is operational. this bit only has effect in normal mode. in bypass mode, the loss-of-clock function is always enabled, regardless of the state of the locen bit. furthermore, the locen bit has no effect on the loss-of-lock detection circuitry. 0 loss of clock disabled 1 loss of clock enabled RM0029 frequency-modulated phase locked loop (fmpll) doc id 15177 rev 8 601/1740 synthesizer fm modulation register (synfmmr) this register controls the frequency modulation (fm) features of the fmpll. fm is not backwards compatible with previous devices. therefore, this register must be used in enhanced mode. it can only be programmed when the fmpll is locked. writing to this register while the fmpll is unlocked has no effect. furthermore, when the pll loses lock, frequency modulation is disabled and the fmpll_synfmmr is reset. 9 lolre loss-of-lock reset enable the lolre bit determines whether system reset is asserted or not upon a loss-of-lock indication. when operating in normal mode, the fmpll must be locked before setting the lolre bit, otherwise reset is immediately asserted. note that once reset is asserted, the operating mode is switched to bypass mode, and once in bypass, a loss-of-lock condition does not generate reset, regardless of the value of the lolre bit. see section 17.5.3, lock detection . 0 ignore loss-of-lock. reset not asserted. 1 assert reset on loss-of-lock when operating in normal mode. 10 locre loss-of-clock reset enable the locre bit determines whether system reset is asserted or not upon a loss-of-clock condition when locen = 1. locre has no effect when locen = 0. if the locf bit in the synsr indicates a loss-of- clock condition, setting the locre bit causes immediate reset. in bypass mode with crystal reference, reset will occur if the reference clock fails, even if locre = 0 or even if locen = 0. the locre bit has no effect in bypass mode with external reference. in this mode, the reference clock is not monitored at all. see section , loss-of-clock reset . 0 ignore loss-of-clock. reset not asserted. 1 assert reset on loss-of-clock. 11 lolirq loss-of-lock interrupt request the lolirq bit enables a loss-of-lock interrupt request when the lolf flag is set. if either lolf or lolirq is negated, the interrupt request is negated. when operating in normal mode, the fmpll must be locked before setting the lolirq bit, otherwise an interrupt is immediately asserted. the interrupt request only happens in normal mode, therefore t he lolirq bit has no effect in bypass mode. see section 17.5.3, lock detection . 0 ignore loss-of-lock. interrupt not requested. 1 enable interrupt request upon loss-of-lock. 12 locirq loss-of-clock interrupt request the locirq bit enables a loss-of-clock interrupt request when the locf flag is set. if either locf or locirq is negated, the interrupt request is negated. if loss-of-clock is detected while in bypass mode, a system reset is generated. therefore, locirq has no effect in bypass mode. see section , loss-of- clock interrupt request . 0 ignore loss-of-clock. interrupt not requested. 1 enable interrupt request upon loss-of-clock. 13?29 reserved, should be cleared. 30?31 erfd enhanced reduced frequency divider this 2-bit field controls a divider at the output of the fmpll. the value specified by the erfd bits establishes the division factor applied to the fmpll frequency. 00 divide by 2 01 divide by 4 10 divide by 8 11 divide by 16 table 347. esyncr2 field descriptions (continued) field description frequency-modulated phase locked loop (fmpll) RM0029 602/1740 doc id 15177 rev 8 figure 370. synthesizer fm modulation register (synfmmr) offset 0x0018 access: user read/write 0123456789101112131415 r bsy mod en mod sel modperiod w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 incstep w reset0000000000000000 table 348. synfmmr field descriptions field description 0 bsy busy this bit is asserted soon after a write access to the fmpll_synfmmr, and remains asserted while the fmpll processes the new frequency modulation programming. the cpu must wait until this bit is negated before attempting another write access to this register. any write attempt while the bsy flag is set will have no effect. 0 write to the fmpll_synfmmr is allowed. 1 the fmpll is still busy processing the previous change on the fmpll_synfmmr; write access to the register is not possible. 1 moden modulation enable this bit enables the frequency modulation. 0 frequency modulation disabled 1 frequency modulation enabled 2 modsel modulation selection this bit selects whether modulation will be centered around the nominal frequency or spread below the nominal frequency. 0 modulation centered around nominal frequency. 1 modulation spread below nominal frequency. 3?15 modperiod modulation period this 13-bit field is the binary equivalent of the modperiod variable derived from the formula: where f fbk represents the frequency of the feedback divider, and f mod represents the modulation frequency. modperiod round f fbk 4f mod -------------------- - () = RM0029 frequency-modulated phase locked loop (fmpll) doc id 15177 rev 8 603/1740 note: the product of incstep and modperiod cannot be larger than (2 15 ? 1). 17.5 functional description this section explains the fmpll operation and configuration. 17.5.1 input clock frequency the fmpll is designed to operate over an input clock frequency range as determined by the operating mode. the operating ranges for each mode are given in table 349 . 17.5.2 clock configuration in legacy mode, the relationship between the output frequency f sys and input frequency f ref is determined by the prediv, mfd and rfd values programmed in the fmpll_syncr, according to the following equation: equation 3 i n legacy mode, the relationship between the vco frequency and the output frequency is determined by the value of the rfd value programmed in the syncr register, according to the following equation: 16 reserved, should be cleared. 17?31 incstep increment step this 14-bit field is the binary equivalent of the incstep variable derived from the formula: where md represents the peak modulation depth in percentage (+/ ? md for centered modulation, ? 2 * md for modulation below nominal frequency), and emfd represents the nominal value of the feedback loop divider. table 348. synfmmr field descriptions (continued) field description incstep round 2 15 1 ? () md emfd 100 5 modperiod -------------------------------------------------------------- () = table 349. input clock frequency at the predivider input mode input frequency range bypass mode with crystal reference normal mode with crystal reference 4 mhz ? 20/40 mhz (1) bypass mode with external reference normal mode with external reference 0 hz ? f sys (2) 1. see section 17.1, information specific to this device , for information on crystal frequencies supported. 2. f sys is the system frequency of the mcu. the predivider ratio has to be chosen such that the input to the pll itself (after the predivider) does not exceed 16 mhz. f sys f ref mfd 4 + prediv 1 + () 2 rfd -------------------------------------------------------- - = f vco f sys frequency-modulated phase locked loop (fmpll) RM0029 604/1740 doc id 15177 rev 8 equation 4 in enhanced mode, the relationship between input and output frequency is determined by the eprediv, emfd and erfd values programm ed in the fmpll_esyncr1 and fmpll_esyncr2, according to the following equation: equation 5 when programming the fmpll, be sure not to violate the maximum system clock frequency or max/min vco frequency specification. in enhanced mode, the vco frequency is calculated according to the following equation: equation 6 note: maximum system clock frequency is 150 mhz and max/min vco frequency is 256 mhz to 512 mhz. furthermore, the prediv or eprediv values must not be set to any value that causes the input frequency to the phase detector to go below 4 mhz. the lock flag is immediately negated after any of the following events: 1. in legacy mode, the prediv or mfd fields of the fmpll_syncr are changed 2. in enhanced mode, the emode, eprediv, emfd of clkcfg[1:2] fields of the fmpll_esyncr1 are changed (q) upon any of these events an internal timer is initialized to count 64 cycles of the pll input clock. during this period, the lock flag is held negated. after the timer expires, the lock flag reflects the value coming from the pll lock detection circuitry. to prevent an immediate reset, the lolre bit must be cleared before doing any of the above operations. changing rfd or erfd does not affect the fmpll, hence no relock delay is incurred. resulting changes in clock frequency are synchronized to the next falling edge of the current system clock. however, rfd or erfd should only be changed when the lock bit is set, to avoid exceeding the allowable system operating frequency. q. note that changing only the clkcfg[0] bit to move from bypass to normal or vice-versa, and keeping the values of the other fmpll_esyncr1 fields unchanged, will not cause the pll to lose lock or the lock flag to be cleared. f vco 4f sys 2 rfd = f sys f ref emfd eprediv 1 + () 2 erfd 1 + () ----------------------------------------------------------------------------- = f vco f ref emfd eprediv 1 + () ---------------------------------------- - = RM0029 frequency-modulated phase locked loop (fmpll) doc id 15177 rev 8 605/1740 coming out of reset, the fmpll will be enabled (on), but running in bypass mode. the recommended procedure to program the fmpll and engage normal mode is: 1. assert the emode bit and program the eprediv and emfd fields of fmpll_esyncr1 and the rfd field of fmpll_esyncr2. 2. poll fmpll_synsr[lock] until it asserts. 3. if required, program the fmpll_synfmmr with desired fm parameters, poll the bsy bit until it negates, then enable fm by asserting the moden bit. 4. engage normal mode by writing to fmpll_esyncr1[clkcfg]. 17.5.3 lock detection a pair of counters monitor the reference and feedback clocks to determine when the system has acquired frequency lock. once the fmpll has locked, the counters continue to monitor the reference and feedback clocks and will report if/when the fmpll has lost lock. the fmpll registers provide the flexibility to select whether to generate an interrupt, assert system reset or do nothing in the event that the fmpll loses lock. loss-of-lock reset and interrupt are only generated when the fmpll is operating in normal mode. the locf bit is not asserted by a loss-of-lock condition detected during bypass, although going to bypass mode from normal mode does not automatically clear the flag if it was asserted while the fmpll was in normal mode. 17.5.4 loss-of-clock detection the fmpll reference and output clocks may be continuously monitored by a module called clock quality monitor (cqm), shown in figure 371 . the intent of the cqm is to assure that the system bus clock is created from good clock sources. whether the clocks are monitored or not is determined by the clock operating mode and control bits in the fmpll registers, as shown in table 350 . in bypass mode with crystal reference, the reference clock is always monitored, regardless of the state of the locen bit. in bypass mode with external reference, the reference clock is not monitored, regardless of the state of the locen bit. this is done so that the whole device frequency range can be sourced from the external clock generator when using external reference mode. the fmpll output may only monitored in normal mode, depending on the state of the locen bit. the clock quality monitor uses an internal 4 mhz rc oscillator as a reference time base to measure the frequency of the crystal oscillator and the fmpll output. the frequency of these clocks are expected to be within the following frequency ranges: reference clock must be within the crystal frequency range (r) pll output must be above 1.5 mhz (minimum vco free-running frequency divided by the maximum erfd) in the event either of the clocks fall outside the expected window, a loss of clock condition is reported. the fmpll can be programmed to switch the system clock to a backup clock in the event of such a failure. additionally, the user may select to have the system enter reset, assert an interrupt request, or do nothing if/when the fmpll reports this condition. r. see section 17.1, information specific to this device , for information on crystal frequencies supported. frequency-modulated phase locked loop (fmpll) RM0029 606/1740 doc id 15177 rev 8 figure 371. clock quality monitor alternate/backup clock selection if loss-of-clock detection is enabled by locen, the fmpll is operating in normal mode and the clock quality monitor detects a failure at the fmpll output clock, then a backup clock selection feature automatically connects the system clock to the reference clock input (either external or crystal reference). after this happens, the system clock remains connected to the reference clock until next system reset, even if the fmpll regains itself and relocks. if, however, the reference clock also fails, either simultaneously or after the fmpll failure, the system clock is connected back to the fmpll output. if the reference fails in normal mode, then no backup clock selection occurs, and the fmpll output continues to be the system clock. if the reference stops, the fmpll will operate in free-running mode. rc oscillator 4 mhz crystal oscillator 4 ? 40 mhz > 1.5 mhz counter 1 counter 2 counter 3 pll control logic table 350. loss-of-clock monitoring operating mode locen (1) reference clock monitored? fmpll output monitored? bypass mode with external reference and pll off ? no no bypass mode with crystal reference and pll off ? yes no bypass mode with external reference and pll running ? no no bypass mode with crystal reference and pll running ? yes no normal mode with external reference 0no no 1no yes normal mode with crystal reference 0no no 1yes yes 1. locen is the loss-of-clock enable bit in either fmpll_syncr or fmpll_esyncr2, depending on fmpll_esyncr1[emode]. RM0029 frequency-modulated phase locked loop (fmpll) doc id 15177 rev 8 607/1740 in bypass mode with crystal reference, a reference fail will force a reset. in bypass mode with external reference, no backup clock selection occurs if the reference fails. loss-of-clock reset when a loss-of-clock condition is recognized, a system reset may be asserted depending on the clock operating mode and control bits in the fmpll registers, as shown in table 351 . fmpll_synsr[locf] and fmpll_synsr[loc] are cleared after reset, therefore, another means must be used externally to determine that a loss-of-clock condition occurred. locen and locre have no effect in bypass mode. if the reference fails while the fmpll is in bypass mode with crystal reference, a system reset is asserted regardless of the state of locen and locre. since bypass is the fmpll reset mode, the crystal oscillator must be present and functioning properly to exit reset when pllref = 1. when pllref = 0, the reference clock is not checked for loss-of-clock, so exit from reset can happen regardless the state of the reference clock. exit from reset is not affected by the state of the fmpll output because the fmpll clock is not monitored in bypass mode. loss-of-clock interrupt request when a loss-of-clock condition is recognized, an interrupt request may be asserted depending on the clock operating mode and control bits in the fmpll registers, as shown in ta ble 35 2 . locen and locirq have no effect in bypass mode. if the reference fails in bypass mode with crystal reference, a system reset is asserted instead of an interrupt request. if the reference fails in bypass with external reference, no reset or interrupts are generated. furthermore, no reset or interrupts are generated when lock is lost due to a write to the table 351. loss-of-clock reset operating mode locen (1) locre (2) reset reference failure fmpll failure bypass mode with external reference and pll off ? ? no no bypass mode with crystal reference and pll off ? ? yes no bypass mode with external reference and pll running ? ? no no bypass mode with crystal reference and pll running ?? yes no normal mode with external reference 0 ? no no 1 0 no no 11 no yes normal mode with crystal reference 0 ? no no 1 0 no no 11 yes yes 1. locen is the loss-of-clock enable bit in either fmpll_syncr or fmpll_esyncr2, depending on fmpll_esyncr1[emode]. 2. locre is the loss-of-clock reset enable bit in either fmpll_syncr or fmpll_esyncr2, depending on fmpll_esyncr1[emode]. frequency-modulated phase locked loop (fmpll) RM0029 608/1740 doc id 15177 rev 8 fmpll_syncr in legacy mode which modifies the prediv or mfd fields, or a write to fmpll_esyncr1 in enhanced mode which modifies the emode, eprediv, emfd or clkcfg[1:0] fields. 17.5.5 frequency modulation frequency modulation uses a triangular profile as shown in figure 372 . the modulation frequency and depth are set using the modperiod and incstep fields of the fmpll_synfmmr. figure 372. triangular frequency modulation table 352. loss-of-clock interrupt request operating mode locen (1) locirq (2) interrupt request reference failure fmpll failure bypass mode with external reference and pll off ? ? ? ? bypass mode with crystal reference and pll off ? ? no ? bypass mode with external reference and pll running ?? ? ? bypass mode with crystal reference and pll running ? ? no ? normal mode with external reference 0? ? no 10 ? no 11 ? yes normal mode with crystal reference 0 ? no no 1 0 no no 11 yes yes 1. locen is the loss-of-clock enable bit in ei ther fmpll_syncr or fmpll_esyncr2, depending on the fmpll_esyncr1[emode]. 2. locirq is the loss-of-clock interrupt enable bi t in either fmpll_syncr or fmpll_esyncr2, depending on the fmpll_esyncr1[emode]. 2 x md md f sys f sys center spread down spread f sys = pll nominal frequency md = modulation depth percentage RM0029 frequency-modulated phase locked loop (fmpll) doc id 15177 rev 8 609/1740 the following equations define how to calculate modperiod and incstep based on the frequency of the feedback divider (f fbk ), the modulation frequency (f mod ) and the modulation depth percentage (md): equation 7 equation 8 modperiod and incstep are subject to the following restriction: equation 9 because of the above rounding operations, the effective modulation depth applied to the fmpll is given by the following formula: equation 10 as an example, suppose the following configuration: input frequency: 4 mhz load divider (emfd): 64 input divider: 1 vco frequency: 4 mhz 64 = 256 mhz pll output frequency: 256 mhz / erfd center spread (modsel = 0) modulation frequency: 24 khz modulation depth: +/ ? 2.0 % (4% peak-to-peak) modperiod = round [(4 10 6 )/(4 24 10 3 )] = round [41.66] = 42 incstep = round [((2 15 ? 1) 2 64) / (100 5 42)] = round [199.722] = 200 modperiod incstep = 42 200 = 8400 (which is less than 2 15 ) md (quantized) = ((42 200 100 5) / ((2 15 ? 1) 64) = 2.00278 % in this example, the modulation depth error is 0.00278%. the fm parameters can only be changed, and fm can only be enabled, when the pll is locked. writing to the fmpll_synfmmr while the pll is unlocked has no effect. modperiod round f fbk 4f mod -------------------- - () = incstep round 2 15 1 ? () md emfd 100 5 modperiod ----------------------------------------------------------------- () = modperiod incstep () 2 15 < 100 5 2 15 1 ? () emfd --------------------------------------------------------------------------------------------------- - () = frequency-modulated phase locked loop (fmpll) RM0029 610/1740 doc id 15177 rev 8 furthermore, when the pll loses lock, the fm parameters are reset and the modulation is disabled until the pll relocks and the fmpll_synfmmr is programmed again. after programming the fm parameters, it takes some time until these parameters get propagated to the pll analog circuitry. during this time, the bsy bit gets asserted. the modulation must only be enabled when the fm parameters have already propagated to the analog circuitry. therefore, the sequence for programming fm is: 1. poll fmpll_synsr[lock] until it asserts. 2. program the modsel, modperiod and incstep fields of the fmpll_synfmmr. 3. poll fmpll_synfmmr[bsy] until it negates. 4. assert fmpll_synfmmr[moden]. RM0029 error correction status module (ecsm) doc id 15177 rev 8 611/1740 18 error correction st atus module (ecsm) 18.1 overview the error correction status module (ecsm) provides control functions regarding information on memory errors reported by error-correcting codes. the ecsm is mapped into the ips space and supports a number of miscellaneous control functions for the platform. 18.2 features program-visible information on the platform configuration and revision optional address map for device?s crossbar switch (xbar) miscellaneous reset status register (ecsm_mrsr) registers for capturing information on memory errors if error-correcting codes (ecc) are implemented 18.3 module memory map the error correction status module does not include any logic that provides access control. rather, this function is supported using the standard access control logic provided by the ips controller. ta ble 35 3 is a 32-bit view of the ecsm?s memory map. table 353. ecsm 32-bit memory map ecsm offset register 0x00 reserved reserved 0x04 reserved reserved 0x08 reserved 0x0c reserved miscellaneous reset status register (ecsm_mrsr) 0x10 reserved miscellaneous wakeup control register (ecsm_mwcr) 0x14 reserved 0x18 reserved 0x1c reserved 0x20 reserved 0x24 miscellaneous user-defined control register (ecsm_mudcr) 0x28 reserved 0x2c ? 0x3c reserved error correction status module (ecsm) RM0029 612/1740 doc id 15177 rev 8 18.4 register descriptions attempted accesses to reserved addresses result in an error termination, while attempted writes to read-only registers are ignored and do not terminate with an error. note: unless noted otherwise, writes to the programming model must match the size of the register , e.g., an n-bit register only supports n-bit writes, etc. attempted writes of a different size than the register width produce an error termination of the bus cycle and no change to the targeted register. 18.4.1 miscellaneous reset status register (ecsm_mrsr) the ecsm_mrsr contains a bit for each of the reset sources to the device. an asserted bit indicates the last type of reset that occurred. only one bit is set at any time in the ecsm_mrsr, reflecting the cause of the most recent reset as signalled by device reset input signals. the ecsm_mrsr can only be read from the ips programming model. any attempted write is ignored. 0x40 reserved ecc configuration register (ecsm_ecr) 0x44 reserved ecc status register (ecsm_esr) 0x48 reserved ecc error generation register (ecsm_eegr) 0x4c reserved 0x50 flash ecc address register (ecsm_fear) 0x54 reserved flash ecc master number register (ecsm_femr) flash ecc attributes (ecsm_feat) register 0x58 flash ecc data register high (ecsm_fedrh) 0x5c flash ecc data register low (ecsm_fedrl) 0x60 ram ecc address register (ecsm_rear) 0x64 reserved ram ecc syndrome register (ecsm_presr) ram ecc master number register (ecsm_remr) ram ecc attributes register (ecsm_reat) 0x68 ram ecc data register high (ecsm_redrh) 0x6c ram ecc data register low (ecsm_redrl) 0x70 ? 0x7c reserved table 353. ecsm 32-bit memory map (continued) ecsm offset register RM0029 error correction status module (ecsm) doc id 15177 rev 8 613/1740 18.4.2 miscellaneous wakeup control register (ecsm_mwcr) implementation of low-power sleep modes and exit from these modes via an interrupt require communication between the ecsm, the interrupt controller (intc) and external logic typically associated with phase-locked loop clock generation circuitry. the miscellaneous wakeup control register (ecsm_mwcr) provides an 8-bit register controlling entry into these types of low-power modes as well as definition of the interrupt level needed to exit the mode. the following sequence of operations is generally needed to enable this functionality. note that the exact details are likely to be system-specific. 1. the processor core loads the appropriate data value into the ecsm_mwcr, setting the enbwcr bit and the desired interrupt priority level. 2. at the appropriate time, the processor ceases execution. the exact mechanism varies by processor core. in some cases, a processor-is-stopped status is signaled to the ecsm and external logic. this assertion, if properly enabled by ecsm_mwcr[enbwcr], causes the ecsm output signal ?enter_low_power_mode? to be set. this, in turn, causes the selected external, low-power mode, to be entered, and the appropriate clock signals disabled. in most implementations, there are multiple low-power modes, where the exact clocks to be disabled vary across the different modes. 3. after entering the low-power mode, the interrupt controller enables a special combinational logic path which evaluates all unmasked interrupt requests. the device remains in this mode until an event which generates an unmasked interrupt request with a priority level greater than the value programmed in the ecsm_mwcr[prilvl] occurs. figure 373. miscellaneous reset status register (ecsm_mrsr) register address: ecsm base + 0x000f (0xfff4_000f) 01234567 rporofplr000000 w reset10000000 = unimplemented table 354. ecsm_mrsr field description name description 0 por power-on reset 1 = last recorded event was caused by a power-on reset (based on a device input signal) 1 ofplr device input reset 1 = last recorded event was a reset caused by a device input reset. error correction status module (ecsm) RM0029 614/1740 doc id 15177 rev 8 4. once the appropriately-high interrupt request level arrives, the interrupt controller signals its presence, and the ecsm responds by asserting an ?exit_low_power_mode? signal. 5. the external logic senses the assertion of the ?exit? signal, and re-enables the appropriate clock signals. 6. with the processor core clocks enabled, the core handles the pending interrupt request. 18.4.3 miscellaneous user-defined control register (ecsm_mudcr) the ecsm_mudcr is used to specify the number of additional wait states required for the device sram. please see the device datasheet for details on the cut-off frequency for the addition of 1 wait state. figure 374. miscellaneous wakeup control register (ecsm_mwcr) register address: ecsm base + 0x13 (0xfff4_0013) 01234567 r enbwcr 0 0 0 prilvl[0:3] w reset00000000 = unimplemented table 355. ecsm_mwcr field description name description 0 enbwcr enable wcr 0 = mwcr is disabled 1 = mwcr is enabled 4?7 prilvl[0:3] interrupt priority level the interrupt priority level is a core-specific definition. it specifies the interrupt priority level needed to exit the low-power mode. specifically, an unmasked interrupt request of a priority level greater than the prilvl value is required to exit the mode. certain interrupt controller implementations include logic associated with this priority level that restricts the data value contained in this field to a [0, maximum - 1] range. see the specific interrupt controller module for details. RM0029 error correction status module (ecsm) doc id 15177 rev 8 615/1740 18.4.4 ecc registers for platform designs including error-correcting code (ecc) implementations to improve the quality and reliability of memories, there are a number of program-visible registers for the sole purpose of reporting and logging of memory failures. these registers include: ecc configuration register (ecsm_ecr) ecc status register (ecsm_esr) ecc error generation register (ecsm_eegr) flash ecc address register (ecsm_fear) flash ecc master number register (ecsm_femr) flash ecc attributes register (ecsm_feat) flash ecc data register (ecsm_fedr) ram ecc address register (ecsm_rear) ram ecc syndrome register (ecsm_presr) ram ecc master number register (ecsm_remr) ram ecc attributes register (ecsm_reat) ram ecc data register (ecsm_redr) the details on the ecc registers are provided in the subsequent sections. figure 375. miscellaneous user-defined control register (ecsm_mudcr) register address: ecsm base + 0x0024 (0xfff4_0024) 0123456789101112131415 r 0swsc00000000000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w reset 0000000000000000 = unimplemented table 356. ecsm_mudcr field description name description 0 reserved 1 swsc sram wait state control 0 = no additional sram wait states 1 = 1 additional sram wait state 2?31 reserved error correction status module (ecsm) RM0029 616/1740 doc id 15177 rev 8 the 32-bit ecc organization essentially provides two completely independent error checking mechanisms for the total 64-bit ram width. the ecc logic provides a 1-of-3 error response vector for each 32 bits of memory: no error, single-bit correctable error, multi-bit non-correctable error. table 357 defines the association between the reported ecc result and the ram bank chip selects. as shown in table 357 , accesses of only a single memory bank report the ecc from that bank directly. for accesses involving both banks, the ?most severe? ecc response is reported with the even bank taking priority if the responses are equivalent. this approach also provides improved correction capabilities compared to the 64-bit ecc implementation. ecc configuration register (ecsm_ecr) the ecc configuration register is an 8-bit control register for specifying which types of memory errors are reported. in all systems with ecc, the occurrence of a non-correctable error causes the current access to be terminated with an error condition. in many cases, this error termination is reported directly by the initiating bus master. however, there are certain situations where the occurrence of this type of non-correctable error is not reported by the master. examples include speculative instruction fetches which are discarded due to a change-of-flow operation, and buffered operand writes. the ecc reporting logic in the ecsm provides an optional error interrupt mechanism to signal all non-correctable memory errors. in addition to the interrupt generation, the ecsm captures specific information table 357. ahb response and ecc reporting for even and odd ecc ram valid even ram valid odd ecc even ecc odd reported ecc ram bus response even ram bus response odd ahb hresp 00 x x no access, no_error xxxx xxxx okay 1 0 none x no_error data xxxx okay 1 0 single x even_single corrected xxxx okay 1 0 multi x even_multi non-corrected xxxx err 0 1 x none no_error xxxx data okay 0 1 x single odd_single xxxx corrected okay 0 1 x multi odd_multi xxxx non-corrected err 1 1 none none no_error data data okay 1 1 single none even_single corrected data okay 1 1 multi none even_multi non-corrected data err 1 1 none single odd_single data corrected okay 1 1 single single even_single corrected corrected okay 1 1 multi single even_multi non-corrected corrected err 1 1 none multi odd_multi data non-corrected err 1 1 single multi odd_multi corrected non-corrected err 1 1 multi multi even_multi non-corrected non-corrected err RM0029 error correction status module (ecsm) doc id 15177 rev 8 617/1740 (memory address, attributes and data, bus master number, etc.) which can be useful for subsequent failure analysis. figure 376. ecc configuration register (ecsm_ecr) register address: ecsm base + 0x0043 (0xfff4_0043) 01234567 r0 0 er1br ef1br 00 erncr efncr w reset00000000 = unimplemented table 358. ecsm_ecr field description name description 2 er1br enable ram 1-bit reporting 0 = reporting of single-bit platform ram corrections is disabled. 1 = reporting of single-bit platform ram corrections is enabled. the occurrence of a single-bit ram correction generates an ecsm ecc interrupt request as signalled by the assertion of ecsm_esr[r1bc]. the address, attributes and data are also captured in the ecsm_rear, ecsm_presr, ecsm_remr, ecsm_reat and ecsm_redr registers. 3 ef1br enable flash 1-bit reporting 0 = reporting of single-bit platform flash corrections is disabled. 1 = reporting of single-bit platform flash corrections is enabled. the occurrence of a single-bit flash correction generates an ecsm ecc interrupt request as signalled by the assertion of ecsm_esr[f1bc]. the address, attributes and data are also captured in the ecsm_fear, ecsm_femr, ecsm_feat and ecsm_fedr registers. 6 erncr enable ram non-correctable reporting 0 = reporting of non-correctable platform ram errors is disabled. 1 = reporting of non-correctable platform ram errors is enabled. the occurrence of a non-correctable multi-bit ram error generates an ecsm ecc interrupt request as signalled by the assertion of ecsm_esr[rnce]. the faulting address, attributes and data are also captured in the ecsm_rear, ecsm_presr , ecsm_remr, ecsm_reat and ecsm_redr registers. 7 efncr enable flash non-correctable reporting 0 = reporting of non-correctable platform flash errors is disabled. 1 = reporting of non-correctable platform flash errors is enabled. the occurrence of a non-correctable multi-bit flash error generates an ecsm ecc interrupt request as signalled by the assertion of ecsm_esr[fnce]. the faulting address, attributes and data are also captured in the ecsm_fear, ecsm_femr, ecsm_feat and ecsm_fedr registers. error correction status module (ecsm) RM0029 618/1740 doc id 15177 rev 8 ecc status register (ecsm_esr) the ecc status register is an 8-bit control register for signaling which types of properly- enabled ecc events have been detected. the ecsm_esr signals the last, properly- enabled memory event to be detected. an ecc interrupt request is asserted if any flag bit is asserted and its corresponding enable bit is asserted. ecc interrupt generation is separated into single-bit error detection/correction, uncorrectable error detection and the combination of the two as defined by the following boolean equations: ecsm_ecc1bit_irq = ecsm_ecr[er1br] & ecsm_esr[r1bc] // platform ram, 1-bit correction | ecsm_ecr[ef1br] & ecsm_esr[f1bc] // platform flash, 1-bit correction ecsm_eccrncr_irq = ecsm_ecr[erncr] & ecsm_esr[rnce] // platform ram, noncorrectable error ecsm_eccfncr_irq = ecsm_ecr[efncr] & ecsm_esr[fnce] // platform flash, noncorrectable error ecsm_ecc2bit_irq = ecsm_eccrncr_irq // platform ram, noncorrectable error | ecsm_eccfncr_irq // platform flash, noncorrectable error ecsm_ecc_irq = ecsm_ecc1bit_irq // 1-bit correction | ecsm_ecc2bit_irq // noncorrectable error where the combination of a properly-enabled category in the ecsm_ecr and the detection of the corresponding condition in the ecsm_esr produces the interrupt request. the ecsm allows a maximum of one bit of the ecsm_esr to be asserted at any given time. this preserves the association between the ecsm_esr and the corresponding address and attribute registers, which are loaded on each occurrence of a properly-enabled ecc event. if there is a pending ecc interrupt and another properly-enabled ecc event occurs, the ecsm hardware automatically handles the ecsm_esr reporting, clearing the previous data and loading the new state and thus guaranteeing that only a single flag is asserted. to maintain the coherent software view of the reported event, the following sequence in the ecsm error interrupt service routine is suggested: 1. read the ecsm_esr and save it. 2. read and save all the address and attribute reporting registers. 3. re-read the ecsm_esr and verify the current contents matches the original contents. if the two values are different, go back to step 1 and repeat. 4. when the values are identical, write a ?1? to the asserted esr flag to negate the interrupt request. RM0029 error correction status module (ecsm) doc id 15177 rev 8 619/1740 figure 377. ecc status register (ecsm_esr) register address: ecsm base + 0x0047 (0xfff4_0047) 01234567 r 0 0 r1bc f1bc 0 0 rnce fnce w reset00000000 = unimplemented table 359. ecsm_esr field description name description 2 r1bc platform ram 1-bit correction 0 = no reportable single-bit platform ram correction has been detected. 1 = a reportable single-bit platform ram correction has been detected. this bit can only be set if ecsm_ecr[er1br] is asserted. the occurrence of a properly-enabled single-bit ram correction generates an ecsm ecc interrupt request. the address, attributes and data are also captured in the ecsm_rear, ec sm_presr, ecsm_remr, ecsm_reat and ecsm_redr registers. to clear this interrupt flag, write a ?1? to this bit. writing a ?0? has no effect. 3 f1bc platform flash 1-bit correction 0 = no reportable single-bit platform flash correction has been detected. 1 = a reportable single-bit platform flash correction has been detected. this bit can only be set if ecsm_ecr[ef1br] is asserted. the occurrence of a properly-enabled single-bit flash correction generates an ecsm ecc interrupt request. the address, attributes and data are also captured in the ecsm_fear, ecsm_femr, ecsm_feat and ecsm_fedr registers. to clear this interrupt flag, write a ?1? to this bit. writing a ?0? has no effect. 6 rnce platform ram non-correctable error 0 = no reportable non-correctable platform ram error has been detected. 1 = a reportable non-correctable platform ram error has been detected. the occurrence of a properly-enabled non-correctable ram error generates an ecsm ecc interrupt request. the faulting address, attributes and data are also captured in the ecsm_rear, ecsm_presr, ecsm_remr, ecsm_reat and ecsm_re dr registers. to clear this interrupt flag, write a ?1? to this bit. writing a ?0? has no effect. 7 fnce platform flash non-correctable error 0 = no reportable non-correctable platform flash error has been detected. 1 = a reportable non-correctable platform flash error has been detected. the occurrence of a properly-enabled non-correctable flash error generates an ecsm ecc interrupt request. the faulting address, attributes and data are also captured in the ecsm_fear, ecsm_femr, ecsm_feat and ecsm_fedr registers. to clear this interrupt flag, write a ?1? to this bit. writing a ?0? has no effect. error correction status module (ecsm) RM0029 620/1740 doc id 15177 rev 8 in the event that multiple status flags are signaled simultaneously, the ecsm records the event with the r1bc as highest priority, then f1bc, then rnce, and finally fnce. ecc error generation register (ecsm_eegr) the ecc error generation register is a 16-bit control register used to force the generation of single- and double-bit data inversions in the memories with ecc, most notably the ram. this capability is provided for two purposes: it provides a software-controlled mechanism for ?injecting? errors into the memories during data writes to verify the integrity of the ecc logic. it provides a mechanism to allow testing of the software service routines associated with memory error logging. it should be noted that while the ecsm_eegr is associated with the ram, similar capabilities exist for the flash, that is, the ability to program the non-volatile memory with single- or double-bit errors is supported for the same two reasons previously identified. for both types of memories (ram and flash), the intent is to generate errors during data write cycles, such that subsequent reads of the corrupted address locations generate ecc events, either single-bit corrections or double-bit non-correctable errors that are terminated with an error response. figure 378. ecc error generation register (ecsm_eegr) register address: ecsm base + 0x004a (0xfff4_004a) 0123456789101112131415 r frcap 0 frc1bi (1) fr11bi (1) 00 frcnci fr1nci 0 errbit[6:0] w reset 0000000000000000 = unimplemented 1. this field is writable only in test mode in cut 1.0 devices. table 360. ecsm_eegr field description name description 0 frcap force ram error injection access protection 0 = all platform masters are able to generate ram ecc errors via the ecsm_eegr. 1 = only the platform master with id=0 (usually the core) can generate ram ecc errors via the ecsm_eegr. the assertion of this bit ensures that ram data inversions can only occur from the master module with the master id of 0. since this is usually the core, this protects the ram from errant or multiple simultaneous attempted data inversions from other master modules and, in the case of a multi-core system, ensures that only one core can issue a ram data inversion. the reset value of the bit is 0 and as a result, ram data inversions can be requested from any master module. it is the responsibility of the software to ensure the proper setting of this bit. RM0029 error correction status module (ecsm) doc id 15177 rev 8 621/1740 2 frc1bi (1) force ram continuous 1-bit data inversions 0 = no ram continuous 1-bit data inversions are generated. 1 = 1-bit data inversions in the ram are continuously generated. the assertion of this bit forces the ram controller to create 1-bit data inversions, as defined by the bit position specified in errbit[6:0], continuously on every write operation. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit is inverted to introduce a 1-bit ecc event in the ram. after this bit has been enabled to generate another continuous 1-bit data inversion, it must be cleared before being set again to correctly re-enable the error generation logic. 3 fr11bi (1) force ram one 1-bit data inversion 0 = no ram single 1-bit data inversion is generated. 1 = one 1-bit data inversion in the ram is generated. the assertion of this bit forces the ram controller to create one 1-bit data inversion, as defined by the bit position specified in errbit[6:0], on the first write operation after this bit is set. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit is inverted to introduce a 1-bit ecc event in the ram. after this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being set again to properly re-enable the error generation logic. 6 frcnci force ram continuous non-correctable data inversions 0 = no ram continuous 2-bit data inversions are generated. 1 = 2-bit data inversions in the ram are continuously generated. the assertion of this bit forces the ram controller to create 2-bit data inversions, as defined by the bit position specified in errbit[6:0] and the overall odd parity bit, continuously on every write operation. after this bit has been enabled to generate another continuous non-correctable data inversion, it must be cleared before being set again to properly re-enable the error generation logic. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit and the overall odd parity bit are inverted to introduce a 2-bit ecc error in the ram. table 360. ecsm_eegr field description (continued) name description error correction status module (ecsm) RM0029 622/1740 doc id 15177 rev 8 7 fr1nci force ram one non-correctable data inversions 0 = no ram single 2-bit data inversions are generated. 1 = one 2-bit data inversion in the ram is generated. the assertion of this bit forces the ram controller to create one 2-bit data inversion, as defined by the bit position specified in errbit[6:0] and the overall odd parity bit, on the first write operation after this bit is set. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit and the overall odd parity bit are inverted to introduce a 2-bit ecc error in the ram. after this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly re-enable the error generation logic. table 360. ecsm_eegr field description (continued) name description RM0029 error correction status module (ecsm) doc id 15177 rev 8 623/1740 if an attempt to force a non-correctable inversion (by asserting ecsm_eegr[frcnci] or ecsm_eegr[frc1nci]) and ecsm_eegr[errbit] equals 64, then no data inversion will be generated. errbit [6:0] the vector defines the bit position which is complemented to create the data inversion on the write operation. for the creation of 2-bit data inversions, the bit specified by this field plus the odd parity bit of the ecc code are inverted. the ram controller follows a vector bit ordering scheme where lsb=0. errors in the ecc syndrome bits can be generated by setting this field to a value greater than the ram width. for example, consider a 64-bit ram implementation and ecc organized on a 32-bit boundary. the 32-bit ecc approach requires 7 code bits for each 32-bit word. for ram data width of 64 bits, the actual sram is 2 (32 bits data + 7 bits for ecc) = 78 bits which is organized as two 39-bit memory banks, ?even? bank and ?odd? bank. the following association between the errbit field and the corrupted memory bit is defined: if errbit = 0, then ram[0] of the odd bank is inverted if errbit = 1, then ram[1] of the odd bank is inverted ... if errbit = 31, then ram[31] of the odd bank is inverted if errbit = 32, then ram[0] of the even bank is inverted if errbit = 33, then ram[1] of the even bank is inverted ... if errbit = 63, then ram[31] of the even bank is inverted if errbit = 64, then ecc parity[0] of the odd bank is inverted if errbit = 65, then ecc parity[1] of the odd bank is inverted ... if errbit = 70, then ecc parity[6] of the odd bank is inverted if errbit = 71, then ecc parity[0] of the even bank is inverted if errbit = 72, then ecc parity[1] of the even bank is inverted ... if errbit = 77, then ecc parity[6] of the even bank is inverted for errbit values between 78 and 95, no bit position is inverted. to accommodate address bus inversions, the errbit values start at 96 as defined: if errbit = 96, then addr[0] is inverted if errbit = 97, then addr[1] is inverted ... if errbit = 114, then addr[18] is inverted if errbit = 115, then addr[19] is inverted for errbit values greater than 115, the address bus inversion has no effect as only the lower 20 bits are used by the platform ram controller. 1. this field is writable only in test mode in cut 1.0 devices. table 360. ecsm_eegr field description (continued) name description error correction status module (ecsm) RM0029 624/1740 doc id 15177 rev 8 the only allowable values for the four control bit enables {fr11bi, frc1bi, frcnci, fr1nci} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. all other values result in unpredictable operations. flash ecc address register (ecsm_fear) the ecsm_fear is a 32-bit register for capturing the address of the last, properly-enabled ecc event in the platform flash memory. depending on the state of the ecc configuration register, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the ecsm_fear, ecsm_femr, ecsm_feat and ecsm_fedrs, and the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; any attempted write is ignored. flash ecc master number register (ecsm_femr) the ecsm_femr is a 4-bit register for capturing the xbar bus master number of the last, properly-enabled ecc event in the flash memory. depending on the state of the ecc configuration register, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the ecsm_fear, ecsm_femr, ecsm_feat and ecsm_fedr registers, and the appropriate flag (fnce) in the ecc status register to be asserted. figure 379. flash ecc address register (ecsm_fear) register address: ecsm base + 0x0050 (0xfff4_0054) 0123456789101112131415 r fear[31:16] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fear[15:0] w reset???????????????? = unimplemented table 361. ecsm_fear field description name description 0?31 fear[31:0] flash ecc address register this 32-bit register contains the faulting access address of the last, properly-enabled flash ecc event. RM0029 error correction status module (ecsm) doc id 15177 rev 8 625/1740 this register can only be read from the ips programming model; any attempted write is ignored. flash ecc attributes (ecsm_feat) register the ecsm_feat register is an 8-bit register for capturing the xbar bus master attributes of the last, properly-enabled ecc event in the flash memory. depending on the state of the ecc configuration register, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the ecsm_fear, ecsm_femr, ecsm_feat and ecsm_fedr registers, and the appropriate flag (fnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; any attempted write is ignored. figure 380. flash ecc master number register (ecsm_femr) register address: ecsm base + 0x0056 (0xfff4_0056) 01234567 r0000 femr[3:0] w reset0000 ???? = unimplemented table 362. ecsm_femr field description name description 4?7 femr[3:0] flash ecc master number register this 4-bit register contains the xbar bus master number of the faulting access of the last, properly-enabled flash ecc event. figure 381. flash ecc attributes (ecsm_feat) register register address: ecsm base + 0x0057 (0xfff4_0057) 01234567 r write size[2:0] prot0 prot1 prot2 prot3 w reset???????? = unimplemented error correction status module (ecsm) RM0029 626/1740 doc id 15177 rev 8 flash ecc data register (ecsm_fedrh, ecsm_fedrl) the ecsm_fedr is a 64-bit register for capturing the data associated with the last, properly-enabled ecc event in the flash memory. depending on the state of the ecc configuration register, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the ecsm_fear, ecsm_femr, ecsm_feat, and ecsm_fedr registers, and the appropriate flag (fnce) in the ecc status register to be asserted. the data captured on a multi-bit non-correctable ecc error is undefined. this register can only be read from the ips programming model; any attempted write is ignored. table 363. ecsm_feat field description name description 0 write amba-ahb hwrite 0 = amba-ahb read access 1 = amba-ahb write access 1?3 size[2:0] amba-ahb hsize 0b000 = 8-bit amba-ahb access 0b001 = 16-bit amba-ahb access 0b010 = 32-bit amba-ahb access 0b011 = reserved 0b1xx = reserved 4?7 protn amba-ahb hprot prot3: cacheable 0 = non-cacheable,1 = cacheable prot2: bufferable 0 = non-bufferable,1 = bufferable prot1: mode 0 = user mode, 1 = supervisor mode prot0: type 0 = i-fetch, 1 = data RM0029 error correction status module (ecsm) doc id 15177 rev 8 627/1740 ram ecc address register (ecsm_rear) the ecsm_rear is a 32-bit register for capturing the address of the last, properly-enabled ecc event in the ram memory. depending on the state of the ecc configuration register, an ecc event in the ram causes the address, attributes and data associated with the access to be loaded into the ecsm_rear, ecsm_presr, ecsm_remr, ecsm_reat and ecsm_redr registers, and the appropriate flag (rnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; any attempted write is ignored. figure 382. flash ecc data register (ecsm_fedrh, ecsm_fedrl) register address: ecsm base + 0x58, +0x5c ( (0xfff4_0058, 0xfff4_005c) 0123456789101112131415 r fedh[31:16] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fedh[15:0] w reset???????????????? 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 r fedl[31:16] w reset???????????????? 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 r fedl[15:0] w reset???????????????? = unimplemented table 364. ecsm_fedr field description name description 0?63 fedh[31:0] fedl[31:0] flash ecc data register this 64-bit register contains the data associated with the faulting access of the last, properly- enabled flash ecc event. the register contains the data value taken directly from the data bus. error correction status module (ecsm) RM0029 628/1740 doc id 15177 rev 8 ram ecc syndrome register (ecsm_presr) the ecsm_presr is an 8-bit register for capturing the error syndrome of the last, properly- enabled ecc event in the ram memory. depending on the state of the ecc configuration register, an ecc event in the ram causes the address, attributes and data associated with the access to be loaded into the ecsm_rear, ecsm_presr, ecsm_remr, ecsm_reat and ecsm_redr registers, and the appropriate flag (rnce) in the ecc status register to be asserted. the ecsm_presr can only be read from the ips programming model; any attempted write is ignored. figure 383. ram ecc address register (ecsm_rear) register address: ecsm base + 0x0060 (0xfff4_0060) 0123456789101112131415 r rear[31:16] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rear[15:0] w reset???????????????? = unimplemented table 365. ecsm_rear field description name description 0?31 rear[31:0] ram ecc address register this 32-bit register contains the faulting access address of the last, properly-enabled ram ecc event. figure 384. ram ecc syndrome register (ecsm_presr) register address: ecsm base + 0x0065 (0xfff4_0065) 01234567 r presr[7:0] w reset???????? = unimplemented RM0029 error correction status module (ecsm) doc id 15177 rev 8 629/1740 note: ta ble 36 7 associates the 8 bits of the ecc syndrome with the exact data bit in error for single-bit correctable code words. this table follows the bit vectoring notation where the lsb = 0. the syndrome value of 0x00 implies no error condition but this value is not readable when the ecsm_presr is read for the no error case. table 366. ecsm_presr field description name description 0?7 presr[7:0] ram ecc syndrome register this 8-bit syndrome field includes optimized syndrome encoding for the entire 39-bit (32-bit data + 7-bit ecc) code word of each bank for single-bit errors. syndrome values for non-correctable errors are not defined. for correctable single-bit errors, the mapping shown in table 367 associates the 8 bits of the syndrome with the data bit in error. table 367. ram syndrome mapping for single-bit correctable errors presr[7:0] data bit in error 0x01 ecc odd[0] 0x02 ecc odd[1] 0x04 ecc odd[2] 0x07 data odd bank[31] 0x08 ecc odd[3] 0x10 ecc odd[4] 0x20 ecc odd[5] 0x40 ecc odd[6] 0x43 data odd bank[0] 0x45 data odd bank[1] 0x46 data odd bank[2] 0x49 data odd bank[3] 0x4a data odd bank[4] 0x4c data odd bank[5] 0x4f data odd bank[21] 0x51 data odd bank[6] 0x52 data odd bank[7] 0x54 data odd bank[8] 0x57 data odd bank[22] 0x58 data odd bank[9] 0x5b data odd bank[23] 0x5d data odd bank[24] 0x5e data odd bank[25] error correction status module (ecsm) RM0029 630/1740 doc id 15177 rev 8 0x61 data odd bank[10] 0x62 data odd bank[11] 0x64 data odd bank[12] 0x67 data odd bank[26] 0x68 data odd bank[13] 0x6b data odd bank[27] 0x6d data odd bank[28] 0x6e data odd bank[29] 0x70 data odd bank[14] 0x73 data odd bank[15] 0x75 data odd bank[16] 0x76 data odd bank[17] 0x79 data odd bank[18] 0x7a data odd bank[19] 0x7c data odd bank[20] 0x7f data odd bank[30] 0x81 ecc even[0] 0x82 ecc even[1] 0x84 ecc even[2] 0x87 data even bank[31] 0x88 ecc even[3] 0x90 ecc even[4] 0xa0 ecc even[5] 0xc0 ecc even[6] 0xc3 data even bank[0] 0xc5 data even bank[1] 0xc6 data even bank[2] 0xc9 data even bank[3] 0xca data even bank[4] 0xcc data even bank[5] 0xcf data even bank[21] 0xd1 data even bank[6] 0xd2 data even bank[7] 0xd4 data even bank[8] 0xd7 data even bank[22] table 367. ram syndrome mapping for single-bit correctable errors (continued) presr[7:0] data bit in error RM0029 error correction status module (ecsm) doc id 15177 rev 8 631/1740 ram ecc master number register (ecsm_remr) the ecsm_remr is a 4-bit register for capturing the xbar bus master number of the last, properly-enabled ecc event in the ram memory. depending on the state of the ecc configuration register, an ecc event in the ram causes the address, attributes and data associated with the access to be loaded into the ecsm_rear, ecsm_presr, ecsm_remr, ecsm_reat and ecsm_redr regi sters, and the appropriate flag (rnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; any attempted write is ignored. 0xd8 data even bank[9] 0xdb data even bank[23] 0xdd data even bank[24] 0xde data even bank[25] 0xe1 data even bank[10] 0xe2 data even bank[11] 0xe4 data even bank[12] 0xe7 data even bank[26] 0xe8 data even bank[13] 0xeb data even bank[27] 0xed data even bank[28] 0xee data even bank[29] 0xf0 data even bank[14] 0xf3 data even bank[15] 0xf5 data even bank[16] 0xf6 data even bank[17] 0xf9 data even bank[18] 0xfa data even bank[19] 0xfc data even bank[20] 0xff data even bank[30] table 367. ram syndrome mapping for single-bit correctable errors (continued) presr[7:0] data bit in error error correction status module (ecsm) RM0029 632/1740 doc id 15177 rev 8 ram ecc attributes register (ecsm_reat) the ecsm_reat register is an 8-bit register for capturing the xbar bus master attributes of the last, properly-enabled ecc event in the ram memory. depending on the state of the ecc configuration register, an ecc event in the ram causes the address, attributes and data associated with the access to be loaded into the ecsm_rear, ecsm_presr, ecsm_remr, ecsm_reat and ecsm_redr regi sters, and the appropriate flag (rnce) in the ecc status register to be asserted. the ecsm_reat register is read-only. figure 385. ram ecc master number register (ecsm_remr) register address: ecsm base + 0x0066 (0xfff4_0066) 01234567 r0000 remr[3:0] w reset0000 ???? = unimplemented table 368. ecsm_remr field description name description 4?7 remr[3:0] ram ecc master number register this 4-bit register contains the xbar bus master number of the faulting access of the last, correctly-enabled ram ecc event. figure 386. ram ecc attributes (ecsm_reat) register register address: ecsm base + 0x0067 (0xfff4_0067) 01234567 r write size[2:0] prot0 prot1 prot2 prot3 w reset???????? = unimplemented RM0029 error correction status module (ecsm) doc id 15177 rev 8 633/1740 ram ecc data register (ecsm_redrh, ecsm_redrl) the ecsm_redr is a 64-bit register for capturing the data associated with the last, properly-enabled ecc event in the ram memory. depending on the state of the ecc configuration register, an ecc event in the ram causes the address, attributes and data associated with the access to be loaded into the ecsm_rear, ecsm_presr, ecsm_remr, ecsm_reat and ecsm_redr regi sters, and the appropriate flag (rnce) in the ecc status register to be asserted. the data captured on a multi-bit non-correctable ecc error is undefined. since the ram controller calculates ecc on a 32-bit boundary, only the 32-bit piece of data containing the error is recorded in the lower 32-bit word. the upper 32 bits will read back all zeroes as defined. this register can only be read from the ips programming model; any attempted write is ignored. table 369. ecsm_reat field description name description 0 write amba-ahb hwrite 0 = amba-ahb read access 1 = amba-ahb write access 1?3 size[2:0] amba-ahb hsize 0b000 = 8-bit amba-ahb access 0b001 = 16-bit amba-ahb access 0b010 = 32-bit amba-ahb access 0b011 = 64-bit amba-ahb access 0b1xx = reserved 4?7 protn amba-ahb hprot prot3: cacheable 0 = non-cacheable, 1 = cacheable prot2: bufferable 0 = non-bufferable, 1 = bufferable prot1: mode 0 = user mode, 1 = supervisor mode prot0: type 0 = i-fetch, 1 = data error correction status module (ecsm) RM0029 634/1740 doc id 15177 rev 8 figure 387. ram ecc data register (ecsm_redr) register address: ecsm base + 0x68, +0x6c (0xfff4_0068, (0xfff4_006c) 0123456789101112131415 r redh[31:16] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rredh[15:0] w reset???????????????? 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 r redl[31:16] w reset???????????????? 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 r redl[15:0] w reset???????????????? = unimplemented table 370. ecsm_redr field description name description 0?63 redh[31:0] redl[31:0] ram ecc data register this 64-bit register contains the data associated with the faulting access of the last, properly-enabled ram ecc event. the register contains the data value taken directly from the data bus. RM0029 system timer module (stm) doc id 15177 rev 8 635/1740 19 system timer module (stm) 19.1 information specific to this device this section presents device-specific parameterization and customization information not specifically referenced in the remainder of this chapter. 19.1.1 device-specific features one 32-bit up counter with 8-bit prescaler four 32-bit compare channels independent interrupt source for each channel counter can be stopped in debug mode 19.2 introduction 19.2.1 overview the system timer module (stm) is a 32-bit timer designed to support commonly required system and application software timing functions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). 19.2.2 modes of operation the stm supports two device modes of operation: normal and debug. when the stm is enabled in normal mode, its counter runs continuously. in debug mode, operation of the counter is controlled by the frz bit in the stm_cr register. if the frz bit is set, the counter is stopped in debug mode, otherwise it continues to run. 19.3 external signal description the stm does not have any external interface signals. 19.4 memory map and register definition the stm programming model has fourteen 32-bit registers. the stm registers can only be accessed using 32-bit (word) accesses. attempted references using a different size or to a reserved address generates a bus error termination. 19.4.1 memory map the stm memory map is shown in ta ble 37 1 . system timer module (stm) RM0029 636/1740 doc id 15177 rev 8 19.4.2 register descriptions the following sections detail the individual registers within the stm programming model. table 371. stm memory map address offset register description size (bits) access location 0x0000 stm control register(stm_cr) 32 r/w on page 19- 637 0x0004 stm count register(stm_cnt) 32 r/w on page 19- 637 0x0008 reserved ? ? ? 0x000c reserved ? ? ? 0x0010 stm channel 0 control register(stm_ccr0) 32 r/w on page 19- 638 0x0014 stm channel 0 interrupt register(stm_cir0) 32 r/w on page 19- 638 0x0018 stm channel 0 compare register(stm_cmp0) 32 r/w on page 19- 639 0x001c reserved ? ? ? 0x0020 stm channel 1 control register(stm_ccr1) 32 r/w on page 19- 638 0x0024 stm channel 1 interrupt register(stm_cir1) 32 r/w on page 19- 638 0x0028 stm channel 1 compare register(stm_cmp1) 32 r/w on page 19- 639 0x002c reserved ? ? ? 0x0030 stm channel 2 control register(stm_ccr2) 32 r/w on page 19- 638 0x0034 stm channel 2 interrupt register(stm_cir2) 32 r/w on page 19- 638 0x0038 stm channel 2 compare register(stm_cmp2) 32 r/w on page 19- 639 0x003c reserved ? ? ? 0x0040 stm channel 3 control register(stm_ccr3) 32 r/w on page 19- 638 0x0044 stm channel 3 interrupt register(stm_cir3) 32 r/w on page 19- 638 0x0048 stm channel 3 compare register(stm_cmp3) 32 r/w on page 19- 639 0x004c ? 0x3fff reserved ? ? ? RM0029 system timer module (stm) doc id 15177 rev 8 637/1740 stm control register (stm_cr) the stm control register (stm_cr) includes the prescale value, freeze control and timer enable bits. stm count register (stm_cnt) the stm count register (stm_cnt) holds the timer count value. figure 388. stm control register (stm_cr) offset 0x000 access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cps 0 0 0 0 00 frz ten w reset0000000000000000 table 372. stm_cr field description field description cps counter prescaler selects the clock divide value for the prescaler (1 ? 256) 0x00 = divide system clock by 1 0x01 = divide system clock by 2 ... 0xff = divide system clock by 256 frz freeze allows the timer counter to be stopped when the device enters debug mode 0 = stm counter continues to run in debug mode. 1 = stm counter is stopped in debug mode. ten timer counter enabled 0 = counter is disabled 1 = counter is enabled system timer module (stm) RM0029 638/1740 doc id 15177 rev 8 stm channel n control register (stm_ccrn) the stm channel n control register (stm_ccrn) has the enable bit for channel n of the timer. stm channel n interrupt register (stm_cirn) the stm channel n interrupt register (stm_cirn) has the interrupt flag for channel n of the timer. figure 389. stm count register (stm_cnt) offset 0x004 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cnt w reset00000000000000000000000000000000 table 373. stm_cnt field description field description cnt timer count value used as the time base for all channels when enabled, the counter increments at the rate of the system clock divided by the prescale value. figure 390. stm channel control register (stm_ccrn) offset 0x10+0x10*n access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 0 000 cen w reset0000000000000 0 00 table 374. stm_ccrn field description field description cen channel enable 0 = the channel is disabled. 1 = the channel is enabled. RM0029 system timer module (stm) doc id 15177 rev 8 639/1740 stm channel compare register (stm_cmpn) the stm channel compare register (stm_cmpn) holds the compare value for channel n. figure 391. stm channel interrupt register (stm_cirn) offset 0x14+0x10*n access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 0 000 cif w reset0000000000000 0 00 table 375. stm_cirn field description field description cif channel interrupt flag the flag and interrupt are cleared by writing a ?1? to this bit. writing a ?0? has no effect. 0 = no interrupt request 1 = interrupt request due to a match on the channel figure 392. stm channel compare register (stm_cmpn) offset 0x18+0x10*n access: read/write 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 r cmp w reset00000000000000000000000000000000 table 376. stm_cmpn register field description field description cmp compare value for channel n if the stm_ccrn[cen] bit is set and the stm_cmpn register matches the stm_cnt register, a channel interrupt request is generated and the stm_cirn[cif] bit is set. system timer module (stm) RM0029 640/1740 doc id 15177 rev 8 19.5 functional description the system timer module (stm) is a 32-bit timer designed to support commonly required system and application software timing functions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the stm has one 32-bit up counter (stm_cnt) that is used as the time base for all channels. when enabled, the counter increments at the system clock frequency divided by a prescale value. the stm_cr[cps] field sets the divider to any value in the range from 1 to 256. the counter is enabled with the stm_cr[ten] bit. when enabled in normal mode the counter continuously increments. when enabled in debug mode the counter operation is controlled by the stm_cr[frz] bit. when the stm_cr[frz] bit is set, the counter is stopped in debug mode, otherwise it continues to run in debug mode. the counter rolls over at 0xffff_ffff to 0x0000_0000 with no restrictions at this boundary. the stm has four identical compare channels. each channel includes a channel control register (stm_ccrn), a channel interrupt register (stm_cirn) and a channel compare register (stm_cmpn). the channel is enabled by setting the stm_ccrn[cen] bit. when enabled, the channel will set the stm_cir[cif] bit and generate an interrupt request when the channel compare register matches the timer counter. the interrupt request is cleared by writing a ?1? to the stm_cirn[cif] bit. a write of ?0? to the stm_cirn[cif] bit has no effect. RM0029 software watchdog timer (swt) doc id 15177 rev 8 641/1740 20 software watchdog timer (swt) 20.1 introduction 20.1.1 overview the software watchdog timer (swt) is a peripheral module that can prevent system lockup in situations such as software getting trapped in a loop or if a bus transaction fails to terminate. when enabled, the swt requires periodic execution of a watchdog servicing operation. the servicing operation resets the timer to a specified time-out period. if this servicing action does not occur before the timer expires the swt generates an interrupt or hardware reset. the swt can be configured to generate a reset or interrupt on an initial time-out, a reset is always generated on a second consecutive time-out. 20.1.2 features the swt has the following features: 32-bit time-out register to set the time-out period programmable selection of system or oscillator clock for timer operation programmable selection of window mode or regular servicing programmable selection of reset or interrupt on an initial time-out programmable selection of fixed or keyed servicing master access protection hard and soft configuration lock bits 20.1.3 modes of operation the swt supports three device modes of operation: normal, debug and stop. when the swt is enabled in normal mode, its counter runs continuously. in debug mode, operation of the counter is controlled by the frz bit in the swt_mcr. if the frz bit is set, the counter is stopped in debug mode, otherwise it continues to run. in stop mode, operation of the counter is controlled by the stp bit in the swt_mcr. if the stp bit is set, the counter is stopped in stop mode; otherwise, it continues to run. 20.2 external signal description the swt module does not have any external interface signals. 20.3 memory map and register definition the swt programming model has seven 32-bit registers. the programming model can only be accessed using 32-bit (word) accesses. references using a different size are invalid. other types of invalid accesses include: writes to read-only registers, incorrect values written to the service register when enabled, accesses to reserved addresses and accesses by masters without permission. if the ria bit in the swt_mcr is set then the swt generates a system reset on an invalid access otherwise a bus error is generated. if either software watchdog timer (swt) RM0029 642/1740 doc id 15177 rev 8 the hlk or slk bits in the swt_mcr are set then the swt_mcr, swt_to, swt_wn, swt_sk registers are read-only. 20.3.1 memory map the swt memory map is shown in table 377 . the reset values of swt_mcr, swt_to and swt_wn are device specific. these values are determined by swt inputs. 20.3.2 register descriptions the following sections detail the individual registers within the swt programming model. swt module control register (swt_mcr) the swt_mcr contains fields for configuring and controlling the swt. the reset value of this register is device specific. some devices can be configured to automatically clear the swt_mcr[wen] bit during the boot process. this register is read-only if either the swt_mcr[hlk] or swt_mcr[slk] bits are set. table 377. swt memory map offset from swt base address (0xfff3_8000) register name register description size (bits) access location 0x0000 swt_mcr swt module control register 32 r/w on page 20- 642 0x0004 swt_ir swt interrupt register 32 r/w on page 20- 644 0x0008 swt_to swt time-out register 32 r/w on page 20- 645 0x000c swt_wn swt window register 32 r/w on page 20- 645 0x0010 swt_sr swt service register 32 r/w on page 20- 645 0x0014 swt_co swt counter output register 32 r on page 20- 646 0x0018 swt_sk swt service key register 32 r/w on page 20- 646 0x001c ? 0x3fff reserved ? ? ? RM0029 software watchdog timer (swt) doc id 15177 rev 8 643/1740 figure 393. swt module control register (swt_mcr) offset 0x0000 access: read/write 0123456789101112131415 r map 0 map 1 map 2 map 3 map 4 map 5 map 6 map 7 00000 0 00 w reset 1 1111111100000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000 key ria wnd itr hlk slk csl stp frz wen w reset0000000100001 0 10 table 378. swt_mcr field description field description mapn master access protection for master n the platform bus master assignments are device specific. 0 = access for the master is not enabled 1 = access for the master is enabled key keyed service mode 0 = fixed service sequence, the fixed sequence 0xa602, 0xb480 is used to service the watchdog 1 = keyed service mode, two pseudorandom key values are used to service the watchdog ria reset on invalid access 0 = invalid access to the swt generates a bus error 1 = invalid access to the swt causes a system reset if wen = 1 wnd window mode 0 = regular mode, service sequence can be done at any time 1 = windowed mode, the service sequence is only valid when the down counter is less than the value in the swt_wn register. itr interrupt then reset 0 = generate a reset on a time-out 1 = generate an interrupt on an initial time-out, reset on a second consecutive time-out hlk hard lock this bit is only cleared at reset. 0 = swt_mcr, swt_to, swt_wn and swt_sk are read/write registers if slk = 0 1 = swt_mcr, swt_to, swt_wn and swt_sk are read-only registers slk soft lock this bit is cleared by writing the unlock sequence to the service register. 0 = swt_mcr, swt_to swt_wn and swt_sk are read/write registers if hlk = 0 1 = swt_mcr, swt_to, swt_wn and swt_sk are read-only registers software watchdog timer (swt) RM0029 644/1740 doc id 15177 rev 8 swt interrupt register (swt_ir) the swt_ir contains the time-out interrupt flag. csl clock selection selects the clock that drives the internal timer 0 = system clock 1 = oscillator clock stp stop mode control allows the watchdog timer to be stopped when the device enters stop mode 0 = swt counter continues to run in stop mode 1 = swt counter is stopped in stop mode frz debug mode control allows the watchdog timer to be stopped when the device enters debug mode 0 = swt counter continues to run in debug mode 1 = swt counter is stopped in debug mode wen watchdog enabled 0 = swt is disabled 1 = swt is enabled table 378. swt_mcr field description (continued) field description figure 394. swt interrupt register (swt_ir) offset 0x0004 access: read/write 0123456789101112131415 r0000000000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0000000 0 0 000 0 0 tif w reset0000000000000 0 00 table 379. swt_ir field description field description tif time-out interrupt flag the flag and interrupt are cleared by writing a ?1? to this bit. writing a ?0? has no effect. 0 = no interrupt request 1 = interrupt request due to an initial time-out RM0029 software watchdog timer (swt) doc id 15177 rev 8 645/1740 swt time-out register (swt_to) the swt time-out (swt_to) register contains the 32-bit time-out period. the reset value for this register is device specific. this register is read-only if either the swt_mcr[hlk] or swt_mcr[slk] bits are set. figure 395. swt time-out register (swt_to) swt window register (swt_wn) the swt window (swt_wn) register contains the 32-bit window start value. this register is cleared on reset. this register is read-only if either the swt_mcr[hlk] or swt_mcr[slk] bits are set. figure 396. swt window register (swt_wn) swt service register (swt_sr) the swt time-out (swt_sr) service register is the target for service operation writes used to reset the watchdog timer. offset 0x008 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r wto w reset00000000000000111111110111100000 table 380. swt_to register field description field description wto watchdog time-out period in clock cycles an internal 32-bit down counter is loaded with this value or 0x100 which ever is greater when the service sequence is written or when the swt is enabled. offset 0x00c access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r wst w reset00000000000000000000000000000000 table 381. swt_wn register field description field description wst window start value when window mode is enabled, the service sequence can only be written when the internal down counter is less than this value. software watchdog timer (swt) RM0029 646/1740 doc id 15177 rev 8 figure 397. swt service register (swt_sr) swt counter output register (swt_co) the swt counter output (swt_co) register is a read-only register that shows the value of the internal down counter when the swt is disabled. figure 398. swt counter output register (swt_co) swt service key register (swt_sk) the swt service key (swt_sk) register holds the previous (or initial) service key value. this register is read-only if either the swt_mcr[hlk] or swt_mcr[slk] bits are set. offset 0x010 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000000000000 00000000 00 0 0 00 w wsc reset00000000000000000000000000000000 table 382. swt_sr field description field description wsc watchdog service code this field is used to service the watchdog and to clear the soft lock bit (swt_mcr[slk]). if the swt_mcr[key] bit is set, two pseudorandom key values are written to service the watchdog, see section 20.4, functional description , for details. otherwise, the sequence 0xa602 followed by 0xb480 is written to the wsc field. to clear the soft lock bit (swt_mcr[slk]), the value 0xc520 followed by 0xd928 is written to the wsc field. offset 0x014 access: read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cnt w reset00000000000000111111110111010001 table 383. swt_co register field description field description cnt watchdog count when the watchdog is disabled (swt_mcr[wen] = 0) this field shows the value of the internal down counter. when the watchdog is enabled the value of this field is 0x0000_0000. values in this field can lag behind the internal counter value for up to six system plus eight counter clock cycles. therefore, the value read from this field immediately after disabling the watchdog may be higher than the actual value of the internal counter. RM0029 software watchdog timer (swt) doc id 15177 rev 8 647/1740 figure 399. swt service register (swt_sk) 20.4 functional description the swt is a 32-bit timer designed to enable the system to recover in situations such as software getting trapped in a loop or if a bus transaction fails to terminate. it includes a control register (swt_mcr), an interrupt register (swt_ir), a time-out register (swt_to), a window register (swt_wn), a service register (swt_sr), a counter output register (swt_co) and a service key register (swt_sk). the swt_mcr includes bits to enable the timer, set configuration options and lock configuration of the module. the watchdog is enabled by setting the swt_mcr[wen] bit. the reset value of the swt_mcr[wen] bit is dependent upon the swt field in the reset configuration half word (see section 21.5.3, reset configuration half word (rchw) ). if the reset value of this bit is 1, the watchdog starts operation automatically after reset is released. the swt_to register holds the watchdog time-out period in clock cycles unless the value is less than 0x100 in which case the time-out period is set to 0x100. this time-out period is loaded into an internal 32-bit down counter when the swt is enabled and each time a valid service operation is performed. the swt_mcr[csl] bit selects which clock (system or oscillator) is used to drive the down counter. the configuration of the swt can be locked through use of either a soft lock or a hard lock. in either case, when locked the swt_mcr, swt_to, swt_wn and swt_sk registers are read-only. the hard lock is enabled by setting the swt_mcr[hlk] bit which can only be cleared by a reset. the soft lock is enabled by setting the swt_mcr[slk] bit and is cleared by writing the unlock sequence to the service register. the unlock sequence is a write of 0xc520 followed by a write of 0xd928 to the swt_sr[wsc] field. there is no timing requirement between the two writes. the unlock sequence logic ignores service sequence writes and recognizes the 0xc520, 0xd928 sequence regardless of previous writes. the unlock sequence can be written at any time and does not require the swt_mcr[wen] bit to be set. when enabled, the swt requires periodic execution of a servicing operation which consists of writing two values to the swt_sr. writing the proper sequence of values loads the internal down counter with the time-out period. there is no timing requirement between the offset 0x018 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000000000000 00000000 00 0 0 00 w sk reset00000000000000000000000000000000 table 384. swt_sk field description field description sk service key this field is the previous (or initial) service key value used in keyed service mode. if swt_mcr[key] is set, the next key value to be written to the swt_sr is (17*sk+3) mod 2 16 . software watchdog timer (swt) RM0029 648/1740 doc id 15177 rev 8 two writes and the service sequence logic ignores unlock sequence writes. if the swt_mcr[key] bit is zero, the fixed sequence 0xa602, 0xb480 is written to the swt_sr[wsc] field to service the watchdog. if the swt_mcr[key] bit is set, then two pseudorandom keys are written to the swt_sr[wsc] field to service the watchdog. the key values are determined by the pseudorandom key generator defined in equation 11 . this algorithm will generate a sequence of 2 16 different key values before repeating. the state of the key generator is held in the swt_sk register. for example, if swt_sk[sk] is 0x0100 then the service sequence keys are 0x1103, 0x2136. in this mode, each time a valid key is written to the swt_sr register, the swt_sk register is updated. so, after servicing the watchdog by writing 0x1103 and then 0x2136 to the swt_sr[wsc] field, swt_sk[sk] is 0x2136 and the next key sequence is 0x3499, 0x7e2c. equation 11 accesses to swt registers occur with no peripheral bus wait states. (the peripheral bus bridge may add one or more system wait states.) however, due to synchronization logic in the swt design, recognition of the service sequence or configuration changes may require up to three system plus seven counter clock cycles. if window mode is enabled (swt_mcr[wnd] bit is set), the service sequence must be performed in the last part of the time-out period defined by the window register. the window is open when the down counter is less than the value in the swt_wn register. outside of this window, service sequence writes are invalid accesses and generate a bus error or reset depending on the value of the swt_mcr[ria] bit. for example, if the swt_to register is set to 5000 and swt_wn register is set to 1000 then the service sequence must be performed in the last 20% of the time-out period. there is a short lag in the time it takes for the window to open due to synchronization logic in the watchdog design. this delay could be up to three system plus four counter clock cycles. the interrupt then reset bit (swt_mcr[itr]) controls the action taken when a time-out occurs. if the swt_mcr[itr] bit is not set, a reset is generated immediately on a time-out. if the swt_mcr[itr] bit is set, an initial time-out causes the swt to generate an interrupt and load the down counter with the time-out period. if the service sequence is not written before the second consecutive time-out, the swt generates a system reset. the interrupt is indicated by the time-out interrupt flag (swt_ir[tif]). the interrupt request is cleared by writing a ?1? to the swt_ir[tif] bit. the swt_co register shows the value of the down counter when the watchdog is disabled. when the watchdog is enabled this register is cleared. the value shown in this register can lag behind the value in the internal counter for up to six system plus eight counter clock cycles. the swt_co can be used during a software self test of the swt. for example, the swt can be enabled and not serviced for a fixed period of time less than the time-out value. then the swt can be disabled (swt_mcr[wen] cleared) and the value of the swt_co read to determine if the internal down counter is working properly. sk n+1 = (17*sk n +3) mod 2 16 RM0029 boot assist module (bam) doc id 15177 rev 8 649/1740 21 boot assist module (bam) 21.1 overview the boot assist module (bam) is a 4 kb block of read-only memory (rom) containing the boot program code for this device. the bam program supports four different boot modes: boot from internal flash serial boot via sci or can interface serial boot via sci or can interface with baud rate detection boot from a memory connected to the external bus interface (ebi) the bam program is executed by the core just after a device reset. depending on the boot mode, the program initializes appropriate minimum device resources to start user code application. 21.2 features initial core mmu setup with minimum address translation for all internal device resources mmu configuration to boot user application, compiled as power architecture technology code or as vle code passes control to user application code in the internal flash memory automatic switch to serial boot mode if internal flash is blank or invalid serial boot by loading user program via can bus or esci to the internal sram ? user programmable 64-bit password protection ? optional automatic detection of the host sci or can speed boot from an external memory device, connected to the ebi controls core watchdog timer or/and the software watchdog timer (swt) 21.3 modes of operation 21.3.1 normal mode the bam program is executed immediately following the negation of reset. 21.3.2 debug mode the bam program is not executed when the device comes out of reset in once debug mode. the user must provide the required device initialization using the development tool before accessing the device resources. 21.3.3 internal boot mode this mode of operation is intended for systems that boot from internal flash memory. the internal flash memory is used for all code and all boot configuration data. boot assist module (bam) RM0029 650/1740 doc id 15177 rev 8 21.3.4 serial boot mode this mode of operation is intended to load a user program into internal sram, using either the esci or can serial interface, then to execute that program. the program can then be used to control the download of data and erasing/programming of the internal or external flash memory. 21.3.5 calibration bus boot mode calibration bus boot is not supported. external bus boot is supported instead. 21.4 memory map the bam occupies 16 kb of memory space, 0xffff_c000 to 0xffff_ffff. the actual code size of the bam program is less than 4 kb and starts at 0xffff_f000, repeating itself down every 4 kilobytes in the bam address space. the cpu starts the bam program execution at its reset vector from address 0xffff_fffc. the bam exits to the user code at 0xffff_fff8 address. the last bam executed instruction is a blr. the link register is preloaded with the user application start address. when booting from internal or external flash, the start address is taken from next to valid rchw 32-bit word.when the device boots serially the start address is set according the serial boot protocol. ta ble 38 5 shows the bam address map. 21.5 functional description 21.5.1 bam program flow chart the bam program flow chart is shown in figure 400 . table 385. bam memory map address description 0xffff_c000 ? 0xffff_efff bam program mirrored 0xffff_f000 ? 0xffff_ffff bam program 0xffff_fffc device reset vector 0xffff_fff8 bam last executed instruction RM0029 boot assist module (bam) doc id 15177 rev 8 651/1740 figure 400. bam program flow chart 21.5.2 bam program operation the bam is accessed by the device core after the negation of rstout , before user code starts. first, the bam program configures the core mmu to allow access to all device internal resources, according to table 386 . this mmu setup remains the same for internal flash boot mode. reset config mmu for internal boot internal boot? y n search for rchw found rchw? y n internal flash boot serial boot? y n setup ebi check rchw found rchw? y n ebi bus boot serial boot exit to user code boot assist module (bam) RM0029 652/1740 doc id 15177 rev 8 the mmu regions are mapped with logical address the same as physical address except for the external bus interface (ebi). the logical ebi address space is mapped to physical address space of the internal flash memory. this allows code, written to run from external memory, to be executed from internal flash. after the mmu configuration, the bam program checks the bootcfg field of the reset status register (siu_rsr) and the appropriate boot sequence is started as shown in ta ble 38 7 . depending on the values stored in the censorship word and serial boot control word in the shadow row of the internal flash memory, the internal flash memory can be enabled or disabled, the nexus port can be enabled or disabled, the password received in the serial boot mode is compared with the fixed public password or compared to a user programmable password in the internal flash memory. table 386. mmu configuration for internal flash boot tlb entry region logical base address physical base address size attributes 0 peripheral bridge b (1) and bam 0xfff0_0000 0xfff0_0000 1 mb guarded big endian global pid 1 internal flash 0x0000_0000 0x0000_0000 16 mb not guarded big endian global pid 2 ebi 0x2000_0000 0x0000_0000 16 mb not guarded big endian global pid 3 internal sram 0x4000_0000 0x4000_0000 256 kb not guarded big endian global pid 4 peripheral bridge a (1) 0xc3f0_0000 0xc3f0_0000 1 mb guarded big endian global pid 1. this device has only a single peripheral bridge, but to ma tch the memory map of other devices the peripherals are mapped to appear as if they are on tw o different peripheral bridges. table 387. boot modes bootcfg [0:1] censorship control 0x00ff_fde0 serial boot control 0x00ff_fde2 boot mode name internal flash state nexus state serial password 00 !0x55aa (1) any value internal?censored enabled disabled flash 0x55aa internal?public enabled enabled public 01 any value 0x55aa serial?flash password enabled disabled flash !0x55aa serial?public password disabled enabled public RM0029 boot assist module (bam) doc id 15177 rev 8 653/1740 the censorship word is a 32-bit word of data stored in the shadow row of internal flash memory. this memory location is read and interpreted by hardware as part of the boot process and is used in conjunction with the bootcfg pin to enable/disable the internal flash memory and the nexus interface. the address of the censorship word is 0x00ff_fde0. the censorship word consists of two fields: censorship control and serial boot control. the censorship word is programmed during manufacturing to be 0x55aa_55aa. this results in a device that is not censored and uses a flash-based password for serial boot mode. figure 401. censorship word the bam program uses the state of bit siu_ccr[disnex] to determine whether the serial password received in serial boot mode should be compared to a public password (fixed value of the 0xfeed_face_cafe_beef) or needs to be compared to a flash password - 64-bit data, stored in the shadow row of internal flash at address 0x00ff_fdd8. if the bit is set, the bam uses the flash serial password, if the bit is cleared, it uses the public password. 10 !0x55aa any value external?no arbitration?censored disabled enabled public 0x55aa external?no arbitration?public enabled enabled public 11 invalid value 1. ?!? = ?not,? as in!0x55aa, means all values except 0x55aa. do not use 0x0000 or 0xffff for the value of the censorship control or serial boot control words. table 387. boot modes (continued) bootcfg [0:1] censorship control 0x00ff_fde0 serial boot control 0x00ff_fde2 boot mode name internal flash state nexus state serial password censorship word @ 0x00ff_fde0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0101010110101010 censorship control - showing an uncensored part (factory default) 1514131211109876543210 0101010110101010 serial boot control - showing the use of the flash based password (factory default) boot assist module (bam) RM0029 654/1740 doc id 15177 rev 8 figure 402. serial boot flash password a valid serial password must be always programmed, regardless the boot mode used. this provides capability to ?rescue? the part using the serial boot mode, if the flash content becomes corrupted for whatever reason. 21.5.3 reset configuration half word (rchw) the reset configuration half word defines boot options and has to be programmed by the user to predefined locations in the internal flash or at the beginning of the external flash device. the next 32-bit word after the rchw has to be programmed with a starting address of the user application. the bam program uses this location to fetch the address, where it passes control to. ta ble 39 0 provides possible rchw locations in the internal flash. when booting from the external flash device, the rchw should reside in the very first 16-bit half word of the flash. figure 403 shows the fields of the rchw. figure 403. reset configuration half word flash password @ 0x00ff_fdd8 - 0x00ff_fddf 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1111111011101101 serial boot password (0x00ff_f dd8) - 0xfeed (factory default) 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 1111101011001110 serial boot password (0x00ff_fdda) - 0xface (factory default) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1100101011111110 serial boot password (0x00ff_fddc) - 0xcafe (factory default) 1514131211109876543210 1011111011101111 serial boot password (0x00ff_ fdde) - 0xbeef (factory default) boot_block_address 0123456789101112131415 swtwteps0vle01011010 boot identifier = 0x5a RM0029 boot assist module (bam) doc id 15177 rev 8 655/1740 the watchdog timeout periods, when the watchdogs are controlled by rchw, are shown in ta ble 38 9 . table 388. rchw field description field description bits 0?3 reserved these bit values are ignored when the halfword is read. write to 0 for future compatibility. swt watchdog timer enable this bit determines if the software watchdog timer is enabled after passing control to the user application code. 0 disable software watchdog timer 1 software watchdog timer maintains its default state out of reset, i.e. enabled. the timeout period is programmed to be 261600 system clocks. wte device core watchdog timer enable this bit determines if the core software watchdog timer is enabled.after passing control to the user application code. 0 disable core software watchdog timer 1 software watchdog timer maintains its default state out of reset, i.e. enabled. the timeout period is programmed to be 2.5*2 17 system clocks. ps0 port size defines the width of the data bus connected to the memory on cs 0. after system reset, cs0 is changed to a 16-bit port by the bam, which fetches the rchw from either 16- or 32-bit external memories. then the bam reconfigures the ebi as a 16-bit bus or a 32-bit bus, according to the settings of this bit. 0 32-bit cs0 port size 1 16-bit cs0 port size used in ebi boot mode only. do not set the port to 32-bits if the device only has a 16-bit data bus. vle vle code indicator this bit is used to configure the mmu entries 1-3 coded as either power architecture instructions or as vle instructions. 0 user code executes as power architecture code 1 user code executes as vle code bootid boot identifier this field serves two functions. first, it is used to indicate which block in flash memory contains the boot program. second, it identifies whether the flash memory is programmed or invalid. the value of a valid boot identifier is 0x5a. table 389. watchdog timeouts crystal frequency (mhz) core wd timeout (1) (ms) 1. 327,680 system clocks swt timeout (2) (ms) 2. 261,600 system clocks 8 40.1 32.7 12 27.3 21.8 16 20.5 16.35 20 16.4 13.08 40 8.2 6.54 boot assist module (bam) RM0029 656/1740 doc id 15177 rev 8 reset boot vector the boot vector, shown in figure 404 , has to be programmed by the user to the user application code memory device (internal or external flash) to the next 32-bit word after the rchw. the value from this location is used by the bam program as a start address of the user application to switch to. figure 404. reset boot vector 21.5.4 internal boot mode when the bam program detects internal flash boot mode, it sets up a machine check exception handler because it will be accessing flash memory locations that may be corrupted and cause a bus error. then the bam program tries to find a valid rchw in six predefined locations. if a valid rchw is not found, the bam program proceeds to check of possibility of booting to the serial boot mode. finding reset configuration half word the bam searches the internal flash memory for a valid reset configuration half word (rchw). possible rchw locations are shown in table 390 . boot_block_address is the address from table 390 where the bam finds a valid rchw. if the bam program finds a valid rchw, the core watchdog is enabled if the rchw[wte] bit is programmed high, the swt is disabled if the rchw[swt] bit is boot_block_address + 0x0000_0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 table 390. possible rchw locations in the internal flash block address 0 0x0000_0000 1 0x0000_4000 2 0x0000_8000 3 0x0000_c000 4 0x0001_0000 5 0x0001_4000 6 0x0001_8000 7 0x0001_c000 8 0x0002_0000 9 0x0003_0000 RM0029 boot assist module (bam) doc id 15177 rev 8 657/1740 programmed low, the bam program fetches the reset vector from the address of the boot_block_address + 0x4, and branches to the reset boot vector (shown in figure 404 ). a user application should have a valid instruction at the reset boot vector address. enabling debug of a censored device when a device is in a censored state, the debug port (jtag/nexus) is disabled and only jtag bsdl commands can be used. access to the nexus/jtag clients on a censored device requires inputting the proper password into the jtag censorship control register during reset. note: when the debug port is enabled on a censored device, it is enabled only until the next reset. figure 405 shows the logic that enables access to nexus clients in a censored device using the jtag port. figure 405. enabling jtag/nexus port access on a censored device the steps to enable the debug port on a censored device are as follows: compare 64-bit password jtag port controller censor_ctrl register nexus client tap controller debug/calibration tool access 64-bit password enable/disable censored flash array other nexus clients ?edma ? e200z4 processor . . boot assist module (bam) RM0029 658/1740 doc id 15177 rev 8 1. after the rstout pin has is negated, hold the device in system reset state using a debugger or other tool. 2. while the device is being held in system reset state shift the 64-bit password into the censor_ctrl register (see section , censor_ctrl register ) via the jtag port using the jtag enable_censor_ctrl instruction. the jtag serial password is compared against the serial boot flash password from the flash shadow block. 3. if there is a match the nexus client tap controller enters normal operation mode and the flag siu_ccr[disnex] is negated, indicating nexus is enabled. upon negation of reset the debug / calibration tool is able to access the device via nexus port and jtag. if the jtag serial password does not match the serial boot flash password or the serial boot flash password is an illegal password then the debug / calibration tool is not able to access the device. after the debug port is enabled, the tool can access the censored device and can erase and reprogram the shadow flash block in order to uncensor the device. note: if the shadow flash block is erased without reprogramming a new valid password before a reset it will contain an illegal password and the debug port will be inaccessible. 4. subsequent resets will clear the jtag censor password register and the nexus client tap controller will hold in reset again. therefore, the tool must resend the jtag serial password, as described above, in order to enable the nexus client tap controller again. 21.5.5 serial boot mode when the bam program transitions to the serial boot mode, unused message buffers in can_a are used for the bam program stack and variables and the swt watchdog is reprogrammed with timeperiod greater than the default value. the mmu setup depends on the way bam enters the serial boot mode. if ebi boot mode is taken, the mmu is set up for that mode (see table 395 ). the serial boot mode can run in either of two modes of operation: standard serial boot mode using fixed baud rates derived from the crystal oscillator used baud rate detection serial boot mode, which allows communication with adaptable speed, based on measured input signal the fixed baud rate mode or baud rate detection mode are selected based on the state of the evto pin, recorded in the siu_rsr[abr] bit. if the bit is set, the baud rate detection mode is selected if the bit is cleared, the fixed baud rate is selected. siu_rsr[abr] bit reflects the inverted state of the evto pin, thus to select baud rate detection mode, the evto pin needs to be driven low. when the fixed baud rate mode is selected, the bam program configures the sci_a_rx pin to be the input of the esci_a module, cn_a_rx pin as an input, and cn_a_tx as an output of the can_a module. when baud rate detection mode is selected, the bam program configures sci_a_rx and cn_a_rx pins as gpi inputs for polling their state by the cpu. ta ble 39 1 shows the configuration summary for thesci and can controllers pins. RM0029 boot assist module (bam) doc id 15177 rev 8 659/1740 the bam configures the communication modules for reception with fixed baud rates as shown in the table 392 and waits for data reception. . if a message with 0x11 id, containing 8 bytes, is received by the can controller first, the bam program transitions to the serial can boot sub-mode, disabling esci, and reconfiguring the sci_a_rx pin to its reset state. if a message from esci is received first, the bam program transitions to the serial sci boot submode, disables can_a module and configures its pins to their reset state. then the bam program transitions to the serial download protocol execution. can controller configuration in the fixed baud rate mode the can controller is configured to operate at a baud rate equal to system frequency divided by 40, using the standard 11-bit identifier format detailed in can 2.0a specification. table 391. can/esci pins configuration for can/esci fixed baud rate boot modes pins reset function initial serial boot mode serial boot mode after a valid can message received serial boot mode after a valid esci message received function pad configuration function pad configuration function pad configuration cn_a_tx gpio cn_a_tx push/pull output, with medium slew rate cn_a_tx push/pull output, with medium slew rate gpio ? cn_a_rx gpio cn_a_rx input with pull-up and hysteresis cn_a_rx input with pull-up and hysteresis gpio ? sci_a_tx gpio gpio ? gpio ? sci_a_tx push/pull output, with medium slew rate sci_a_rx gpio sci_a_rx input with pull-up and hysteresis gpio ? sci_a_rx input with pull-up and hysteresis table 392. serial boot mode ? baud rate & watchdog summary crystal frequency (mhz) system clock frequency (mhz) desired esci baud rate (baud) actual esci baud rate (baud) esci error (%) can baud rate (baud) core watchdog (1) timeout period (s) swt timeout period during serial boot (s) f xtal f sys = f xtal f sys / 833.33 f sys / 832 ? f sys / 40 2.5 * 2 27 / f sys 223696213 / f sys 8 8 9600 9615.4 0.16 200k 42 27.96 12 12 14400 14423. 0 0.16 300k 28 18.64 16 16 19200 19230.8 0.16 400k 21 13.98 20 20 24000 24038.5 0.16 500k 16.8 11.18 1. the swt is used as a watchdog during serial boot mode, but t he core watchdog is enabled just before switching to the user application to provide compatibility with earlier parts. boot assist module (bam) RM0029 660/1740 doc id 15177 rev 8 see table 392 for examples of baud rates. only one message buffer 0 is used for all communications. the bit timing is configured as shown in figure 406 . figure 406. can bit timing the bam program ignores can errors and all received data is assumed to be good and is echoed out on the cn_a_tx signal. it is the responsibility of the host computer to compare the ?echoes? with the sent data and restart the process if an error is detected. sci controller configuration in fixed baud rate mode the esci is configured for 1 start bit, 8 data bits, no parity, 1 stop bit and to operate at a baud rate equal to system clock divided by 832. see table 392 for examples of baud rates. the bam program ignores the esci errors: all data received will be assumed to be good and will be echoed out on the txd signal. it is the responsibility of the host computer to compare the echoes with the sent data and restart the process if an error is detected. serial boot mode download protocol the download protocol follows four steps: 1. host sends 64-bit password. 2. host sends start address, size of download code in bytes, and vle bit. 3. host sends the application code data. 4. the device switches to the loaded code at the start address. the communication is done in half-duplex manner, any transmission from host is followed by the device transmission. the host computer should not send data until it receives echo from the device. all multibyte data structures have to be sent most significant byte (msb) first. sync_seg time segment 1 time segment 2 nrz signal 1 time quanta 1 bit time 7 time quanta 2 time quanta transmit point sample point note: 1 time quanta = 4 system clock periods RM0029 boot assist module (bam) doc id 15177 rev 8 661/1740 when the can is used for serial download, the data is packed into standard can messages in the following manner: a message with 0x11 id and 8-byte length is used to send the password. the device transmits the same data, but the message id is set to 0x1. a message with 0x12 id and 8-byte length is used to send the start address, length, and the vle mode bit. the device transmits back the same data, but with id set to 0x2. messages with 0x13 id are used to send the downloaded data. the device transmits back received data with message id of 0x3. when the sci is used for serial download, the data has to be sent on a byte-by-byte basis. the device transmits back the received data. download protocol execution the bam program executes the serial boot as follows: 1. download 64-bit password. the received 8-byte password is checked for validity. for a password to be valid, none of its four 16-bit half words must equal 0x0000 or 0xffff. the bam program then checks the censorship status of the device by checking the bit siu_ccr[disnex]. if nexus is disabled, the device is considered to be censored and the password is compared with a password stored in the shadow row in internal flash memory. if nexus is enabled, the device is not considered to be censored and the password is compared to the fixed value = 0xfeed_face_cafe_beef. if the password check fails, the device stops responding. to get the device out of that state, the reset signal must be asserted. if the password check passes, the bam transitions to the next step in the protocol. 2. download start address, size of download, and vle bit. the next 8 bytes received by the device are considered to contain a 32-bit start address, the vle mode bit, and a 31-bit code length (see figure 407 ). figure 407. start address, vle bit and download size in bytes the start address defines where the received data will be stored and where the device will branch after the download is finished. the two least significant bits of the start 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 start_address[0:15] 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 start_address[16:31] 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 vle code_length[0:14] 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 code_length[15:30] boot assist module (bam) RM0029 662/1740 doc id 15177 rev 8 address are ignored by the bam program, such that the loaded code should be 32-bit word aligned. the length defines how many data bytes to be loaded. the vle mode bit instructs the device to program mmu entries 1?3 with vle attribute. if it is 1, the downloaded code must be compiled to vle instructions, if it is 0 the code contains power instructions. 3. download data. each byte of data received is stored in the device memory, starting at the address specified in the previous protocol step, and incrementing through memory until the number of bytes of data received and stored in memory matches the number specified in the previous protocol step. bam program buffers incoming data, collecting up to eight bytes. the buffered data is written to the ram with 64-bit writes to prevent ecc errors, which may happen if the device ram is protected by 64-bit ecc code. once the buffered data is written to the ram the bam program refreshes the swt watchdog. note: only system ram supports 64-bit writes; therefore, attempting to download data to other ram apart from system ram will cause errors. if the start address of the downloaded data is not on an 8-byte boundary, the bam will write 0x0 to the memory locations from the proceeding 8-byte boundary to the start address (maximum 4 bytes). the bam also writes 0x0 to all memory locations from the last byte of data downloaded to the following 8 byte boundary (maximum 7 bytes) and additional 8 zero bytes to prevent possible ecc errors may be caused by the cpu prefetching. 4. switch to the loaded code. the bam program waits for the last echo message transmission to complete, then the active communication controller is disabled. its pins revert to gpio inputs. to provide compatibility with older devices, the bam writes the core time base registers (tbu and tbl) with 0x0 and enables the core watchdog to cause a reset after a time- out period of 2.5 x 2 27 system clock cycles and disables swt watchdog. see ta ble 39 2 for examples of time out periods. the bam code passes control to the loaded code at start address, which was received in step 2 of the protocol. note: the loaded code must periodically refresh the core watchdog timer or change the timeout period to a value that will not cause resets during normal operation. baud rate detection procedure to improve baud rate detection accuracy the baud rate detection routine is copied to the beginning of the system ram from the bam rom. then the cpu branches to the ram. the device configures the cn_a_rx and sci_a_rx pins as general purpose inputs and starts to poll them until one of them goes low. if the cn_a_rx pin transitions first, the bam program starts can baud rate detection routine, ignoring sci_a_rx. after detecting the can baud rate, the bam program transitions to the can download protocol routine described above. if the sci_a_rx pin transitions first, the sci baud rate detection and download protocol routines are called, ignoring any further can pins activity. RM0029 boot assist module (bam) doc id 15177 rev 8 663/1740 sci baud rate detection the host has to send a zero byte to allow the device to detect the serial link baud rate. the host transmits 1 start bit, 8 zero data bits and 1 stop bit. the device does not echo it. the device polls the sci_a_rx pin for high to low transition and starts the core time base counter (tbu and tbl). then the device polls for low to high transition on the pin and when it happens, the device turns off the tb counter. the tb content is used to calculate incoming signal baud rate. the sci baud rate is equal to the tb content divided by 144 (measured over 9 bits with 16 system clocks per bit). can baud rate detection the host transmits a zero length message with zero 11-bit id and the device measures time over 40 bits, polling cn_a_rx pin for high and low, according to the sent data. the device does not acknowledge this message. the can baud rate depends on the number of quanta per bit and serial clock frequency, which is defined by a prescaler. the can baud rate detection routine selects these parameters to maximize number of quanta per bit and achieve minimum difference between measured value and duration of the 40 can bits, to be programmed with selected pair of the parameters. the can controller can be programmed with 8 to 25 number of quanta per bit. the bit timing parameters, selected by the baud rate detection routine, are shown in table 393 . (see flexcan chapter for the parameters definition). . table 393. can bit timing lookup table time quanta per bit time segment 1 time segment 2 rjw propseg pseg1 pseg2 81332 92332 103332 114332 123442 134443 145443 156444 167443 178443 187554 198554 207664 218664 227664 238664 boot assist module (bam) RM0029 664/1740 doc id 15177 rev 8 maximum and minimum speeds of the serial communication modules are defined by the device system frequency and shown in table 394 . 21.5.6 booting from the external bus interface (ebi) for devices packaged in the 324-ball bga or chip scale packages (csp), there is an option to boot from a memory device on the external bus. drive the bootcfg0 high to select serial boot mode. note: for serial boot the user needs to connect a boot memory device with a programmed valid rchw to the ebi. the bam program sets up the mmu entries for ebi and internal flash (see table 395 ), ebi bus pins and tries to read rchw from logical address 0x2000_0000. if the valid rchw is read from that address, the bam program reads user application code start address from logical address 0x2000_0004, parses rchw, sets up watchdogs, updates ebi, sram and internal flash mmu entries, according the rchw[vle] bit and passes control to the user code. if no valid rchw was read, bam switches to the serial boot mode. 247774 258774 table 393. can bit timing lookup table (continued) time quanta per bit time segment 1 time segment 2 rjw propseg pseg1 pseg2 table 394. maximum and minimum detectable baud rates f sys = f xtal [mhz] max baud rate for can (f sys /8) (1) [bit/s] min can baud rate (f sys /25/256) [bit/s] max baud rate for sci (f sys /160) [bit/s] min baud rate for sci (f sys /16/2 16 ) [bit/s] 8 1m 1250 50k 7.6 12 1m 1875 75k 11.5 16 1m 2500 100k 15.2 20 1m 3125 125k 19 1. limited to 1 mbit/s by can standard RM0029 boot assist module (bam) doc id 15177 rev 8 665/1740 ebi configuration for external bus interface boot mode the bam program sets up ebi related registers as shown in table 396 . table 395. mmu configuration for ebi boot and serial boot modes tlb entry region logical base address physical base address size attributes 1 internal flash 0x0000_0000 0x2000_0000 16 mbytes not guarded big endian global pid 2 ebi 0x2000_0000 0x2000_0000 16 mbytes not guarded big endian global pid table 396. ebi register settings register value comments ebi_mcr 0x0000_0801 16-bit wide bus ebi_br0 0x2000_0803 burst inhibit ebi_or0 0xff80_00f0 set 15 wait states, 8 mb siu_pcr0 0x443 selects cs[0] function, sets pad to 20 pf drive strength, enables weak pull device for pad and enables pullup siu_pcr[8:11] 0x440 selects addr[12:15] and sets pads to 20 pf drive strength siu_pcr[12:27] 0x40c selects addr[16:31], sets pads to medium slew rate and enables weak pull device for pads siu_pcr[28:43] 0x440 selects data[0:15] and sets pads to 20 pf drive strength siu_pcr64 0x443 selects we [0]/be [0] function, sets pad to 20 pf drive strength, enables weak pull device for pad and enables pullup siu_pcr[68:69] 0x443 selects oe and ts functions, sets pads to 20 pf drive strength, enables weak pull device for pads and enables pullup configurable enhanced modular io subsystem (emios200) RM0029 666/1740 doc id 15177 rev 8 22 configurable enhanced modular io subsystem (emios200) 22.1 device-specific features sixteen 24-bit wide channels 3 channels internal timebases can be shared between channels 1 timebase from the etpu can be imported and used by the channels global enable feature for all emios200 and etpu timebases doze mode is not supported each channel has its own pin (not available on all package types) 22.2 introduction the emios200 module provides the capability to generate or measure timed events, for example generating pwm waveforms or measuring input pulse width. it is implemented with its own configuration of timer channels to suit the target applications needs, while maintaining full backwards compatibility with previous emios implementations. the spc564a74xx, spc564a80xx has one emios200 module that implements twenty-four 24- bit counters. the overall architecture of the emios200 resembles that of its predecessor, the mios. the mios timer block provided a framework where a set of sublocks with different timer functions were assembled to attend the specific needs of a device. the spc564a74xx, spc564a80xx emios200 builds on this concept by using a modified unified channel module that provides a superset of the functionality of individual mios channels, while providing a consistent user interface. this allows more flexibility as each channel can be programmed for different functions in different applications of the device. in addition, the emios200 architecture allows the use of dedicated channels that perform specific functions not included in mios inheritance. note: the spc564a74xx, spc564a80xx emios200 uses a modified version of the unified channel block that contains a reduced set of functions . see section 22.2.3, channel configurations , for details. figure 408 shows the block diagram of the spc564a74xx, spc564a80xx emios200 module. RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 667/1740 figure 408. emios200 block diagram 22.2.1 features the emios timer module provides the capability to generate or measure events in hardware. the emios module features include: twenty-four 24-bit wide channels 3 channels? internal timebases can be shared between channels 1 timebase from etpu2 can be imported and used by the channels global enable feature for all emios and etpu timebases dedicated pin for each channel (not available on all package types) ? ? ? ? ? ? channel[7] channel[0] [b] emios[7] emios[0] [a] ? ? ? ? ? ? counter buses (time bases) all submodules internal counter clock enable iib output disable input[3:0] global time base enable global time base bit (gtbe) output system clock biu ip interface clock prescaler output disable control bus channel[15] channel[8] [c] emios[15] emios[8] ? ? ? ? ? ? channel[23] channel[16] [d] emios[23] emios[16] enhanced modular i/o system (emios200) configurable enhanced modular io subsystem (emios200) RM0029 668/1740 doc id 15177 rev 8 each channel (0?23) supports the following functions: general-purpose input/output (gpio) single-action input capture (saic) single-action output compare (saoc) output pulse-width modulation buffered (opwmb) input period measurement (ipm) input pulse-width measurement (ipwm) double-action output compare (daoc) modulus counter buffered (mcb) output pulse width and frequency modulation buffered (opwfmb) 22.2.2 modes of operation there are three main operating modes of emios200: run mode, module disable mode, and debug mode. run mode is the normal operation mode. module disable mode is used for mcu power management. the clock to the non-memory-mapped logic in the emios200 is stopped while in module disable mode. module disable mode is entered when emios_mcr[mdis] = 1. debug mode is individually programmed for each channel. when entering this mode, the unified channel registers? contents are frozen but remain available for read and write access through the ip interface. 22.2.3 channel configurations ta ble 39 7 shows all configurations available in the spc564a74xx, spc564a80xx emios200. these modes are described in section , channel modes of operation . note: not all configurations are available on all channels. if an unimplemented mode is selected (by writing a reserved value to mode[0:6] in a channel?s emios_ccr[n]) the results are unpredictable. see section , emios200 channel control register (emios_ccr[n]) , for more detail. table 397. all available spc564a74xx, spc564a80xx emios channel configurations description name location general purpose input / output gpio on page 22-694 single action input capture saic on page 22-694 single action output compare saoc on page 22-695 input pulse width measurement ipwm on page 22-697 input period measurement ipm on page 22-698 double action output compare daoc on page 22-700 modulus counter buffered (up / down) mcb on page 22-701 output pulse width and frequency modulation buffered opwfmb on page 22-704 output pulse width modulation buffered opwmb on page 22-709 RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 669/1740 22.3 external signals description each channel has one external input and one external output signal. depending on the chip integration, the input and output signals can be connected to two separate pins, or to a single bidirectional pin. see chapter 3: signal description for details. 22.4 memory map/register definition 22.4.1 memory map the overall address map organization is shown in table 398 . note: whenever an access to either an absent register, an absent channel or a reserved address is performed, the emios200 responds by asserting a transfer error signal from the slave bus (or stac bus). table 398. spc564a74xx, spc564a80xx emios memory map offset from emios_base (0xc3fa_0000) register location global registers 0x0000 emios_mcr ? module configuration register on page 22- 678 0x0004 emios_gfr ? global flag register on page 22- 680 0x0008 emios_oudr ? output update disable register on page 22- 681 0x000c emios_ucdis ? channel disable register on page 22- 682 0x000c?0x001f reserved channel 0 registers 0x0020 emios_cadr[0] ? channel a data register on page 22- 682 0x0024 emios_cbdr[0] ? channel b data register on page 22- 683 0x0028 emios_ccntr[0] ? channel counter register on page 22- 684 0x002c emios_ccr[0] ? channel control register on page 22- 685 0x0030 emios_csr[0] ? channel status register on page 22- 689 0x0034 emios_alta[0] (1) ? alternate a register on page 22- 690 0x0038?0x003f reserved configurable enhanced modular io subsystem (emios200) RM0029 670/1740 doc id 15177 rev 8 channel 1 registers 0x0040 emios_cadr[1] ? a register on page 22- 682 0x0044 emios_cbdr[1] ? b register on page 22- 683 0x0048 emios_ccntr[1] ? counter register on page 22- 684 0x004c emios_ccr[1] ? control register on page 22- 685 0x0050 emios_csr[1] ? status register on page 22- 689 0x0054 emios_alta[1] (1) ? alternate a register on page 22- 690 0x0058?0x005f reserved channel 2 registers 0x0060 emios_cadr[2] ? a register on page 22- 682 0x0064 emios_cbdr[2] ? b register on page 22- 683 0x0068 emios_ccntr[2] ? counter register on page 22- 684 0x006c emios_ccr[2] ? control register on page 22- 685 0x0070 emios_csr[2] ? status register on page 22- 689 0x0074 emios_alta[2] (1) ? alternate a register on page 22- 690 0x0078?0x007f reserved channel 3 registers 0x0080 emios_cadr[3] ? a register on page 22- 682 0x0084 emios_cbdr[3] ? b register on page 22- 683 0x0088 emios_ccntr[3] ? counter register on page 22- 684 0x008c emios_ccr[3] ? control register on page 22- 685 0x0090 emios_csr[3] ? status register on page 22- 689 table 398. spc564a74xx, spc564a80xx emios memory map (continued) offset from emios_base (0xc3fa_0000) register location RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 671/1740 0x0094 emios_alta[3] (1) ? alternate a register on page 22- 690 0x0098?0x009f reserved channel 4 registers 0x00a0 emios_cadr[4] ? a register on page 22- 682 0x00a4 emios_cbdr[4] ? b register on page 22- 683 0x00a8 emios_ccntr[4] ? counter register on page 22- 684 0x00ac emios_ccr[4] ? control register on page 22- 685 0x00b0 emios_csr[4] ? status register on page 22- 689 0x00b4 emios_alta[4] (1) ? alternate a register on page 22- 690 0x00b8?0x00bf reserved channel 5 registers 0x00c0 emios_cadr[5] ? a register on page 22- 682 0x00c4 emios_cbdr[5] ? b register on page 22- 683 0x00c8 emios_ccntr[5] ? counter register on page 22- 684 0x00cc emios_ccr[5] ? control register on page 22- 685 0x00d0 emios_csr[5] ? status register on page 22- 689 0x00d4 emios_alta[5] (1) ? alternate a register on page 22- 690 0x00d8?0x00df reserved channel 6 registers 0x00e0 emios_cadr[6] ? a register on page 22- 682 0x00e4 emios_cbdr[6] ? b register on page 22- 683 0x00e8 emios_ccntr[6] ? counter register on page 22- 684 table 398. spc564a74xx, spc564a80xx emios memory map (continued) offset from emios_base (0xc3fa_0000) register location configurable enhanced modular io subsystem (emios200) RM0029 672/1740 doc id 15177 rev 8 0x00ec emios_ccr[6] ? control register on page 22- 685 0x00f0 emios_csr[6] ? status register on page 22- 689 0x00f4 emios_alta[6] (1) ? alternate a register on page 22- 690 0x00f8?0x00ff reserved channel 7 registers 0x0100 emios_cadr[7] ? a register on page 22- 682 0x0104 emios_cbdr[7] ? b register on page 22- 683 0x0108 emios_ccntr[7] ? counter register on page 22- 684 0x010c emios_ccr[7] ? control register on page 22- 685 0x0110 emios_csr[7] ? status register on page 22- 689 0x0114 emios_alta[7] (1) ? alternate a register on page 22- 690 0x0118?0x011f reserved channel 8 registers 0x0120 emios_cadr[8] ? a register on page 22- 682 0x0124 emios_cbdr[8] ? b register on page 22- 683 0x0128 emios_ccntr[8] ? counter register on page 22- 684 0x012c emios_ccr[8] ? control register on page 22- 685 0x0130 emios_csr[8] ? status register on page 22- 689 0x0134 emios_alta[8] (1) ? alternate a register on page 22- 690 0x0138?0x013f reserved channel 9 registers 0x0140 emios_cadr[9] ? a register on page 22- 682 table 398. spc564a74xx, spc564a80xx emios memory map (continued) offset from emios_base (0xc3fa_0000) register location RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 673/1740 0x0144 emios_cbdr[9] ? b register on page 22- 683 0x0148 emios_ccntr[9] ? counter register on page 22- 684 0x014c emios_ccr[9] ? control register on page 22- 685 0x0150 emios_csr[9] ? status register on page 22- 689 0x0154 emios_alta[9] (1) ? alternate a register on page 22- 690 0x0158?0x015f reserved channel 10 registers 0x0160 emios_cadr[10] ? a register on page 22- 682 0x0164 emios_cbdr[10] ? b register on page 22- 683 0x0168 emios_ccntr[10] ? counter register on page 22- 684 0x016c emios_ccr[10] ? control register on page 22- 685 0x0170 emios_csr[10] ? status register on page 22- 689 0x0174 emios_alta[10] (1) ? alternate a register on page 22- 690 0x0178?0x017f reserved channel 11 registers 0x0180 emios_cadr[11] ? a register on page 22- 682 0x0184 emios_cbdr[11] ? b register on page 22- 683 0x0188 emios_ccntr[11] ? counter register on page 22- 684 0x018c emios_ccr[11] ? control register on page 22- 685 0x0190 emios_csr[11] ? status register on page 22- 689 0x0194 emios_alta[11] (1) ? alternate a register on page 22- 690 0x0198?0x019f reserved table 398. spc564a74xx, spc564a80xx emios memory map (continued) offset from emios_base (0xc3fa_0000) register location configurable enhanced modular io subsystem (emios200) RM0029 674/1740 doc id 15177 rev 8 channel 12 registers 0x01a0 emios_cadr[12] ? a register on page 22- 682 0x01a4 emios_cbdr[12] ? b register on page 22- 683 0x01a8 emios_ccntr[12] ? counter register on page 22- 684 0x01ac emios_ccr[12] ? control register on page 22- 685 0x01b0 emios_csr[12] ? status register on page 22- 689 0x01b4 emios_alta[12] (1) ? alternate a register on page 22- 690 0x01b8?0x01bf reserved channel 13 registers 0x01c0 emios_cadr[13] ? a register on page 22- 682 0x01c4 emios_cbdr[13] ? b register on page 22- 683 0x01c8 emios_ccntr[13] ? counter register on page 22- 684 0x01cc emios_ccr[13] ? control register on page 22- 685 0x01d0 emios_csr[13] ? status register on page 22- 689 0x01d4 emios_alta[13] (1) ? alternate a register on page 22- 690 0x01d8?0x01df reserved channel 14 registers 0x01e0 emios_cadr[14] ? a register on page 22- 682 0x01e4 emios_cbdr[14] ? b register on page 22- 683 0x01e8 emios_ccntr[14] ? counter register on page 22- 684 0x01ec emios_ccr[14] ? control register on page 22- 685 0x01f0 emios_csr[14] ? status register on page 22- 689 table 398. spc564a74xx, spc564a80xx emios memory map (continued) offset from emios_base (0xc3fa_0000) register location RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 675/1740 0x01f4 emios_alta[14] (1) ? alternate a register on page 22- 690 0x01f8?0x01ff reserved channel 15 registers 0x0200 emios_cadr[15] ? a register on page 22- 682 0x0204 emios_cbdr[15] ? b register on page 22- 683 0x0208 emios_ccntr[15] ? counter register on page 22- 684 0x020c emios_ccr[15] ? control register on page 22- 685 0x0210 emios_csr[15] ? status register on page 22- 689 0x0214 emios_alta[15] (1) ? alternate a register on page 22- 690 0x0218?0x021f reserved channel 16 registers 0x0220 emios_cadr[16] ? a register on page 22- 682 0x0224 emios_cbdr[16] ? b register on page 22- 683 0x0228 emios_ccntr[16] ? counter register on page 22- 684 0x022c emios_ccr[16] ? control register on page 22- 685 0x0230 emios_csr[16] ? status register on page 22- 689 0x0234 emios_alta[16] (1) ? alternate a register on page 22- 690 0x0238?0x023f reserved channel 17 registers 0x0240 emios_cadr[17] ? a register on page 22- 682 0x0244 emios_cbdr[17] ? b register on page 22- 683 0x0248 emios_ccntr[17] ? counter register on page 22- 684 table 398. spc564a74xx, spc564a80xx emios memory map (continued) offset from emios_base (0xc3fa_0000) register location configurable enhanced modular io subsystem (emios200) RM0029 676/1740 doc id 15177 rev 8 0x024c emios_ccr[17] ? control register on page 22- 685 0x0250 emios_csr[17] ? status register on page 22- 689 0x0254 emios_alta[17] (1) ? alternate a register on page 22- 690 0x0258?0x025f reserved channel 18 registers 0x0260 emios_cadr[18] ? a register on page 22- 682 0x0264 emios_cbdr[18] ? b register on page 22- 683 0x0268 emios_ccntr[18] ? counter register on page 22- 684 0x026c emios_ccr[18] ? control register on page 22- 685 0x0270 emios_csr[18] ? status register on page 22- 689 0x0274 emios_alta[18] (1) ? alternate a register on page 22- 690 0x0278?0x027f reserved channel 19 registers 0x0280 emios_cadr[19] ? a register on page 22- 682 0x0284 emios_cbdr[19] ? b register on page 22- 683 0x0288 emios_ccntr[19] ? counter register on page 22- 684 0x028c emios_ccr[19] ? control register on page 22- 685 0x0290 emios_csr[19] ? status register on page 22- 689 0x0294 emios_alta[19] (1) ? alternate a register on page 22- 690 0x0298?0x029f reserved channel 20 registers 0x02a0 emios_cadr[20] ? a register on page 22- 682 table 398. spc564a74xx, spc564a80xx emios memory map (continued) offset from emios_base (0xc3fa_0000) register location RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 677/1740 0x02a4 emios_cbdr[20] ? b register on page 22- 683 0x02a8 emios_ccntr[20] ? counter register on page 22- 684 0x02ac emios_ccr[20] ? control register on page 22- 685 0x02b0 emios_csr[20] ? status register on page 22- 689 0x02b4 emios_alta[20] (1) ? alternate a register on page 22- 690 0x02b8?0x02bf reserved channel 21 registers 0x02c0 emios_cadr[21] ? a register on page 22- 682 0x02c4 emios_cbdr[21] ? b register on page 22- 683 0x02c8 emios_ccntr[21] ? counter register on page 22- 684 0x02cc emios_ccr[21] ? control register on page 22- 685 0x02d0 emios_csr[21] ? status register on page 22- 689 0x02d4 emios_alta[21] (1) ? alternate a register on page 22- 690 0x02d8?0x02df reserved channel 22 registers 0x02e0 emios_cadr[22] ? a register on page 22- 682 0x02e4 emios_cbdr[22] ? b register on page 22- 683 0x02e8 emios_ccntr[22] ? counter register on page 22- 684 0x02ec emios_ccr[22] ? control register on page 22- 685 0x02f0 emios_csr[22] ? status register on page 22- 689 0x02f4 emios_alta[22] (1) ? alternate a register on page 22- 690 0x02f8?0x02ff reserved table 398. spc564a74xx, spc564a80xx emios memory map (continued) offset from emios_base (0xc3fa_0000) register location configurable enhanced modular io subsystem (emios200) RM0029 678/1740 doc id 15177 rev 8 22.4.2 global registers all global control registers are 32-bit wide but some do not use the most significant 8 bits because the spc564a74xx, spc564a80xx has 24 channels and 24-bit counters. emios200 module configuration register (emios_mcr) the emios_mcr contains global control bits for the emios200 module. channel 23 registers 0x0300 emios_cadr[23] ? a register on page 22- 682 0x0304 emios_cbdr[23] ? b register on page 22- 683 0x0308 emios_ccntr[23] ? counter register on page 22- 684 0x030c emios_ccr[23] ? control register on page 22- 685 0x0310 emios_csr[23] ? status register on page 22- 689 0x0314 emios_alta[23] (1) ? alternate a register on page 22- 690 0x0318?0x3fff reserved 1. the alternate address register provides and alternate read-only address to access a2 channel register in gpio modes. if emios_cadr[ n ] is used with emios_alta[ n ], both a1 and a2 registers can be accessed in these modes. table 398. spc564a74xx, spc564a80xx emios memory map (continued) offset from emios_base (0xc3fa_0000) register location figure 409. emios200 module configuration register (emios_mcr) address: emios_base (0xc3fa_0000) + 0x0000 access: user read/write 0 1 2 3 4 5 6789101112131415 r0 mdis frz gtbe etb gpren 000000 srv[0:3] w reset0 0 0 0 0 0 0000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r gpre[0:7] 00000000 w reset0 0 0 0 0 0 0000000000 RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 679/1740 table 399. emios_mcr field description field description mdis module disable puts the emios200 in low power mode. the mdis bit is used to stop the clock to the module, except access to the emios_mcr, emios_oudr and emios_ucdis registers. 0 clock is running 1 enter low power mode frz freeze enables the emios200 to freeze the channel registers when debug mode is requested at the mcu level. each channel should have the fren bit set in its emios_ccr[n] register order to enter the freeze state. while in freeze state, the emios200 continues to operate to allow the mcu access to the channel registers. the channel remains frozen until the frz bit is written to zero, the mcu exits debug mode or the channel?s fren bit is cleared. 0 exit freeze state 1 stops channels operation when in debug mode and the fren bit is set in the emios_ccr[n] register gtbe global time base enable the gtbe bit is used to export a global time base enable from the module and provide a method to start time bases of several blocks simultaneously. 0 global time base enable out signal negated 1 global time base enable out signal asserted the global time base enable input controls the internal counters. when asserted, internal counters are enabled. when negated, internal counters disabled. etb external time base the etb bit selects the time base source that drives counter bus[a]. 0 counter bus[a] assigned to emios channel 1 stac drives counter bus [a] if etb is set to select stac as the counter bus[a ] source, the gtbe must be set to enable the stac to counter bus[a]. see the stac bus configuration regi ster (etpu_redcr) section of the etpu chapter for more information about the stac. gpren global prescaler enable the gpren bit enables the prescaler counter. 0 prescaler disabled (no clock) and prescaler counter is cleared 1 prescaler enabled configurable enhanced modular io subsystem (emios200) RM0029 680/1740 doc id 15177 rev 8 emios200 global flag register (emios_gfr) - srv[0:3] server time slot selects the address of a specific stac server to which the stac client submodule is assigned. see section 22.5.3, stac client submodule . 0000 etpu engine a, tcr1 0001 reserved 0010 etpu engine a, tcr2 0011 reserved 0100?1111 reserved gpre[0:7] global prescaler the gpre bits select the clock divider value for the global prescaler. table 399. emios_mcr field description (continued) field description gpre divide ratio 0000_0000 1 0000_0001 2 0000_0010 3 0000_0011 4 . . . . . . 1111_1110 255 1111_1111 256 figure 410. emios200 global flag register (emios_gfr) address: emios_base (0xc3fa_0000) + 0x0004 access: user read-only 0123456789101112131415 r00000000f23f22f21f20f19f18f17f16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rf15f14f13f12f11f10f9f8f7f6f5f4f3f2f1f0 w reset0000000000000000 RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 681/1740 emios200 output update disable register (emios_oudr) table 400. emios_gfr field description field description f n flag the emios_gfr is a read-only register that groups the flag bits from all channels. these bits are mirrors of the flag bits of each channel register (emios_csr[ n ]). see section , emios200 channel status register (emios_csr[n]) , for more detail. figure 411. emios200 output update disable register (emios_oudr) address: emios_base (0xc3fa_0000) + 0x0008 access: user read/write 0123456789101112131415 r00000000 ou 23 ou 22 ou 21 ou 20 ou 19 ou 18 ou 17 ou 16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ou 15 ou 14 ou 13 ou 12 ou 11 ou 10 ou9 ou8 ou7 ou6 ou5 ou4 ou3 ou2 ou1 ou0 w reset0000000000000000 table 401. emios_oudr field description field description ou n channel [ n ] output update disable when running a channel in mc, mcb, or an output mode, values are written to registers a2 and b2. ou n bits are used to disable transfers from registers a2 to a1 and b2 to b1. each bit controls one channel. 0 transfer enabled. depending on the operation mode, transfer may occur immediately or in the next period. unless stated otherwise, transfer occurs immediately. 1 transfers disabled. configurable enhanced modular io subsystem (emios200) RM0029 682/1740 doc id 15177 rev 8 emios200 channel disable register (emios_ucdis) - 22.4.3 channel registers all channel control registers are 32-bit wide but some do not use the most significant 8 bits because the spc564a74xx, spc564a80xx has 24 channels and 24-bit counters. emios200 channel a data register (emios_cadr[n]) depending on the mode of operation, internal registers a1 or a2, used for matches and captures, can be assigned to address emios_cadr[ n ]. a1 and a2 are cleared by reset. ta ble 40 3 summarizes the emios_cadr[ n ] write and read accesses for all operation modes. for more information see section , channel modes of operation . figure 412. emios200 channel disable register (emios_ucdis) address: emios_base (0xc3fa_0000) + 0x000c access: user read/write 0123456789101112131415 r00000000 chdi s23 chdi s22 chdi s21 chdi s20 chdi s19 chdi s18 chdi s17 chdi s16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r chdi s15 chdi s14 chdi s13 chdi s12 chdi s11 chdi s10 chdi s9 chdi s8 chdi s7 chdi s6 chdi s5 chdi s4 chdi s3 chdi s2 chdi s1 chdi s0 w reset0000000000000000 table 402. emios_ucdis field description field description chdis n disable channel [n] the chdis[n] bit is used to disable a channel by stopping its respective clock. 0 channel [n] enabled 1 channel [n] disabled figure 413. emios200 channel a data register (emios_cadr[ n ]) offset: uc[ n ] base address + 0x0000 access: user read/write 0123456789101112131415 r00000000 a[0:23] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r a[0:23] w reset0000000000000000 RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 683/1740 emios200 channel b data register (emios_cbdr[n]) depending on the mode of operation, internal registers b1 or b2 can be assigned to address emios_cbdr[ n ]. both b1 and b2 are cleared by reset. table 403 summarizes the emios_cbdr write and read accesses for all operation modes. for more information see section , channel modes of operation . depending on the channel?s configuration, it may or may not have the emios_cbdr. this means that if at least one mode that requires the register is implemented, then the register is present. otherwise, it is absent. spc564a74xx, spc564a80xx has register b (emios_cbdr) in all channels. figure 414. emios200 channel b data register (emios_cbdr[ n ]) offset: uc[ n ] base address + 0x0004 access: user read/write 0123456789101112131415 r00000000 b[0:23] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r b[0:23] w reset0000000000000000 configurable enhanced modular io subsystem (emios200) RM0029 684/1740 doc id 15177 rev 8 emios200 channel counter register (emios_ccntr[n]) the emios_ccntr[ n ] contains the value of the internal counter for emios channel n . when gpio mode is selected or t he channel is froz en the emios_ccntr[ n ] is read/write. for all other modes, the emios_ccntr[ n ] is a read-only register. when entering some operation modes, this register is automatically cleared (refer to section , channel modes of operation , for details). depending on its configuration, a channel may have an internal counter or not. if at least one mode that requires the counter is implemented, the counter is present, otherwise it is not. table 403. emios_cadr[ n ], emios_cbdr[ n ], and emios_alta[ n ] values assignment operation mode register access write read write read alt write alt read gpio a1, a2 a1 b1,b2 b1 a2 a2 saic (1) ? a2b2b2 ? ? saoc (1) a2 a1 b2 b2 ? ? ipwm ? a2 ? b1 ? ? ipm ? a2 ? b1 ? ? daoc a2 a1 b2 b1 ? ? mcb (1) a2 a1 b2 b2 ? ? opwfmb a2 a1 b2 b1 ? ? opwmb a2a1b2b1 ? ? 1. in this mode, the register emios_cbdr[n] is not used but b2 can be accessed. figure 415. emios200 channel counter register (emios_ccntr[ n ]) offset: uc[ n ] base address + 0x0008 access: user read/write 0123456789101112131415 r00000000 c[0:23] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r c[0:23] w reset0000000000000000 1. in gpio mode or freeze action, this register is writable. RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 685/1740 emios200 channel control register (emios_ccr[n]) this register contains bits reflecting the status of channel input/output signals, the overflow condition of the internal counter, and several read/write control bits for emios channel n . figure 416. emios200 channel control register (emios_ccr[ n ]) offset: uc[ n ] base address + 0x000c access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r fren odis odissl ucpre uc pren dma 0 if fck fen 0 w reset0 0 0 0 000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 forc ma forc mb 0 bsl ed sel ed pol mode w reset0 0 0 0 000000000000 table 404. emios_ccr field description field description fren freeze enable the fren bit, if set and validated by bit emios_mcr[frz], freezes all registers? values when in debug mode, allowing the mcu to perform debug functions. 0 normal operation 1 freeze unified channel registers? values odis output disable the odis bit allows disabling the output pin when running any of the output modes with the exception of gpio mode. 0 the output pin operates normally. 1 the output pin is driven to the value in edpol for opwfmb and opwmb modes and to the complement of edpol for other modes, but the channel continues to operate normally, that is, it continues to produce flag and matches. when the selected output disable input signal is negated, the output pin operates normally. odissl output disable select the odissl bits select one of the four output disable input signals. odissl input signal 00 output disable input 0 01 output disable input 1 10 output disable input 2 11 output disable input 3 configurable enhanced modular io subsystem (emios200) RM0029 686/1740 doc id 15177 rev 8 ucpre prescaler the ucpre bits select the clock divider value for the internal prescaler of the channel controlled by this register. ucpren prescaler enable the ucpren bit enables the prescaler counter. 0 prescaler disabled (no clock) and prescaler counter is loaded with ucpre value 1 prescaler enabled dma direct memory access the dma bit selects whether the flag generation (see section , emios200 channel status register (emios_csr[n]) ) is used as an interrupt or as a dma request. 0 flag/overrun assigned to interrupt request 1 flag/overrun assigned to dma request if input filter the if bits control the programmable input filter, selecting the minimum input pulse width that can pass through the filter. for output modes, these bits have no meaning. fck filter clock select the fck bit selects the clock source for the programmable input filter. 0 prescaled clock 1 main clock table 404. emios_ccr field description (continued) field description ucpre divide ratio 00 1 01 2 10 3 11 4 if (1) 1. filter latency is three clock edges. minimum input pulse width [flt_clk periods] 0000 bypassed (2) 2. the input signal is synchronized before arriving to the digital filter. 0001 02 0010 04 0100 08 1000 16 all others reserved RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 687/1740 fen flag enable the fen bit allows the unified channel flag bit to generate an interrupt signal or a dma request signal (the type of signal to be generated is defined by the dma bit). 0 disable (flag does not generate an interrupt or dma request) 1 enable (flag generates an interrupt or dma request) forcma force match a for output modes, the forcma bit is equivalent to a successful comparison on comparator a (except that the flag bit is not set). this bit is cleared by reset and is always read as 0. this bit is valid for every output operation mode which uses comparator a, otherwise it has no effect. 0 has no effect 1 force a match at comparator a for input modes, the forcma bit is not used and writing to it has no effect. forcmb force match b for output modes, the forcmb bit is equivalent to a successful comparison on comparator b (except that the flag bit is not set). this bit is cleared by reset and is always read as 0. this bit is valid for every output operation mode which uses comparator b, otherwise it has no effect. 0 has no effect. 1 force a match at comparator b. for input modes, the forcmb bit is not used and writing to it has no effect. bsl bus select the bsl bits are used to select either one of the counter buses or the internal counter to be used by the unified channel. table 404. emios_ccr field description (continued) field description bsl selected bus 00 all channels: counter bus[a]. when bsl = 0, channel 23 must be in mcb mode. 01 ? counter bus[b] is driven by channel 0 and can supply time base to channels 0 to 7. ? counter bus[c] is driven by channel 8 and can supply time base to channels 8 to 15. ? counter bus[d] is driven by channel 16 and can supply time base to channels 16 to 23. when bsl = 1, channels 0, 8 and 16 must be in mcb mode. 10 reserved 11 all channels: internal counter configurable enhanced modular io subsystem (emios200) RM0029 688/1740 doc id 15177 rev 8 edsel edge selection for input modes, the edsel bit selects if the internal counter is triggered by both edges of a pulse or by a single edge only as defined by the edpol bit. when not shown in the mode of operation description, this bit has no effect. 0 single edge triggering defined by the edpol bit. 1 both edges triggering. for gpio in mode, the edsel bit selects if a flag can be generated. 0 a flag is generated as defined by the edpol bit. 1 no flag is generated. for saoc mode, the edsel bit selects the behavior of the output flip-flop at each match. 0 the edpol value is transferred to the output flip-flop. 1 the output flip-flop is toggled. edpol edge polarity for input modes, the edpol bit asserts which edge triggers either the internal counter or an input capture or a flag. when not shown in the mode of operation description, this bit has no effect. 0 trigger on a falling edge. 1 trigger on a rising edge. for output modes, the edpol bit is used to select the logic level on the output pin. 0 a match on comparator a clears the output flip-flop, while a match on comparator b sets it. 1 a match on comparator a sets the output flip-f lop, while a match on comparator b clears it. mode mode selection the mode bits select the mode of operation of the unified channel, as shown in table 405 . refer to table 397 for more information on the different modes. if a reserved value is written to mode, the results are unpredictable. table 404. emios_ccr field description (continued) field description table 405. mode values mode[0:6] mode of operation 0000000 general purpose input/output mode (input) 0000001 general purpose input/output mode (output) 0000010 single action input capture 0000011 single action output compare 0000100 input pulse width measurement 0000101 input period measurement 0000110 double action output compare (with flag set on b match) 0000111 double action output compare (with flag set on both match) 0001000 through 1001111 reserved (1) RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 689/1740 emios200 channel status register (emios_csr[n]) 101000b (2) modulus counter buffered (up counter) 101001b (2) reserved (1) 10101bb (2) modulus counter buffered (up/down counter) 10110b0 output pulse width and frequency modulation buffered 10110b1 ? 10111b1 (2) reserved (1) 11000b0 (2) output pulse width modulation buffered 1100001 through 1111111 reserved (1) 1. if a reserved value is written to mode, the results are unpredictable. 2. b = adjust parameters for the mode of operation. refer to section , channel modes of operation , for details. table 405. mode values (continued) mode[0:6] mode of operation figure 417. emios200 channel status register (emios_csr[ n ]) address: uc[ n ] base address + 0x0010 access: user read/write 0 12345678910111213 14 15 rovr000000000000 0 0 0 ww1c reset0 000000000000 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rovfl000000000000ucinucoutflag ww1c w1c reset0 000000000000 0 0 0 table 406. emios_csr[ n ] field description field description ovr overrun the ovr bit indicates that flag generation occurred when the flag bit was already set. this bit can be cleared by clearing the flag bit or by software writing a ?1?. 0 overrun has not occurred. 1 overrun has occurred. ovfl overflow the ovfl bit indicates that an overflow has occurred in the internal counter. this bit must be cleared by software writing a ?1?. 0 an overflow has not occurred. 1 an overflow has occurred. configurable enhanced modular io subsystem (emios200) RM0029 690/1740 doc id 15177 rev 8 emios200 uc alternate a register (emios_alta[n]) the emios_alta[ n ] register provides an alternate read-only address to access a2 channel registers in gpio, pec, wpta, and opwmt modes. if the emios_cadr[ n ] is used with emios_alta[ n ], both a1 and a2 registers can be accessed in these modes. 22.5 functional description the emios200 provides independently operating channels that can be configured and accessed by a host mcu. the channels are reduced-function versions of unified channels. the four time bases can be shared by the channels through four counter buses and each channel can generate its own time base. the emios200 block is reset asynchronously. all registers are cleared on reset. ucin unified channel input pin the ucin bit reflects the input pin state after being filtered and synchronized. ucout unified channel output the ucout bit reflects the output pin state. flag flag the flag bit is set when an input capture or a match event in the comparators occurred. this bit must be cleared by software writing a ?1?. 0 flag cleared. 1 flag set event has occurred. when the dma bit is set, the flag bit can be cleared by the dma controller. table 406. emios_csr[ n ] field description (continued) field description figure 418. emios200 uc alternate a register (emios_alta[ n ]) address: uc[ n ] base address + 0x0014 access: user read/write 0123456789101112131415 r00000000 alta[0:23] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r alta[0:23] w reset0000000000000000 RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 691/1740 22.5.1 unified channel (uc) figure 419 shows the emios200 unified channel (s) block diagram. each unified channel consists of: counter bus selector, which selects the time base to be used by the channel for all timing functions a programmable clock prescaler two double buffered data registers a and b that allow up to two input capture and/or output compare events to occur before software intervention is needed. two comparators (equal only) a and b, which compares the selected counter bus with the value in the data registers internal counter, which can be used as a local time base or to count input events programmable input filter, which ensures that only valid pin transitions are received by channel programmable input edge detector, which detects the rising, falling or either edges an output flip-flop, which holds the logic level to be applied to the output pin emios200 status and control register an output disable input selector, which selects the output disable input signal that will be used as output disable s. the emios200 unified channel has a reduced set of functions when compared to legacy unified channel implementations. configurable enhanced modular io subsystem (emios200) RM0029 692/1740 doc id 15177 rev 8 figure 419. unified channel block diagram figure 420 shows both the unified channel control and datapath block diagram. the control block is responsible for the generation of signals to control the multiplexes in the datapath sub-block. each mode is implemented by a dedicated logic independent from others modes, thus allowing to optimize the logic by disabling the mode and therefore its associated logic. the unused gates are removed during the synthesis phase. targeting the logic optimization, a set of registers is shared by the modes thus providing sequential events to be stored. the datapath block provides the channel a and b registers, the internal time base and comparators. multiplexors select the input of comparators and data for the registers inputs, thus configuring the datapath in order to implement the channel modes. the outputs of a and b comparators are connected to the control block. channel controller clock prescaler programmable filter channel data path comparator a comparator b uc_cnt_rd_data[ n ] uc_cnt_rd_data[ n ] counter bus[0] counter bus[1] match logic mode logic counter bus unified channel control signals RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 693/1740 figure 420. unified channel control and datapath block diagrams channel modes of operation the mode of operation of channel n is determined by the mode select bits mode[0:6] in the emios_ccr[n] (see table 405 for details). when entering an output mode (except for gpio mode), the output flip-flop is set to disabled state according to odis bit in the emios_ccr[n]. as the internal counter emios_ccntr[n] continues to run in all modes (except for gpio mode), it is possible to use it as a time base if the resource is not used in the current mode. a2 b2 b1 a1 cnt local counter bus global counter bus a comparator bsl[0] bsl[1]+logic bsl[1]+logic bsl[1]+logic internal counter [b/c/d] b comparator datapath control block control signals input filter input mode 0 logic general purpose registers mode 1 logic mode n logic mode decoder mode register == == [a] configurable enhanced modular io subsystem (emios200) RM0029 694/1740 doc id 15177 rev 8 to provide smooth waveform generation while allowing a and b registers to be asynchronously updated during uc operation, the double-buffered modes (mcb, opwfmb and opwmb) are provided. in these modes a and b registers are double buffered. general purpose input/output mode (gpio) mode in gpio mode, all input capture and output compare functions are disabled, the internal counter (emios_ccntr[n]) is cleared and disabled. all control bits remain accessible. in order to prepare the channel for a new operation mode, writing to registers emios_cadr[n] or emios_cbdr[n] stores the same value in registers a1/a2 or b1/b2, respectively. writing to register emios_alta[n] stores a value only in register a2. the emios_ccr[n]?s mode[6] bit selects between input (mode[6] = 0) and output (mode[6] = 1) modes. note: it is required that when changing mode[0:6], the application software goes to gpio mode first in order to reset the channel?s internal functions properly. failure to do this could lead to invalid and unexpected output compare or input capture results or the flags being set incorrectly. in gpio input mode (mode[0:6] = 0000000), flag generation is determined according to the emios_ccr[n]?s edpol and edsel bits and the input pin status can be determined by reading the emios_csr[n]?s ucin bit. in gpio output mode (mode[0:6] = 0000001), the channel is used as a single output port pin and the value of the emios_ccr[n]?s edpol bit is permanently transferred to the output flip-flop. when changing the emios_ccr[n]?s mode bits, the application software must go to gpio mode first to reset the channel?s internal functions properly. failure to do this could lead to invalid and unexpected output compare or input capture results or the flags being set incorrectly. single action input capture (saic) mode in saic mode (mode[0:6] = 0000010), when a triggering event occurs on the input pin, the value on the selected time base is captured into register a2. the flag bit is set along with the capture event to indicate that an input capture has occurred. emios_cadr[n] returns the value of register a2. as soon as the saic mode is entered exiting from gpio mode the channel is ready to capture events. the events are captured as soon as they occur thus reading register a always returns the value of the latest captured event. subsequent captures are enabled with no need of further reads from emios_cadr[n]. the flag is set at any time a new event is captured. the input capture is triggered by a rising, falling or either edges in the input pin, as configured by edpol and edsel bits in emios_ccr[n]. figure 421 and figure 422 show how the unified channel can be used for input capture. RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 695/1740 figure 421. single action input capture with rising edge triggering example figure 422. single action input captur e with both edges triggering example single action output compare (saoc) mode in saoc mode (mode[0:6] = 0000011) a match value is loaded in register a2 and then immediately transferred to register a1 to be compared with the selected time base. when a match occurs, the edsel bit selects whether the output flip-flop is toggled or the value in edpol is transferred to it. along with the match the flag bit is set to indicate that the output compare match has occurred. writing to emios_cadr[n] stores the value in register a2 and reading to register emios_cadr[n] returns the value of register a1. an output compare match can be simulated in software by setting the forcma bit in emios_ccr[n]. in this case, the flag bit is not set. when saoc mode is entered exiting from gpio mode the output flip-flop is set to the complement of the edpol bit in the emios_ccr[n]. the counter bus can be either internal or external and is selected through bsl[0:1] bits. figure 423 and figure 424 show how the channel can be used to perform a single output compare with edpol value being transferred to the output flip-flop and toggling the output flip-flop at each match, respectively. note that once in saoc mode the matches are enabled thus the desired match value on register a1 must be written before the mode is entered. a1 register can be updated at any time thus modifying the match value which will reflect in the output signal generated by the channel. subsequent matches are enabled with selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 flag pin/register a2 (captured) value 2 0xxxxxxx 0x001000 0x001250 0x0016a0 input signal 1 edge detect edge detect edge detect notes: 1. after input filter 2. cadr[n] <= a2 edsel = 0 edpol = 1 selected counter bus 0x001000 0x001102 flag set event a2 (captured) value 2 0xxxxxxx0x001000 input signal 1 edge detect notes: 1. after input filter 2. cadr[n] <= a2 0x001103 0x001108 0x001104 0x001105 0x001106 0x001107 0x001001 flag pin/register edge detect flag clear edge detect 0x001103 0x001108 edsel = 1 edpol = x configurable enhanced modular io subsystem (emios200) RM0029 696/1740 doc id 15177 rev 8 no need of further writes to emios_cadr[n]. the flag is set at the same time a match occurs (see figure 425 ). note: the channel internal counter in saoc mode is free-running. it starts counting as soon as the saoc mode is entered. figure 423. saoc example with edpol value being transferred to the output flip-flop figure 424. saoc example toggling the output flip-flop figure 425. saoc example with flag behavior selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000 output flip-flop update to a1 a1 value 1 0xxxxxxx 0x001000 flag pin/register 0x001000 0x001000 0x001000 a1 match a1 match a1 match notes: 1. cadr[n] = a2 edsel = 0 edpol = 1 a2 = a1 according to ou[n] bit selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000 a1 value 1 0xxxxxxx 0x001000 output flip-flop update to a1 flag pin/register a1 match a1 match a1 match 0x001000 0x001000 0x001000 notes: 1. cadr[n] = a2 edsel = 1 edpol = x a2 = a1 according to ou[n] bit selected counter bus 0x0 0x2 flag set event a2 value 1 0x1 output flip-flop note: 1. cadr[n] <= a2 0x0 0x2 0x1 0x2 0x0 0x1 0x1 flag pin/register flag clear edsel = 1 system clock a1 match edpol = x RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 697/1740 input pulse width measurement (ipwm) mode the ipwm mode (mode[0:6] = 0000100) allows the measurement of the width of a positive or negative pulse by capturing the leading edge on register b1 and the trailing edge on register a2. successive captures are done on consecutive edges of opposite polarity. the leading edge sensitivity (that is, pulse polarity) is selected by edpol bit in the emios_ccr[n]. registers emios_cadr[n] and emios_cbdr[n] return the values in registers a2 and b1, respectively. the capture function of register a2 remains disabled until the first leading edge triggers the first input capture on register b2. when this leading edge is detected, the count value of the selected time base is latched into register b2; the flag bit is not set. when the trailing edge is detected, the count value of the selected time base is latched into register a2 and, at the same time, the flag bit is set and the content of register b2 is transferred to register b1 and to register a1. if subsequent input capture events occur while the corresponding flag bit is set, registers a2, b1 and a1 will be updated with the latest captured values and the flag will remain set. registers emios_cadr[n] and emios_cbdr[n] return the value in registers a2 and b1, respectively. in order to guarantee coherent access, reading emios_cadr[n] forces b1 be updated with the content of register a1. at the same time transfers between b2 and b1 are disabled until the next read of emios_cbdr[n]. reading emios_cbdr[n] forces b1 be updated with a1 register content and re-enables transfers from b2 to b1, to take effect at the next trailing edge capture. transfers from b2 to a1 are not blocked at any time. the input pulse width is calculated by subtracting the value in b1 from a2. figure 426 shows how the channel can be used for input pulse width measurement. figure 426. input pulse width measurement example figure 427 shows the a1 and b1 updates when emios_cadr[n] and emios_cbdr[n] reads occur. note that a1 register has always coherent data related to a2 register. note also that when emios_cadr[n] read is performed b1 register is loaded with a1 register content. this guarantees that the data in register b1 has always the coherent data related to the last emios_cadr[n] read. the b1 register updates remain locked until selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 a2(captured) value 2 b2(captured) value b1 value 3 0xxxxxxx 0x001000 0x001250 0x0016a0 0xxxxxxx 0x001100 0x001525 0xxxxxxx 0x001000 0x001250 input signal 1 babab 1. after input filter notes: flag pin/register 2. cadr[n] = a2 3. cbdr[n] = b1 edpol = 1 a1 value 3 0xxxxxxx 0x001000 0x001250 configurable enhanced modular io subsystem (emios200) RM0029 698/1740 doc id 15177 rev 8 emios_cbdr[n] read occurs. if emios_cadr[n] read is performed b1 is updated with a1 register content even if b1 update is locked by a previous emios_cadr[n] read operation. figure 427. b1 and a1 updates at emios_cadr[n] and emios_cbdr[n] reads reading emios_cadr[n] followed by emios_cbdr[n] always provides coherent data. if no coherent data is required for any reason, the sequence of reads should be inverted, therefore emios_cbdr[n] should be read prior to emios_cadr[n]. note that even in this case b1 register updates will be blocked after emios_cadr[n] read, thus a second emios_cbdr[n] is required in order to release b1 register updates. input period measurement (ipm) mode the ipm mode (mode[0:6] = 0000101) allows the measurement of the period of an input signal by capturing two consecutive rising edges or two consecutive falling edges. successive input captures are done on consecutive edges of the same polarity. the edge polarity is defined by the edpol bit in the emios_ccr[n]. when the first edge of selected polarity is detected, the selected time base is latched into the registers a2 and b2, and the data previously held in register b2 is transferred to register b1. on this first capture the flag line is not set, and the values in registers b1 is meaningless. on the second and subsequent captures, the flag line is set and data in register b2 is transferred to register b1. when the second edge of the same polarity is detected, the counter bus value is latched into registers a2 and b2, the data previously held in register b2 is transferred to data register b1 and to register a1. the flag bit is set to indicate the start and end points of a complete period have been captured. this sequence of events is repeated for each subsequent capture. registers emios_cadr[n] and emios_cbdr[n] return the values in register a2 and b1, respectively. in order to allow coherent data, reading emios_cadr[n] forces a1 content be transferred to b1 register and disables transfers between b2 and b1. these transfers are disabled until the next read of the emios_cbdr[n]. reading emios_cbdr[n] forces a1 content to be transferred to b1 and re-enables transfers from b2 to b1, to take effect at the next edge capture. selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 a2(captured) value 2 b2(captured) value b1 value 3 0xxxxxxx 0x001000 0x001250 0x0016a0 0xxxxxxx 0x001100 0x001525 0xxxxxxx 0x001000 input signal 1 babab 1. after input filter notes: flag pin/register 2. cadr[n] = a2 edpol = 1 a1 value 3 0xxxxxxx 0x001000 0x001250 0x001000 0x001250 read cadr[n] read cbdr[n] 3. cbdr[n] = b1 RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 699/1740 the input pulse period is calculated by subtracting the value in b1 from a2. figure 428 shows how the channel can be used for input period measurement. figure 428. input period measurement example figure 429 describes the a1 and b1 register updates when emios_cadr[n] and emios_cbdr[n] read operations are performed. when emios_cadr[n] read occurs the content of a1 is transferred to b1 thus providing coherent data in a2 and b1 registers. transfers from b2 to b1 are then blocked until emios_cbdr[n] is read. after emios_cbdr[n] is read, register a1 content is transferred to register b1 and the transfers from b2 to b1 are re-enabled to occur at the transfer edges, which is the leading edge in the figure 429 example. figure 429. a1 and b1 updates at emios_cadr[n] and emios_cbdr[n] reads selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 a2(captured) value 2 a1 value b2 (captured) value 0xxxxxxx 0x001000 0x001250 0xxxxxxx 0x001000 0x001250 0x0016a0 0xxxxxxx 0x001000 0x001250 0x0016a0 input signal 1 edpol = 1 flag pin register notes: 1. after input filter 2. cadr[n] = a2 3. cbdr[n] = b1 a a a b1 value 3 0xxxxxxx 0x001000 0x001250 selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 a2(captured) value 2 b2(captured) value b1 value 3 0xxxxxxx 0x001000 0x001250 0x0016a0 0xxxxxxx 0x001000 0xxxxxxx 0x001000 input signal 1 a aa flag pin/register edpol = 1 a1 value 0xxxxxxx 0x001000 0x001000 0x001250 0x001250 read cadr[n] read cbdr[n] 0x001250 notes: 1. after input filter 2. cadr[n] = a2 3. cbdr[n] = b1 0x0016a0 configurable enhanced modular io subsystem (emios200) RM0029 700/1740 doc id 15177 rev 8 double action output compare (daoc) mode in the daoc mode the leading and trailing edges of the variable pulse width output are generated by matches occurring on comparators a and b. there is no restriction concerning the order in which a and b matches occur. when the daoc mode is entered, exiting from gpio mode both comparators are disabled and the output flip-flop is set to the complement of the edpol bit in the emios_ccr[n]. data written to a2 and b2 are transferred to a1 and b1, respectively, on the next system clock cycle if bit ou[n] of the emios_oudr is cleared (see figure 432 ). the transfer is blocked if ou[n] bit is set. comparator a is enabled only after the transfer to a1 register occurs and is disabled on the next a match. comparator b is enabled only after the transfer to b1 register occurs and is disabled on the next b match. comparators a and b are enabled and disabled independently. the output flip-flop is set to the value of edpol when a match occurs on comparator a and to the complement of edpol when a match occurs on comparator b. mode[6] controls if the flag is set on both matches (mode[0:6] = 0000111) or just on the b match (mode[0:6] = 0000110). flag bit assertion depends on comparator enabling. if subsequent enabled output compares occur on registers a1 and b1, pulses will continue to be generated, regardless of the state of the flag bit. at any time, the forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a comparison event in comparator a or b, respectively. note that the flag bit is not affected by these forced operations. note: if both registers (a1 and b1) are loaded with the same value, the b match prevails concerning the output pin state (output flip-flop is set to the complement of edpol), the flag bit is set and both comparators are disabled. figure 430 and figure 431 show how the channel can be used to generate a single output pulse with flag bit being set on the second match or on both matches, respectively. figure 430. double action output compare with flag set on the second match selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 a1 value 1 b1 value 2 0xxxxxxx 0x001100 0x001100 0x001100 0xxxxxxx 0x001000 0x001000 0x001000 output flip-flop mode a1 match b1 match update to a1 and b1 flag pin/register a1 match b1 match [6] = 0 notes: 1. cadr[n] = a1 (when reading) 2. cbdr[n] = b1 (when reading) a2 = a1according to ou[n] bit b2 = b1according to ou[n] bit RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 701/1740 figure 431. double action output compare with flag set on both matches figure 432. daoc with transfer disabling example modulus counter buffered (mcb) mode the mcb mode provides a time base which can be shared with other channels through the internal counter buses. register a1 is double buffered thus allowing smooth transitions between cycles when changing a2 register value on the fly. a1 register is updated at the cycle boundary, which is defined as when the internal counter transitions to 0x1. selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 a1 value 1 b1 value 2 0xxxxxxx 0x001100 0x001100 0x001100 0xxxxxxx 0x001000 0x001000 0x001000 output flip-flop a1 match b1 match update to a1 and b1 flag pin/register a1 match b1 match notes: 1. cadr[n] = a1 (when reading) 2. cbdr[n] = b1 (when reading) a2 = a1according to ou[n] bit b2 = b1according to ou[n] bit mode [6] = 1 selected counter bus 0x0 0x2 flag set event a1 value 2 0xx output flip-flop 2. cadr[n] = a1 (when reading) 0x0 0x2 0x1 0x2 0x0 0x1 0x1 flag pin/register flag clear edsel = 1 system clock enabled a1 match edpol = x b2 value 5 0x2 b1 value 4 0xx a2 value 3 0x1 ou 1 enabled b1 match 0x1 0xx 0xx 0x2 0x1 write to a2 0x2 0x2 0x1 0x2 0x1 0x1 0x2 write to b2 write to a2 write to b2 write to a2 write to b2 mode[0] = 1 3. cadr[n] = a2 (when writing) 4. cbdr[n] = b1 (when reading) 5. cbdr[n] = b2 (when writing) note: 1. ou[n] bit of the oudr configurable enhanced modular io subsystem (emios200) RM0029 702/1740 doc id 15177 rev 8 the internal counter values operates within a range from 0x1 up to register a1 value. if when entering mcb mode exiting from gpio mode the internal counter value is not within that range then the a match will not occur causing the channel internal counter to wrap at the maximum counter value which is 0xff_ffff for a 24-bit counter. after the counter wrap occurs it returns to 0x1 and resume normal mcb mode operation. thus in order to avoid the counter wrap condition make sure its value is within the 0x1 to a1 register value range when the mcb mode is entered. mode[6] bit selects internal clock source if cleared or external if set. when external clock is selected the input channel pin is used as the channel clock source. the active edge of this clock is defined by edpol and edsel bits in the emios_ccr[n]. when entering mcb mode, if the up counter is selected by mode[4] = 0 (mode[0:6] = 101000b), the internal counter starts counting from its current value to up direction until a1 match occurs. the internal counter is set to 0x1 when its value matches a1 value and a clock tick occurs (either prescaled clock or input pin event). if the up/down counter is selected by setting mode[4] = 1, the counter changes direction at a1 match and counts down until it reaches the value 0x1. after it has reached 0x1 it is set to count in up direction again. the b1 register is used to generate a match in order to set the internal counter in up-count direction if up/down mode is selected. register b1 cannot be changed while this mode is selected. note that differently from the mc mode, the mcb mode counts between 0x1 and the a1 register value. only values greater than 0x1 must be written at a1 register. loading values other than those leads to unpredictable results. the counter cycle period is equal to a1 value in up counter mode. if in up/down counter mode, the period is defined by the expression: (2*a1)-2. figure 433 describes the counter cycle for several a1 values. register a1 is loaded with the a2 register value at the cycle boundary. thus any value written to the a2 register within cycle n will be updated to a1 at the next cycle boundary and therefore will be used on cycle n+1 . the cycle boundary between cycle n and cycle n+1 is defined as when the internal counter transitions from a1 value in cycle n to 0x1 in cycle n+1 . note that the flag is generated at the cycle boundary and has a synchronous operation, meaning that it is asserted one system clock cycle after the flag set event. RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 703/1740 figure 433. modulus counter buffered (mcb) up count mode figure 434 describes the mcb in up/down counter mode (mode[0:6] = 10101bb). the a1 register is updated at the cycle boundary. if a2 is written in cycle n , this new value will be used in cycle n+1 for a1 match. flags are generated only at a1 match start if mode[5] is 0. if mode[5] is set to 1 flags are also generated at the cycle boundary. figure 434. modulus counter buffered (mcb) up/down mode figure 435 describes in more detail the a1 register update process in up counter mode. the a1 load signal is generated at the last system clock period of a counter cycle. thus, a1 is updated with a2 value at the same time that the counter (emios_ccntr[n]) is loaded with 0x1. the load signal pulse has the duration of one system clock period. if a2 is written within cycle n its value is available at a1 at the first clock of cycle n+1 and the new value is used for match at cycle n+1 . the update disable bits ou[n] of emios_oudr can be used to emioscnt[n] time write to a2 match a1 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000007 flag set event a1 value 0x000006 0x000005 0x000007 0x000007 0x000005 0x000007 a2 value flag pin/register prescaler ratio = 1 cycle n cycle n+1 cycle n+2 flag clear emioscnt[n] time write to a2 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000007 flag set event a1 value 0x000006 0x000005 0x000007 0x000005 0x000007 a2 value flag pin/register prescaler ratio = 1 cycle n+1 cycle n+2 cycle n flag clear configurable enhanced modular io subsystem (emios200) RM0029 704/1740 doc id 15177 rev 8 control the update of this register, thus allowing to delay the a1 register update for synchronization purposes. figure 435. mcb mode a1 register update in up counter mode figure 436 describes the a1 register update in up/down counter mode. note that a2 can be written at any time within cycle n in order to be used in cycle n+1 . thus a1 receives this new value at the next cycle boundary. note that the update disable bits ou[n] of emios_oudr can be used to disable the update of register a1. figure 436. mcb mode a1 register update in up/down counter mode output pulse width and frequency modulation buffered (opwfmb) mode this mode (mode[0:6] = 10110b0) provides waveforms with variable duty cycle and frequency. the internal channel counter is automatically selected as the time base when this mode is selected. the a1 register indicates the duty cycle and b1 register the frequency. both a1 and b1 registers are double buffered to allow smooth signal generation when changing the registers values on the fly. 0% and 100% duty cycles are supported. a1 value 0x000008 0x000008 0x000001 internal counter 0x000004 0x000006 a2 value 0x000008 0x000004 0x000006 0x000002 0x000004 0x000006 write to a2 write to a2 match a1 match a1 a1 load signal 8 4 6 match a1 counter = a1 time cycle n cycle n+1 cycle n+2 prescaler ratio = 2 a1 value 0x000006 a2 value 0x000006 0x000005 0x000006 0x000005 a1 load signal counter = 2 emioscnt[n] time write to a2 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000006 cycle n cycle n+1 cycle n+2 prescaler ratio = 2 RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 705/1740 at opwfmb mode entry the output flip-flop is set to the value of the edpol bit in the emios_ccr[n]. in order to provide smooth and consistent channel operation this mode differs substantially from the opwfm mode. the main differences reside in the a1 and b1 registers update, on the delay from the a1 match to the output pin transition and on the range of the internal counter values which starts from 0x1 up to b1 register value. if when entering opwfmb mode exiting from gpio mode the internal counter value is not within that range then the b match will not occur causing the channel internal counter to wrap at the maximum counter value which is 0xff_ffff for a 24-bit counter. after the counter wrap occurs it returns to 0x1 and resume normal opwfmb mode operation. thus in order to avoid the counter wrap condition make sure its value is within the 0x1 to b1 register value range when the opwfmb mode is entered. when a match on comparator a occurs the output register is set to the value of edpol. when a match on comparator b occurs the output register is set to the complement of edpol. b1 match also causes the internal counter to transition to 0x1, thus restarting the counter cycle. only values greater than 0x1 are allowed to be written to b1 register. loading values other than those leads to unpredictable results. figure 437 describes the operation of the opwfmb mode regarding output pin transitions and a1/b1 registers match events. note that the output pin transition occurs when the a1 or b1 match signal is deasserted which is indicated by the a1 match negedge detection signal. if register a1 is set to 0x4 the output pin transitions four counter periods after the cycle had started, plus one system clock cycle. note that in the example shown in figure 437 the internal counter prescaler has a ratio of two. figure 437. opwfmb a1 and b1 match to output register delay figure 438 describes the generated output signal if a1 is set to 0x0. since the counter does not reach zero in this mode, the channel internal logic infers a match as if a1 = 0x1 with the difference that in this case, the posedge of the match signal is used to trigger the output pin 8 1 4 match a1 negedge detection 5 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 emioscnt time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 system clock prescaler prescaler ratio = 2 configurable enhanced modular io subsystem (emios200) RM0029 706/1740 doc id 15177 rev 8 transition instead of the negedge used when a1 = 0x1. note that a1 posedge match signal from cycle n+1 occurs at the same time as b1 negedge match signal from cycle n . this allows using the a1 posedge match to mask the b1 negedge match when they occur at the same time. the result is that no transition occurs on the output flip-flop and a 0% duty cycle is generated. figure 438. opwfmb mode with a1 = 0 (0% duty cycle) figure 439 describes the timing for the a1 and b1 registers load. the a1 and b1 load use the same signal which is generated at the last system clock period of a counter cycle. thus, a1 and b1 are updated respectively with a2 and b2 values at the same time that the counter (emios_ccntr[n]) is loaded with 0x1. this event is defined as the cycle boundary. the load signal pulse has the duration of one system clock period. if a2 and b2 are written within cycle n their values are available at a1 and b1, respectively, at the first clock of cycle n+1 and the new values are used for matches at cycle n+1 . the update disable bits ou[n] of emios_oudr can be used to control the update of these registers, thus allowing to delay the a1 and b1 registers update for synchronization purposes. in figure 439 it is assumed that both the channel and global prescalers are set to 0x1 (each divide ratio is two), meaning that the channel internal counter transitions at every four system clock cycles. flags can be generated only on b1 matches when mode[5] is cleared, or on both a1 and b1 matches when mode[5] is set. since b1 flag occurs at the cycle boundary, this flag can be used to indicate that a2 or b2 data written on cycle n were loaded to a1 or b1, respectively, thus generating matches in cycle n+1 . note that the flag has a synchronous operation, meaning that it is asserted one system clock cycle after the flag set event. 1 4 match a1 negedge detection 5 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 emioscnt time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 system clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection no transition at this point 1 cycle n cycle n+1 prescaler ratio = 2 RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 707/1740 figure 439. opwfmb a1 and b1 registers update and flags figure 440 describes the operation of the output disable feature in opwfmb mode. differently from the opwfm mode, the output disable forces the channel output flip-flop to edpol bit value. this functionality targets applications that use active high signals and a high to low transition at a1 match. in this case edpol should be set to 0. note that both the channel and global prescalers are set to 0x0 (each divide ratio is one), meaning that the channel internal counter transitions at every system clock cycle. edpol = 0 cycle n cycle n+1 cycle n+2 a1 value 1 b1 value b2 value 0x8 0x2 0x6 0x8 0x1 internal counter 0x4 0x6 mode [6] = 1 a2 value 1 0x2 0x4 0x6 0x2 0x4 0x6 0x8 0x6 output pin write to b2 write to a2 write to a2 match a1 match a1 match b1 match b1 match b1 a1/b1 load signal due to b1 match cycle n-1 flag set event flag pin/register prescaler ratio = 4 flag clear configurable enhanced modular io subsystem (emios200) RM0029 708/1740 doc id 15177 rev 8 figure 440. opwfmb mode with active output disable note that the output disable has a synchronous operation, meaning that the assertion of the output disable input pin causes the channel output flip-flop to transition to edpol at the next system clock cycle. if the output disable input is deasserted the output pin transition at the following a1 or b1 match. in figure 440 it is assumed that the output disable input is enabled and selected for the channel. please, refer to section , emios200 channel control register (emios_ccr[n]) , for a detailed description about the odis and odissl bits, respectively enable and selection of the output disable inputs. the forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on comparators a or b respectively. similarly to a b1 match forcmb sets the internal counter to 0x1. the flag bit is not set by the forcma or forcmb bits being asserted. figure 441 describes the generation of 100% and 0% duty cycle signals. it is assumed edpol = 0 and the resultant prescaler value is 1. initially a1 = 0x8 and b1 = 0x8. in this case, b1 match has precedence over a1 match, thus the output flip-flop is set to the complement of edpol bit. this cycle corresponds to a 100% duty cycle signal. the same output signal can be generated for any a1 value greater or equal to b1. edpol = 0 cycle n cycle n+1 cycle n+2 a1 value b1 value b2 value 0x000008 0x000002 0x000006 0x000008 0x000001 internal counter 0x000004 0x000006 mode [6] = 1 a2 value 0x000002 0x000004 0x000006 0x000002 0x000004 0x000006 0x000008 0x000006 output pin write to b2 write to a2 write to a2 match a1 match a1 match b1 match b1 match b1 due to b1 match cycle n-1 flag set event output disable flag pin/register prescaler ratio = 1 flag set event RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 709/1740 figure 441. opwfmb mode from 100% to 0% duty cycle a 0% duty cycle signal is generated if a1 = 0x0 as shown in figure 441 cycle 9. in this case b1 = 0x8 match from cycle 8 occurs at the same time as the a1 = 0x0 match from cycle 9. please, refer to figure 438 for a description of the a1 and b1 match generation. in this case a1 match has precedence over b1 match and the output signal transitions to edpol. output pulse width modulation buffered (opwmb) mode opwmb mode (mode[0:6] = 11000b0) is used to generate pulses with programmable leading and trailing edge placement. an external counter driven in mcb up mode must be selected from one of the counter buses. a1 register value defines the first edge and b1 the second edge. the output signal polarity is defined by the edpol bit. if edpol is zero, a negative edge occurs when a1 matches the selected counter bus and a positive edge occurs when b1 matches the selected counter bus. the a1 and b1 registers are double buffered and updated from a2 and b2, respectively, at the cycle boundary. the load operation is similar to the opwfmb mode. please refer to figure 439 for more information about a1 and b1 registers update. flag can be generated at b1 matches, when mode[5] is cleared, or in both a1 and b1 matches, when mode[5] is set. if subsequent matches occur on comparators a and b, the pwm pulses continue to be generated, regardless of the state of the flag bit. forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on a1 or b1 respectively. flag bit is not set by the forcma and forcmb operations. at opwmb mode entry the output flip-flop is set to the value of the edpol bit in the emios_ccr[n]. some rules applicable to the opwmb mode are listed as follows: b1 matches have precedence over a1 matches if they occur at the same time within the same counter cycle a1 = 0 match from cycle n has precedence over b1 match from cycle n-1 a1 matches are masked out if they occur after b1 match within the same cycle any value written to a2 or b2 on cycle n is loaded to a1 and b1 registers at the following cycle boundary (assuming ou[n] bit of emios_oudr is not asserted). thus the new values will be used for a1 and b1 matches in cycle n+1 . 0x000008 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 0% 100% emioscnt edpol = 0 a1 value b1 value output pin 0x000008 prescaler ratio = 1 cycle 1cycle 2cycle 3cycle 4cycle 5cycle 6cycle 7cycle 8cycle 9 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 a2 value 0x000008 0x000001 configurable enhanced modular io subsystem (emios200) RM0029 710/1740 doc id 15177 rev 8 figure 442 describes the operation of the opwmb mode regarding a1 and b1 matches and the transition of the channel output pin. in this example edpol is set to zero. figure 442. opwmb mode matches and flags note that the output pin transitions are based on the negedges of the a1 and b1 match signals. figure 442 shows in cycle n+1 the value of a1 register being set to zero. in this case the match posedge is used instead of the negedge to transition the output flip-flop. figure 443 describes the channel operation for 0% duty cycle. note that the a1 match posedge signal occurs at the same time as the b1 = 0x8 negedge signal. in this case a1 match has precedence over b1 match, causing the output pin to remain at edpol bit value, thus generating a 0% duty cycle signal. 1 4 match a1 negedge detection 6 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000006 clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection 1 cycle n cycle n+1 8 6 flag set event selected counter bus flag pin/register RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 711/1740 figure 443. opwmb mode with 0% duty cycle figure 444 describes the operation of the opwmb mode with the output disable signal being asserted. the output disable forces a transition in the output pin to the edpol bit value. after deasserted, the output disable allows the output pin to transition at the following a1 or b1 match. note that the output disable does not modify the flag bit behavior. note that there is one system clock delay between the assertion of the output disable signal and the transition of the output pin to edpol. 1 4 match a1 negedge detection 8 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 selected time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection 1 cycle n cycle n+1 8 counter bus flag set event flag pin/register configurable enhanced modular io subsystem (emios200) RM0029 712/1740 doc id 15177 rev 8 figure 444. opwmb mode with active output disable figure 445 shows a waveform changing from 100% to 0% duty cycle. edpol in this case is zero. in this example b1 is programmed to the same value as the period of the external selected time base. figure 445. opwmb mode from 100% to 0% duty cycle in figure 445 if b1 is set to a value lower than 0x8 it is not possible to achieve 0% duty cycle by only changing a1 register value. since b1 matches have precedence over a1 matches the output pin transitions to the opposite of edpol bit at b1 match. note also that if b1 is set to 0x9, for instance, b1 match does not occur, thus a 0% duty cycle signal is generated. edpol = 0 cycle n cycle n+1 cycle n+2 a1 value b1 value b2 value 0x000008 0x000002 0x000006 0x000008 0x000001 selected 0x000004 0x000006 mode [6] = 1 a2 value 0x000002 0x000004 0x000006 0x000002 0x000004 0x000006 0x000008 0x000006 output pin write to b2 write to a2 write to a2 match a1 match a1 match b1 match b1 match b1 due to b1 match cycle n-1 flag set event output disable counter bus flag pin/register flag clear 0x000008 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 0% 100% selected edpol = 0 a1 value b1 value output pin 0x000008 prescaler = 1 cycle 1 cycle 2 cycle 3 cycle 4 cycl e 5 cycle 6 cycle 7 cycle 8 cycle 9 counter bus 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 a2 value RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 713/1740 input programmable filter (ipf) the ipf ensures that only valid input pin transitions are received by the channel edge detector. a block diagram of the ipf is shown in figure 446 . the ipf is a 5-bit programmable up counter that is incremented by the selected clock source, according to bits if[0:3] in emios_ccr[n]. figure 446. lnput programmable filter submodule diagram the input signal is synchronized by system clock. when a state change occurs in this signal, the 5-bit counter starts counting up. as long as the new state is stable on the pin, the counter remains incrementing. if a counter overflows occurs, the new pin value is validated. in this case, it is transmitted as a pulse edge to the edge detector. if the opposite edge appears on the pin before validation (overflow), the counter is reset. at the next pin transition, the counter starts counting again. any pulse that is shorter than a full range of the masked counter is regarded as a glitch and it is not passed on to the edge detector. a timing diagram of the input filter is shown in figure 447 . figure 447. input programmable filter example the filter is not disabled during either freeze state or negated gtbe input. clock prescaler (cp) the cp divides the gcp output signal to generate a clock enable for the internal counter of the unified channels. the gcp output signal is prescaled by the value defined in the ucpre[0:1] bits in the emios_ccr[n]. the prescaler is enabled by setting the ucpren bit in the emios_ccr[n] and can be stopped at any time by clearing this bit, thereby stopping the internal counter in the channel. if3 filter out ipg_clk prescaled clock if2 if1 if0 clk fck emiosi 5-bit up counter synchronizer clock time selected clock emiosi 5-bit counter filter out if [0:3] = 0010 configurable enhanced modular io subsystem (emios200) RM0029 714/1740 doc id 15177 rev 8 in order to ensure safe working and avoid glitches the following steps must be performed whenever any update in the prescaling rate is desired: 1. write ?0? at both bit emios_mcr[gpren] and ucpren bit in emios_ccr[n], thus disabling prescalers; 2. write the desired value for prescaling rate at ucpre[0:1] bits in emios_ccr[n]; 3. enable channel prescaler by writing ?1? at ucpren bit in emios_ccr[n]; 4. enable global prescaler by writing ?1? at bit emios_mcr[gpren]. the prescaler is not disabled during either freeze state or negated gtbe input. effect of freeze on the unified channel when in debug mode, bit emios_mcr[frz] and the fren bit in the emios_ccr[n] are both set, the internal counter and channel capture and compare functions are halted. the channel is frozen in its current state. during freeze, all registers are accessible. when the channel is operating in an output mode, the force match functions remain available, allowing the software to force the output to the desired level. note that for input modes, any input events that may occur while the channel is frozen are ignored. when exiting debug mode or freeze enable bit is cleared (bit emios_mcr[frz] or fren in the emios_ccr[n]), the channel actions resume but may be inconsistent until the channel enters gpio mode again. 22.5.2 ip bus interface unit (biu) the biu provides the interface between the internal interface bus (iib) and the peripheral bus, allowing communication among all submodules and this ip interface. the biu allows 8, 16 and 32 bits access. they are performed over a 32-bit data bus in a single cycle clock. effect of freeze on the biu when bit emios_mcr[frz] is set and the module is in debug mode, the operation of biu is not affected. 22.5.3 stac client submodule the shared time and angle count (stac) bus provides access to one external time base, imported from the stac bus to the emios unified channels. the etpu module?s time bases and angle count can be exported and/or imported through the stac client submodule interface. time bases and/or angle information of the etpu engine can be exported to the emios module, which is only a stac client. there are restrictions on engine export/import targets: an engine cannot export from or import to itself, nor can it import time base and/or angle count if in angle mode. the device?s stac server identification assignment is shown in table 407 . the time slot assignment is fixed, so only time bases running at system clock divided by four or slower can be integrally exported. the stac client submodule runs with the system clock, and its time slot timing is synchronized with the etpu timing on reset. the time slot sequence is 0- 1-2-3. RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 715/1740 figure 448 provides a block diagram for the stac client submodule. figure 448. stac client submodule block diagram emios_mcr[srv] bits select the time slot of the stac output bus. figure 449 shows a timing diagram for the stac client submodule. figure 449. timing diagram for stac bus and stac client submodule output every time the selected time slot changes, the stac client submodule output is updated. effect of freeze on the stac client submodule when bit emios_mcr[frz] is set and the module is in debug mode, the operation of the stac client submodule is not affected; that is, there is no freeze function in this submodule. table 407. stac client submodule server slot assignment time base server id tcr1 0 tcr2 2 srv3 srv2 srv1 srv0 stac bus time base stac client submodule (24-bit wide) output time slot selector bits ts[02] stac bus (submodule input) ts[00] ts[01] ts[02] time base (submodule output) ts[01] xx the srv bits are set to capture ts[01]. ts[03] ts[00] ts[03] ts[00] ts[01] system clock ts[01] stac bus (redc input) ts[00] ts[01] ts[02] 1. maximum of 16 time slots (ts n ) notes: ts[01] ts[00] tsn1 ts[02] time base (redc output) ts[01] ts[01] xx 2. the srv bits capture ts[01] configurable enhanced modular io subsystem (emios200) RM0029 716/1740 doc id 15177 rev 8 22.5.4 global clock prescaler submodule (gcp) the gcp divides the system clock to generate a clock for the cps of the channels. the main clock signal is prescaled by the value defined in the gpre[0:7] bits in the emios_mcr. the global prescaler is enabled by setting bit emios_mcr[gpren] and can be stopped at any time by clearing this bit, thereby stopping the internal counters in all the channels. in order to ensure safe working and avoid glitches the following steps must be performed whenever any update in the prescaling rate is desired: 1. write ?0? at bit emios_mcr[gpren], thus disabling global prescaler. 2. write the desired value for prescaling rate at gpre[0:7] bits in emios_mcr. 3. enable global prescaler by writing ?1? at bit emios_mcr[gpren]. the prescaler is not disabled during either freeze state or negated gtbe input. effect of freeze on the gcp when bit emios_mcr[frz] is set and the module is in debug mode, the operation of gcp submodule is not affected, that is, there is no freeze function in this submodule. 22.6 initialization/application information on resetting the emios200 the channels enter gpio input mode. 22.6.1 considerations before changing an operating mode, the uc must be programmed to gpio mode and emios_cadr[n] and emios_cbdr[n] registers must be updated with the correct values for the next operating mode. then the em ios_ccr[n] can be written with the new operating mode. if a channel is changed from one mode to another without performing this procedure, the first operation cycle of the selected time base can be random, that is, matches can occur in random time if the contents of emios_cadr[n] or emios_cbdr[n] were not updated with the correct value before the time base matches the previous contents of emios_cadr[n] or emios_cbdr[n]. when interrupts are enabled, the software must clear the flag bits before exiting the interrupt service routine. 22.6.2 application information correlated output signals can be generated by all output operation modes. bits ou[n] of the emios_oudr can be used to control the update of these output signals. in order to guarantee that the internal counters of correlated channels are incremented in the same clock cycle, the internal prescalers must be set up before enabling the global prescaler. if the internal prescalers are set after enabling the global prescaler, the internal counters may increment in the same ratio but at a different clock cycle. channel/modes initialization the following basic steps summarize basic output mode startup, assuming the channels are initially in gpio mode: RM0029 configurable enhanced modular io subsystem (emios200) doc id 15177 rev 8 717/1740 1. [global] disable global prescaler. 2. [timebase channel] disable channel prescaler. 3. [timebase channel] write initial value at internal counter. 4. [timebase channel] set a/b register. 5. [timebase channel] set channel to mcb up mode. 6. [timebase channel] set prescaler ratio. 7. [timebase channel] enable channel prescaler. 8. [output channel] disable channel prescaler. 9. [output channel] set a/b register. 10. [output channel] select timebase input through bsl[1:0] bits. reaction module (reacm) RM0029 718/1740 doc id 15177 rev 8 23 reaction module (reacm) 23.1 introduction the reaction module (reacm) is composed of 6 channels. each channel contains three outputs. the primary application of this module is in the area of solenoid control for direct injection systems, valve control in automatic transmissions and others. it is connected to the on-chip adc which monitors the current on the solenoid or valve. based on that the reaction channel generates a pwm signal that modulates the current circulating in the solenoid or valve. it is a cost effective solution due to extensive sharing of several resources among channels and parameterized register banks for adequate dimensioning of resources and functionality. 23.1.1 features the reacm features include: per-channel architecture for independent output control interface with on-chip adc for fast response times hardware connection with on-chip timer channels with channel routing capability innovative concept of shared modulation control innovative concept of dynamic timer allocation 3 outputs per channel to support different driver architectures flexibility to operate based on timing and threshold on-the-fly capture of adc result reference for fast calibration open and short circuit monitoring capability note: dma is not supported in spc564a80 devices. 23.1.2 modes of operation programing mode after a reset is applied, the reaction module is in programming mode. in this mode all channels are disabled and outputs are at logic zero. note that this state does not necessarily mean that zero is the neutral state for the channel load, so care must be taken in order to disconnect the channel from the load in this case. in the programming mode the host cpu writes all module parameters including: RM0029 reaction module (reacm) doc id 15177 rev 8 719/1740 1. modulation word data (see section 23.4.2, modulation control words bank ) 2. channel control data (see section 23.3.7, reacm channel n configuration register (reacm_chcrn) ) 3. threshold data (see section 23.3.12, reacm threshold bank register (reacm_thbk) ) 4. timer bank data (see section 23.3.10, reacm shared timer bank registers (reacm_stbk) ) 5. hold-off timer bank data (see section 23.3.11, reacm hold-off timer bank registers (reacm_hotbk) ) 6. timer router data (see section 23.3.9, reacm channel n router register (reacm_chrrn) ) 7. adc router data (see section 23.3.4, reacm threshold router register (reacm_thrr) ) the last action to perform is to enable the channel, after which the channel is able to respond to timer signals and adc data, thus able to perform modulation on the output pins. it is recommended to keep the timer signals inactive until all data to all reaction channel modules are programmed and all channels have been put in the enabled mode. low power mode coming out of reset all channels are in the disabled state. the channel may also be in low power mode depending on a parameter that configures the initial state of the mdis in the reacm module configuration register (reacm_mcr) (see figure 453 ). if reacm_mcr[mdis] = 1 the module clock may be disabled allowing for a low power state. the low power mode is controlled either by reacm_mcr[mdis] or by a global stop signal. there is no explicit clock gating implemented in hardware within the reaction module. note: low power mode must be entered only when all channels are disabled by reacm_chcrn[chen] = 00. channel modes after a channel is in enabled mode that channel is also said to be in the normal mode of operation, which means it responds to timer signals from the timer inputs connected to the reaction module and also to adc results received from the on-chip adc module. channel outputs are controlled in accordance with those inputs in order to perform an output modulation process. when performing a modulation the reaction channel is said to be in the active state . the modes a reaction channel can be in and the ability to execute a modulation related to the modes are: disabled: the channel cannot execute modulation. enabled: the channel is able to execute a modulation. it may be in the active or inactive state. ? inactive state: the channel is not executing a modulation. ? active state: the channel is executing a modulation. debug mode the reaction module debug operation is defined by bits frz and fren in the reacm module configuration register (reacm_mcr) (see figure 453 ). in debug mode all timers are halted, including the timers in the shared time bank and hold-off timers. reaction module (reacm) RM0029 720/1740 doc id 15177 rev 8 the module can enter debug mode either by software control or by the hardware debug input signal controlled by the chip logic. in both cases the reaction module only enters debug mode if enabled by bit reacm_mcr[fren]: if the fren bit and the frz bit are both is asserted the module enters debug mode. if the fren bit is asserted and a global debug signal is issued the module enters debug mode. in debug mode, the channel outputs are held at hod (high output drive), lod (low output drive), or drive off (doff) state, as determined by the current channel state. when resuming normal operation after exiting debug mode the channel output is set to doff until the next timer control rising edge occurs. the adc maximum limit detection (reacm_chsrn[maxl]) flag is the only flag that operates in debug mode. all other flags keep the state present when the module entered debug mode. note that the corresponding error flag in the reacm global error flag register (reacm_gefr) ( figure 457 ) is also set. the reacm adc sensor input register (reacm_sinr) allows direct access for write to the tag and adc result values input to the reaction module. this software control may be used for module debug purposes. please see figure 456 . 23.1.3 block diagram figure 450 shows the on-chip connections of the reaction module. the adc module is the source of data monitored from external sensors, usually voltage information, which is used by the reaction channel modulation to generate an pwm signal control signal in order to maintain the load current within a certain predefined boundary. the on-chip etpu module is commonly used as the source for controlling the activation of a reaction channel. alternatively an emios or pit module can be used to provide that control signal. RM0029 reaction module (reacm) doc id 15177 rev 8 721/1740 figure 450. reaction module system interconnection each reaction channel has three independently programmable outputs. the outputs do not have a predefined on or off state meaning that the definition of on and off depends upon the application. figure 451 illustrates the interconnection between a reaction channel and the blocks in the reaction module. the indexes next to the blocks indicate the order in which each submodule executes an action during the modulation process. a simplified sequence of these steps is described as follows: 1. a new adc result from the eqadc module is received, triggering one reaction channel. 2. the triggered reaction channel generates the modulation word address based on the data programmed in the internal configuration register. 3. a modulation word is selected by the reaction channel. 4. the selected modulation word generates the address for the threshold bank. 5. the threshold bank selected data is compared against the incoming adc result. 6. the comparison result is sent back to the channel. 7. the reaction channel executes modulation action and updates the channel output. in order to execute steps 1 through 7 the reaction module takes five module clock cycles. the reaction channel sets the outputs according to fields hod or lod provided by the selected modulation word. etpu etpu reaction module cpu register access bus (etpu channels) device pins adc side port adc sampled data reaction channels rchn_a rchn_b rchn_c system sdm (psi) can be driven by cpu timer channels reaction module (reacm) RM0029 722/1740 doc id 15177 rev 8 figure 451. channel interaction with internal submodules figure 452 shows the reaction module internal architecture. the channels are controlled by a modulation control word provided by the modulation control bank submodule. the modulation word has information about the type of modulation to be executed as well as the addresses for the threshold and timer banks. the channel stores information such as the address of the modulation word and initial values for the output pins after the channel is enabled . note that the modulation process only initiates after the channel is moved to the active state. the following sections describe this process in more detail. after the activation, the channel sets the outputs with a predefined value stored in the reacm channel n configuration register (reacm_chcrn). only after this initialization process is the channel ready to start a modulation process. note that the channel only considers an adc result as valid if it is within a window defined by the timer input, usually connected to the on-chip etpu. the reaction channel can access more than one modulation word by incrementing the internal modulation_addr field in the reacm_chcrn. the original value of this field is preserved, thus when a new modulation cycle is initiated the same modulation address value may be used. modulation control bank bank timer timer bank chn comparator timer channels eqadc side port timer bank holdoff rchn_a rchn_b rchn_c [15:0] greater or equal threshold 1 adc result adc tag reaction channel shared timer bank 2 3 4 5 6 7 RM0029 reaction module (reacm) doc id 15177 rev 8 723/1740 figure 452. reaction module block diagram ta ble 40 8 lists the spc564a74xx, spc564a80xx reaction module outputs. : timer timer bank ch0 ch1 ch2 ch5 timer bank hold-off rch0_a rch0_b rch0_c rch1_a rch1_b rch1_c rch2_a rch2_b rch2_c rch5_a rch5_b rch5_c modulation control bank word n word n+1 word n+2 address data allocate timer select timeout bank comparator threshold address 32-bit 32-bit adc router eqadc side port router info adc data tag adc tag timer router router info 32-bit ch sel 16 6 timer channels [15:0] 12-bit 16-bit 3 timers timer cnt value hold-off cnt value (psi) reaction channel reaction channel reaction channel reaction channel store adc result threshold n threshold n+1 table 408. reaction module outputs reaction channel output pin rch0_a etpu14 reaction module (reacm) RM0029 724/1740 doc id 15177 rev 8 timer channels, such as etpu channel outputs, are connected to the channel router. this submodule routes each timer channel to a reaction channel. note that one timer channel can be routed to more than one reaction channel. the modulation process starts when an adc result arrives and the time window is active. the adc router sends a trigger signal to all channels indicating that an adc result is available. the channel address resolution is based on the tag field received with the incoming adc result. after decoding the tag field the channel accesses the modulation word using the information stored in the reacm_chcrn. the threshold bank submodule stores values to be used on the comparison with incoming adc results. the address for the stored values is generated by the modulation control word bank. this address generation is actually executed in a two-step process since the modulation word is first addressed by the channel which then generates the address for the threshold bank. after having both inputs defined the comparator generates the comparison result back to the channels. the hold-off timer bank address is also stored in the modulation word. the reaction channel uses that information for the modulation process which requires the output to remain off during a certain amount of time. the hold-off counter itself is located inside each one of the channels. rch0_b etpu20 rch0_c etpu21 rch1_a etpu15 rch1_b etpu9 rch1_c etpu10 rch2_a etpu16 rch2_b emios2 rch2_c emios4 rch3_a etpu17 rch3_b emios10 rch3_c emios11 rch4_a etpu18 rch4_b etpu11 rch4_c etpu12 rch5_a etpu19 rch5_b etpu28 rch5_c etpu29 table 408. reaction module outputs (continued) reaction channel output pin RM0029 reaction module (reacm) doc id 15177 rev 8 725/1740 23.2 signal description ta ble 40 9 shows the chip-level signals for the reaction module. 23.2.1 reacm_rchn ? reacm channel (n) output pin a, b and c each reaction channel provides three outputs to be connected to device primary output pads. these outputs can be configured as necessary in order to meet application requirements. thus the active state as well as overall functionality are defined by the registers within the reaction module and the defined sequence of operation. the reset state for these outputs is zero. 23.3 memory map and register definition this section provides a detailed description of all reaction module registers accessible to the end user. 23.3.1 module memory map ta ble 41 0 presents the reaction module memory map. table 409. signal properties name function rchn_a output pin ?a? of reaction channel ?n? rchn_b output pin ?b? of reaction channel ?n? rchn_c output pin ?c? of reaction channel ?n? table 410. reaction module memory map offset from reacm base address (0xc3fc_7000) register name size in words location 0x0000 reacm module configuration register (reacm_mcr) 1 on page 23- 727 0x0004 reacm timer configuration register (reacm_tcr) 1 on page 23- 728 0x0008 reacm threshold router register (reacm_thrr) 1 on page 23- 729 0x000c reserved 0x0010 reacm adc sensor input register (reacm_sinr) 1 on page 23- 730 0x0014 ? 0x001f reserved 0x0020 reacm global error flag register (reacm_gefr) 1 on page 23- 731 0x0024 ? 0x00ff reserved reaction module (reacm) RM0029 726/1740 doc id 15177 rev 8 23.3.2 reacm module configuration register (reacm_mcr) the reacm module configuration register (reacm_mcr) contains the control bits to configure the general operation of the reaction module. 0x0100 + (n*0x10) reacm channel n configuration register (reacm_chcrn) (n = 0?5) 6 on page 23- 732 0x0100 + (n*0x10 + 0x4) reacm channel n status register (reacm_chsrn) (n = 0?5) 6 on page 23- 735 0x0100 + (n*0x10 + 0x8) reacm channel n router register (reacm_chrrn) (n = 0?5) 6 on page 23- 738 0x0100 + (n*0x10 + 0xc) reserved (n = 0?5) 0x0160 ? 0x02ff reserved 0x0300 ? 0x0308 reacm shared timer bank registers (reacm_stbk) 3 on page 23- 739 0x030c ? 0x037f reserved 0x0380 ? 0x0388 reacm hold-off timer bank registers (reacm_hotbk) 3 on page 23- 740 0x038c ? 0x03ff reserved 0x0400 ? 0x045c reacm threshold bank register (reacm_thbk) 24 on page 23- 740 0x0460 ? 0x05ff reserved 0x0600 reacm adc result maximum limit check register (reacm_adcmax) 1 on page 23- 741 0x0604 ? 0x067f reserved 0x0680 reacm modulation range pulse width register (reacm_rangepwd) 1 on page 23- 742 0x0684 ? 0x06bf reserved 0x06c0 reacm modulation minimum pulse width register (reacm_minpwd) 1 on page 23- 743 0x06c4 ? 0x06ff reserved 0x0700 ? 0x072c reacm modulation control word bank registers (reacm_mwbk) 12 on page 23- 743 0x0730 ? 0x0fff reserved table 410. reaction module memory map (continued) offset from reacm base address (0xc3fc_7000) register name size in words location RM0029 reaction module (reacm) doc id 15177 rev 8 727/1740 figure 453. reacm module configuration register (reacm_mcr) address: reacm_base (0xc3fc_7000) + 0x0000 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0 mdis frz 0 fren tpren hpren gien ovren 0000000 w ovrc reset000000000 0 000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 0 000000 w reset000000000 0 000000 table 411. reacm_mcr field descriptions field description 0 ovrc overrun detection flag clear the ovrc clears the ovr flag if write 0x1. this bit reads always as 0x0. if a set event occurs at the same time a flag clear is done, the set event has precedence over the clear thus the flag remains set. 0 no action 1 clears ovr bit 1 mdis module disable the mdis bit puts the reaction module in low power mode. communication through the slave-bus interface is ignored in this mode except writes to the reacm_mcr which are allowed, except for the frz and fren bits. the global debug signal state is not changed internally while in low power mode. 0 normal mode 1low power mode 2 frz freeze control the frz bit controls the state of the reaction module regarding debug operation. if fren bit is asserted and frz bit is also asserted the module enters debug mode. in this mode all time bases are halted and the channels outputs are controlled solely by software. see section , debug mode . this bit cannot be written if mdis bit is asserted or when the reaction module is in stopped by a device stop request. 0 normal mode 1 debug mode 3 reserved, should be cleared. 4 fren freeze enable the fren bit enables the reaction module to enter debug mode. the debug mode is controlled either by the frz bit or by a global debug signal. this bit cannot be written if mdis bit is asserted or when the reaction module is in stopped by a device stop request. 0 debug mode disabled 1 debug mode enable 5 tpren timer prescaler enable the tpren bit enables the shared timer prescaler in the reaction module. 0 prescaler disabled 1 prescaler enabled reaction module (reacm) RM0029 728/1740 doc id 15177 rev 8 23.3.3 reacm timer configuration register (reacm_tcr) the reacm timer configuration register (reacm_tcr) contains the prescaler settings to configure the operation of the reaction module holdoff timer and shared timers. it is recommended to change the value of the prescalers either when the prescalers are disabled by its control enable bits hpren and tpren in the reacm_mcr or when the counters are not being used by any channel. note that the prescalers are completely independent, thus modifying hpre does not affect tpre and modifying tpre does not affect hpre. figure 454. reacm timer configur ation register (reacm_tcr) 6 hpren hold-off prescaler enable the hpren bit enables the hold-off prescaler in the reaction module. 0 prescaler disabled 1 prescaler enabled 7 gien global interrupt enable the gien bit enables the assertion of the interrupt request to the cpu when any of the channel flags or the ovr flag are set. the channel error flag bits are: maxl, ocdf, scdf and taer. note that for the interrupt to be asserted these flag bits need also to be enabled by the corresponding enable bit defined in section 23.3.7, reacm channel n configuration register (reacm_chcrn) . 0 interrupt disabled 1 interrupt enabled the gien bit only affects the general interrupt signal, and not the individual channel interrupts. gien=0 does not inhibit the channel interrupts. 8 ovren overrun detection interrupt enable the ovren enables the ovr flag, when set, to generate a global interrupt request for the cpu. 0 interrupt disabled 1 interrupt enabled 9?31 reserved, should be cleared. table 411. reacm_mcr field descriptions (continued) field description address: reacm_base (0xc3fc_7000) + 0x0004 access: user read/write 012345678 9101112131415 r0000 hpre[11:0] w reset000000000 0 000 000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 tpre[7:0] w reset000000000 0 000 000 RM0029 reaction module (reacm) doc id 15177 rev 8 729/1740 23.3.4 reacm threshold router register (reacm_thrr) the reacm threshold router register (reacm_thrr) routes the adc result to the threshold bank. since a tag is assigned for each adc result coming from the on-chip adc module, this tag is specified in this register and used for the routing process. these adc result is written to the threshold value bank as soon as it is received by the reaction module. note that thradc0 and thradc1 tag values may also be used by the reaction channels. in this case the results are routed to both, the channel and the threshold bank. note: due to the timing in which these parallel events occur, if the channel uses the same threshold bank address in which the incoming adc result was written to, this adc result is used for the channel modulation being executed. figure 455. reacm threshold router register (reacm_thrr) table 412. reacm_tcr field descriptions field description 0?3 reserved, should be cleared. 4?15 hpre [11:0] hold-off timer prescaler the hpre[11:0] field defines the rate of the hold-off timers on each reaction channel. if its value is zero the prescaler is bypassed thus the hold-off timer operates at the module clock rate. if hpre = 0x01 the module operates at module clock divide by two and so forth up to hpre = 0xfff which defines system clock divided by 4096. 16?23 reserved, should be cleared. 24?31 tpre [7:0] timer prescaler the tpre[7:0] field defines the rate of the timers on the timer bank. if its value is zero the prescaler is bypassed thus the timer operates at the module clock rate. if tpre = 0x01 the timer operates at module clock divide by two and so forth up to tpre = 0xff which defines module clock divided by 256 as the frequency of operation for the timer. address: reacm_base (0xc3fc_7000) + 0x0008 access: user read/write 012345678 9101112131415 r000000 wren1 wren0 0 0 000000 w reset000000000 0 000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 thradc1[3:0] 0 0 0 0 thradc0[3:0] w reset000000000 0 000000 reaction module (reacm) RM0029 730/1740 doc id 15177 rev 8 23.3.5 reacm adc sensor input register (reacm_sinr) the reacm adc sensor input register (reacm_sinr) is used to monitor the adc interface (see section 23.4.6, adc interface ) and allows the software to define the adc result and tag values for the reaction module. also, adc values captured after filtering can be transferred to the reaction module by the cpu. writes to this register overwrite any value coming from the adc interface, thus it should be used when no adc conversion has the reaction module as the target. writing to this register triggers the reaction channel selected by the tag value to execute a comparison and to evaluate an eventually new value for the channel outputs. figure 456. reacm adc sensor input register (reacm_sinr) table 413. reacm_thrr field descriptions field description 0?5 reserved, should be cleared. 6 wren1 write enable bit for thradc1 the wren1 write enable bit 1 controls if the adc result having a tag matching to thradc1 field will be written into address one of the threshold bank. 1write received adc result to threshold bank address one 0do not write received adc result to threshold bank 7 wren0 write enable bit for thradc0 the wren0 write enable bit 0 controls if the adc result having a tag matching to thradc0 field will be written into address zero of the threshold bank. 1write received adc result to threshold bank address zero 0do not write received adc result to threshold bank 8?19 reserved, should be cleared. 20?23 thradc1 [3:0] adc result router value for threshold bank address one the thradc1[3:0] field controls the routing from the received adc result to the threshold bank address one. any adc result which tag matching thradc1 will be routed to threshold bank. 24?27 reserved, should be cleared. 28?31 thradc0 [3:0] adc result router for threshold bank address zero the thradc0[3:0] field controls the routing from the received adc result to the threshold bank address zero. any adc result which tag matching thradc0 will be routed to threshold bank. address: reacm_base (0xc3fc_7000) + 0x0010 access: user read/write 012345678 9101112131415 r000000 0 0 00 adc_tag[3:0] w reset000000000 0 000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r adc_result[15:0] w reset000000000 0 000000 RM0029 reaction module (reacm) doc id 15177 rev 8 731/1740 23.3.6 reacm global error flag register (reacm_gefr) the reacm global error flag register (reacm_gefr) helps the software in the resolution of error conditions signaled by the reaction channels. this allows a faster service in error handling. this register mirrors the error flag in the reacm channel n status register (reacm_chsrn). figure 457. reacm global error flag register (reacm_gefr) table 414. reacm_sinr field descriptions field description 0?11 reserved, should be cleared. 12?15 adc_tag [3:0] tag value the adc_tag[3:0] represents the tag for the adc conversion which is used by the reaction module to select the reaction channel to execute the modulation. 16?31 adc_result [15:0] adc conversion result value the adc_result[15:0] represents the value resulting from an adc conversion. this value is used for the reaction channel modulation process or for capturing by the threshold bank. address: reacm_base (0xc3fc_7000) + 0x0020 access: user read/write 012345678 9101112131415 rovr00000000 0 00 0000 w reset000000000 0 00 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 0 ef5 ef4 ef3 ef2 ef1 ef0 w reset000000000 0 00 0000 table 415. reacm_gefr field descriptions field description 0 ovr overrun detection flag the ovr flag is used to indicate that an overrun condition was detected at the adc interface. see section 23.4.6, adc interface . 1overrun detected 0overrun not detected 1?25 reserved, should be cleared. 26?31 efn error flag the efn error flag bit indicates an error condition occurred in channel n. this bit is provided for a fast channel error resolution in the reaction module. the condition could be any error indicated by maxl, ocdf, scdf, sqer, raer, or taer error flags as described in section 23.3.8, reacm channel n status register (reacm_chsrn) . the efn bit is automatically cleared if the corresponding channel flags are all cleared. reaction module (reacm) RM0029 732/1740 doc id 15177 rev 8 23.3.7 reacm channel n configuration register (reacm_chcrn) the reacm channel n configuration register (reacm_chcrn) controls the channel behavior. figure 458. reacm channel n confi guration register (reacm_chcrn) address: reacm_base (0xc3fc_7000) + 0x0100 + (n* 0x0010 + 0x0000) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r chen[1:0] swmc maxlen ocdfen scdfen taeren sqeren raeren dmaen choff 00 doff[2:0] w reset0000 0 00 0 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 00 0 bsb[2:0] 0 0 modulation _addr[5:0] w reset0000 0 00 0 00000000 table 416. reacm_chcrn field descriptions field description 0?1 chen[1:0] channel enable bits the chen[1:0] bits control the activation of the reaction channel. once changed from disabled , chen = 00, to any enabled state, the channel reads the first modulation word and initializes itself in order to be ready to execute a modulation as soon as a timer control window is detected or swmc = 1, if software modulation control is selected by chen = 11. 00 channel disabled, meaning that it does not execute any modulation even if a timer window is detected or swmc is made active. in this mode doff field in the reacm_chcr defines the state of the channel outputs. 01 channel is enabled for timer control only, meaning that as soon as a timer window is detected a modulation sequence starts. 10 reserved 11 channel enabled for software control only, meaning that as soon as swmc bit is set a modulation sequence starts. if chen is programed with 01 or 11 enabling a channel, and the etpu time window is already active (or swmc = 1), the reaction channel disregards this window and waits until the next window activation in order to start the modulation process by moving to the active state. in order to start a modulation controlled by softwa re, it is necessary to first write chen = 1 and only after that write swmc = 1. 2 swmc software modulation control bit if this bit is set, the channel initiates a modulation. it is equivalent to the assertion of an etpu channel connected to the reaction module. in order for this functionality to be used it is required that chen[1:0] = 11. 1 channel executes modulation 0 channel does not perform modulation RM0029 reaction module (reacm) doc id 15177 rev 8 733/1740 3 maxlen adc result maximum limit interrupt enable bit the maxlen enables the maxl flag, when set, to generate an interrupt request for the cpu. 1 interrupt enabled 0 interrupt disabled 4 ocdfen ocdf interrupt enable bit the ocdfen bit enables the ocdf bit to issue an interrupt request. 1 ocdf interrupt enabled 0 ocdf interrupt disabled 5 scdfen scdf interrupt enable bit the scdfen bit enables the scdf bit to issue an interrupt request. 1 scdf interrupt enabled 0 scdf interrupt disabled 6 taeren taer interrupt enable bit the taeren bit enables the taer bit to issue an interrupt request. 1 taer interrupt enabled 0 taer interrupt disabled 7 sqeren modulation word sequence error interrupt enable the sqeren bit enables the sqer flag to generate an interrupt request. 1 sqer interrupt enabled 0 sqer interrupt disabled 8 raeren resource allocation error interrupt enable the raeren bit enables the raer flag to generate an interrupt request. 1 raer interrupt enabled 0 raer interrupt disabled 9 dmaen direct memory access enable bit the dmaen bit enables a dma request by the channel when an modulation word sequence advance occurs. 1 enables channel dma request 0 disables channel dma request 10 choff output disable bit the choff bit allows disabling the output pin. doff[2:0] field is used as disable state for the channel outputs. the output pins will set to doff value if choff is asserted. note that disabling the channel through choff does not disable the channel operation, only the channel outputs are forced to doff state. 1 output disable enabled 0 output disable disabled 11?12 reserved, should be cleared. table 416. reacm_chcrn field descriptions (continued) field description reaction module (reacm) RM0029 734/1740 doc id 15177 rev 8 23.3.8 reacm channel n stat us register (reacm_chsrn) the reacm channel n status register (reacm_chsrn) provides access to the channel flags and flag clear bits. it also provides access to the current values of the channel output being driven and the modulation word being accessed by the channel. 13?15 doff[2:0] drive off control field the doff[2:0] field defines the reaction channel output disabled state. this condition is achieved either when chen = 00, or after chen activation, or when output is disabled by choff in the channel configuration register. it is possible to control the channel outputs directly through the software by writing to the doff bits. refer to table 417 . in this case the channel should be in the disabled state, chen = 00. if the doff value is changed just after the channel is enabled, it is not assured the new doff value is immediately used in the channel output. 16?20 reserved, should be cleared. 21?23 bsb[2:0] bank support bits the bsb[2:0] provides control for a banked mode operation of the reaction module. each bit in this field controls the channel outputs ch n _c, ch n _b and ch n _a respectively. when asserted the channel output implements an or with the corresponding output of the subsequent channel. 24?25 reserved, should be cleared. 26?31 modulation_addr [5:0] address for modulation control bank the modulation_addr[5:0] field has the address of the modulation word in the modulation control bank. this address is used as a base address for the first modulation word. the reaction channel can access subsequent words in the modulation control bank by incrementing the modulation address field. note that this field is not modified by the reaction channel in this process. table 416. reacm_chcrn field descriptions (continued) field description table 417. output assignment through doff doff channel output comments doff[0] chn_a doff[0] bit defines chn_a output pin value doff[1] chn_b doff[1] bit defines chn_b output pin value doff[2] chn_c doff[2] bit defines chn_c output pin value RM0029 reaction module (reacm) doc id 15177 rev 8 735/1740 figure 459. reacm channel n status register (reacm_chsrn) address: reacm_base (0xc3fc_7000) + 0x0100 + (n* 0x0010 + 0x0004) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0 0 modact maxl ocdf scdf taer sqer raer chout[2:0] 0 0 0 0 w reset0000 0 0000 0 000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 0 0 0 0 0 0 modulation_pointer[5:0] w maxlc ocdfc scdfc taerc sqerc raerc reset0000 0 0000 0 00000 table 418. reacm_chsrn field descriptions field description 0?1 reserved, should be cleared. 2 modact modulation active flag the modact flag indicates that the channel is enabled and active thus executing a modulation cycle. 1 channel is active 0 channel is not active 3 maxl adc maximum limit detection flag the maxl flag indicates that the adc result which tag is addressing this channel achieved or passed the maximum allowed limit specified in the adcmax register. this flag is set only if the channel is in the active state (see section , channel modes ). 1 adc maximum limit detected 0 normal operation 4 ocdf open circuit detection flag the ocdf flag indicates that an open circuit was detected in the channel load using the pwm monitored modulation, as described in section 23.6, monitored modulation . this flag is set only of the channel is in the active state. 1 open circuit detected 0 normal operation 5 scdf short circuit detection flag the scdf flag indicates that a short circuit was detected in the channel load using the pwm monitored modulation, as described in section 23.6, monitored modulation . this flag is set if the channel activation window signal is set (etpu channel or swmc bit). 1 short circuit detected 0 normal operation reaction module (reacm) RM0029 736/1740 doc id 15177 rev 8 6 taer timer allocation error the timer allocation error bit indicates that the channel tried to allocate a timer counter in the shared timer bank without success. this situation is an indication that the timer resources available in the module are not sufficient to execute the required functionality. this error indication is used during software development and should not occur during normal use of the module since it may result in incorrect operation. this flag is set only of the channel is in the active state. 1 error occurred during timer allocation 0 no error occurred during timer allocation. 7 sqer modulation word sequence error flag the sqer bit indicates a modulation sequence error occurred, meaning that the time window which defines a modulation cycle ended in a premature modulation phase. the correct modulation phase for the time window to close is when sm field in the modulation word indicates no advance , or sm = 00. this flag is set only of the channel is in the active state. 1 modulation sequence error occurred 0 modulation sequence error did not occur. 8 raer resource allocation error flag the raer bit indicates that a resource allocation error occurred. the possible allocation errors are: modulation control word address is out of available range (including if the modulation_pointer increments to an inexistent mcw address or wraps to 0x0), threshold value bank address is out of available range, hold-off timer bank address is out of available range, shared timer bank address is out of available range, channel input router points to an inexistent etpu channel, and when the hold-off timer is select for both modulation and sequence advance at the same time (i.e, sm = 10 and mm = 01). note that the amount of hardware resources is configuration dependent thus may vary according to module instantiations in the soc. this flag is intended to help on the debug of the reaction module during software development and can be set only if the channel is in the enabled state. 1 allocation error occurred 0 no allocation error occurred the condition that sets the raer bit must be resolved prior to clear the bit, otherwise the bit can be set again. 9?11 chout[2:0] channel output monitoring bits the chout[2:0] channel output monitoring bits provides for the software the ability to monitor the output provided by the channel. this data is not buffered thus represents the channel output at the time the cpu read access is done. chout[0] corresponds to the chn_a output, chout[1] corresponds to the chn_b output and chout[2] corresponds to the ch n _c output pin. these bits are available independent of the channel mode or state. 12?18 reserved, should be cleared. 19 maxlc adc maximum limit flag clear the maxlc clears the maxl flag if write 0x1. this bit reads always as 0x0. if a set event occurs at the same time a flag clear is done, the set event has precedence over the clear thus the flag remains set. 1 clears maxl bit 0 no action table 418. reacm_chsrn field descriptions (continued) field description RM0029 reaction module (reacm) doc id 15177 rev 8 737/1740 23.3.9 reacm channel n router register (reacm_chrrn) the reacm channel n router register (reacm_chrrn) controls the channel interconnection to external timers, such as etpu and emios and adc result data. the channels have access to any 16 timer inputs and any adc sample tag from 0 to 15. note that this architecture allows several reaction channels to point to the same timer channel or to the same adc result. 20 ocdfc open circuit detection flag clear the ocdfc clears the ocdf flag if write 0x1. this bit reads always as 0x0 1 clears ocdf bit 0 no action 21 scdfc short circuit detection flag clear the scdfc bit clears the scdf flag if write ?1?. this bit is self negated thus read always as ?0?. if a set event occurs at the same time a flag clear is done, the set event has precedence over the clear thus the flag remains set. 1 clears scdf 0 no action 22 taerc taer clear bit the taerc bit clears the taer bit if write ?1?. this bit is self-negated thus reads always as ?0?. if a set event occurs at the same time a flag clear is done, the set event has precedence over the clear thus the flag remains set. 1 clears taer 0 no action 23 sqerc modulation word sequence error flag clear the sqerc bit clears the sqer flag in the channel status register. 1 sqer flag is cleared 0 sqer flag is not cleared 24 raerc resource allocation error flag clear the raerc bit clears the raer flag in the channel status register. 1 raer flag is cleared 0 raer flag is not cleared 25 reserved, should be cleared. 26?31 modulation_ pointer[5:0] modulation bank address generated by the channel the modulation_pointer[5:0] gives to the software the information of the current address being generated by the channel to access the modulation word. note that the address increments from a base address stored in the channel, modulation_addr[5:0]. this register is not buffered thus represents the current address being generated. table 418. reacm_chsrn field descriptions (continued) field description reaction module (reacm) RM0029 738/1740 doc id 15177 rev 8 figure 460. reacm channel n router register (reacm_chrrn) address: reacm_base (0xc3fc_7000) + 0x0100 + (n* 0x0010 + 0x0008) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000 0 0000 0 00 adcr[3:0] w reset0000 0 0000 0 000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 0 00 0 0000 chir[3:0] w reset0000 0 0000 0 000000 table 419. reacm_chrrn field descriptions field description 0?11 reserved, should be cleared. 12?15 adcr[3:0] adc result router field the adcr[3:0] field selects which adc result is used by the reaction channel for the modulation. the tag[3:0] received along with the adc result is used for comparison with the adcr[3:0] field in order to define if the received result is used by the reaction channel. 16?27 reserved, should be cleared. 28?31 chir[3:0] channel input router field the chir[3:0] field selects which etpu channel is used by the reaction channel for the modulation. see table 420 for valid values. table 420. reacm_chrrn[chir] values chir[3:0] etpu a channel 0b0000 10 0b0001 11 0b0010 12 0b0011 13 0b0100 14 0b0101 15 0b0110 16 0b0111 17 0b1000 18 0b1001 19 0b1010 20 0b1011 21 RM0029 reaction module (reacm) doc id 15177 rev 8 739/1740 23.3.10 reacm shared timer bank registers (reacm_stbk) the reacm shared timer bank registers (reacm_stbk) is a set of registers which define the values used by the reaction module timer. the timer values are programmed by the host cpu during the configuration of the reaction module. modulation word accessed by the reaction channel contains the address of a specific timer value stored in the shared timer bank. by selecting a timer value the reaction channel also selects and enables a counter. when this counter reaches the selected timer value a timeout indication is generated for the reaction channel that initiated the counter. this event is used, for example, to indicate that a next modulation word should be used for the modulation. figure 461. reacm shared timer bank registers (reacm_stbk) 23.3.11 reacm hold-off timer bank registers (reacm_hotbk) the reacm hold-off timer bank registers (reacm_hotbk) is a set of registers that defines the values used by the reaction channels to measure hold-off time on certain modulation schemes. the timer values are programmed by software and addressed by the reaction channel based on the data read from a modulation word. 0b1100 to 0b1111 reserved table 420. reacm_chrrn[chir] values (continued) chir[3:0] etpu a channel address: reacm_base (0xc3fc_7000) + (from 0x0300 to 0x0308) access: user read/write 012345678 9101112131415 r000000000 0 000000 w reset000000000 0 000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r shared_timer[15:0] w reset000000000 0 000000 table 421. reacm_stbk field descriptions field description 0?15 reserved, should be cleared. 16?31 shared_timer [15:0] timer value the shared_timer[15:0] value is one element of the timer register bank. up to three timer values can be stored within the timer bank. when using the shared timer for sequence advance, the counted time (considering prescaler) must be greater than 64 clock cycles. reaction module (reacm) RM0029 740/1740 doc id 15177 rev 8 figure 462. reacm hold-off timer bank registers (reacm_hotbk) 23.3.12 reacm threshold bank register (reacm_thbk) the reacm threshold bank register (reacm_thbk) holds the value to be used for comparison against results received from the adc. based on that comparison the reaction channel decides the channel output value to be either hod or lod. figure 463. reacm threshold bank register (reacm_thbk) address: reacm_base (0xc3fc_7000) + (from 0x0380 to 0x0388) access: user read/write 012345678 9101112131415 r000000000 0 000000 w reset000000000 0 000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hold_off[11:0] w reset000000000 0 000000 table 422. reacm_hotbk field descriptions field description 0?19 reserved, should be cleared. 20?31 hold_off[11:0] hold-off timer value the hold_offt[11:0] value is one element of the hold-off timer register bank. up to three values can be stored within the hold-off timer bank. when using the hold-off timer for sequence advance, the counted time (c onsidering prescaler) must be greater than 64 clock cycles. address: reacm_base (0xc3fc_7000) + (from 0x0400 to 0x045c) access: user read/write 01234567 8 9101112131415 r000000000 0 000000 w reset000000000 0 000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r threshold_value[15:0] w reset000000000 0 000000 RM0029 reaction module (reacm) doc id 15177 rev 8 741/1740 23.3.13 reacm adc result maximum lim it check register (reacm_adcmax) the reacm adc result maximum limit check register (reacm_adcmax) holds the maximum expected value of the adc result. if a value greater than adc_max_limit is received the maxl bit in the corresponding channel status register error is asserted. figure 464. reacm adc result maximum limit check register (reacm_adcmax) 23.3.14 reacm modulation range pulse width register (reacm_rangepwd) the reacm modulation range pulse width register (reacm_rangepwd) provides the value used to check if the pwm pulse width generated during the modulation process is larger than a maximum pulse width specified by (min_pwd + range_pwd). the checking is performed by the channel logic during appropriate time intervals, see table 423. reacm_thbk field descriptions field description 0?15 reserved, should be cleared. 16?31 threshold_value [15:0] threshold value the threshold_value[15:0] unsigned value is one element of the threshold register register used for a threshold modulation. address: reacm_base (0xc3fc_7000) + (from 0x0600) access: user read/write 012345678 9101112131415 r w reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r adc_max_limit[15:0] w reset000000000 0 000000 table 424. reacm_adcmax field descriptions field description 0?15 reserved, should be cleared. 16?31 adc_max_limit[15:0] maximum limit allowed for the adc result the adc_max_limit[15:0] value indicates the maximum expected value for the adc result. the maxl bit in the corresponding channel status register is set in case a greater or equal value is received from the adc. if set to zero no limit checking is performed, thus maxl bit will not be set anyway. adc results are always considered unsigned unle ss specific note states the contrary. since adc received results are 14-bit values a two bit sign extension must be performed before any comparison is executed. reaction module (reacm) RM0029 742/1740 doc id 15177 rev 8 section 23.6, monitored modulation . this function is implemented by sharing the use of reaction channel hold-off counter, thus if the hold-off timer is used by the channel sequence mode (sm in the reacm modulation control word bank registers (reacm_mwbk)), this checking function is not active. figure 465. reacm modulation range pul se width register (reacm_rangepwd) 23.3.15 reacm modulation minimum pu lse width register (reacm_minpwd) the reacm modulation minimum pulse width register (reacm_minpwd) provides the value used to check if the pulse width generated during the pwm modulation process on the channel outputs is shorter than a minimum pulse width specified by this register. the checking is performed by using the channel internal hold-off timer during appropriate times on the channel operation when this counter is not being used for the hold-off modulation cycle. address: reacm_base (0xc3fc_7000) + (from 0x0680) access: user read/write 012345678 9101112131415 r w reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r range_pwd[11:0] w reset 00000 0 00 0000 table 425. reacm_rangepwd field descriptions field description 0?19 reserved, should be cleared. 20?31 range_pwd[11:0] range pulse width the range_pwd[11:0] field defines the maximum pulse width allowed by the channel pwm generation. the checking is performed by the channel internal hold-off timer at appropriate times in the pwm modulation process. the maximum pulse is defined as (range_pwd + min_pwd) (see section 23.3.15, reacm modulation minimum pulse width register (reacm_minpwd) for min_pwd description). if range_pwd = 0x00 then no maximum pulse width checking is performed. the range_pwd value should be calculated considering the prescaler settings used for the hold_off counter. for a programmed (range_pwd + min_pwd) value, a pulse narrower than or equal to (range_pwd + min_pwd + 1) does not set the ocdf flag. RM0029 reaction module (reacm) doc id 15177 rev 8 743/1740 figure 466. reacm modulation minimum pulse width register (reacm_minpwd) 23.3.16 reacm modulation control word bank registers (reacm_mwbk) the reacm modulation control word bank registers (reacm_mwbk) are a set of registers that controls the reaction channel modulation scheme. these registers are programmed by software and read by the reaction channels. all the information required by the reaction channels to perform a modulation is stored in these words. all channels have access to the same words thus sharing of modulation words among channels is possible in this architecture. figure 467. reacm modulation control word bank registers (reacm_mwbk) address: reacm_base (0xc3fc_7000) + (from 0x06c0) access: user read/write 012345678 9101112131415 r w reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r min_pwd[11:0] w reset000000000 0 000000 table 426. reacm_minpwd field descriptions field description 0?19 reserved, should be cleared. 20?31 min_pwd[11:0] minimum pulse width the min_pwd[11:0] field defines the minimum pulse width allowed by the channel pwm generation. the checking is performed by the channel hold-off timer. if min_pwd[11:0] = 0x00 then no checking is done even for maximum pulse width or minimum pulse width. the min_pwd value should be calculated consi dering the prescaler settings used for the hold_off counter.for a programmed min_pwd value, a pulse wider than (min_pwd + 1) does not set the scdf flag. address: reacm_base (0xc3fc_7000) + (from 0x0700 to 0x072c) access: user read/write 012345678 9101112131415 r loop ioss 0 mm[1:0] 0 sm[1:0] 0 hod[2:0] 0 lod[2:0] w reset000000000 0 00 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 threspt[5:0] stpt[3:0] 0 hdofftpt[3:0] w reset000000000 0 00 0000 reaction module (reacm) RM0029 744/1740 doc id 15177 rev 8 table 427. reacm_mwbk field descriptions field description 0 loop loop control bit the loop control bit indicates that the next modulation control word accessed by the reaction channel when a modulation word address increment event occurs should be the one indicated by the channel modulation_addr[5:0] register with no offset. 1 loop back to initial channel modulation word 0 increment to the next modulation word 1 ioss initial output state selection the ioss bit indicates the state of the channel output pin when the modulation word is just accessed by the reaction channel. this access occurs when the channel is activated by a timer input channel being asserted, by software using swmc bit in the reacm_chcr or when the modulation phase advances, e.g. due to a timer event. 1 hod[2:0] is initially used for chn_c, chn_b and chn_a respectively 0 lod[2:0] is initially used for chn_c, chn_b and chn_a respectively ioss must not be 0b0 when mm is 0b01(threshold-holdoff). 2 reserved, should be cleared. 3?4 mm[1:0] modulation mode the mm[1:0] modulation mode field indicates the type of the modulation that is executed by the channel. table 428 defines the modulation modes. ioss must not be 0b0 when mm is 0b01(threshold-holdoff). 5 reserved, should be cleared. 6?7 sm[1:0] sequencer mode the sm[1:0] field defines the event that makes the channel address the next modulation word. this event can be a timer event or a threshold level event. note that the channel does not necessarily increment the modulation word address thus the same modulation word is executed again in the new modulation sequence. table 429 defines the sequencer modes. for time-out event selections, it is required the related time be greater than 64 clock cycles 8 reserved, should be cleared. 9?11 hod[2:0] high output drive the hod[2:0] field defines the values driven on the chn_c, chn_b and chn_a channel output pins, respectively, when the channel is at on state. set hod[2:0]=lod[2:0] when using threshold- threshold modulation together with sequence advance, in order to avoid fast glitches during the sequence advance 12 reserved, should be cleared. 13?15 lod[2:0] low output drive the lod[2:0] field defines the values driven on the chn_c, chn_b and chn_a channel output pins, respectively, when the channel is at off state. set hod[2:0]=lod[2:0] when using threshold- threshold modulation together with sequence advance, in order to avoid fast glitches during the sequence advance 16 reserved, should be cleared. RM0029 reaction module (reacm) doc id 15177 rev 8 745/1740 17?22 threspt[5:0] threshold pointer the threspt[5:0] threshold pointer is the address of the threshold bank that holds values to be used for adc result comparisons in the modulation process. this pointer has the resolution for a 16-bit data stored in the register described in section 23.3.12, reacm threshold bank register (reacm_thbk) . 23?26 stpt[3:0] shared timer pointer the stpt[3:0] shared timer pointer field is the pointer for the shared timer bank. the shared timer is used as timer sequencer defining the advance of modulation words. 27 reserved, should be cleared. 28?31 hdoffpt[3:0] hold-off pointer the hdoffpt[3:0] field is the address of the hold-off timer value in the hold-off timer bank that is used in the modulation cycle. note that there are modulation sequences that do not require hold-off measurement such as threshold/threshold modulations. table 427. reacm_mwbk field descriptions (continued) field description table 428. mm[2:0] configuration: modulation modes mm[2:0] modulation type modulation description 00 threshold/threshold modulation occurs between two threshold levels defined by threspt upper level threshold pointer and threspt +1 which corresponds to a lower level threshold pointer. output on state is defined by hod and output off state is defined by lod. 01 threshold/hold-off modulation occurs between an upper level threshold defined by threspt and a hold-off time is initiated after that level is achieved which set channel outputs to an off state. 10 reserved ? 11 reserved ? table 429. sm[1:0] configuration: sequencer modes sm[1:0] event event description 00 no advance current modulation word is used, no advance is performed on any event. no timer is activated by this modulation word. 01 timer time-out advance to the next modulation word when a timer time-out event is detected. the timer is activated when the modulation word is accessed by the channel. 10 hold-off timer time-out advance to the next modulation word when a hold-off timer time- out event is detected. the hold-off timer is activated when the modulation word is accessed by the channel. 11 threshold level achieved advance to the next modulation word when a threshold level is achieved. the threshold level is defined by the threspt pointer. see section section 23.10.1, advancing modulation phase on a threshold level . reaction module (reacm) RM0029 746/1740 doc id 15177 rev 8 23.4 functional description the following sections describe the reaction module functionality. the reaction module is designed to allow a closed feedback loop control over the driver load currents. the load can be an injector for a direct injection system or an electromagnetic actuator for a robotized transmission. in both cases it is expected that a solenoid will actually be the load. the module architecture is based on shared resources submodules that can be used by all six reaction channels. please refer to figure 452 for details about the module architecture. the reaction module comprises the following internal submodules: reaction channel modulation control word bank shared timer bank hold-off bank threshold bank the following sections describe each one of these submodules and their combined operation. 23.4.1 reaction channel the reaction channel is the core of the reaction module. each channel controls three output pins and is controlled by a control finite state machine (fsm) that receives parameters to generate a modulated waveform as well as the timer control window, usually provided by etpu. the adc interface indicates to the channel that a new adc result is available. if activated by the etpu channel, the reaction channel reads the modulation word which provides addresses for the threshold value bank, shared timer bank and hold-off timer bank. the date provided by the threshold bank is compared with the incoming adc result. based on that comparison the reaction channel state machine selects the values for the output pin registers. the modulation only occurs if activated by the timer control signal, which can be generated by etpu, or can be controlled by software by writing to the swmc, software modulation control bit, in the channel configuration register. the mm and sm fields in the modulation word provide the modulation mode and sequencer mode control, respectively. figure 468 describes the internal architecture of the reaction channel and its interconnection with other submodules. RM0029 reaction module (reacm) doc id 15177 rev 8 747/1740 figure 468. reaction channel architecture simplified diagram the addresses stored in the modulation word are pointers to timers and threshold banks. hod and lod provides the 3-bit field which controls the states, high and low, respectively for the reaction channel output pins. the reaction channel fsm selects the values for the output pins as well as the load signal used to update those values. the modulation executed by the reaction channel is based on the feedback loop provided by the adc results. these results are routed to one side of a comparator while the other comparator input receives the selected threshold value from the threshold bank. the comparison result indicates for the reaction channel fsm if the output pin value should be defined either by hod or by lod. as a result a pwm is generated on the output pins. note that since there are three independent outputs the pwm signal can be generated on any output or even on several outputs at the same time. usually a pwm signal is generated in one of the outputs only, while the others outputs are used to control power supply switching, for example. three wave forms are shown at the right side of figure 468 . on the top there is control signal from etpu which defines the boundaries of the modulated waveform. in the middle there is the pwm waveform which is used to drive the power on and off at the load, thus generating the third waveform which represents the current passing through the load. 23.4.2 modulation control words bank the modulation control word provides information about the modulation type to be performed and the addresses for several address banks. figure 467 describes the reacm doff[2:0] modulation_addr[5:0] mm[1:0] sm[1:0] hod[2:0] lod[2:0] threspt[5:0] hdoffpt[3:0] holdoff timer threshold value[15:0] adc etpu initial value low selection high selection sequencing mode modulation mode fsm load sel time out compare new result trigger address address reaction channel activate/deactivate etpu window reaction pwm modulated current output pins feed back from the controlled load v t t i t v } +1 reaction module (reacm) RM0029 748/1740 doc id 15177 rev 8 modulation control word bank registers (reacm_mwbk) and figure 469 describes the interfaces of this submodule with some other submodules in the reaction module. the informations stored in the modulation word are: modulation control parameters for the reaction channel threshold value register bank address hold-off bank address shared timer bank address dma support all channels share the information stored in the modulation control word bank, which provides a size-effective implementation avoiding the duplication of information and allowing flexible implementation. the sharing of modulation control words allows several channels to execute the same modulation sequence. the modulation control is designed to be used by all reaction channels as a centralized resource. however, only one channel is able to access the modulation bank at a given time. therefore, there is a priority in the selection of the channel that will have the access granted, but note that this condition does not occur too often since adc results are provided for one channel at a time. an arbiter in the modulation control word bank selects one of the channels which are requesting access to a modulation word. the priority criteria is fixed and based on the channel number, considering channel 0 the highest priority channel. the channel selected by the arbiter receives an acknowledge signal which indicates that channel was selected and therefore can access the modulation word. note: in order to avoid an initial delay when processing a timer window start event, the channel performs a speculative read operation of the first modulation word when it is enabled (chen is configured). therefore, when the modulation cycle is triggered by the timer window start event, all needed information for the modulation is already stored inside the channel. figure 469. modulation control word bank interfaces request sel arbiter/ request[15:1] modulation addr modulation loop ioss timerpt hdoffpt threspt cpu control word bank channel reaction access granted request other channels sm mm hod lod addr for the threshold bank addr for the timer bank addr for the hold-off bank sel addr holdoff bank modulation word ch0 modulation information timer RM0029 reaction module (reacm) doc id 15177 rev 8 749/1740 23.4.3 shared timer bank the shared timer bank is an innovative concept of dynamic timer allocation. since the number of timers can be smaller than the number of channels in the reaction module, there is a possibility that all timers are allocated at a certain time. this architecture is based on the low probability of such scenario since the timer allocation is a sporadic event. the timers in the shared timer bank are usually in idle state until they are allocated by a channel. any timer can be allocated as soon as it is idle. the shared timers work in conjunction with a timer bank which stores values to be used by the timing measurement. the shared timer bank block is composed of two submodules: three 16-bit counters a bank with maximum of 16 selectable 16-bit time values if there is an attempt to allocate more than three timers then an error flag taer (see figure 459 ) is set and no timer is allocated by the requesting channel. as a general guideline the system should be dimensioned in such a way that the timer allocation is always possible. note: in case of an allocation error the channel forces doff to its output pin preventing any damage to occur to the actuator being controlled. this state will not change until bit taer is cleared. during the timer allocation the channel also provides the timerpt pointer which selects a timing value. the valued pointed by timerpt is loaded into one of the three counters which counts down until reaching zero. at this time a timeout indication is sent to the requesting channel and the timer is deallocate, moving back to idle state. in case of several timer activation requests being issued at the same time, the logic in the timer bank will prioritize giving higher priority for the channel with lower number, thus channel zero has higher priority than the others. no flags are set in the case several requests are issued simultaneously unless there are more requests than the number of available timers. in this case the taer error flag is set in the requesting channel status register. figure 470 presents a block diagram of the timer bank. reaction module (reacm) RM0029 750/1740 doc id 15177 rev 8 figure 470. shared timer bank block diagram 23.4.4 hold-off timer bank the hold-off timer bank stores time values that are used by the hold-off periods during the modulation process. this bank is shared among all channels and is addressed based on the hdoffpt pointer in the modulation control word. figure 471 shows a block diagram of this bank and its interconnections. figure 471. hold-off timer bank block diagram timer allocation timer0 channel timer timer1 timer2 timer selection channel channel[15:0] timer value pointer [3:0] shared time bank timer error indication cpu allocation request [15:0] in case no timer is available timeout indication (back to channel) set channel taerr flag ch tag ch tag ch tag 4 4 4 allocation req/ack allocation req/ack allocation req/ack 4 4 4 timeout timeout timeout sel channel logic 16 16 16 16 one line per channel one line per channel shared timer 0 shared timer 1 shared timer 2 timer bank hold-off hdoffpt hold-off time value[11:0] 12 4 (to all reaction channels) cpu modulation control hdt hdt hdt ch0 ch1 chn 16 hold-off timer reaction channels RM0029 reaction module (reacm) doc id 15177 rev 8 751/1740 the modulation control word generates the address for the hold-off timer bank which then generates the hold-off value for the channels. the channel that addressed the modulation word captures the 12-bit value storing it in the channel hold-off timer. in figure 471 channel ch0 is requesting access to the modulation word thus receiving the hold-off value from the hold-off timer bank. each reaction channel has its own internal hold-off timer. 23.4.5 threshold bank and comparator the threshold bank and comparator contains the threshold levels to be compared against the adc results. this submodule also performs the comparison between the adc result and the selected threshold value. the threshold bank can be programmed with up to 64 threshold values depending on the configuration defined during the module integration. an adc result received from the on-chip adc is connected to the adc router and then to the comparator. see figure 472 . this result stays at the comparator input until the reaction channel and modulation control word selects the address of the threshold value. the threspt field in the modulation control word submodule is used as the address for the threshold bank. note that if threshold/threshold modulation mode is used two comparisons need to be executed with two different threshold values. after the first comparison is made the threspt pointer is incremented and a new comparison is done: first comparison: comp = adc_data threshold_value[threspt] second comparison: comp = adc_data < threshold_value[threspt + 1] the comp (comparison result) is routed to the channel selected by the received tag. once having received the comparison result the channel takes the appropriate actions in order to execute the modulation mode as defined by the modulation control word. figure 472. threshold bank and comparator block diagram adc_data[15:0] threspt[5:0] comparison comparator . . . comp bank 0 31 reg write logic xbar master or etpu adc router on-chip adc modulation control result reaction channel threshold bank modulation addr comp received tag 4 chn reaction module (reacm) RM0029 752/1740 doc id 15177 rev 8 23.4.6 adc interface the adc interface connects to the eqadc module through a parallel side port also called psi. please refer to chapter 25: enhanced queued analog-to-digital converter (eqadc) for more information about this interface. the eqadc sends conversion results to the reaction module which are received by the adc interface submodule. the adc interface is capable of distinguishing between adc results, time stamps and prefill information from eqadc. only adc results with no prefill are considered by the reaction module as valid adc samples. the tag value received with the conversion result indicates which channel the result is addressed to. the adc interface is also responsible to indicate for the selected reaction channel that a new adc result is available. it is also possible to access the adc interface data through the reacm_sinr register. note: the adc interface data (adc_tag and adc_result) should not be updated until all reaction channels (with adcr = adc_tag) process the received data. the ovr flag is set in the case of an overrun condition occurs, indicating that at least one adc data was lost. input buffer overrun the ovr flag indicates than an input buffer overrun occurred. this buffer is normally written by the adc interface (psi) but can be written also by the cpu using the reacm_sinr register. the adc interface data (adc_tag and adc_result) should not be updated until all reaction channels (with adcr = adc_tag) process the received data. the ovr flag is set in the case of an overrun condition occurs, indicating that at least one adc data was lost (the input data that caused the overrun is lost). the following situations can generate an input overrun: two consecutive sample data are received from adc or from cpu. adc and cpu sending sample data at the same time (asynchronous events). input buffer is holding sample data that are being processed by some channel and a new sample is received from adc or cpu (normal mode of operation). figure 473. adc interface block diagram adc_result adc_tag adc interface control psi bus adc result for the connected to all ack comparison in the threshold bank submodule from eqadc new result received 4 connected to all channels reaction channels xbar master or etpu RM0029 reaction module (reacm) doc id 15177 rev 8 753/1740 the maximum throughput supported by the reaction module depends upon the tag of the incoming adc data. if only one reaction channel is addressed by the adc tag then the maximum supported adc data rate is one sample each five clock cycles. if two reaction channels are addressed by the same adc tag, thus having the same chrrn adcr field, and are active at the same time, the maximum supported rate is one adc data on each 10 clock cycles. in general if (n) channels share the same tag and are active at the same time the maximum supported adc data rate is 5(n) clock cycles. these limitations are related to the sharing of internal reaction module resources such as the modulation word bank. the adc conversion data should remain stable in the adc interface until it is used by all channel s which matching tag and chrrn adcr fields. note that if all active channels have differ ent chrrn adcr fields, that is, are assigned to different tags, the maximum supported adc rate is five clock cycles. if multiple channels have the same chrrn adcr field but only one is active at a time, then the maximum supported adc data rate is also five clock cycles. on-the-fly adc data acquisition the adc interface and the threshold bank can operate in a learn mode, meaning that the received adc result can be stored in the threshold bank and used for comparisons. this functionality allows the user to interactively calibrate the modulation levels or capture on- the-fly levels from the external application board for debug purposes. the reacm_thrr is used for that purpose. see figure 455 for more details about the register architecture. figure 474 describes the main connections between the adc interface and threshold bank submodules. the routing of received adc results to be stored in the threshold bank is independent from the routing of the same result to the reaction channels (see figure 460 ). thus the same adc result can be used in a comparison and stored in the threshold bank. figure 474. adc interface and thr eshold bank interconnections adc_data[15:0] comp bank reg write logic cpu adc interface on-chip adc threshold bank thrr write to threshold bank threshold router register to comparator wr_en reaction module (reacm) RM0029 754/1740 doc id 15177 rev 8 23.4.7 prescalers the prescalers provide internal system clock divided signals to be used by internal timers. the reaction module contains two prescalers: a 12-bit prescaler hpre[11:0] and an 8-bit prescaler tpre[7:0]. both are defined in the reacm timer configuration register (reacm_tcr) (see figure 454 for details). prescaler hpre[11:0] is dedicated to the hold- off timers within the reaction channels. prescaler tpre[7:0] is used by the shared timer bank counters. the hpre[11:0] and tpre[7:0] prescalers are enabled by hpren and tpren bits, respectively, in the reacm module configuration register (reacm_mcr) (see figure 453 ). note that prescalers operate in a similar way regarding their activation. once the prescaler is enabled by hpren or tpren bits in the reacm_mcr, it starts a new count sequence meaning that it is put in reset state and will generate the first prescaler tick after it reaches the programmed value defined by the hpre or tpre fields. 23.4.8 banked mode support banked mode is a reaction module hardware configuration which allows the sharing of reaction channel output pins at the device i/o level. the banked mode architecture allows the stacking of up to four reaction channels. figure 475 shows the connection between two adjacent channels, ch0 and ch1. the reacm_chcrn bsb bits are used to control the configuration of channel output logic. thus if bsb[0] in reaction channel [0] is asserted to 1 and the channel is not in the active state, ch0_a output is switched from ch[0] out[0] to ch[1] out[0]. if a channel is active, that is, executing a modulation, it takes control over its outputs independent of the bsb bits setting. the banked mode logic is extended to reaction channels ch[2] and ch[3] thus defining a group of four channels. for simplification, figure 475 shows only channels ch[0] and ch[1] logic. note: when chen = 00 for ch0 (channel disabled), the bsb bits do not influence the channel output, which is driven ch0?s doff. therefore, a banked injector driven by ch1 will have part of its controls off, even if ch1 is enabled. to use bsb of ch0 in this case, an option is to program channel ch0 with chen = 11 (channel enabled) and with swmc = 0 (modulation off). in case of using ch2 in banked mode with ch0, the intermediate channel ch1 should also be configured with chen different from 00. RM0029 reaction module (reacm) doc id 15177 rev 8 755/1740 figure 475. banked mode showing stacking of channels [0] and [1] the banked mode support hardware is implemented on groups of four channels. the groups are defined as ch[3:0] and ch[5:4]. thus ch[3] and ch[5] do not connect to the subsequent channel which are ch[4] and ch[0] respectively. 23.5 modulation modes this section describes the modulation modes provided by the reaction module. 23.5.1 threshold/threshold mode this mode is programmed by using reacm_mcwbx[mm] = 00. in this modulation mode the reaction channel tries to maintain the adc results between two threshold limits. the modulation actions are as follows: adc result [threspt]: the reaction channel turns the outputs off by loading lod[2:0] to the channel outputs. adc result < [threspt + 1]: the reaction channel turns the outputs on by loading hod[2:0] to the channel outputs. [threspt + 1] adc result < [threspt]: the reaction channel keeps the outputs unchanged. figure 476 indicates the threshold/threshold modulation mode. ch[0] (1) ch[1] bsb[0] bsb[1] bsb[2] out[0] out[1] out[2] from channel [2] och0_a och0_b och0_c och1_a och1_b och1_c active 0 1 0 1 0 1 0 1 0 1 0 1 bsb[0] bsb[1] bsb[2] out[0] out[1] out[2] active chan chan notes: 1. ch[0] should be enabled by chen to use bsb. f/f f/f f/f f/f f/f f/f ch0_a ch0_b ch0_c ch1_a ch1_b ch1_c reaction module (reacm) RM0029 756/1740 doc id 15177 rev 8 figure 476. threshold/th reshold modulation mode there can be overshoots or undershoots in the real application related to the threshold limits. this occurs due to following: 1. feedback values are periodically sampled thus can present gaps on the measured values, for example when the sample occurs the value already passed the range defined by the limits. 2. there is a delay between the sampling of feedback value and the reaction of the reaction channel. this is mainly caused by the adc conversion time and its maximum sampling frequency. 23.5.2 threshold/hold-off mode this modulation mode is programmed by using reacm_mcwbx[mm] = 01. in this mode the output pins are driven with hod[2:0] until the adc results matches or is greater than the programmed threshold. the output controls are then driven with lod[2:0] for a fixed amount of time defined by the hold-off timer. note that the upper threshold limit and the hold-off timer pointer are indicated by the modulation word in the reacm_mcr register. note: adc samples are not considered reliable in hold-off time, therefore no comparison for maxl or for output definition are performed. if these comparisons are necessary, the threshold / threshold modulation mode can be used. figure 477. threshold/hold-off modulation mode injector time upper limit lower limit feedback set output to lod set output to hod i injector time upper threshold limit feedback hold-off hold-off hold-off hold-off time time time time output is lod output is hod RM0029 reaction module (reacm) doc id 15177 rev 8 757/1740 23.5.3 limitations on the modulation process this section describes the channel limitations on the modulation process such as the width and distance between consecutive modulation pulses. minimum distance between consecutive timer control pulses the control signal generated by the external timer that controls the modulation process in a worst case scenario has a minimum distance of 64 system clock periods. this is required for the reaction channel state machine to proper re-start the modulation process and address the correct modulation word. the worst case scenario considers a reaction module with 16 channels and all channels being activated at the same time. if this minimum distance is violated the modulation on the second pulse will not be executed, meaning that the channel output will be defined by the doff field. note: no error flag is set if this violation occurs. figure 478 describes the channel behavior if the minimum time between two consecutive timer control pulses is violated. figure 478. limitation on the off modulation timing minimum timer control pulse width there is no limitation on the timer control pulse minimum width. the channel just finishes the modulation process when the pulse ends even if the modulation words did not complete the expected sequence. thus if a modulation phase is designed to have four modulation words starting from word 0, and the timer pulse ends at the second word (word 1) then the modulation process finishes at this point in time. the channel output is set to doff one clock cycle after the timer pulse ends and the flag sqer is set because the sm bit field for the second modulation word is not 00. this flag occurs to indicate that the modulation was ended before the last phase of the sequence that uses the modulation word 3 and has sm = 00. figure 479 describes the channel behavior when an early end of the timer control pulse occurs. note that the channel output is driven to doff which causes the modulation to end. note that an early end of pulse only affects the current modulation cycle. meaning that on on off etpu ch0 reaction ch0 time i time timer control modulated current on minimum distance between pulses was violated v modulation does not start channel waits for neg edge to re-enable modulation modulation occurs on the next timer pulse off on <64 >64 reaction module (reacm) RM0029 758/1740 doc id 15177 rev 8 the next modulation cycle the modulation word 0 is executed first and all subsequent words are executed in the appropriate sequence. figure 479. early end of timer control pulse note: in some applications the modulation runs continuously and the input timer control signal is not used as a modulation pulse control but only as an enabling signal. therefore, if the modulation is turned off, the reacm can issue a modulation word sequence error by setting sqer flag. in this case, this sqer flag can be ignored (masked) without prejudice. an option, if the application permits, is to disable the reacm channel (chen = 00), thus avoiding unwanted sqer error. choff behavior during modulation the choff?channel output disable bit ( figure 458 ) is intended to disable the channel immediately before a modulation cycle had ended. this is important on error conditions detected by the software, thus setting the channel outputs to a safe state defined by doff. it is important to notice that in order to reactivate the channel by setting choff = 0 does not implies that the channel outputs immediately returns to the state defined by hod and lod on the modulation word being executed. instead, the hod and lod are driven to the channel outputs only when one of the following conditions occur: a sequence advance event (timeout or threshold, depending on sm). a new sample is received (no matter if the comparison matches or not). a hold-off timeout. module initialization to execute the modulation process the reaction module must be initialized with a correct sequence. one method is described as follows: abd c e timer control signal i time time off on off modulation word 0 modulation word 1 modulation word 2 modulation word 3 early end of pulse doff modulation words 3 and 4 are not executed modulation word 2 is partially executed abd ce modulation word 0 modulation word 1 modulation word 2 modulation word 3 RM0029 reaction module (reacm) doc id 15177 rev 8 759/1740 1. make sure etpu channels are at zero, inactive state. 2. set up eqadc module. 3. program the modulation words. 4. program the threshold bank. 5. program the shared timer bank. 6. program the holdoff timer bank. 7. program timer configuration register. 8. program the module configuration register. 9. program the channel router register. 10. program the channel configuration register. 11. start etpu channels. it is important to notice that the channel activation, by setting chen = 01, should be done after all other registers have been configured and before the input timer control signals are active. violating this order may lead to errors when the modulation cycle is executed by the channel. note: if a glitch is introduced in the input timer control pulse, the channel stops to modulate and does not operate during the pulse just after the glitch. the glitch value for wrong operation ranges from 1 system clock to about 5 times the number of channels. 23.6 monitored modulation the modulation executed by the reaction channel can be monitored by measuring the width of the pwm pulses provided by the channel. if the pulse becomes too narrow it means that the load impedance is probably too low, thus indicating a possible short circuit. if the pwm pulses become too wide it may indicate an open circuit on the solenoid. the limits for narrow and wide pulses are defined by range_pwd and min_pwd registers (see figure 465 and figure 466 ). these values apply to all reaction channels. the pwm pulses are measured by the hold-off timers within the reaction channels. this is possible only during idle periods of this timer, for example from the moment a hold-off timeout occurs until the maximum threshold is reached when hod is being used for the channel output pins. during this period the hold-off counter is not used and thus it can measure pulse widths and compare them against predefined limits defined by range_pwd and min_pwd registers, as shown in figure 480 . note: consider an uncertainty of (+1) in the value min_pwd and (min_pwd + range_pwd) when calculating the pulse width limits. the hold-off prescaler contributes to this uncertainty. for a programmed min_pwd value, a pulse wider than (min_pwd+1) does not set the scdf flag. for a programmed (range_pwd + min_pwd) value, a pulse narrower than or equal to (range_pwd + min_pwd + 1) does not set the ocdf flag. reaction module (reacm) RM0029 760/1740 doc id 15177 rev 8 figure 480. fails detected by the modulation monitoring figure 481 describes in more detail an open circuit detection using the hold-off timer. note that the hold-off timer is used when the output is at the on state, which means hod is used to drive the outputs, thus hold-off functionally is not required at this moment. the hold-off timer is loaded with min_pwd and starts counting. after a time-out occurs range_pwd value is loaded and the hold-off counter starts counting again. an open circuit is detected if the timer times-out on the second range_pwd counting and the pwm pulse is still high, meaning that the outputs did not switched to lod. in this case the ocdf flag is set in the chsr, channel status register, of the corresponding channel. see figure 459 . a - normal operation b - open circuit c - short circuit wide pulse narrow pulse current cannot achieve predefined limit current passed predefined limit RM0029 reaction module (reacm) doc id 15177 rev 8 761/1740 figure 481. open circuit detection using hold-off timer figure 482 describes how the hold-off timer detects a short circuit. the hold-off timer is loaded with min_pwd value and enabled. the condition that indicates that a short circuit occurred is the hold-off timer still running and lod is loaded to the channel output pins. that means the pwm pulse are too narrow and a short circuit have occurred. in this case the scdf flag is set in the chsr, channel status register, of the corresponding channel. figure 459 . figure 482. short circuit detection using hold-off timer b - open circuit wide pulse current cannot achieve predefined limit load hdo timer with min_pwd load hdo with range_pwd hdo timeout indicating error set ocdr in the status register to indicate short circuit c - short circuit narrow pulse current passed predefined limit load hdo timer with min_pwd timeout occurred in hdo transition detected in the pwm pulse scdr bit is set in the status register an interrupt is generated if enabled reaction module (reacm) RM0029 762/1740 doc id 15177 rev 8 note: in order to define range_pwd value it is required to consider that the hold-off timer already measured min_pwd, thus actually the maximum allowed pulse width = (min_pwd + range_pwd). in other words, range_pwd = (maximum allowed pulse width ? min_pwd). if min_pwd = 0x00 or range_pwd = 0x00 no pulse width is performed. the chsr scdf flag does not set if the pulse was finished by disabling the modulation (i.e., etpu channel = 0 or swmc = 0) or by disabling the channel, chen = 00, even if it ended shorter than min_pwd. however this flag can set in some situations that really indicates a short pulse detection but it is the result of some internal condition of the reaction module. the known situations are listed below: when the shared timer error occurs (taer flag is set), a narrow pulse can be generated and scdf flag is set. when the chcr choff bit is set, a narrow pulse can be generated and scdf flag is set. the chsr ocdf flag only sets when the channel is enabled (chen not null) and the etpu channel signal or swmc is active too. however, the ocdf flag can set in some cases when the choff bit is set. in this case, this ocdf flag should be disregarded because it is a false indication of the detector. there can be a conflict of resource allocation if the hold-off timer is used as the timer for the sequencer mode sm = 10. in this case it is not possible to detected minimum or maximum pulse widths thus the monitored modulation is deactivated. which means the use of the hold-off timer in the sequence mode has precedence over the monitored modulation. this configuration is not considered an error though, since it may occur during one of the phases of a modulation cycle and return to a sequence mode where the monitored modulation is possible. thus no flags will be set to signal this conflict condition. 23.7 dma support the reaction module provides supports for one dma channel per reaction channel. the dma request signal is controlled by the dmaen bit in the channel configuration register figure 458 and by the dma bit in the modulation control word, figure 467 . if the dmaen = 1 and the dma = 1 then a dma request is issued by the reaction channel. note that the dma request is deaserted if the dma done signal is asserted even though the channel is still pointing to the same modulation control word that generated the dma request. in order for a new dma request be issued after the dma done is issued, the reaction channel must access a new modulation control word or execute a new modulation cycle controlled by the timer input signal. figure 483 shows the dma protocol executed by the reaction channel. the dma request signal is asserted when the modulation word 1 is executed by the channel. this signal remains asserted until a dma done signal is issued by the dma controller. RM0029 reaction module (reacm) doc id 15177 rev 8 763/1740 figure 483. dma req/done protocol 23.8 reset overview the reaction module is reset whenever any mcu reset occurs. in order to re-initialize the reaction channels the chen, channel enable register should be used. once disabled the channel output is set to doff state and the channel configuration can be changed safely. the disable/enable operation does not change the channel setup, thus the configuration registers remain at the state as before the channel was disabled. the modulation control word addressed by the channel after the enable bit is asserted is defined by the modulation addr field in the channel configuration register. 23.9 reaction module interrupts the reaction module issues one global interrupt signal and one interrupt signal per channel. if using the global interrupt signal the resolution of the interrupt source need to be performed by reading the global error flag register to evaluate which channel issued the interrupt. after that the channel status register need to be read to distinguish between the several interrupt sources by evaluating the flags maxl, ocdf, scdf, taer, and sqer. d ab c e d f timer control signal current in injector time time off on off ab c e modulation word 0 modulation word 1 modulation word 2 modulation word 3 modulation word 4 dma done signal time dma req signal time reaction module (reacm) RM0029 764/1740 doc id 15177 rev 8 23.9.1 interrupt sources there are several sources of interrupts that indicates a faulty condition: maxl: maximum adc result value was reached ocdf: open circuit detected which indicates an open circuit and thus a potential malfunction in the circuitry controlled by the reaction module. note that differently from the taer, this flag does not indicate a faulty condition in the channel but in the circuit outside the device. scdf: short circuit detected which indicates a short circuit was detected on the off-chip logic controlled by the reaction channel. taer: timer allocation error which indicates a required timer resource was not allocated properly thus leading to faulty operation of the reaction module. sqer: sequencer error occurred meaning that the timer input signal was deasserted in a modulation phase with sm != 00. 23.10 use cases figure 484 shows an example of the reaction module used to control an injector solenoid. note that this is a dual injector which is also called banked injector. two reaction channels are used to control this injector. the injector boost transistor on the top applies a higher voltage in order to minimize the time necessary for the injector to start injecting fuel. transistors a and b control which injector is active in the injector bank. a sensor resistor is used to feed the current flowing through the solenoid back to the on-chip adc. the current is sampled by the adc and the result is sent to the reaction module, allowing closed loop control. note: this injector bank architecture does not allow both injectors to operate at the same time since the sensor in the feedback loop is shared by both injectors. RM0029 reaction module (reacm) doc id 15177 rev 8 765/1740 figure 484. boosted banked direct injection with passive recirculation two etpu channels are used to provide timing control signals, one for ch0 and one for ch1. the on-chip adc monitors the sensor current periodically and send the digitalized results to the reaction module. in a banked configuration as shown in this example one adc channel is used to monitor both injectors current. note that only one channel is active at a given time since the etpu time windows are not active at the same time for both reaction channels. please see figure 485 for more details. vboost vbatt boost ctrl inj b top inj a top injector a injector b inj b bot inj a bot feedback to the on-chip adc current monitor resistor reaction module reaction module (reacm) RM0029 766/1740 doc id 15177 rev 8 figure 485. etpu ch10/1 controlling reaction ch0/1 there are several possible configurations for a banked mode application. the objective on those configurations is to share hardware resources such as reaction module channels, adc monitor inputs and mcu pins, among others related to the injector driver which is not covered in detail in this document. figure 486 shows a more detailed diagram of the interconnection between the injector bank and the reaction module. two reaction channels are used in this application. ch0 is used to control injector a and ch1 is used to control injector b. however, the vboost/vbatt selection is controlled by ch0 ch0_a output only since when vboost driver is switched off vbatt power source is applied to the injectors by the direct bias of the diode connecting vbatt to the injector bank. time on off etpu ch0 etpu ch1 reaction ch0 reaction ch1 v time v time i i time time control time control modulated current modulated current RM0029 reaction module (reacm) doc id 15177 rev 8 767/1740 figure 486. system level connection in a banked configuration it is important to notice that even if two reaction channels control different injectors they can share the data stored in the modulation word control. in this case both channels should vboost vbatt injector a injector b boost circuit timer channel router modulation word control adc interface result bank ch0 ch1 ch2 ch5 comparator ch0_a ch0_b ch0_c ch1_a ch1_b ch1_c ch2_a ch2_b ch2_c ch5_a ch5_b ch5_c eqadc etpu ch1 ch2 reaction module sensor etpu time windows signals mcu bank reaction module (reacm) RM0029 768/1740 doc id 15177 rev 8 execute the same type of modulation and use the same threshold values. note also that the data stored in the threshold bank in this case is also shared between these channels. this is an important feature of the reaction module architecture since it allows the sharing of resources and therefore provides savings in size without compromising the module functionality. figure 487 shows an example of the required current levels through injector a and b. in order to generate this waveform, the reaction module uses one modulation control word for each one of the five phases of the waveform from a through f. in this example the module should be configured in the following way: 1. set the reacm_chrr0 chir[3:0] = 0x0, thus routing etpu chan nel 0 to reaction channel 0 2. set the reacm_chrr1 chir[3:0] = 0x1, thus routing etpu chan nel 1 to reaction channel 1 3. set the reacm_chrr0 adcr[3:0] = 0x0, th us routing adc tag 0 to reaction channel 0 4. set the reacm_chrr1 adcr[3:0] = 0x0, th us routing adc tag 0 to reaction channel 1 5. program modulation word control bank according to figure 488 6. program shared timer bank reacm_stbk for addresses from 0 through 3 with timing intervals related to the duration of phases a,b,c and d respectively. 7. program appropriate values in the threshold bank. since threshold-threshold modulation is to be used in this example, four pairs of values should be provided for phases a,b,c and d respectively. each pair corresponds to one address of the reacm_thbk starting at address 0x0400. 8. program configuration registers for bot h channels, reacm_chcr0/1. the parameters are doff[2:0] which defines the off state of the channel outputs and the modulation_addr = 0x0, which defines the address of the modulation control word. it is assumed that the modulation word zero is the first word to be accessed by both channels. since four modulation words will be used the addresses will be incremented by the reaction channel as needed, thus only the address for the first word is required. note that modulaton_addr = 0x0 points to the first modulation word in the modulation word bank. 9. program the prescalers hpre and tpre in the reacm_tcr register. also enable the prescalers by setting the tpren and hpren bits in the reacm_mcr register. 10. enable channels ch0 and ch1 to start the modulation sequence by programing field chen = 01 on reacm_chcr1/0 registers. at this time the reaction channel ch0 accesses the modulation control word zero and switches to on state as defined by the data stored hod[2:0] field. up to this point any activity in the etpu channel or income adc result is ignored by the reaction module. after chen field is programed, the reaction channels wait until a timer window is initiated by etpu for the modulation process to start. RM0029 reaction module (reacm) doc id 15177 rev 8 769/1740 figure 487. modulation phases the current through the injectors are initially zero since the reaction channel output is in the off state as configured by the doff[2:0] field. the etpu timer window is at the off state as well. the modulation starts when the etpu channel time window switches to on state. modulation phase a starts at this time as described in figure 487 . the modulation word 0 is used. in this application this phase corresponds to the boosted peak phase . this process allows the fuel injection to start sooner because of the sharp edge of the current which is important for a precise control of the fuel to be injected. phase a is the setup to execute a threshold-threshold modulation but note that only i0 value is used since the phase advances when a certain current is achieved. the following is a description of the bit fields in the modulation word in order to execute the modulation described in phase a : loop = 0 the initial value should be hod (ioss = 1) threshold-threshold modulation mode is obtained with mm = 00 this phase ends when the threshold value i0 is achieved (sm = 11) necessary to have hod = 111 for boosted operation and sensor active, lod setting is not important in this case since it is not used i0 is read from threshold bank by using threspt = 0x0 that points to address 0 of this bank i1 is read from threshold bank by using (threspt + 1) = 0x1 hold-off timer is not used, therefore hdoffpt can have any value (x) at point b, phase b is initiated by the threshold being achieved from phase a . ch0 increments the modulation word address to modulation_addr = 0x1 and the second c ab c e d timer control signal current in injector time time off on off ab d modulation word 0 modulation word 1 modulation word 2 modulation word 3 i0 i3 i2 i5 i4 etpu reaction module (reacm) RM0029 770/1740 doc id 15177 rev 8 modulation word is read by the channel. as a result of the second modulation word decoding the vboost voltage is disabled causing a peak modulation with vbatt . the phase is called the peak vbatt phase . for phase b a threshold-threshold modulation is used with levels i2 and i3 during a period defined by tb . please see figure 488 . a timeout event is received from the shared timer submodule and a new modulation word is read. phase c corresponds to the recirculation phase . energy from the injector is transferred back to the boost circuitry. in this phase the current can not be measured because there is no current flowing through the sensor resistor. a threshold-threshold modulation mode is used. the shared timer is started at the beginning of this phase and td delay is measured. the channel outputs are kept in the off state. when the shared timer times out after td delay the modulation word address is incremented, modulation_addr = 0x4 and the hold phase is initiated. this phase is typically longer compared to the other phases and defines the amount of fuel that will be injected. threshold-threshold modulation mode is used between levels i4 and i5 and vbatt is selected as the power supply. the phase ends based on the etpu time window switching to off at point e . at this time the channel outputs are set to off and the channel points to modulation_addr = 0x0 which is the address of the first modulation word. note that this address is not necessarily 0x0. this modulation process is executed by a sequence of modulation words as described in figure 488 . 23.10.1 advancing modulation phase on a threshold level the modulation phase may be set to advance when a specific threshold value is reached. the use case for this scenario is described in figure 489 . this functionality is used to assure a specific current level was achieved before the reaction channel advances to the next modulation phase, thus making sure that the solenoid had the fastest opening speed. figure 488. modulation words for injector application modulation control words reacm_mcw, see figure 469 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 fields l i mm sm hod lod threshpt stpt hdoffpt phasea 0 1 00 11 111 101 000010 (i0) 000011 (i1) 0001 (tb) x phase b 0 0 00 01 011 001 000010 (i2) 000011 (i3) 0010 (tc) x phase c 0 0 00 01 000 000 x (1) 0011 (td) x phase d 0 0 00 00 011 001 000100 (i4) 000101 (i5) x x 1. any value RM0029 reaction module (reacm) doc id 15177 rev 8 771/1740 figure 489. advancing modulation phase on a threshold level in the example shown in figure 489 the modulation word 0 has the field sm = 11 meaning that it should advance if the adc comparator, which compares adc results and threshold values, is true. this means that the adc result is greater or equal to the threshold value pointed by threspt modulation word 0 field. the advance from phase a to phase b in figure 489 is described as follows: initially at time a the reaction channel output is loaded with hod[2:0] as indicated by ioss value, both fields of modulation word 0. if adc result [threspt] the reaction channel turns the outputs off by loading lod[2:0] to the channel outputs and advance to the next modulation cycle at time b . note: the advance on threshold, sm = 11, is intended to be used with ioss = 1, thus the advance occurs when the level from the adc is greater or equal to the value pointed by threspt. ioss = 0 is a reserved value for this bit in this configuration and should not be used. 23.10.2 controlling the loop function the loop field in the modulation word controls the sequencing of modulation words to be executed by the channel. if loop = 1 and a phase is ended the next modulation word address returns to the initial modulation address programmed in the channel when the cycle was initiated. in this case a loop in the modulation bank is created. this loop ends when the cycle ends. d a b ce d f timer control signal current in injector time time off on off a b ce modulation word 0 modulation word 1 modulation word 2 modulation word 3 modulation word 4 i3 i2 i5 i4 etpu i0 reaction module (reacm) RM0029 772/1740 doc id 15177 rev 8 figure 490 shows the sequence of modulation words within a modulation cycle if loop function is used. note that an alternate modulated waveform is generated using only two modulation words, in this case modulation word 0 and modulation word 1. figure 490. loop function used within a modulation cycle 23.10.3 banked mode figure 491 describes the interconnection of four channels controlling two injector banks. note that two output pins are not connected since the boost control is shared between channels [0] and [1] and channels [2] and [3]. figure 491. four channels controlling two injector banks in banked mode phase a phase b phase c phase d phase e modulation cycle loop = 0 loop = 1 loop = 0 loop = 1 loop = 0 modulation word 0 modulation word 1 modulation word 0 modulation word 1 modulation word 0 vboost vbatt injector a injector b boost circuit ch0 ch0_a ch0_b ch0_c sensor vboost vbatt injector c injector d sensor banked logic ch1 ch1_a ch1_b ch1_c banked logic ch2 ch2_a ch2_b ch2_c banked logic ch3 ch3_a ch3_b ch3_c banked logic RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 773/1740 24 enhanced time processing unit (etpu2) 24.1 information specific to this device this section presents device-specific parameterization and customization information not specifically referenced in the remainder of this chapter. 24.1.1 device-specific features single engine, 32 channel scm size: 14 kb, no ecc support sdm size: 3 kb, no ecc support nexus class 1 support channels 24 to 29 input sources are selected via siu imux (see section 16.6.22: imux select register 8 (siu_isel8) ) channel outputs can be serialized through via onboard dspi channel outputs 26 to 31 can be used to trigger the eqadc tcrclk and channel 0 are connected together internally on the 176-pin lqfp package 24.2 introduction etpu is an intelligent, semi-autonomous co-processor designed for timing control. operating in parallel with the host cpu, the etpu processes instructions, real-time input events, performs output waveform generation, and accesses shared data without host intervention. consequently, for each timer event, the host cpu setup and service times are minimized or eliminated. high-level assembler, compiler and documentation allows customers to develop their own functions on the etpu. etpu is an enhanced version of the tpu module. although there is no compatibility at microcode level, etpu maintains several features of older tpu versions, making it easy to port older applications, at the same time adding several features listed in section , etpu enhancements over tpu3 . this document also includes the new features belonging to the version of the etpu known as etpu2. the new features are summarized in section , etpu2 enhancements over etpu . etpu architecture aims at high resolution timing capabilities. from a system perspective, high resolution timing is limited by host cpu overhead required for servicing timing tasks such as period measurement, pulse measurement, pulse width modulated waveform generation, etc. on the etpu, high resolution timing is achieved by three main capabilities: reduced latency: pin actions are immediate. reduce or eliminate host interrupt service time. double action channel capability reducing the channel request rate. etpu provides higher resolution than the host cpu can achieve and creates no host overhead for servicing timing tasks. enhanced time processing unit (etpu2) RM0029 774/1740 doc id 15177 rev 8 latency is the interval from occurrence of an event to the start of event servicing. etpu can service its own events without interrupting the host. there are two types of timing events: input pin transition selected time base match, that is, a selected time base counter reached or exceeded a preprogrammed value service time is the time spent servicing an event. in general, in microcontrollers the service time is constrained because the instruction set is not optimized for time function synthesis. the etpu instruction set is optimized, so that time functions can be implemented with much fewer instructions than the host cpu. instructions execute faster, service time is reduced and program memory compacted. instructions executed by the etpu are connected directly to the etpu timing hardware and allow parallelism of hardware related actions. 24.2.1 overview figure 492 shows a top-level etpu block diagram. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 775/1740 figure 492. etpu block diagram (single-engine) the etpu engine is responsible for processing input pin transitions and output pin waveform generation based on the time bases . the etpu engine has its own microprocessor and dedicated hardware for processing signals on i/o pins and can also interface with external time bases through the stac bus. the etpu engine cpu, hereafter called the microengine , fetches microinstructions from a shared code memory (scm) . shared parameter ram ( spram)? holds etpu application parameters and work data. it is accessed by host and the microengine. bus interface unit (biu) ?allows host to access etpu registers, scm and spram. etpu engine 1 p. ram shared code memory biu registers scm pins host cpu debug if slave bus, global signals, interrupt signals, dma interface signals pad-interface signals stac signals enhanced time processing unit (etpu2) RM0029 776/1740 doc id 15177 rev 8 each i/o signal pair is associated with a dedicated channel , which provides hardware for input signal processing and output signal generation, in relationship with selected time bases. the etpu, as a microprocessed subsystem, works much like a typical real-time system: it runs microengine code from instruction memory (scm) to handle specific events, accessing data memory (spram) for parameters, work data and application state info; events may originate from i/o channels (due to pin transitions and/or time base matches), host cpu requests or inter-channel requests; events that call for local etpu processing activate the microengine by issuing a service request . the service request microcode may set an interrupt to the host cpu. i/o channel events cannot directly interrupt the host cpu. each channel is associated with a function , which defines its behavior: the function is a software entity consisting, within the etpu, of a set of microengine routines that attend to service requests. the function routines are also responsible for channel configuration. function routines reside in scm, which may contain several functions. a function may be assigned to several channels, but a channel can be associated with just one function at a given moment. the association between functions and channels is defined by host cpu, and is explained in detail in section 24.5.1, functions and threads . etpu hardware supplies resource sharing features that support concurrency: a hardware scheduler dispatches the service request microengine routines based on a set of priorities defined by the host cpu. each channel has its associated priority; a service request routine cannot be interrupted until it ends. this sequence of uninterrupted instruction execution is called a thread . channel-specific context (registers and flags) is automatically switched between the end of a thread and the beginning of the next one. spram arbitration, a dual-parameter coherency controller and semaphores can be used to ensure coherent access to etpu data shared by both etpu engines and host cpu. etpu engine the etpu engine consists of two 24-bit time bases, 32 independent timer channels, a task scheduler, a microengine, and a host interface and 32-bit shared parameter ram (spram). in dual-engine implementations of the etpu, spram is used for both etpu engine?s data storage and for passing information between the etpu engines and the host cpu. figure 493 shows the block diagram for the etpu engine. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 777/1740 figure 493. etpu engine block diagram etpu engines 1 and 2 are sometimes called etpu 1 and etpu 2 throughout this document. time bases two 24-bit counters tcr1 and tcr2 provide reference time bases for all match and input capture events. prescalers for both time bases are controlled by the host cpu through bit fields in the etpu engine configuration registers. the etpu is able to export/import time to/from tcr1 or tcr2 in accordance to the red line bus specification. the clock for each of tcr1 and tcr2 clock can be independently derived from the system clock or from an external input via the tcrclk clock pin. in addition, the tcr2 timebase can be derived from special angle-clock hardware which enables implementing angle-based functions. this feature is added to support advanced angle based engine control applications. for further details refer to section 24.5.6, time bases . tcr1 tcr2/ microengine code ipi host interface channel control time base configuration engine configuration scheduler control and data control timer channels channel 0 channel 1 channel 31 channel control tcrclk pin mdu angle count service requests red line interface red line (scm) parameter ram shared (spram) shared memory fetch and decode execution data code darkblue line unit debug interface to ndedi control and data ipi indigo line ipi skyblue, green ipi purple line (pins) lines enhanced time processing unit (etpu2) RM0029 778/1740 doc id 15177 rev 8 etpu timer channels the etpu engine has 32 independent channels, each corresponding to an input/output signal pair. the channels time resolution is 24 bits, and are all identical. each channel consists of logic which supports two events and output controls. the event logic contains two 24-bit capture registers, two 24-bit match registers, greater-equal and equal-only comparators. supporting two events enables many combinations of double- action functions (for example the channel can handle two events with a single microcode service). the channel configuration can be changed by the microengine on the fly. each channel can perform double capture, double match and other capture-match combinations. channel modes available can do ordered or unordered match. some modes are also provided that can block one match by the occurrence of the other. service request can be generated on one or both of the match events. input signal can be separated from output signal in each channel. they can, optionally, be combined in a single i/o pin driver. an output buffer enable signal, controlled by microcode, is provided for this case. digital filters are provided for the input signals, with distinct filtering modes available. each channel can use any time base or angle counter for either match or capture operation. for example, a match on tcr1 can capture the value of tcr2. the channels can request service from the microengine due to recognized pin transitions (input events) or timebase matches. the etpu channels also support the basic single-action operations found on tpu3 functionality with the exception that time resolution is 24 bits. channel configuration combinations: single input capture, no match (tpu3 functionality). single input capture with single match timeout (tpu3 functionality). single input capture with double match timeout with several double match submodes. double input capture with single or double match timeout with several double match submodes. single output match (tpu3 functionality). double output match with several double match submodes. input-dependent output generation. the double match functionality has various combinations for generation of service request and determining pin actions. for more details refer to section 24.5.5, enhanced channels . in addition to the predefined channel configurations above, the user can also program its own channel configuration, defining how input captures, matches and service-requests are related. host interface the host interface allows the host cpu to control the operation of the etpu. the host cpu must initialize the etpu by writing to the appropriate host interface registers to assign a function and priority to each channel. in addition, the host writes to the host service request and channel configuration registers to further define function operation for each initialized channel. refer to section 24.5.2, host interface for a detailed description. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 779/1740 when the scm is implemented by ram, the host must first initialize it with the proper microcode program prior to enabling any etpu function, and then enable etpu access (which also disables host access). shared parameter ram (spram) the spram works as data ram which can be accessed by the host cpu and up to two etpu engines. this memory is used for information transfer between the host cpu and the etpu, as data storage for the etpu microcode program or for communication between the two etpu engines. spram width is 32 bits, and is accessible by the host as byte, 16-bit or 32-bit wide. etpu can access it as full 32 bits, lower 24 bits or upper byte (8-bit). the host can also access the spram space mirrored in other area with parameter signal extension (pse). parameter signal extension accesses differ from the usual host accesses to the original spram area as follows: writes are effective only to the lower 3 bytes of a word: the word?s most significant byte is kept unaltered in spram. reads return the lower 3 bytes of a word sign-extended to 32 bits, i.e.: the most significant bit of the word s 2nd most significant byte is copied in all 8 bits of the most significant read byte. each etpu channel can be associated with a variable number of parameters located in the spram, according to its selected function. in addition, the spram can be fully shared between two etpu engines, enabling direct communication between them. high flexibility of the spram utilization is achieved as follows: each channel has a programmable base address pointing to the address of its first parameter with two parameter granularity. this way the spram can be partitioned according to the actual function needs. the microcode can access the first 128 parameters of the selected channel in channel relative access mode. each engine can access all the spram address space in indirect addressing mode. blocks of data are easily transferred using stack operation. absolute addressing mode can access the first 256 parameters (tpu3 functionality), implementing a shared pool of parameters holding global variables. in the host address space each parameter occupies four bytes. etpu usage of the upper byte is achieved by having a 32-bit p register which can access the upper byte, the lower 24 bits or all the 32 bits. the microcode can switch between access sizes at any time. each function may require a different number of parameters. during the etpu initialization the host has to program channel base addresses, allocating proper parameters for each channel according to its selected function. scheduler out of reset, all channels are disabled. the host cpu makes a channel active by assigning it one of three priorities: high, middle, or low. the scheduler determines the order in which channels are serviced based on channel number and assigned priority. the priority mechanism, implemented in hardware, ensures that all requesting channels are serviced. for additional details refer to section 24.5.3, scheduler . enhanced time processing unit (etpu2) RM0029 780/1740 doc id 15177 rev 8 microengine etpu microengine is a simple vliw implementation that performs each instruction in a microcycle of two system clocks, while prefetching the next instruction through an instruction pipeline. instruction execution time is constant unless it gets wait states from the spram arbitration. two etpu engines share code memory without having any performance degradation by interleaving their accesses (the shared code memory has one-clock access time). instruction width is 32 bits. the microengine instruction set provides basic arithmetic and logic operations, flow control (jumps and subroutine calls), spram access, and channel configuration and control. the instruction formats are defined in such a way that allow particular combinations of two or three of these operations with unconflicting resources to be executed in parallel in the same microcycle. microengine has also an independent multiply/divide/mac unit that performs these complex operations in parallel with other microengine instructions. channel functionality is tightly integrated to the instruction set through channel control operations and conditional branch operations, which support jumps/calls on channel- specific conditions. this allows quick and terse channel configuration and control code, contributing to reduced service time. detailed description can be found in section 24.5.8, microengine . single vs. dual etpu engine system an etpu implementation can include one or two etpu engines. the number is engines is specific to the microcontroller design and cannot be changed. note: the spc564a74xx, spc564a80xx etpu has one etpu2 engine. on devices with two etpu engines, the etpu parameter ram (spram), code memory (scm) and bus interface unit (biu) are shared by both engines, enabling processor core- to-etpu communication and etpu engine-to-engine communication. in dual-engine etpus the shared biu includes coherency logic which supports dual- parameter (8 bytes) coherency in transfers between the processor core and etpu, using a temporary parameter area within the spram. more details on this can be found on section 24.5.4, parameter sharing and coherency . 24.2.2 features etpu feature summary the etpu includes these distinctive features: up to 32 channels per etpu engine?each channel is associated with an i/o signal pair. ? enhanced input digital filters on the input pins for improved noise immunity. the etpu digital filter can use 2 samples, 3 samples or work in continuous mode. ? identical, orthogonal channels, except for channel 0: each channel can perform any time function. each time function can be assigned to more than one channel at a given time, so each signal can have any functionality. channel 0 has the same RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 781/1740 capabilities of the others, but can also work with special angle counter logic (see below). ? link service request allows activation of a channel function by request of another channel, even between etpu engines. ? host service request allows activation of a channel function by host cpu request ? each channel has an event mechanism which supports single and double action functionality in various combinations. it includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and equal-only comparators. 2 independent 24-bit time bases for channel synchronization: ? first time base clocked by system clock with programmable prescaler division from 1 to 512 (in steps of 2), or by output of second time base prescaler. ? first time base can also be clocked by external signal with programmable prescaler division of 1 to 256. ? second time base clocked by external signal with programmable prescaler division from 1 to 64. ? second time base external clock source can be replaced by system clock divided by 8. ? both time bases can be exported or imported via shared time and counter) bus. ? second time base counter can work as an angle counter, enabling angle based applications to match angle instead of time. ? second time base can also be used as a pulse accumulator gated by external signal. event-triggered vliw processor (microengine): ? 2 stage pipeline implementation (fetch and execution), with separate instruction memory - scm - and data memory - spram (harvard architecture) ? fixed-length instruction execution in two system clock microcycle ? interleaved scm access in dual etpu engine avoids contention in time for instruction memory ? scm address space of up to 16k positions (64 kbytes) ? spram with interleaved access in dual etpu engine avoids contention for data memory ? spram address space of up to 8 kbytes (both engines). ? instruction set with embedded channel support, including specialized channel control subinstructions and conditional branching on channel-specific flags. ? channel-oriented addressing: channel-bound address mode with host configured channel base address allows channel data isolation, independent of microengine application code. ? channel-bound data address space of up to 128 32-bit parameters (512 bytes) ? global parameter address mode allows access to common channel data of up to 256 32-bit parameters (1024 bytes) ? support for indirect and stacked data access schemes. ? parallel execution of: data access, alu, channel control and flow control subinstructions in selected combinations. ? 32-bit microengine registers and 24-bit resolution alu, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte enhanced time processing unit (etpu2) RM0029 782/1740 doc id 15177 rev 8 operands; single-bit manipulation, shift operations, sign extension and conditional execution. ? additional 24-bit multiply/mac/divide unit which supports all signed/unsigned multiply/mac combinations, and unsigned 24-bit divide. the mac/divide unit works in parallel with the regular microcode commands. resource sharing features support channel sharing of channel registers, memory and microengine time: ? hardware scheduler works as a ?task management? unit, dispatching event service routines by predefined, host-configured priority. ? automatic channel context switch when a ?task switch? occurs, i.e., one function thread ends and another begins to service a request from other channel: channel-specific registers, flags and parameter base address are automatically loaded for the next serviced channel. ? individual channel priority setting in 3 levels: high, middle and low. ? scheduler priority scheme allows calculation of worst-case latency for event servicing and ensures servicing all channels by preventing permanent blockage. ? spram shared between host cpu and both etpu engines, supporting communication either between channels and host or inter-channel. ? hardware implementation of 4 semaphores supports resource sharing between both etpu engines. ? hardware semaphores directly supported by the microengine instruction set. ? dual-parameter coherency hardware support allows atomic (to host) access to 2 parameters by microengine(s) in back-to-back accesses. ? coherent dual-parameter controller allows atomic (to microengines) accesses to 2 parameters by the host. test and development support features: ? nexus class 3 debug support (optional, associated with the etpu-nexus block ndedi). ? software breakpoints. ? debug interface supporting single-step execution, forced microinstruction execution, hardware breakpoints and watchpoints on several conditions. ? scm (code memory) continuous signature-check built-in self test (misc, or multiple input signature calculator), runs concurrently with etpu normal operation. etpu enhancements over tpu3 32 orthogonal channels with enhanced functionality. full support for double action with double match and double transition submode combinations. input and output features separated in channel logic and microinstructions, allowing input and output signals to be processed separately or combined. increased time resolution and execution unit to 24 bits increased linear code memory, shared by two etpu engines, configurable up to 16k positions (64 kbytes) increased parameter ram address range (8 kbytes each engine) and width (32 bits per parameter). the parameter ram can be dynamically allocated to support variable RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 783/1740 number of parameters for each channel. each channel can have access to at least 256 parameters. the parameter ram is fully shared by two etpu engines (spram), supporting direct inter-engine communication with the help of hardware semaphores. enhanced arithmetic operations, including add/subtract with carry, absolute value, multiple shift and rotate, conditional execution with variable operand widths enhanced logic operations, including bitwise operations (and, or, xor) and bit manipulation, with conditional execution. support for read-modify-write of any bit in the spram. hardware for multiply/mac/divide, running in parallel to execution of other operations. the 24-bit divide result is available after 13 other unrelated instructions. multiplication supports any data width of both operands (8, 16 or 24 bits), signed or unsigned. a 24x24 multiply/mac result is available after four other unrelated instructions. a 24x8 multiply/mac result is available after one other unrelated instruction. supports export/import of time bases from other sources through the real time bus (stac - shared time and counter bus). this internal bus is used for sharing real time data between multiple peripherals. contains angle clock hardware, supported by microcode, which can provide a 24-bit angle bus instead of time bus. this feature enables the etpu to run angle based engine control applications. more interrupt types. each etpu channel can generate a data transfer request interrupt, in addition to regular interrupts, and one global exception interrupt. data transfer requests can be used either as interrupt sources or dma requests. this feature takes advantage of dma peripherals which offload the host. interrupt overflow status is also provided. improved visibility to the host (pin states, time bases, serviced channel) an edge case of priority inversion on tpu3 scheduler was resolved. supports channel link requests between etpu engines enhanced time processing unit (etpu2) RM0029 784/1740 doc id 15177 rev 8 etpu2 enhancements over etpu tcr1, channel logic and digital filters (both channel and tcrclk) now have an option to run at divisions of full system clock speed, besides system clock / 2. channels support unordered transitions: transition b can now be detected before transition a. related to this enhancement, tdla and tdlb can now be independently negated by microcode. added a new user programmable channel mode: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode. microinstructions now provide an option to issue interrupt and data transfer requests selected by chan. they can also be requested simultaneously at the same instruction. channel flags 0 and 1 can now be tested for branching, besides selecting the entry point. channel digital filters can be bypassed. scheduler priority-passing mechanism can now be disabled. new watchdog mechanism kills threads over a programmable timeout. new counter allows microengine load information collection for performance analysis channels 1 and 2 (besides channel 0) can now be selected to control the eac. timebase prescalers are now reset when the gtbe input is negated, guaranteeing synchronization with emios in all cases. new misc flag indicates when an scm signature calculation round is completed. this allows measuring of the average misc scan period in a real application situation. new channel tccea flag allows continuous capture even after tdla is set, making it fully compatible with tpu behavior. new branch condition prss tells the pin state at the time when a channel (match or transition) service request occurred. mrlea/b can now be negated independently by microcode. new engine relative address mode allows a function to access sdm address space common to one engine, but distinct between engines. error correction support for code (scm) and data (sdm) memories (available on selected mcus). all changes above are upward compatible with the classic etpu, so that legacy object code (both host and microcode) runs on etpu+ and etpu2 without modification. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 785/1740 24.2.3 modes of operation the etpu2 is capable of working in the following modes: user configuration mode user has the ability to program the etpu cores with user time functions, having access to the shared code memory (scm). user mode user does not access the etpu shared code memory: ? use of predefined etpu functions ? no need for etpu core programming ability debug mode user debugs etpu code, accessing special trace/debug features via nexus interface: ? hardware breakpoint/watchpoint setting ? access to internal registers ? single-step execution ? forced instruction execution ? software breakpoint insertion and removal. module disable mode etpu engine clocks are stopped through a register write to etpu_ecr bit mdis, saving power. input sampling stops. etpu engines can be in module disable mode independently. module disable mode stops only the engine clock, so that the shared biu, and global channel registers can be accessed, and interrupts and dmas can be cleared and enabled/disabled. an engine only enters module disable mode when any currently running thread is finished (see section 24.5.1, functions and threads ). stop mode stop mode is entered when etpu answers device stop request assertion with stop acknowledge. the definition of which clocks are stopped is made at the mcu level, which defines whether or not registers can be accessed, interrupts and dma requests cleared. these modes are loosely selected: there is no unique register field or signals to choose between them. some features of one mode can be used with features of other mode(s). more on this subject can be found on section , etpu mode selection , below. note: throughout this document, an engine is said to be ?stopped? if it is either in module disable mode or stop mode. etpu mode selection user and user configuration are the production operating modes, and differ from each other only in access to scm. user programmability is only possible with a ram scm. on chips where the scm is implemented as a ram, it can either be accessed directly from ip-bus for code loading, or for software breakpoint setting. on chips with a rom scm, an internal scm emulation ram may be used, depending on the specific mcu implementation, to replace rom scm for test or debug purposes. scm emulation ram is selected in an mcu-specific way. for more details, see section , scm emulation . for more information on scm access, debug and test features, refer to section 24.5.10: test and development support . enhanced time processing unit (etpu2) RM0029 786/1740 doc id 15177 rev 8 debug mode is characterized by the use of the debug interface features. debug features may be implemented using the etpu-ndedi internal interface. specifically, this interface may be used with nexus implementation blocks to provide nexus class 3 debug features. the use of etpu-ndedi interface and nexus implementation is mcu-dependent. module disable mode is entered by setting etpu_ecr bit mdis. etpu engines can be individually stopped going into module disable mode (there is one etpu_ecr for each engine). each engine can leave module disable mode by writing mdis = 0 (which can only be done if vis = 0). stop mode is activated by ip-bus (device stop request). in this case, the etpu waits for both etpu engines to enter in stop mode, and then asserts the stop acknowledge line. etpu leaves stop mode when device stop request is negated, but only if vis = 0. if device stop request is negated and vis = 1, etpu will leave stop mode as soon as vis = 0. note: an engine can stay in module disable mode when it leaves stop mode if its bit mdis = 1, even if the other leaves it. 24.3 external signal description 24.3.1 overview there are 69 external signals associated with each etpu engine: 32 channel input signals, 32 channel output signals, 4 output disable inputs, and tcrclk clock input, totaling 138 in a dual-engine system. these signals are described in table 430 . depending on the mcu integration, the input and output signals of a channel can be tied to one pin. in this case, the direction of each channel signal, either output or input, is determined by the activation of an output enable driver signal. etpu provides one output buffer enable signal for each channel, controlled by microcode. the tcrclk signal is used to clock tcr1/2 counters or gate the tcr2 clock. in angle mode it is used as a tooth signal input. refer to section 24.5.6, time bases , and section 24.5.7, eac ? etpu angle counter , for proper use of this signal. table 430. etpu signal properties name direction function reset state pull up ipp_ind_etpuch_1(0) to ipp_ind_etpuch_1(31) input etpu engine 1 channel signals ? mcu dependent ipp_do_etpuch_1(0) to ipp_do_etpuch_1(31) output etpu engine 1 channel signals 0 / hi-z (1) mcu dependent ipp_ind_etpu_odis_1(0) to ipp_ind_etpu_odis_1(3) input etpu engine 1 output disable signals ? mcu dependent ipp_ind_tcrclk_1 input clock/gate for etpu engine 1 tcr counters; entry of the tooth signal in angle mode ? mcu dependent ipp_ind_etpuch_2(0) to ipp_ind_etpuch_2(31) input etpu engine 2 channel signals ? mcu dependent ipp_do_etpuch_2(0) to ipp_do_etpuch_2(31) output etpu engine 2 channel signals 0 / hi-z (1) mcu dependent RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 787/1740 24.3.2 detailed signal descriptions ipp_do_etpuch_[1|2]([0 ? 31]) ? etpu channel output signals each channel output signal is associated with a channel. the microcode may affect the logic level of an output signal (t) by implementing one of two actions: specify the logic level output to the signal when there is a match or a transition. immediately force a logic level. the output signal may also be forced to a logic level, independently of the output value from the channel logic, by one of the four (each engine) output disable input signals ipp_ind_etpuodis (see section , ipp_ind_etpu_odis_[1|2]([0 ? 3]) etpu channel output disable signals ). the output signal driver may be, depending on mcu integration, enabled by the output buffer enable internal signal that comes from etpu. in this case, the output buffer can be controlled by microcode, through a specific microinstruction field. there is one independent output buffer enable signal for each channel. for more information on output control from microcode, refer to section , transition detection and pin action control . ipp_ind_etpuch_[1|2]([0 ? 31]) ? etpu channel input signals each channel input signal is associated with a channel. the microcode can directly control the effect of the transition edge. each channel can be programmed to sense a transition when a rising and/or falling edge is detected. the channel logic can also process two transition events, and relate these events to each other and to other programmed timer events. the edge sensitivities of the two transition events are configured independently by microcode. for further information refer to section 24.5.5, enhanced channels , and section , transition detection and pin action control . each channel input signal has an associated synchronizer made of two flip-flops sampling the signal on every other system clock (u) , followed by a digital filter. this digital filter can work in three submodes, whose purpose is to filter out noise pulses that have width less then a programmed value of system clocks, preventing these transitions from being input to the transition detect logic. the synchronizer and digital filter are guaranteed to pass pulses that are greater than a programmed value. all channel input filters in one engine work on the ipp_ind_etpu_odis_2(0) to ipp_ind_etpu_odis_2(3) input etpu engine 2 output disable signals ? mcu dependent ipp_ind_tcrclk_2 input clock/gate for etpu engine 2 tcr counters; entry of the tooth signal in angle mode ? mcu dependent 1. value 0 refers to the reset value of the signal. hi-z refers to the state of the pads, if controlled by the etpu output buffe r enable signals, i.e., etpu output buffer enable resets in negated state. table 430. etpu signal properties (continued) name direction function reset state pull up t. note that the minimum pulse width is one microcycle (t wo system clocks), and slow 5v pads may not be able to transfer it on time. for generation of very short pulses the etpu pads have to be programmed by the system integration for fast operation mode with the voltage levels defined for fast pad operation in the mcu technology. u. sampled on the t4 microcycle phase, see section 24.7.1, microcycle and i/o timing . enhanced time processing unit (etpu2) RM0029 788/1740 doc id 15177 rev 8 same mode and sampling clock. for more information on channel input filters, refer to section , enhanced digital filter ? edf . in one of the angle modes, the output of the digital filter of channel 0 is replaced by the output of tcrclk digital filter (see section 24.5.7, eac ? etpu angle counter ). ipp_ind_tcrclk_etpu_[1|2] ? time base clock signal ? tcrclk tcrclk is an input signal used to control the time bases tcr1 and tcr2. there is one independent tcrclk input for each engine. for pulse accumulator operations tcrclk can be used as a gate for a counter based on the system clock divided by eight. for angle operations tcrclk can be used to get the tooth transition indications in angle mode. further details can be found on section 24.5.6, time bases , and section 24.5.7, eac ? etpu angle counter . like the channel input signals, the tcrclk si gnal has an associated synchronizer followed by a digital filter. this digital filter can work in two submodes, whose purpose is to filter out noise pulses that have width less then a programmed value of system clocks, preventing these transitions from being input to the transition detect logic. the synchronizer and digital filter are guaranteed to pass pulses that are greater than a programmed value. the clock and operation submode of the tcrclk filter is configured independently of the other channel input filters, through the field etpu_tbcr[tcrcf]. for more information on filter submodes, refer to section , tcrclk digital filter . in one of the angle modes, the output of the digital filter of channel 0 is replaced with the output of tcrclk signal digital filter (see section 24.5.7, eac ? etpu angle counter ). ipp_ind_etpu_odis_[1|2]([0 ? 3]) etpu channel output disable signals each of these four input signals are used to force the outputs of a group of eight channels to an inactive level. when an odis input is active, all the channels in its group of eight that have their bits odis = 1 in etpu_cxcr have their outputs forced to the opposite of the value specified in bit opol of the same register. therefore, channels can be individually selected to be affected by the output disable signals, as well as their disabling forced polarity (see figure 528 ). the output disable channel groups are defined in table 431 . in a dual-engine etpu there are 8 output disable signals for the 64 channels. table 431. output disable channel groups output disable signal (1) 1. the etpu2 output_disable signals ipp_ind_etpu_odis_1(0 to 3) are connected to the emios channel _flags_ (channel 11 to 8) respectively. channels ipp_ind_etpu_odis_[1|2](0) 0 to 7 ipp_ind_etpu_odis_[1|2](1) 8 to 15 ipp_ind_etpu_odis_[1|2](2) 16 to 23 ipp_ind_etpu_odis_[1|2](3) 24 to 31 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 789/1740 24.4 memory map/register definition the guideline for the description of all bits and fields throughout section 24.4, memory map/register definition , is to provide only a brief explanation (without examples or method of use) of the features, since it will be used mainly as a reference for the reader that is studying section 24.5, functional description , where those features are explained in detail. 24.4.1 memory map the etpu system simplified memory map is shown in tab le 4 32 . each of the register areas shown may have their own reserved address areas. ta ble 43 3 shows a detailed memory map. offsets are relative to the etpu base address, which is mcu-dependent. note: for spc564a74xx, spc564a80xx, the etpu2 base address is 0xc3fc_0000. the scm used area is informed to the etpu address decoding logic through the plug etpu_scmsize_plug[4:0]. scm unused area is decoded and returns a fixed opcode, determined by the register etpu_scmoffdatar. table 432. high level memory map offset use 0x00 ? 0x1f system configuration registers 0x20 ? 0x2f etpu 1 time base registers 0x30 ? 0x3f reserved (1) 0x40 ? 0x4f reserved (1) 0x50 ? 0x5f reserved (1) 0x60 ? 0x6f etpu 1 extra engine registers 0x70 ? 0x7f reserved (1) 0x80 ? 0xff reserved (1) 0x100 ? 0x13f reserved 0x140 ? 0x1ff reserved (1) 0x200 ? 0x2ff etpu 1/2 global channel registers 0x300 ? 0x3ff reserved (1) 0x400 ? 0x7ff etpu 1 channel registers 0x800 ? 0xbff etpu 2 channel registers 0xc00 ? 0x7fff reserved (1) 0x8000 ? 0xbfff (2) spram 0xc000 ? 0xffff (2) spram pse mirror (3) 0x10000 ? 0x1ffff (2) scm (4) 1. reserved addresses must not be used. access to these memory positions complete with 0-wait-states, but may cause unpredictable behavior. 2. actual sizes of scm and spram are mcu-dependent. 3. parameter sign extension access area, see section , parameter access enhanced time processing unit (etpu2) RM0029 790/1740 doc id 15177 rev 8 4. scm access is available only when bit vis = 1 on register etpu_mcr, under certain conditions (see section , etpu_mcr ? etpu module configuration register ). table 433. detailed memory map offset use location 0x00 etpu_mcr ? etpu module configuration register on page 24- 795 0x04 etpu_cdcr ? etpu coherent dual-parameter controller register on page 24- 799 0x08 reserved 0x0c etpu_misccmpr ? etpu misc compare register on page 24- 801 0x10 etpu_scmoffdatar ? etpu scm off-range data register (1) on page 24- 802 0x14 etpu_ecr_1 ? etpu 1 engine configuration register on page 24- 804 0x18 reserved 0x1c reserved 0x20 etpu_tbcr_1 ? etpu 1 time base configuration register on page 24- 809 0x24 etpu_tb1r_a ? etpu time base 1 (tcr1) visibility register on page 24- 814 0x28 etpu_tb2r_a ? etpu time base 2 (tcr2) visibility register on page 24- 815 0x2c etpu_redcr_1 - etpu 1 stac configuration register on page 24- 816 0x30 reserved 0x34 reserved 0x38 reserved 0x3c reserved 0x40 reserved 0x44 reserved 0x48 reserved 0x4c reserved 0x50 reserved 0x54 reserved 0x58 reserved 0x5c reserved 0x60 etpu_wdtr_1 ? etpu 1 watchdog timer register on page 24- 818 0x64 reserved RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 791/1740 0x68 etpu_idle_1 ? etpu 1 idle counter register on page 24- 819 0x6c reserved 0x70 reserved 0x74 reserved 0x78 reserved 0x7c reserved 0x80 ? 0xff reserved 0x100 reserved 0x104 reserved 0x108 reserved 0x10c reserved 0x110 reserved 0x114 reserved 0x118 reserved 0x11c reserved 0x120 reserved 0x124 reserved 0x128 reserved 0x12c reserved 0x130 reserved 0x134 reserved 0x138 reserved 0x13c ? 0x1ff reserved 0x200 etpu_cisr_1 ? etpu 1 channel interrupt status register on page 24- 822 0x204 reserved 0x208 reserved 0x20c reserved 0x210 etpu_cdtrsr_1 ? etpu 1 channel data transfer request status register on page 24- 822 0x214 reserved 0x218 reserved 0x21c reserved 0x220 etpu_ciosr_1 ? etpu 1 channel interrupt overflow status register on page 24- 823 table 433. detailed memory map (continued) offset use location enhanced time processing unit (etpu2) RM0029 792/1740 doc id 15177 rev 8 0x224 reserved 0x228 reserved 0x22c reserved 0x230 etpu_cdtrosr_1 ? etpu 1 channel data transfer request overflow status register on page 24- 825 0x234 reserved 0x238 reserved 0x23c reserved 0x240 etpu_cier_1 ? etpu 1 channel interrupt enable register on page 24- 826 0x244 reserved 0x248 reserved 0x24c reserved 0x250 etpu_cdtrer_1 ? etpu 1 channel data transfer request enable register on page 24- 827 0x254 reserved 0x258-0x27f reserved 0x280 etpu_cpssr_1 ? etpu 1 channel pending service status register on page 24- 828 0x284 reserved 0x288 reserved 0x28c reserved 0x290 etpu_cssr_1 ? etpu 1 channel service status register on page 24- 828 0x294 reserved 0x298 reserved 0x29c reserved 0x300 ? 0x3ff reserved 0x400 etpu_c0cr_1 ? etpu 1 channel 0 configuration register on page 24- 832 0x404 etpu_c0scr_1 ? etpu 1 channel 0 status and control register on page 24- 835 0x408 etpu_c0hsrr_1 ? etpu 1 channel 0 host service request register on page 24- 838 0x40c reserved 0x410 etpu_c1cr_1 ? etpu 1 channel 1 configuration register on page 24- 832 table 433. detailed memory map (continued) offset use location RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 793/1740 0x414 etpu_c1scr_1 ? etpu 1 channel 1 status and control register on page 24- 835 0x418 etpu_c1hsrr_1 ? etpu 1 channel 1 host service request register on page 24- 838 0x41c reserved . . 0x5f0 etpu_c31cr_1 ? etpu 1 channel 31 configuration register on page 24- 832 0x5f4 etpu_c31scr_1 ? etpu 1 channel 31 status and control register on page 24- 835 0x5f8 etpu_c31hsrr_1 ? etpu 1 channel 31 host service request register on page 24- 838 0x5fc ? 0x7ff reserved 0x800 reserved 0x804 reserved 0x808 reserved 0x80c reserved 0x810 reserved 0x814 reserved 0x818 reserved 0x81c reserved . . . 0x9f0 reserved 0x9f4 reserved 0x9f8 reserved 0x9fc ? 0x7fff reserved 0x8000 ? 0xbfff (2) shared parameter ram ? spram 0xc000 ? 0xffff (2) shared parameter ram?spram ? pse mirror (3) 0x10000 ? 1ffff (4) shared code memory ? scm (5) 1. this register is not implemented in some mcus; see section , etpu_scmoffdatar ? etpu scm off-range data register . 2. the actual spram size is mcu-dependent. 3. parameter sign extension access area, see section , parameter access table 433. detailed memory map (continued) offset use location enhanced time processing unit (etpu2) RM0029 794/1740 doc id 15177 rev 8 4. the actual scm size is mcu-dependent. when the size not the maximum, the unused scm address range returns the value of the register etpu_scmoffdatar. 5. scm access is available only when bit vis = 1 on register etpu_mcr, under certain conditions (see section , etpu_mcr ? etpu module configuration register ). scm can only be written in 32-bit accesses. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 795/1740 24.4.2 system configuration registers etpu_mcr ? etpu module configuration register this register is global to both etpu engines, and resides in the shared biu. etpu_mcr gathers global configuration and status in the etpu system, including global exception. it is also used for configuring the scm (shared code memory) operation and test. figure 494. etpu_mcr register offset: etpu_base + 0x0000 access: user read/write 0 1 2345678 9101112131415 r0 sdmerr wdtoa wdtob mge 1 mge 2 ilf1 ilf2 scmerr 00 scmsize wgec reset 0 0 0000000 00 scmsize 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 scmmisc scmmisf scmmisen 00 vis 00000 gtbe w scmmiscc reset 0 0 0000000 0000000 = unimplemented or reserved table 434. etpu_mcr field description field description 0 gec?global exception clear this write-only bit negates global exception request and clears global exception status bits mge1, mge2, ilf1, ilf2 and scmmisf. 1: negate global exception, clear status bits mge1, mge2, ilf1, ilf2 and scmmisf 0: keep global exception request and status bits mge1, mge2, ilf1, ilf2 and scmmisf as is. gec works the same way in module disable mode. enhanced time processing unit (etpu2) RM0029 796/1740 doc id 15177 rev 8 1 sdmerr?sdm read error this flag indicates that an sdm read error occurred on a microengine read, generating a global exception. errors from host reads neither set this flag nor generate global exceptions. this bit is cleared by writing 1 to gec. 1: global exception requested by sdm read error is pending. 0: no global exception pending because of sdm read error. 2 wdtoa?watchdog timeout flag wdtoa indicates that a watchdog timeout occurred in etpu engine a, generating a global exception. this bit is cleared by writing 1 to gec. 1: global exception requested by watchdog timeout 0: no global exception pending because of watchdog timeout. 3 wdtob?watchdog timeout flag wdtob indicates that a watchdog timeout occurred in etpu engine b, generating a global exception. this bit is cleared by writing 1 to gec. 1: global exception requested by watchdog timeout 0: no global exception pending because of watchdog timeout. 4 mge1?microcode global exception ? engine a this bit indicate that a global exception was asserted by microcode executed on etpu engine a. the determination of the reason why the global exception was asserted is application dependent: it can be coded in an spram status parameter, for instance. this bit is cleared by writing 1 to gec. 1: global exception requested by microcode is pending 0: no microcode-requested global exception pending. 5 mge2?microcode global exception ? engine b this bit indicate that a global exception was asserted by microcode executed on etpu engine b. the determination of the reason why the global exception was asserted is application dependent: it can be coded in an spram status parameter, for instance. this bit is cleared by writing 1 to gec. 1: global exception requested by microcode is pending 0: no microcode-requested global exception pending. 6 ilf1?illegal instruction flag ? etpu a the ilf1 bit is set by the microengine to indicate that an illegal instruction was decoded in engine a. this bit is cleared by host writing 1 to gec. see section , illegal instructions , for more details. 1: illegal instruction detected by etpu a. 0: illegal instruction not detected. 7 ilf2?illegal instruction flag ? etpu b the ilf2 bit is set by the microengine to indicate that an illegal instruction was decoded in engine b. this bit is cleared by host writing 1 to gec. see section , illegal instructions , for more details. 1: illegal instruction detected by etpu b. 0: illegal instruction not detected. table 434. etpu_mcr field description field description RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 797/1740 8 scmerr?scm read error this flag indicates that an scm read error occurred on a microengine read, generating a global exception. errors from host reads neither set this flag nor generation global exceptions. this bit is cleared by writing 1 to gec. 1: global exception requested by scm read error is pending. 0: no global exception pending because of scm read error. 9-10 reserved 11-15 scmsize[4:0]?scm size this read-only field holds the number of 2 kbyte scm blocks minus 1. this bit is write protected when any of the engines are not halted or stopped (1) . when vis = 1, the etpu_ecr mdis bits are write protected, and only 32-bit aligned scm writes are supported. the value written to scm is unpredictable if other transfer sizes are used. 16-19 reserved 20 scmmisc, scmmiscc?scm misc complete, scm misc complete clear flag scmmisc indicates that misc has completed the evaluation of the scm signature since reset or the since the last time it was cleared. scmmisc is cleared by writing 1 to scmmiscc (at same bit position), and is not cleared when misc is disabled (scmmisen = 0). scmmisc asserts at the end of the scm memory scan, either if the signature matches or not. 1: misc completed at least one scm signature calculation and compare since the last time scmmisc was cleared. 0: misc has not yet completed an scm signature calculation and compare since the last time scmmisc was cleared.writes are supported. the value written to scm is unpredictable if other transfer sizes are used. 21 scmmisf?scm misc flag the scmmisf bit is set by the scm misc (multiple input signature calculator) logic to indicate that the calculated signature does not match the expected value, at the end of a misc iteration. see section 24.5.10: test and development support , for more details. 1: misc has read entire scm array and the expected signature in etpu_misccmpr does not match the value calculated. 0: signature mismatch not detected. this bit is cleared when global exception is cleared by writing 1 to gec. table 434. etpu_mcr field description field description enhanced time processing unit (etpu2) RM0029 798/1740 doc id 15177 rev 8 22 scmmisen?scm misc enable the scmmisen bit is used for enabling/disabling the operation of the misc logic. scmmisen is readable and writable at any time. the misc logic will only operate when this bit is set to 1. when the bit is reset the misc address counter is set to the initial scm address. when enabled, the misc will continuously cycle through the scm addresses, reading each and calculating a crc. in order to save power, the misc can be disabled by clearing the scmmisen bit. see section 24.5.10: test and development support , for more details. 1: misc operation enabled. 0: misc operation disabled. the misc logic is reset to its initial state. scmmisen resets automatically when misc logic dete cts an error, i.e., when scmmisf transitions from 0 to 1, disabling the misc operation. 23-24 reserved 25 vis?scm visibility bit vis bit turns scm visible to the ip-bus and rese ts misc state (but scmmisen keeps its value). 1: scm is visible to the slave bus. misc state is reset. 0: scm is not visible to the slave bus. accessing scm address space issues a bus error, writes are protected and reads are meaningless. this bit is write protected when any of the engines are not halted or stopped (2) . when vis = 1, the etpu_ecr mdis bits are write protected, and only 32-bit aligned scm writes are supported. the value written to scm is unpredictable if other transfer sizes are used. 26-30 reserved 31 gtbe?global time base enable gtbe enables time bases in both engines, allowing them to be started synchronously. 1: time bases in both engines are enabled to run. 0: time bases in both engines are disabled to run. global time base enable action may also depend on other blocks, as explained in section , gtbe ? global time base enable . when gtbe is turned off with angle mode enabled, the eac must be reinitialized before gtbe is turned on again. the eac reinitialization procedure is described in section , restarting angle logic . 1. engine is stopped in module disable or stop modes, but access es to registers in stop mode is defined in the mcu level. 2. engine is stopped in module disable or stop modes, but access es to registers in stop mode is defined in the mcu level. table 434. etpu_mcr field description field description RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 799/1740 etpu_cdcr ? etpu coherent dual-parameter controller register etpu shared parameter ram (spram) can be accessed by the mcu?s processor core and the etpu?s microengine(s) concurrently. in general, there is no guaranteed order by which a group of parameters is accessed, which may lead to a lack of internal consistency if two or more related parameters are read when only part of them is updated. the etpu provides mechanisms to guarantee parameter coherency, including the use of transfer service thread mechanism. and a mailbox (or ?software semaphore?) mechanism. a third mechanism, the coherent dual-parameter controller (cdc), is also provided. it is used by the processor core to coherently transfer pairs of parameters between a parameter buffer located on spram and locations on spram where parameters are accessed directly by the channels. coherency is guaranteed by spram access arbitration. although limited to two parameters only, it has low latency and wastes no microengine resources. this register is used to configure and initiate cdc transfers between the parameter buffer area and the channel parameter area. 1. the host asserts the sts bit to start the data transfer. 2. cdc contends for the spram and starts the transfer. 3. when the data transfer is complete, sts returns to 0. the host receives wait-states for writing sts = 1 while cdc contends for spram and during the transfer. 4. the write access ends when cdc finishes the transfer. the host receives wait-states during the cdc transfer. note: if the host writes to the etpu_cdcr with sts = 0 or does not write the sts bit, the cdc transfer does not occur. cdc programming can be summarized as follows: 1. if it is a write transfer, i.e., from host to channel, write the two parameters into temporary area. 2. write the etpu_cdcr with sts = 1 and the remaining cdc programming parameters: parameter width (32 or 24 bits, field pwidth), transfer direction (read or write, field wr), temporary parameter area base address (field pbbase), and the absolute addresses of the parameters to be transferred (concatenation of the fields ctbase and param0/1). 3. if it is a read transfer, i.e., from channel to host, read the two parameters from the temporary area into host memory/registers. enhanced time processing unit (etpu2) RM0029 800/1740 doc id 15177 rev 8 figure 495. etpu_cdcr register offset: etpu_base + 0x004 access: user read/write 0 1 2345678 9101112131415 r sts ctbase pbbase w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pwid th param0 wr param1 w reset0 0 00000000000000 = unimplemented or reserved table 435. etpu_cdcr field description field description 0 sts?start bit this bit is set by the host in order to start the data transfer between the parameter buffer pointed by pbbase and the target addresses selected by the concatenation of fields ctbase and param0/1. the host receives wait-states until the data transfer is complete, when this bit is reset by coherency logic (see section , coherent dual-parameter controller (cdc) ). therefore, host always reads sts as 0. 1: (write) starts a coherent transfer. 0: (write) does not start a coherent transfer. 1-5 ctbase[4:0]?channel transfer base this field concatenates with fields param0/param1 to determine the absolute word offset (from the spram base) of the parameters to be transferred: parameter 0 word address = {ctbase, param0} + spram base word address parameter 1 word address = {ctbase, param1} + spram base word address 6-15 pbbase[9:0]?parameter buffer base address this field points to the base address of the parameter buffer location, with granularity of 2 parameters (8 bytes). the host (byte) address of the first parameter in the buffer is pbbase*8 + spram base byte address. the microengine absolute (word) address of the first parameter in the buffer is pbbase*2. 16 pwidth?parameter width selection this bit selects the width of the parameters to be transferred between the pb and the target address. 1: transfer 32-bit parameters. all 32 bits of the parameters are written in the destination address. 0: transfer 24-bit parameters. the upper byte remains unchanged in the destination address. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 801/1740 etpu_misccmpr ? etpu misc compare register the etpu includes a feature called the multiple input signature calculator (misc) which comprises hardware that sequentially reads all shared code memory (scm) and calculates a 32-bit crc signature. the etpu_misccmpr stores the 32-bit expected value to be compared to the signature generated by the misc. the sequence is as follows: 1. the host loads the etpu_misccmpr with the expected value to be found at the end of the misc cycle 2. the host starts signature calculation by writing bit scmmisen = 1 in the etpu_mcr. the misc zeroes the signature accumulator and starts reading scm data and calculating the signature. 3. after last scm position is read, misc compares the value in the signature accumulator against the value in the etpu_misccmpr. if there is a mismatch, the misc stops, issues a global exception and the sc mm i sf bit in the etpu_mcr assumes value 1. if no mismatch is found, misc repeats the procedure automatically. 17-23 param0[6:0]?channel parameter number 0 this field, in concatenation with ctbase[4:0], determines the word address offset (from the spram base) of the parameters that are destination or source (defined by wr) of the coherent transfer. the word spram address offset of the parameters are {ctbase, param0}.note that param0 and param1 allow non-contiguous parameters to be transferred coherently. the parameter pointed by {ctbase, param0} is the first transferred. 24 wr?read/write selection this bit selects the direction of the coherent data transfer. 1: write operation. data transfer is from the pb to the selected parameter ram address. 0: read operation. data transfer is from the selected parameter ram address to the pb. 25-31 param1[6:0]?channel parameter number 1 this field, in concatenation with ctbase[4:0] determines the word address offset (from the spram base) of the parameters that are destination or source (defined by wr) of the coherent transfer. the word spram address offset of the parameters are {ctbase, param1}.note that param0 and param1 allow non-contiguous parameters to be transferred coherently. the parameter pointed by {ctbase, param0} is the first transferred. table 435. etpu_cdcr field description field description enhanced time processing unit (etpu2) RM0029 802/1740 doc id 15177 rev 8 figure 496. etpu_misccmpr register etpu_scmoffdatar ? etpu scm off-range data register when read accesses are made, either by the host or an etpu2 microengine, to addresses above the limit corresponding to the scmsize value in the etpu_mcr, the value read comes from the etpu_scmoffdatar. the host can program the register at initialization with an opcode value with operations that try to protect or recover the system from runaway code, for instance: terminate the thread, clear channel flags, disable match and transition service requests, issue an interrupt, or jump to an error recovery procedure. writes to unimplemented addresses do not return an error and can write on unspecified mirror addresses, so they should be avoided. the reset value is mcu dependent. offset: etpu_base + 0x00c access: user read/write 0 1 2345678 9101112131415 r etpumisccmp[31:16] w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r etpumisccmp[15:0] w reset0 0 00000000000000 = unimplemented or reserved table 436. etpu_misccmpr field description field description 0-31 etpumisccmp[31:0]?expected multiple input signature register value see section , scm test ? multiple input signature calculator . RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 803/1740 offset: etpu_base + 0x010 access: user read/write 0 1 2345678 9101112131415 r etpuscmoffdata[31:16] w reset etpu_scm_off_range_data_plug[31:16] (1) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r etpuscmoffdata[15:0] w reset etpu_scm_off_range_data_plug[15:0] = unimplemented or reserved 1. the reset value depends on the mcu, and is usually 0xf3775ffb, an instruction that clears mrles, mrls and tdls, disables channel service requests, ends the thread and generates an illegal instruction global exception. figure 492. etpu_scmoffdatar register table 437. etpu_scmoffdatar field description field description 0-31 etpuscmoffdata[31:0]?scm off-range read data value see section , scm off-range data . enhanced time processing unit (etpu2) RM0029 804/1740 doc id 15177 rev 8 etpu_ecr ? etpu engine configuration register each engine has its own etpu_ecr. etpu_ecr holds configuration and status fields that are programmed independently in each engine. offset: etpu_a: etpu_base + 0x014; etpu_b: etpu_base + 0x018 access: user read/write 0 1 2345678 9101112131415 r fend mdis 0stf0000hltf000 fcss fpsck w reset 0 0/1 (1) 0000000(1 (2) )0000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cdfc 0 erba sppd is 00 etb w reset0 0 00000000000000 = unimplemented or reserved 1. the mdis reset value is mcu-dependent. please consult the reference manual of the specific mcu. 2. engine may go to debug state (halted) soon after reset, depending on the ndedi configuration. figure 492. etpu_ecr register table 438. etpu_ecr field description field description 0 fend?force end fend assertion terminates any current running thread as if an end instruction have been executed (see section , ending current thread ? end ). 1: ends any ongoing thread. 0: normal operation. this bit is self-negating when the thread ends. writing fend = 1 is ignored and fend stays 0 when the microengine is in tst, halted, stopped, or idle (no thread executing). only on rare occasions (e.g., during a long stall, see section , microengine stall ) fend can be read as 1, because it negates as soon as the end begins execution. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 805/1740 1 mdis?module disable bit when mdis is set, the engine shuts down its internal clocks, going into module disable mode. tcr1 and tcr2 cease to increment, and input sampling stops. the engine asserts the stop flag (stf) bit to indicate that it has stopped however, the biu continues to run, and the host can access all registers except for the channel registers (see list of channel registers on section 24.4.7, channel configuration and control registers ). after mdis is set, even before stf asserts, data read from the channel registers is not meaningful and writes are ineffective, issuing a bus error. when the mdis bit is asserted while the microcode is executing, the etpu will stop when the thread is complete. 1: commands engine to stop its clocks. 0: etpu engine runs. stop completes on the next system clock after the stop condition is valid. the mdis bit is write-protected when vis = 1. the timebase registers can still be read with mdis = 1, but writes are ineffective and a bus error is issued. global channel registers and spram can be accessed normally. once mdis is switched from 1 to 0 or vice versa, it must not be written a different value until stf changes accordingly. 2 reserved 3 stf?stop flag bit the etpu system is fully stopped after the etpu engine asserts its stop flag (stf). in case of an ip-bus stop, the etpu acknowledges the stop only after any ongoing thread is complete and the etpu engine has stopped. 1: engine has stopped (after the local mdis bit has been asserted, or after the ip-bus stop line has been asserted). 0: engine is operating. summarizing engine stop conditions, which stf reflects: stf_1:= (after stop completed) mdis_1 | device stop request stf_2:= (after stop completed) mdis_2 | device stop request stf_1 and stf_2 mean stf bit from engine 1 and stf bit from engine 2 respectively. 4-7 reserved table 438. etpu_ecr field description field description enhanced time processing unit (etpu2) RM0029 806/1740 doc id 15177 rev 8 8 hltf?halt mode flag if etpu engine entered halt state, this flag is asserted. the flag remains asserted while the microengine is in halt state, even during a single-step or forced instruction execution. see section , development support features , for further details about entering halt mode. 1: etpu engine is halted 0: etpu engine is not halted. 9-11 reserved 12 fcss?filter clock source selection speeds up the filter clock source before the prescaler, allowing more input capture resolution at minimum prescaling. 1: use system clock as edf clock source before prescaler 0: use system clock / 2 as edf clock source before prescaler. fcss = 1 also makes the channel work on t2/t4 timing mode (see section , t2/t4 channel timing ). 13-15 fpsck[2:0]?filter prescaler clock control fpsck controls the prescaling of the clocks used in digital filters for the channel input signals and tcrclk input, as shown in table 439 . filtering can be controlled independently by engine, but all input digital filters in the same engine have same clock prescaling. for more details see section , filter clock prescaler . a new value written to fpsck only becomes effective when the filter prescaler finishes the current count. table 438. etpu_ecr field description field description table 439. filter prescaler clock control filter control sample on system clock divided by: 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 256 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 807/1740 16-17 cdfc[1:0]?channel digital filter control these bits select a digital filtering mode for the channels when configured as inputs for improved noise immunity (refer to table 440 ). the etpu has three digital filtering modes for the channels which provide programmable trade-off between signal latency and noise immunity (see section , enhanced digital filter ? edf ). changing cdfc during etpu normal input channel operation is not recommended since it changes the behavior of the transition detection logic while executing its operation. 18 reserved 19-23 erba?engine relative base address this field value is concatenated with the aid instruction field in engine relative address mode to form the spram address (see section , engine relative addressing mode ). 24 sppdis?schedule priority passing disable sppdis is used to disable the priority passing mechanism of the microengine scheduler (see section , primary scheme ? priority among channels on different levels ). 1: scheduler priority passing mechanism disabled. 0: scheduler priority passing mechanism enabled. sppdis bit must not be changed while any channel is enabled. 25-26 reserved table 438. etpu_ecr field description field description table 440. channel digital filter control cdfc selected digital filter 00 tpu2/3 two sample mode: using the filter clock which is the system clock divided by (2, 4, 8,.., 256) as a sampling clock (selected by fpsck field in etpu_ecr), comparing two consecutive samples which agree with each other sets the input signal state. this is the default reset state. 01 etpu bypass mode: the input signal is taken unfiltered, also making the channels work on t2/t4 timing mode (1) . 1. see section , t2/t4 channel timing 10 etpu three sample mode: similar to the tpu2/3 two sample mode, but comparing three consecutive samples which agree with each other sets the input signal state. 11 etpu continuous mode: signal need to be stable for the whole filter clock period. this mode compares all the values at the rate of system clock (fcss = 1) or system clock divided by two (fcss = 0), between two consecutive filter clock pulses. signal needs to be continuously stable for the entire period. if all the values agree with each other, input signal state is updated. enhanced time processing unit (etpu2) RM0029 808/1740 doc id 15177 rev 8 27-31 etb[4:0]?entry table base the field determines the location of the microcode entry table for the etpu functions in scm (see section , entry points ). table 441 shows the entry table base address options. table 438. etpu_ecr field description field description table 441. entry table base address options etb entry table base address for host address entry table base address for microcode address 00000 0x000 0x000 00001 0x800 0x200 00010 0x1000 0x400 . . . . . . . . . . . . 11110 0xf000 0x3c00 11111 0xf800 0x3e00 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 809/1740 24.4.3 time base registers each etpu2 engine has two internally-generated time bases?time counter registers? tcr1 and tcr2. they provide 24-bit time bases, shared by all 32 channels of their associated etpu2 engine. the registers in the following sections control the configuration and visibility of the time bases. there is one of each of these registers for each etpu engine. note: writes to this register issue bus error and are ineffective when mdis = 1. reads are always allowed. etpu_tbcr ? etpu time base configuration register this register configures several timebase options. figure 497. etpu_tbcr register offset: etpu_a: etpu_base + 0x020 etpu_b: etpu_base + 0x040 access: user read/write 0 1 2345678 9101112131415 r tcr2ctl tcrcf am 000 tcr2p w reset0 0 10000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tcr1ctl tcr1cs 00000 tcr1p w reset0 0 00000000000000 = unimplemented or reserved enhanced time processing unit (etpu2) RM0029 810/1740 doc id 15177 rev 8 table 442. etpu_tbcr field description field description 0-2 tcr2ctl[2:0]?tcr2 clock/gate control these bits are part of the tcr2 clocking system (see section 24.5.6, time bases ). they determine the clock source for tcr2 before the prescaler. tcr2 can count on any detected edge of the tcrclk signal or use it for gating system clock divided by 8. after reset - tcrclk signal rising edge is selected. tcr2 can also be clocked by an internal peripheral timebase signal or system clock divided by 8. tcr2ctl also determines the tcrclk edge selected for angle tooth detection in angle mode. see table 443 . table 443. tcr2 clock source tcr2ctl am = 0 am = 1 tcr2 clock before prescaler angle tooth detection 000 gated div8 clock (system clock / 8). in this case, when the external tcrclk signal is low, the div8 clock is blocked, preventing it from incrementing the tcr2 prescaler. when the external tcrclk signal is high, tcr2 prescaler is incremented at the frequency of the system clock divided by 8. do not use with am = 1 001 rise transition on tcrclk signal increments the tcr2 prescaler. rise edge 010 fall transition on tcrclk signal increments the tcr2 prescaler. fall edge 011 rise or fall transition on tcrclk signal increments the tcr2 prescaler. both edges 100 div8 clock (system clock / 8) do not use with am = 1 101 peripheral timebase clock source 110 do not use with am = 0 no edge (1) 1. tcrclk edges are not detected by the eac logic, but they can still be detected by the channel 0 logic if am = 01. 111 tcr2 frozen, except as stac client do not use with am = 1 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 811/1740 3-4 tcrcf[1:0]?tcrclk signal filter control this field controls the tcrclk digital filter (see section , tcrclk digital filter ), determining whether the tcrclk signal input (after a synchronizer) is filtered with the same filter clock as the channel input signals (see section , enhanced digital filter ? edf ) or uses the system clock divided by 2, and also whether the tcrclk digital filter works in integrator mode or two sample mode (see table 444 ). 5-6 am?angle mode selection this field enables the enhanced angle counter logic to generate angle information (see section 24.5.7, eac ? etpu angle counter ), and also select the tooth signal input and the channel used to process it, as shown in table 445 . when eac is not disabled by am and neither tcr1 nor tcr2 are stac clients, the eac (etpu angle clock) hardware provides angle information to the channels using the tcr2 bus. when am is reset (non-angle mode), the eac operation is disabled, and its internal registers can be used as general purpose. for more information, see section 24.5.7, eac ? etpu angle counter . if tcr1 or tcr2 is a stac bus client (see section , stac interface ), the eac operation is forbidden, and if am is set the angle logic does not work properly. changing am may cause spurious transition detection s on the channel selected by am, depending on the channel mode and state (see section , transition detection and time base capture ). if am must be changed with gtbe = 1, the recommended procedure is described in section , restarting angle logic . 7-9 reserved table 442. etpu_tbcr field description (continued) field description table 444. tcrclk filter clock/mode tcrcf filter clock filter mode 00 system clock divided by 2 two sample 01 filter clock of the channels two sample 10 system clock divided by 2 integrator 11 filter clock of the channels integrator table 445. am - angle mode selection value tcr2 value tooth signal tooth processing channel 0 0 timebase (eac operation disabled) not applicable 0 1 angle ticks tcrclk input 0 1 0 channel 1 input 1 1 1 channel 2 input 2 enhanced time processing unit (etpu2) RM0029 812/1740 doc id 15177 rev 8 10-15 tcr2p[5:0]?timer count register 2 prescaler control these bits are part of the tcr2 clocking system (see section 24.5.6, time bases ). tcr2 is clocked from the output of a prescaler. the prescaler divides its input by (tcr2p+1) allowing frequency divisions from 1 to 64. the prescaler input is the system clock di vided by 8 (in gated or non-gated clock mode), or internal timebase input, or tcrclk filtered input. this field has no effect on tcr2 in angle mode. 16-17 tcr1ctl?tcr1 clock/gate control tcr1ctl is part of the tcr1 clocking system (see section 24.5.6, time bases ). it determines, together with tcr1cs, the clock source for tcr1. tcr1 can count on detected rising edge of the tcrclk signal, a peripheral timebase source, system clock, or the system clock divided by 2 (see table 446 ). after reset tcrclk signal is selected 18 tcr1cs?tcr1 clock source tcr1cs provides the option to double the tcr1 incrementing speed, using system clock as its clock source instead of system clock / 2. 1: use system clock as tcr1 clock source before the prescaler; can only be set in specific combinations with tcr1ctl (see table 446 ). 0: use system clock / 2 as tcr1 clock source before the prescaler, if that clock source is selected by tcr1ctl. tcr1cs = 1 also makes the channel work on t2/t4 timing mode (see section , t2/t4 channel timing ). the clock source of the eac angle tick generator will st ill be an even division of system clock if tcr1cs = 1, obeying to the fields tcr1p as if tcr1cs = 0 (see section , angle tick generator ). 19-23 reserved table 442. etpu_tbcr field description (continued) field description table 446. tcr1 clock source tcr1ctl tcr1cs (1) 1. all other combinations of tcr1ctl and tcr1cs are reserved. tcr1 clock before prescaler 00 0 selects tcrclk as clock source for the tcr1 prescaler (2) 2. this selection must not be used in angle mode. 01 0 selects peripheral timebase clock as source for the tcr1 prescaler 10 0 selects system clock divided by 2 as clock source for the tcr1 prescaler 10 1 selects system clock as clock source for the tcr1 prescaler 11 0 tcr1 frozen, except as a stac client; RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 813/1740 24-31 tcr1p[7:0]?timer count register 1 prescaler control tcr1 is clocked from the output of a prescaler. the input to the prescaler is the internal etpu system clock divided by 2, system clock, or the output of tcrclk filter, or peripheral timebase input. the prescaler divides this input by (tcr1p+1) allowing frequency divisions from 1 up to 256. table 442. etpu_tbcr field description (continued) field description enhanced time processing unit (etpu2) RM0029 814/1740 doc id 15177 rev 8 etpu_tb1r ? etpu time base 1 (tcr1) visibility register this register provides visibility of the tcr1 time base for host read access (see section 24.5.6, time bases ). this register is read-only. the value of the tcr1 time base shown can be driven by the tcr1 counter or imported from stac bus, depending on the configuration set in etpu_redcr. figure 498. etpu_tb1r register offset: etpu_a: etpu_base + 0x024; etpu_b: etpu_base + 0x044 access: user read 0 1 2345678 9101112131415 r0 0 000000 tcr1[23:7] w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tcr1[8:0] w reset0 0 00000000000000 = unimplemented or reserved table 447. etpu_tb1r field description field description 0-7 reserved 8-31 tcr1[23:0]?tcr1 value tcr1 value used on matches and captures. see section 24.5.6, time bases . RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 815/1740 etpu_tb2r ? etpu time base 2 (tcr2) visibility register this register provides visibility of the tcr2 time base for host read access (see section 24.5.6, time bases ). this register is read-only. the value of the tcr2 time base shown can be driven by the tcr2 counter, the angle mode logic, or imported from stac, depending on angle mode and stac configurations set in registers etpu_tbcr and etpu_redcr. figure 499. etpu_tb2r register offset: etpu_a: etpu_base + 0x028; etpu_b: etpu_base + 0x048 access: user read 0 1 2345678 9101112131415 r0 0 000000 tcr2[23:7] w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tcr2[8:0] w reset0 0 00000000000000 = unimplemented or reserved table 448. etpu_tb2r field description field description 0-7 reserved 8-31 tcr2[23:0]?tcr2 value tcr2 value used on matches and captures. see section 24.5.6, time bases . enhanced time processing unit (etpu2) RM0029 816/1740 doc id 15177 rev 8 etpu_redcr ? etpu stac configuration register this register configures the etpu stac bus operation as a stac server/client module (see section , stac interface ). figure 500. etpu_redcr register offset: etpu_a: etpu_base + 0x02c; etpu_b: etpu_base + 0x04c access: user read/write 0 1 2345678 9101112131415 r ren 1 rsc 1 0 0 server_id1 0 0 0 0 srv1 w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ren 2 rsc 2 0 0 server_id2 0 0 0 0 srv2 w reset0 0 00001000000000 = unimplemented or reserved table 449. etpu_redcr field description field description 0 ren1?tcr1 resource (1) client/server operation enable bits this bit enables or disables client/server operation to etpu stac resources. ren1 enables tcr1 stac bus operations. 1: server/client operation for resource 1 is enabled. 0: server/client operation for resource 1 is disabled. 1 rsc1?tcr1 resource server/client assignment bits this bit selects the etpu data resource assignment to be used as servers or clients. rsc1 selects the functionality of tcr1. for server mode, external plugging determines the unique server address assigned to each tcr. for a client mode, the srv1 field determines the server address to which the client listens. 1: resource server operation. 0: resource client operation. when tcr1 is configured as a stac bus client (ren2 = 1, rsc2 = 0) the etpu angle clock hardware cannot be used. rsc1 must not be changed when the respective ren1 bit is asserted. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 817/1740 2-3 reserved 4-7 server_id1?stac id 1 stac server id (read-only plug values) used for tcr1 when stac servers. 12-15 srv1?tcr1 resource server these bits select the address of the specific stac server to which the local tcr1 listens when configured as a stac client. srv1 selects the stac server of tcr1. 16 ren2?tcr2 resource (2) client/server operation enable bits this bit enables or disables client/server operation to etpu stac resources. ren2 enables tcr2 stac bus operations. 1: server/client operation for resource 2 is enabled. 0: server/client operation for resource 2 is disabled. 17 rsc2?tcr2 resource server/client assignment bits this bit selects the etpu data resource assignment to be used as servers or clients. rsc2 selects the functionality of tcr2. for server mode, external plugging determines the unique server address assigned to each tcr. for a client mode, the srv2 field determines the server address to which the client listens. 1: resource server operation. 0: resource client operation. when tcr1 or tcr2 is configured as a stac bus cli ent (ren2 = 1, rsc2 = 0) the etpu angle clock hardware cannot be used. rsc2 must not be changed when the respective ren1,2 bit is asserted. 18-19 reserved 20-23 server_id2?stac id 2 stac server id (read-only plug values) used for tcr2 when stac servers. 24-27 reserved 28-31 srv2?tcr2 resource server these bits select the address of the specific stac server to which the local tcr2 listens when configured as a stac client. srv2 selects the stac server of tcr2. 1. resource identifies any parameter that changes along the time and can be exported / imported from other device. in etpu context, a resource can be tcr1 or tcr2 (either time or angle values). 2. resource identifies any parameter that changes along the time and can be exported / imported from other device. in etpu context, a resource can be tcr1 or tcr2 (either time or angle values). table 449. etpu_redcr field description field description enhanced time processing unit (etpu2) RM0029 818/1740 doc id 15177 rev 8 24.4.4 engine related registers this section gathers registers that are engine-related, other than etpu_ecr (see section , etpu_ecr ? etpu engine configuration register ). etpu_wdtr ? etpu watchdog timer register this register configures the watchdog timer for the engine. figure 501. etpu_wdtr register offset: etpu_a: etpu_base + 0x060; etpu_b: etpu_base + 0x070 access: user read/write 0 1 2345678 9101112131415 r wdm 00000000000000 w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r wdcnt[15:0] w reset0 0 00000000000000 = unimplemented or reserved table 450. etpu_wdtr field description field description 0-1 wdm?watchdog mode wdm selects the watchdog operation mode, as shown below. for more information on the watchdog operation, see section , watchdog . 00: disabled 01: reserved 10: thread length 11: busy length the watchdog must be disabled first before a new mode is configured. 2-15 reserved RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 819/1740 etpu_idle ? etpu idle register the idle counter register (etpu_idle) continuously counts microcycles in which the microengine is not busy with channel service. it can be used to measure the microengine utilization by rating the count measured during a period of time to the number of microcycles contained in the period. the idle counter does not count microcycles when the engine is stopped, or is in tst or halt states. each etpu2 engine has an associated etpu_idle register. figure 502. etpu_idle register 16-31 wdcnt[15:0]?watchdog count this field indicates the maximum number of microcyles allowed for a thread (in thread length mode) or a sequence of threads (in busy length mode) before the current running thread is forced to end. for more information on watchdog operation, see section , watchdog . the tst microcycles are also counted by the watchdog. table 450. etpu_wdtr field description (continued) field description offset: etpu_a: etpu_base + 0x068; etpu_b: etpu_base + 0x078 access: user read/write 0 1 2345678 9101112131415 r idle_cnt[31:16] w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r idle_cnt[15:0] w iclr reset0 0 00000000000000 = unimplemented or reserved table 451. etpu_idle field description field description 0-31 idle_cnt[31:0]?idle count this is a freerunning count of the number of idle microcycles in the microengine. for more information on idle counter operation, see section , idle counter . enhanced time processing unit (etpu2) RM0029 820/1740 doc id 15177 rev 8 31 iclr?idle clear this write-only bit is used to clear the idle count idle_cnt. 1: clear the idle count idle_cnt 0: do not clear idle count idle_cnt table 451. etpu_idle field description (continued) field description RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 821/1740 24.4.5 channel registers layout the channel registers area is shown in figure 503 and detailed in the next sections for etpu systems of 32 channels per engine. reserved areas are placed to allow doubling the number of channels to 64 for each etpu engine. figure 503. channel registers area 24.4.6 global channel registers the registers in this section group, by type, the interrupt status and enable bits from all the channels. this organization eases management of all channels or groups of channels by a single interrupt handler routine. these bits, except the service and watchdog status, are mirrored in the individual channel registers, grouped by channel. global channel registers reserved engine 1 channel registers reserved engine 2 channel registers reserved 0x200 0x26c 0x400 0x600 0x800 0xa00 enhanced time processing unit (etpu2) RM0029 822/1740 doc id 15177 rev 8 etpu_cisr ? etpu channel interrupt status register host interrupt status (see section , interrupts and data transfer requests ) from all channels are grouped in etpu_cisr. their bits are mirrored from the channel status/control registers (see section 24.4.7, channel configuration and control registers ) and host must write 1 to clear a status bit. figure 504. etpu_cisr register etpu_cdtrsr ? etpu channel data transfer request status register data transfer request status (see section , interrupts and data transfer requests ) from all channels are grouped in etpu_cdtrsr. their bits are mirrored from the channel status/control registers (see section , etpu_cxscr ? etpu channel x status control register ). offset: etpu_a: etpu_base + 0x200; etpu_b: etpu_base + 0x204 access: user read/write 0 1 2345678 9101112131415 r cis3 1 cis3 0 cis2 9 cis2 8 cis2 7 cis2 6 cis2 5 cis2 4 cis2 3 cis2 2 cis2 1 cis2 0 cis1 9 cis1 8 cis1 7 cis1 6 w cic3 1 cic3 0 cic2 9 cic2 8 cic2 7 cic2 6 cic2 5 cic2 4 cic2 3 cic2 2 cic2 1 cic2 0 cic1 9 cic1 8 cic1 7 cic1 6 reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cis1 5 cis1 4 cis1 3 cis1 2 cis1 1 cis1 0 cis9 cis8 cis7 cis6 cis5 cis4 cis3 cis2 cis1 cis0 w cic1 5 cic1 4 cic1 3 cic1 2 cic1 1 cic1 0 cic9 cic8 cic7 cic6 cic5 cic4 cic3 cic2 cic1 cic0 reset0 0 00000000000000 = unimplemented or reserved table 452. etpu_cisr field description field description 0-31 cisx?channel x interrupt status 1: indicates that channel x has a pending interrupt to the host cpu. 0: indicates that channel x has no pending interrupt to the host cpu. 0-31 cicx?channel x interrupt clear 1: clear interrupt status bit. 0: keep interrupt status bit unaltered. for details about interrupts see section , channel interrupt and data transfer requests . RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 823/1740 figure 505. etpu_cdtrsr register etpu_ciosr ? etpu channel interrupt overflow status register interrupt overflow status (see section , interrupts and data transfer requests ) from all channels is grouped in the etpu_ciosr. their bits are mirrored from the channel offset: etpu_a: etpu_base + 0x210; etpu_b: etpu_base + 0x214 access: user read/write 0 1 2345678 9101112131415 r dtr s 31 dtr s 30 dtr s 29 dtr s 28 dtr s 27 dtr s 26 dtr s 25 dtr s 24 dtr s 23 dtr s 22 dtr s 21 dtr s 20 dtr s 19 dtr s 18 dtr s 17 dtr s 16 w dtr c 31 dtr c 30 dtr c 29 dtr c 28 dtr c 27 dtr c 26 dtr c 25 dtr c 24 dtr c 23 dtr c 22 dtr c 21 dtr c 20 dtr c 19 dtr c 18 dtr c 17 dtr c 16 reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dtr s 15 dtr s 14 dtr s 13 dtr s 12 dtr s 11 dtr s 10 dtr s 9 dtr s 8 dtr s 7 dtr s 6 dtr s 5 dtr s 4 dtr s 3 dtr s 2 dtr s 1 dtr s 0 w dtr c 15 dtr c 14 dtr c 13 dtr c 12 dtr c 11 dtr c 10 dtr c 9 dtr c 8 dtr c 7 dtr c 6 dtr c 5 dtr c 4 dtr c 3 dtr c 2 dtr c 1 dtr c 0 reset0 0 00000000000000 = unimplemented or reserved table 453. etpu_cdtrsr field description field description 0-31 dtrsx?channel x data transfer request status these bits mimic the corresponding etpu dma requests. dtrsx can be cleared by software (writing 1 to dtrcx) or by the assertion of corresponding dma completion acknowledge line. 1: indicates that channel x has a pending data transfer request. 0: indicates that channel x has no pending data transfer request. 0-31 dtrcx?channel x data transfer request clear 1: clear status bit. 0: keep status bit unaltered for details about interrupts see section , channel interrupt and data transfer requests . enhanced time processing unit (etpu2) RM0029 824/1740 doc id 15177 rev 8 status/control registers (see section , etpu_cxscr ? etpu channel x status control register ) and a write of ?1? clears a status bit. figure 506. etpu_ciosr register offset: etpu_a: etpu_base + 0x220; etpu_b: etpu_base + 0x224 access: user read/write 0 1 2345678 9101112131415 r cios 31 cios 30 cios 29 cios 28 cios 27 cios 26 cios 25 cios 24 cios 23 cios 22 cios 21 cios 20 cios 19 cios 18 cios 17 cios 16 w cioc 31 cioc 30 cioc 29 cio c 28 cio c 27 cio c 26 cio c 25 cio c 24 cioc 23 cioc 22 cio c 21 cio c 20 cio c 19 cio c 18 cio c 17 cio c 16 reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cios 15 cios 14 cios 13 cios 12 cios 11 cios 10 cios 9 cios 8 cios 7 cios 6 cios 5 cios 4 cios 3 cios 2 cios 1 cios 0 w cioc 15 cioc 14 cioc 13 cio c 12 cio c 11 cio c 10 cio c 9 cio c 8 cioc 7 cioc 6 cio c 5 cio c 4 cio c 3 cio c 2 cio c 1 cio c 0 reset0 0 00000000000000 = unimplemented or reserved table 454. etpu_ciosr field description field description 0-31 ciosx?channel x interrupt overflow status 1: indicates that interrupt overflow occurred in the channel. 0: indicates that no interrupt overflow occurred in the channel. 0-31 ciocx?channel x interrupt overflow clear 1: clear status bit. 0: keep status bit unaltered. for details about interrupt overflow, see section , interrupt and data transfer request overflow . RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 825/1740 etpu_cdtrosr ? etpu channel data transfer request overflow status register data transfer request overflow status (see section , interrupts and data transfer requests ) from all channels is grouped in the etpu_cdtrosr. their bits are mirrored from the channel status/control registers (see section , etpu_cxscr ? etpu channel x status control register ) and a write of ?1? clears a status bit. figure 507. etpu_cdtrosr register offset: etpu_a: etpu_base + 0x230; etpu_b: etpu_base + 0x234 access: user read/write 0 1 2345678 9101112131415 r dtr os 31 dtr os 30 dtr os 29 dtr os 28 dtr os 27 dtr os 26 dtr os 25 dtr os 24 dtr os 23 dtr os 22 dtr os 21 dtr os 20 dtr os 19 dtr os 18 dtr os 17 dtr os 16 w dtr oc 31 dtr oc 30 dtr oc 29 dtr oc 28 dtr oc 27 dtr oc 26 dtr oc 25 dtr oc 24 dtr oc 23 dtr oc 22 dtr oc 21 dtr oc 20 dtr oc 19 dtr oc 18 dtr oc 17 dtr oc 16 reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dtr os 15 dtr os 14 dtr os 13 dtr os 12 dtr os 11 dtr os 10 dtr os 9 dtr os 8 dtr os 7 dtr os 6 dtr os 5 dtr os 4 dtr os 3 dtr os 2 dtr os 1 dtr os 0 w dtr oc 15 dtr oc 14 dtr oc 13 dtr oc 12 dtr oc 11 dtr oc 10 dtr oc 9 dtr oc 8 dtr oc 7 dtr oc 6 dtr oc 5 dtr oc 4 dtr oc 3 dtr oc 2 dtr oc 1 dtr oc 0 reset0 0 00000000000000 = unimplemented or reserved table 455. etpu_cdtrosr field description field description 0-31 dtrosx?channel x data transfer request overflow status 1: indicates that data transfer request overflow occurred in the channel. 0: indicates that no data transfer request overflow occurred in the channel. 0-31 dtrocx?channel x data transfer request overflow clear 1: clear status bit. 0: keep status bit unaltered. for details about data transfer request overflow, see section , interrupt and data transfer request overflow . enhanced time processing unit (etpu2) RM0029 826/1740 doc id 15177 rev 8 etpu_cier ? etpu channel interrupt enable register host interrupt enable (see section , interrupts and data transfer requests ) from all channels are grouped in etpu_cier. their bits are mirrored from the channel configuration registers (see section , etpu_cxcr ? etpu channel x configuration register ). figure 508. etpu_cier register offset: etpu_a: etpu_base + 0x240; etpu_b: etpu_base + 0x244 access: user read/write 0 1 2345678 9101112131415 r cie 31 cie 30 cie 29 cie 28 cie 27 cie 26 cie 25 cie 24 cie 23 cie 22 cie 21 cie 20 cie 19 cie 18 cie 17 cie 16 w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cie 15 cie 14 cie 13 cie 12 cie 11 cie 10 cie 9 cie 8 cie 7 cie 6 cie 5 cie 4 cie 3 cie 2 cie 1 cie 0 w reset0 0 00000000000000 = unimplemented or reserved table 456. etpu_cier field description field description 0-31 ciex?channel x interrupt enable 1: interrupt enabled for channel x 0: interrupt disabled for channel x. for details about interrupts see section , channel interrupt and data transfer requests . RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 827/1740 etpu_cdtrer ? etpu channel data transfer request enable register data transfer request enable (see section , interrupts and data transfer requests ) from all channels are grouped in etpu_cdtrer. these bits are mirrored from the channel configuration registers (see section , etpu_cxcr ? etpu channel x configuration register ). figure 509. etpu_cdtrer register offset: etpu_a: etpu_base + 0x250; etpu_b: etpu_base + 0x254 access: user read/write 0 1 2345678 9101112131415 r dtre 31 dtre 30 dtre 29 dtr e 28 dtr e 27 dtr e 26 dtr e 25 dtr e 24 dtre 23 dtre 22 dtr e 21 dtr e 20 dtr e 19 dtr e 18 dtr e 17 dtr e 16 w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dtre 15 dtre 14 dtre 13 dtr e 12 dtr e 11 dtr e 10 dtr e 9 dtr e 8 dtre 7 dtre 6 dtr e 5 dtr e 4 dtr e 3 dtr e 2 dtr e 1 dtr e 0 w reset0 0 00000000000000 = unimplemented or reserved table 457. etpu_cdtrer field description field description 0-31 dtrex?channel x data transfer request enable 1: data transfer request enabled for channel x. 0: data transfer request disabled for channel x. for details about interrupts see section , channel interrupt and data transfer requests . enhanced time processing unit (etpu2) RM0029 828/1740 doc id 15177 rev 8 etpu_cpssr ? etpu channel pending service status register etpu_cpssr is a read-only register that holds the status of the pending channel service requests (see section 24.5.1, functions and threads ). figure 510. etpu_cpssr register etpu_cssr ? etpu channel service status register etpu_cssr holds the current channel service status on whether it is being serviced or not (see section 24.5.1, functions and threads ). only one bit may be asserted in this register at a given time. when no channel is being serviced the register read value is 0x00000000. etpu_cssr is a read-only register. the register can be read during normal etpu operation for monitoring the scheduler activity. offset: etpu_a: etpu_base + 0x280; etpu_b: etpu_base + 0x284 access: user read 0 1 2345678 9101112131415 r sr31 sr30 sr29 sr28 sr27 sr26 sr25 sr24 sr23 sr22 sr21 sr20 sr19 sr18 sr17 sr16 w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 w reset0 0 00000000000000 = unimplemented or reserved table 458. etpu_cpssr field description field description 0-31 srx?pending service request x indicates a pending service request for channel x. 1: pending service request for channel x 0: no service request pending for channel x pending sr status is a logic or of all service requests pending: if only hsr is active, srx clears only at the end of the thread. srx clear due to the other request sources is microcode dependent. the pending service status bit for a channel is 1 when a service request is pending, even if the channel is disabled (cprx = 0). there can be a delay of one clock between writing hsr > 0 in register etpu_cxhsrr of a channel and its respective bit being asserted in etpu_cpssr. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 829/1740 note: channel service status does not always reflect decoding of the chan register, since the later can be changed by the service thread microcode. figure 511. etpu_cssr register offset: etpu_a: etpu_base + 0x290; etpu_b: etpu_base + 0x294 access: user read 0 1 2345678 9101112131415 r ss31 ss30 ss29 ss28 ss27 ss26 ss25 ss24 ss23 ss22 ss21 ss20 ss19 ss18 ss17 ss16 w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ss15 ss14 ss13 ss12 ss11 ss10 ss9 ss8 ss7 ss6 ss5 ss4 ss3 ss2 ss1 ss0 w reset0 0 00000000000000 = unimplemented or reserved table 459. etpu_cssr field description field description 0-31 ssx?service status x indicates that channel x is currently being serviced. it is updated at the 1st microcycle of a time slot transition (see section , time slot transition ), or when the microengine ends the thread. 1: channel x is currently being serviced 0: channel x is not currently being serviced enhanced time processing unit (etpu2) RM0029 830/1740 doc id 15177 rev 8 24.4.7 channel configurat ion and control registers each channel has a group of three registers used to control, configure and check status of that channel as shown in ta ble 46 0 . this organization eases individual channel management. note: 1.a bus error is issued on read or write accesses to these registers when etpu_ecr bit mdis = 1. writes are ineffective on bus error. 2. the siu_isel8 register is used to multiplex the etpu[24:29] inputs. when siu_sel8 is in its default state etpu channels 24?29 will not be connected to their respective output pin, irrespective of the siu_pcr[pa] field. see section 16.6.22, imux select register 8 (siu_isel8) . one contiguous area is used to map all channel registers of each etpu engine as shown in ta ble 46 1 . table 460. channel registers structure channel offset register name 0x00 etpu_cxcr ? etpu channel configuration register 0x04 etpu_cxscr ? etpu channel status/control register 0x08 etpu_cxhsrr ? etpu channel host service request register 0x0c reserved table 461. channel registers map offset registers structure 0x400 etpu 1 channel 0 registers structure 0x410 etpu 1 channel 1 registers structure 0x420 etpu 1 channel 2 registers structure 0x430 . . 0x5e0 etpu 1 channel 30 registers structure 0x5f0 etpu 1 channel 31 registers structure 0x600 reserved 0x800 etpu 2 channel 0 registers structure 0x810 etpu 2 channel 1 registers structure 0x820 . . 0x9e0 etpu 2 channel 30 registers structure 0x9f0 etpu 2 channel 31 registers structure 0xa00 reserved RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 831/1740 there are 64 structures defined, one for each available channel in the etpu system (32 for each engine). the base address for the structure presented can be calculated by using the following equation: channel_register_base = etpu_engine_channel_base + (channel_number * 0x10) where: etpu_engine_channel_base = etpu_base + 0x400 for engine 1 etpu_engine_channel_base = etpu_base + 0x800 for engine 2 enhanced time processing unit (etpu2) RM0029 832/1740 doc id 15177 rev 8 etpu_cxcr ? etpu channel x configuration register etpu_cxcr gathers configurations set individually per channel. figure 512. etpu_cxcr register offset: channel_register_base + 0x0 access: user read/write 0 1 2345678 9101112131415 r cie dtre cpr 00 etpd etcs 000 cfs w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r odis opol 000 cpba w reset0 0 00000000000000 = unimplemented or reserved table 462. etpu_cxcr field description field description 31 cie?channel interrupt enable (this bit is mirrored from etpu_cier ? see section , etpu_cier ? etpu channel interrupt enable register .) 1: enable interrupt for this channel. 0: disable interrupt for this channel. see section , channel interrupt and data transfer requests . 30 dtre?channel data transfer request enable (this bit is mirrored from etpu_cdtrer ? see section , etpu_cdtrer ? etpu channel data transfer request enable register .) 1: enable data transfer request for this channel. 0: disable data transfer request for this channel. see section , channel interrupt and data transfer requests . RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 833/1740 2-3 cpr[1:0]?channel priority this field defines the priority level for the channel, used by the hardware scheduler (see section 24.5.3, scheduler ). 00: disabled 01: low 10: middle 11: high 4-5 reserved 6 etpd?entry table pin direction this bit selects which channel signal, input or output, is used in the entry point selection. the etpd value has to be compatible with the function chosen for the channel, selected in the field cfs. for details about entry table and condition encoding schemes, refer to section , entry points . 1: use psto for entry point selection. 0: use psti for entry point selection. 7 etcs?entry table condition select this bit determines the channel condition encoding scheme that selects, according to channel conditions, the entry point to be taken in an entry table. etcs value has to be compatible with the function chosen for the channel, selected in field cfs. two condition encoding schemes are available. for details about entry table and condition encoding schemes, refer to section , entry points . 1: select alternate entry table condition encoding scheme. 0: select standard entry table condition encoding scheme. the fields etcs, cfs and cpba must only be changed while the channel is disabled (field cpr = 00). 8-10 reserved 11-15 cfs[4:0]?channel function select this field defines the function to be performed by the channel (see section 24.5.1, functions and threads ). the function assigned to the channel has to be compatible with the channel condition encoding scheme, selected by field etcs. the fields etcs, cfs and cpba must only be changed while the channel is disabled (field cpr = 00). table 462. etpu_cxcr field description field description enhanced time processing unit (etpu2) RM0029 834/1740 doc id 15177 rev 8 16 odis?output disable this bit enables the channel to have its output forced to the value opposite to opol when the output disable input signal corresponding to the channel group that it belongs is active. see section , ipp_ind_etpu_odis_[1|2]([0 ? 3]) etpu channel output disable signals and figure 528 . 1: turns on the output disable feature for the channel 0: turns off the output disable feature for the channel. 17 opol?output polarity determines the output signal polarity. the activation of the output disable signal forces, when enabled by the odis bit, the channel output signal to the opposite of this polarity (see figure 528 ). 1: output active high (output disable drives output to low) 0: output active low (output disable drives output to high) 18-20 reserved 21-31 cpba[10:0]?channel x parameter base address the value of this field times 8 specifies the spram parameter base host (byte) address for channel x (2- parameter granularity; see section , spram organization ). as seen by the host, the channel parameter base (byte) address is: without parameter sign extension: etpu_base + 0x8000 + cpba*8 with parameter sign extension: etpu_base + 0xc000 + cpba*8 the fields etcs, cfs and cpba must only be changed while the channel is disabled (field cpr = 00). table 462. etpu_cxcr field description field description RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 835/1740 etpu_cxscr ? etpu channel x status control register etpu_cxscr gathers the interrupt status bits of the channel, and also the function mode definition (read-write). bits cis, cios and dtrs for each channel can be also accessed from etpu_cisr, etpu_ciosr and etpu_cdtrsr registers respectively (see section 24.4.6, global channel registers ). host must write 1 to clear a status bit. figure 513. etpu_cxscr register offset: channel_register_base + 0x4 access: user read/write 0 1 2345678 9101112131415 r cis cios 0 0 0 0 0 0 dtrs dtr os 000000 wcic cioc dtrc dtr oc reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ripsopsobe00000000000 fm w reset 0/1 (1) 0 00000000000000 = unimplemented or reserved 1. the ips value after reset is mcu dependent table 463. etpu_cxscr field description field description 31 cis?channel interrupt status 1: channel has a pending interrupt to the host cpu. 0: channel has no pending interrupt to the host cpu. 31 cic?channel interrupt clear 1: clear interrupt status bit. 0: keep interrupt status bit unaltered. these bits are mirrored in etpu_cisr ? see section , etpu_cisr ? etpu channel interrupt status register . see also section , channel interrupt and data transfer requests . 30 cios?channel interrupt overflow status 1: interrupt overflow asserted for this channel 0: interrupt overflow negated for this channel enhanced time processing unit (etpu2) RM0029 836/1740 doc id 15177 rev 8 30 cioc?channel interrupt overflow clear 1: clear status bit. 0: keep status bit unaltered. these bits are mirrored in etpu_ciosr ? see section , etpu_ciosr ? etpu channel interrupt overflow status register . see also section , interrupt and data transfer request overflow . 2-7 reserved 8 dtrs?data transfer request status 1: channel has a pending data transfer request. 0: channel has no pending data transfer request. 8 dtrc?data transfer request clear 1: clear status bit. 0: keep status bit unaltered these bits are mirrored in etpu_cisr ? see section , etpu_cdtrsr ? etpu channel data transfer request status register . see also section , channel interrupt and data transfer requests . 9 dtros?data transfer request overflow status 1: data transfer request overflow asserted for this channel data transfer request overflow negated for this channel 9 dtroc?data transfer request overflow clear 1: clear status bit. keep status bit unaltered. these bits are mirrored in etpu_cdtrosr ? see section , etpu_cdtrosr ? etpu channel data transfer request overflow status register . see also section , interrupt and data transfer request overflow . 10-15 reserved 16 ips?channel input pin state this bit shows the current value of the filtered channel input signal state 17 ops?channel output pin state this bit shows the current value driven in the channel output signal, including the effect of the external output disable feature (see section , ipp_ind_etpu_odis_[1|2]([0 ? 3]) etpu channel output disable signals . if the channel input and output signals are connected to the same pad, ops reflects the value driven to the pad (if obe = 1). this is not necessarily the actual pad value, which drives the value in the bit ips. table 463. etpu_cxscr field description field description RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 837/1740 18 obe?output buffer enable this bit shows the state of the channel output buffer enable signal, controlled by microcode. 19-29 reserved 30-31 fm[1:0]?channel function mode (1) each function uses this field for specific configuration. these bits can be tested by microengine code (see section , conditional/unconditional branch ). 1. these bits are equivalent to the tpu/tpu2/tpu3 host sequence (hsq) bits. table 463. etpu_cxscr field description field description enhanced time processing unit (etpu2) RM0029 838/1740 doc id 15177 rev 8 etpu_cxhsrr ? etpu channel x host service request register etpu_cxhsrr is used by the host to issue service requests to the channel. figure 514. etpu_cxhsrr register offset: channel_register_base + 0x8 access: user read/write 0 1 2345678 9101112131415 r0 0 00000000000000 w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 00000000000 hsr w reset0 0 00000000000000 = unimplemented or reserved table 464. etpu_cxhsrr field description field description 0-28 reserved 29-31 hsr[2:0]?host service request this field is used by the host cpu to request service to the channel (see section , host service requests ). hsr = 000: no host service request pending hsr > 000: function-dependent host service request pending. hsr value turns to 000 automatically at the end of microengine service for that channel, but only if the thread started due to an hsr. host should write hsr > 0 only when hsr = 0. writing hsr = 000 withdraws a pending request if scheduler did not begin to resolve the entry point yet, but it does not abort the service thread from that point on. for more details, see section , entry points , and section , host service requests . RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 839/1740 24.5 functional description 24.5.1 functions and threads etpu processing is event-driven, in the sense that etpu microcode only runs to service a request from an event. service requests may result from the occurrence of any of the following events: host cpu writing a non-zero value to the channel hsr (host service request) field in etpu_cxhsr. occurrence of a time base match, an input signal transition, or a specific combination of them (depending on the channel mode currently configured). a link service request. a given event is always associated to only one channel: there is one hsr register field for each channel each signal is associated with only one channel, which has its own match registers and independent mode configuration. each link service request can have only one channel as a target. service request processing is done by a set of microengine routines. a set of related routines that implement a specific channel application is called a function . one or more functions reside on scm, limited only by the scm space available, size of microcode functions and the number of entry points available. each engine can be controlled by up to 32 functions at a time. a function can be assigned to several channels, but only one function can be assigned to a given channel at a time. this is defined by the host through the channel configuration registers (see section 24.4.7, channel configuration and control registers ). the term thread will be used hereafter to refer to a service routine of a function, or its execution. a thread is constructed of a specific number of microinstructions, typically the code necessary to calculate the next phase of waveform to be input to, or output from, a given channel. once a thread begins, its execution cannot be interrupted. a thread normally finishes when an end microinstruction is executed. a given thread is selected and called by the scheduler depending on the following: the type of event that generated the service request. the function assigned to the target channel. target channel pin state. the state of the channel logic. the priority assigned to the target channel, relative to the priorities of other channels with pending service requests the mechanism to select a thread based on the channel function and type of event is described in the section , entry points . the priority mechanism that determines the order of thread execution amongst pending service requests is described in section 24.5.3, scheduler . enhanced time processing unit (etpu2) RM0029 840/1740 doc id 15177 rev 8 entry points entry table each thread has its entry point , which contains the scm address of its first instruction, besides other information. for a complete entry point description, see section , entry point format . once the scheduler chooses a channel among pending service requests, the entry point is taken from an entry table , based on the function assigned for the channel and other conditions. entry table layout is shown in figure 515 . figure 515. entry table the entry table is organized by functions. each function can have up to 32 entry points of 16 bits each, corresponding to 32 possible threads per function. each entry point location in the table corresponds to a combination of events and channel states (see section , entry point address generation ). a single thread can be associated to more than one combination, having its entry point repeated in the table. each 32-bit word in the entry table holds two entry points. note that the entry table can be placed in any scm address multiple of the entry table size, determined by the field etb[4:0] in the register etpu_ecr. however, it is recommended to place the entry table at the start of the scm to get continuous code memory and to ease the eventual migration of the code from larger parts down to smaller ones without rearranging the binary image, but this is not a restriction. unused entry points may be used for microcode, so this organization extends the microcode continuous area to the unused area of the entry table. for this purpose, function numbers should be selected from 0 up to 31. if, for example, only 8 functions are implemented, only the entry table code 01ff 03ff 05ff code addr. host addr. scm 7fc ffc 17fc 07ff 1ffc 09ff 0bff 0dff 0fff 27fc 2ffc 37fc 3ffc function 0 entry points 0-31 function 1 entry points 0-31 function 2 entry points 0-31 function 31 entry points 0-31 0,0 0,1 0,30 0,31 1,0 1,1 1,30 1,31 2,0 2,1 2,30 2,31 31,0 31,1 31,30 31,31 32 bits entry table organization 0e00 0e10 0e20 0e30 0ff0 0e0f 0e1f 0e2f 0fef 0fff code addr. entry table 0e00 11ff 13ff 15ff 47fc 4ffc 57fc 17ff 5ffc 19ff 1bff 1dff 1fff 67fc 6ffc 77fc 7ffc code RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 841/1740 locations for functions 0 to 7 are used, and the entry table locations for functions 8 to 31 can be used as microinstruction memory (adding extra continuous 1536 bytes for microprogram usage). one way of implementing different sets of functions is having more than one entry table, and configuring the etpu with the appropriate one for the application by changing field etpu_ecr[etb]. note that the engines can use different entry tables, with or without the same set of functions. entry point address generation the entry point address within the entry table is determined by the function assigned to the channel, the state of the channel, the type of event, and the condition encoding scheme. together with the entry table base address, they form the entry point address at the scm, as shown in figure 516 . figure 516. entry point address (host address offset) the type of event and channel state are coded in the encoded channel conditions field c[4:0], according to one of two encoding schemes: standard entry table condition encoding scheme, shown in table 465 , which privileges host service requests. alternate entry table condition encoding scheme, shown in table 466 , which focus on other events and state decoding. the events that take part on condition encoding generate a service request, and have four origins: 1. match recognition (caused by greater/equal match, or equal-only, between the value tcr1/2 and the value stored in the channel match registers). etpu channels support single and double match in various modes of match recognition; see section , match recognition . 2. transition detect service request (channel input signal transition detection of a selected edge). the etpu channels support single and double transition, which together with the double match options provide various modes of transition detection; see section , transition detection and time base capture . 3. channel linking service request (microcode writing the channel number to the link register). link service request allows one channel to activate another (see section , channel link ). 4. host service request (host writes a non-zero value to the hsr bits of the channel; see section , host service requests ). etb[4:0] (etpu_ecr) (etpu_cxcr) encoded (c4-c1) channel conditions cfs[4:0] encoded (c0) channel conditions a5-a2 a10-a6 a1 a15-a11 half-word select word address a0 = 0 enhanced time processing unit (etpu2) RM0029 842/1740 doc id 15177 rev 8 note: even if a transition or match service request is inhibited (by channel mode/state or sri), the transition detection and match recognition are taken into account for condition encoding. that is, the mrla/b and tdla/b flags are used, not their respective service requests. columns host request bits, link request, matcha/transb, and matchb/transa determine the type of event. a non-zero value in these columns represents the recognition of the event, while ?x? indicates that its recognition is irrelevant. values 1 and 0 mean that event was recognized or not, respectively. note that match and transition events may occur and not be recognized, and in this case it assumes value 0 for the condition encoding. the recognition of such an occurred event depends on the channel mode assigned and other conditions, as described in section 24.5.5, enhanced channels . the host service request bits column refers to the value written by the host cpu to the host service request register (etpu_cxhsrr) of the channel being serviced. note that the bits on this row are coded (3-bit representation). if the value of hsr is not zero, then the host actually requested service. the link request column refers to the occurrence of a channel link request. the matcha/transb column refers to the recognition of either a match event specified by matcha channel register or the detection of a channel input signal event specified by the ipacb configuration register (see section , pin control registers ). the matchb/transa column refers to the recognition of either a match event specified by matchb channel register or the detection of a channel input signal event specified by the ipaca configuration register (see section , pin control registers ). for the channel input signal, matcha and matchb provide double timeout conditions which depend on the channel mode programming (see section , channel modes ). if the channel is used for output only, there are no transition detections, so the matchb/transa column represents only match b, and matcha/transb column the match a. in this case match a and match b are separated to give better state resolution in double match output functions. for more information about channel requests refer to section 24.5.5, enhanced channels . besides those events, the following channel state conditions help to determine the entry point: 1. channel flags 0 and 1: these are channel-internal flags (not in spram) associated with a channel. their values are set by microcode (see section , channel flags operations ). 2. input pin state or output flip flop: the state (0 or 1) of the channel input signal after the enhanced filter (see section , enhanced digital filter ? edf ), or the state driven to the output signal. which one (input or output) is used is selected by the etpu_cxcr bit etpd. the two entry table condition encoding schemes combine events and state conditions differently, as detailed in the following sections. standard condition encoding scheme in this scheme, shown in table 465 , all seven hsr combinations are used and other event type columns are marked ?x? when hsr is non-zero, indicating that host service request has priority over any other type of event. however, when an hsr service thread is called (entry numbers 0 to 9), other events may also have been recognized, and it is microcode responsibility to check them. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 843/1740 when hsr is 0, i.e., host did not issue a service request to the channel, the other event conditions, the input signal state and channel flags determine the entry point. note that channel flag 1 does not influence the encoding in this scheme. table 465. standard channel condition encoding scheme no. encoded channel conditions [c4-c0] host service request bits link request matcha / transb match.2 / transa in/output pin state (1) channel flag1 channel flag0 0 00000 001 x x x 0 x 0 1 00001 001 x x x 0 x 1 2 00010 001 x x x 1 x 0 3 00011 001 x x x 1 x 1 4 00100 010 x x x x x x 5 00101 011 x x x x x x 6 00110 100 x x x x x x 7 00111 101 x x x x x x 8 01000 110 x x x x x x 9 01001 111 x x x x x x 10 01010 000 1 11 xx 0 11 01011 000 1 11 xx 1 12 01100 000 0 0 1 0x0 13 01101 000 00 10 x 1 14 01110 000 00 11 x 0 15 01111 000 00 11 x 1 16 10000 000 0 10 0x0 17 10001 000 0 100 x 1 18 10010 000 0 101 x 0 19 10011 000 0 101 x 1 20 10100 000 0 11 0x0 21 10101 000 0 110 x 1 22 10110 000 0 111 x 0 23 10111 000 0 111 x 1 enhanced time processing unit (etpu2) RM0029 844/1740 doc id 15177 rev 8 alternate condition encoding scheme this scheme is shown in table 466 . because the hsr bits cannot be tested by microcode, only three distinct host service request can be used: 1. hsr = 010 or 011, which are coded into the same entry points (0 to 3) 2. hsr = 100,101 or 001, which are all coded into entry point 4 3. hsr = 110 or 111, which are both coded into entry point 5 the remaining entry points use both channel flags for better state decoding, making this scheme better suited for functions which need more states and/or faster state decoding, without needing many hsrs. 24 11000 000 1 0 0 0x0 25 11001 0001000 x 1 26 11010 0001001 x 0 27 11011 0001001 x 1 28 11100 000 1 0 1 xx0 29 11101 000 1 0 1 xx 1 30 11110 000 1 1 0xx 0 31 11111 000 1 1 0 xx 1 host service request 1. the etpu_cxcr bit etpd selects between input and output pin state. table 465. standard channel condition encoding scheme (continued) no. encoded channel conditions [c4-c0] host service request bits link request matcha / transb match.2 / transa in/output pin state (1) channel flag1 channel flag0 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 845/1740 table 466. alternate channel condition encoding scheme no. encoded channel conditions [c4-c0] host service request bits link request matcha / transb match.2 / transa in/output pin state (1) channel flag1 channel flag0 0 00000 01x x x x 0 x 0 1 00001 01x x x x 0 x 1 2 00010 01x x x x 1 x 0 3 00011 01x x x x 1 x 1 4 00100 10x/001 x x x x x x 5 00101 11x x x x x x x 6 00110 000 1 000xx 700111 000 1 001xx 8 01000 000 x 100 00 9 01001 000 x 10001 10 01010 000 x 10010 11 01011 000 x 10011 12 01100 000 x 101 00 13 01101 000 x 10101 14 01110 000 x 10110 15 01111 000 x 10111 16 10000 000 x 010 00 17 10001 000 x 01001 18 10010 000 x 01010 19 10011 000 x 01011 20 10100 000 x 011 00 21 10101 000 x 01101 22 10110 000 x 01110 23 10111 000 x 01111 24 11000 000 x 110 00 25 11001 000 x 11001 enhanced time processing unit (etpu2) RM0029 846/1740 doc id 15177 rev 8 entry point format entry point information includes a preload-parameter selection field, a match enable field, and the first microcode address of the thread. the entry point format is illustrated in figure 517 . figure 517. entry point format pp?preload parameter 26 11010 000 x 11010 27 11011 000 x 11011 28 11100 000 x 111 00 29 11101 000 x 11101 30 11110 000 x 11110 31 11111 000 x 11111 host service request 1. the etpu_cxcr bit etpd selects between input and output pin state. table 466. alternate channel condition encoding scheme (continued) no. encoded channel conditions [c4-c0] host service request bits link request matcha / transb match.2 / transa in/output pin state (1) channel flag1 channel flag0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pp me microcode address field description 0-13 microcode address microcode address this field specifies the microcode address on which the thread is to begin execution RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 847/1740 time slot transition the time slot transition period (also called tst for short) is the interval between the servicing of two channels, during which all channel-specific context is loaded for the new serviced channel. the primary tasks completed during this period include: set mef for the first microcycle plus eventual wait-states. reset the mef for one microcycle after the first microcycle plus wait-states. update of the chan register with the number of the new channel to be serviced. parallel update of erta and ertb from capturea and captureb registers of the new serviced channel. sampling of the branch conditions of the new channel to be serviced into the branch logic (this means flags tdla/b, mrla/b, lsr, fm[1], fm[0], and pss). the branch conditions are coherent with the timebase capture values sampled into erta/b (if mrla/b, tdla/b are set at the same time of the sampling, either both old flag state and capture values are sampled, or both new values are sampled). formation of the entry point address. copy the me bit in the entry point into mef. access to the entry point location and getting the first microinstruction address. preload of two parameters from the spram into p (32 bits) and diob (24 bits). fetch the first instruction of the thread to be executed for the new channel. preset the rar value (see section , rar ? report address register ). 14 me match enable me specifies whether match event recognitions are enabled or disabled for the thread associated with the entry point during the thread execution. if they are disabled, a match recognition can only occur after channel service. for more details refer to section , match recognition . matches are disabled during the thread. matches are enabled during the thread. the disabling of match a/b recognition by mef is dependent on ipaca/b configuration on the serviced channel (see section , pin control registers ). if ipaca = 1xx, match a is not disabled by me = 0. likewise, ipacb = 1xx overrides the effect of me on match b to ?always on? if ipaca/b = 0xx, match a/b is disabled for one microcycle during tst (see section , time slot transition ) and is re-enabled when entry point is loaded, if me = 1. note that if the comparator is in equal-only mode and the time base reaches the value of the match register during the time that recognition is disabled (beginning of tst, plus whole thread if me = 0), the match recognition is lost. if the comparator is in greater-equal mode, the match event may be recognized after the disabling period if it satisfies the ?greater-than? condition. 15 pp preload parameter pp indicates which pair of channel parameters are loaded into registers p and diob from the spram prior to the execution of a thread. preloading occurs during the time-slot transition period (see section , time slot transition ) microengine register p is preloaded from parameter 0 and diob from parameter 1. microengine register p is preloaded from parameter 2 and diob from parameter 3. the parameter numbers are offsets from the channel parameter base address. for more info, see section , parameter access . field description enhanced time processing unit (etpu2) RM0029 848/1740 doc id 15177 rev 8 the preload operation is 32-bit wide for p and 24-bit wide for diob. the p register is loaded with all the 32-bit parameter. the diob register is loaded with the lower 24-bits of the parameter. the microcode can switch at any time to access the lower 24-bits, upper byte, or all the 32-bits of any parameter in the spram. preload of p-diob pair of parameters is atomic with respect to host and cdc accesses, and so are coherent with their dual- parameter coherent transfers. for more details see section 24.5.4, parameter sharing and coherency . no instructions are executed at the engine where the time slot transition period occurs, but the other engine can execute normally. match a/b is unconditionally disabled on the second tst microcycle, if ipaca/b = 0xx (respectively). during the rest of time slot transition, match recognition can be disabled or not, depending on ipaca/b field and me. see section , match recognition . time slot transition takes a minimum of 3 microcycles (6 system clocks), which may be extended due to spram arbitration wait-states for the first preload access (see section , spram arbitration ). when no wait-states are received ( figure 518 ), diob is preloaded twice, one for each pp value, and the correct value remains in diob when the entry point is loaded. figure 519 and figure 520 show the timing for one and two wait-states, respectively. registers b, c, d and sr are not altered by tst and keep their values from the previous thread. the values of registers a, macl and mach are not guaranteed at the thread start. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 849/1740 figure 518. tst timing ? no wait-states system clock chan register end signal erta, ertb preload pc inst spram wait t2 t4 t2 t4 t2 t4 t2 t4 t2 t4 t2 t4 t2 t4 diob end y entry addr y1st inst addr entry point y 1st inst channel x channel y x end tst1 tst2 tst3 y 3rd inst preload p diob pp=1 p entry point pp time slot transition diob pp=0 diob entry point pp y2nd inst addr mef y 1st inst y 2nd inst y 2nd inst y 3rd inst y 3rd inst addr y4th inst addr hsr sampled for flags for entry point entry point and branch condition x y enhanced time processing unit (etpu2) RM0029 850/1740 doc id 15177 rev 8 figure 519. tst timing ? 1 wait-state system clock chan register end signal erta, ertb preload hsr sampled for flags for entry point pc inst spram wait t2 t4 t2 t4 t2 t4 t2 t4 t2 t4 t2 t4 t2 t4 diob entry point and branch condition end y entry addr y1st inst addr entry point y 1st inst channel x channel y x end tst1 wait tst1 tst2 tst3 preload p time slot transition y2nd inst addr mef diob pp=1 diob pp=0 y 1st inst p entry point pp diob entry point pp x y RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 851/1740 figure 520. tst timing ? 2 wait-states for more information on channel-specific registers and flags, refer to section 24.5.5, enhanced channels . for more information on p, erta/b and diob registers refer to section , registers . thread ending threads can finish by either: an instruction with the end field active (see section , ending current thread ? end ). a forced end by host writing to the etpu_ecr bit fend (see section , etpu_ecr ? etpu engine configuration register ). a forced end caused by watchdog timeout (see section , watchdog ). system clock chan register end signal erta, ertb preload spram wait t2 t4 t2 t4 t2 t4 t2 t4 t2 t4 t2 t4 t2 t4 diob channel x channel y x end tst1 wait tst1 wait tst1 tst2 tst3 y 1st inst preload p time slot transition mef pc inst end y entry addr y1st inst addr entry point y 1st inst y2nd inst addr hsr sampled for flags for entry point entry point and branch condition diob pp=1 diob pp=0 p entry point pp diob entry point pp xy enhanced time processing unit (etpu2) RM0029 852/1740 doc id 15177 rev 8 watchdog each engine has a watchdog mechanism to prevent a thread or a sequence of threads from running too long, impacting the latency of the other channel services. the watchdog is configured through the register etpu_wdtr (see section , etpu_wdtr ? etpu watchdog timer register ). when the watchdog is enabled, an internal counter increments on each microcycle when a thread is executing. if the count is greater than the value specified in the etpu_wdtr field wdcnt and a thread is still executing, the watchdog: 1. forces an end of the thread 2. issues a global exception and sets the etpu_mcr bit wdto (see section , etpu_mcr ? etpu module configuration register ). the watchdog can be configured in one of the following modes, defining how the internal watchdog count is reset: thread length mode : the watchdog count is reset at the end of each thread. busy length mode : the watchdog count is reset when the microengine goes idle. a sequence of threads, one right after another, keeps the count running. the counter is also reinitialized when a thread is forced to end, so that a new count begins if another tst initiates at the following microcycle. the following applies to the watchdog mechanism: microcycles during tst and sdm access wait-states (on tst or instruction execution) are counted. if the watchdog count equals wdcnt in the la st microinstruction (with sdm wait-states or not) of a thread servicing a channel. if the watchdog count expires (gets greater than wdcnt) during the tst, the thread is forced end on its first instruction. the watchdog count does not wrap, so that a thread (in thread length mode) or a thread sequence (in busy length mode) that lasts for more than the maximum value of wdcnt does get a forced end. note: watchdog must not be enabled when the microengine enters halt mode. the counter does not run when the engine is stopped, and resets when the watchdog is disabled. 24.5.2 host interface system configuration system configuration registers are described in section 24.4.2, system configuration registers . detailed explanation on the configured functionalities is found throughout section 24.5, functional description , and a specification for the initial configuration sequence is found on section 24.6.1, configuration sequence . interrupts and data transfer requests interrupt types and sources each one of the etpu channels can be a source of two requests: channel interrupt request and data transfer request . channel interrupts are targeted to a host cpu. data transfer requests may be targeted to a data transfer module (e.g., a dma controller). interrupt and data transfer registers are used by the host to enable interrupts and data RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 853/1740 transfer requests, indicate their status and service them. interrupt and data transfer requests have the same sets of registers and external signals, and are handled in the same way. they differ only by the fact that data transfer requests are also cleared by the assertion of respective dma completion acknowledge line. data transfer requests can be used as another source for host interrupts at mcu integration if not used with a dma. note: interrupt and data transfer requests can be cleared even when engines are in module disable mode, through the global channel registers, and also dma completion for data transfer requests. channel interrupts and data transfer requests can only be issued by etpu microcode, through one of the channel control instruction fields (see section , channel interrupt and data transfer requests ). both channel interrupt and data transfer requests can be individually enabled for each channel. etpu interrupt and data transfer registers are mirrored in two organizations: grouped by channel and grouped by type (interrupt status, interrupt enable, data transfer status, data transfer enable). this allows either ?channel-oriented? or ?bundled channel? host interrupt service schemes, or a combination of them. for a detailed description, refer to section 24.4.5, channel registers layout , and section 24.4.6, global channel registers . etpu can also assert a global exception interrupt indicating a global illegal state. there are three possible sources for a global exception: execution of an illegal instruction by the microengine (see section , illegal instructions ). this global exception source is flagged by the bits ilf1 and ilf2 in register etpu_mcr. an scm signature mismatch detected by the multiple input signature calculator (misc). see section , scm test ? multiple input signature calculator . this source is flagged by the bit scmmisf in register etpu_mcr. microcode request, through microinstruction field circ (see section , channel interrupt and data transfer requests ). this global exception source is flagged by bits mge1(engine 1) and mge2(engine 2) in register etpu_mcr. the cause of this illegal state is application-dependent. the microcode may write an error code into the spram to indicate the cause of the exception, for instance. an sdm or scm non-correctable error due to a microengine access global exceptions cannot be directly disabled within etpu, except by disabling its sources (misc and microcode), and it is cleared by writing 1 to the gec bit in etpu_mcr. clearing global exception clears all global exception source status bits (ilf1, ilf2, scmmisf, mge1, mge2). if gec is written 1 at the same time any of the sources issues a global exception, both the interrupt and the status bit of that source remains asserted. the assertion of global exception by one of the sources above does not prevent the others from asserting it too, so any number of them, in any combination, can be flagged. note: there can be a race between the clear of a global exception and occurrence of a new set condition, such that the set happens just before the clear and cannot be sensed by the host. therefore, global exception cannot be used as a normal interrupt source: it should only be used for emergency procedures. interrupt and data transfer request overflow if a channel interrupt was issued, its status bit is still set, and microcode issues another channel interrupt, the interrupt overflow status bit is set for that channel. interrupt overflow enhanced time processing unit (etpu2) RM0029 854/1740 doc id 15177 rev 8 status can be checked by the host in channel status register etpu_cxscr bit cios ( section , etpu_cxscr ? etpu channel x status control register ), mirrored in register etpu_ciosr ( section , etpu_ciosr ? etpu channel interrupt overflow status register ). interrupt overflow status is not cleared automatically when interrupt status is cleared. the same mechanism and respective registers (etpu_cdtrosr) are available for data transfer requests. if interrupt is set and cleared at the same time, set prevails and overflow is not altered (keeps the same state as it was before, asserted or not). global exception has no overflow status. parameter access parameter access widths from the host side the spram address space is mapped in bytes, and each 32-bit parameter occupies 4 contiguous, aligned bytes. the host can read/write the spram by 8- , 16-, or 32-bit accesses in aligned addresses. in 32-bit access, host can access all 32 bits or only the lower 24 bits with an automatic sign extension (see section , parameter sign extension area ). parameter addresses and endianness to access parameter number xxx , etpu microengine(s) would select address xxx. the host would add (xxx*4) to the spram base address to access the same parameter. for example, parameter 0x101 is seen by the host in (spram base address +0x404) . an example of spram memory map is shown in figure 521 . the host can access the spram with a 32-bit-wide bus cycle to a four-byte aligned address, 16-bit-wide bus cycle to a two- byte aligned address, or 8-bit wide bus cycle to any byte address. the address of the 24-bit parameters and the most significant byte depends on the endianness of the mcu. for more details, see the section 24.6.6, endianness . parameter concurrency host accesses to parameters may occur in parallel with etpu microengine accesses. readings taken from a group of parameters while they are being simultaneously updated may lack coherency. etpu provides mechanisms to ensure parameter coherency in accesses from both host side and microengine side, including the use of a coherent dual- parameter transfer mechanism, described in detail on section 24.5.4, parameter sharing and coherency . parameter sign extension area the spram address space to the host is mirrored in a parameter sign extension (pse) area (see section 24.4.1, memory map ). accesses from the host to the pse area differ from accesses to the standard spram address space as follows: writes : the most significant byte of the parameters is not written, and the spram retains the old byte value, regardless of the host access size. reads : the most significant bit of the 24-bit parameter (that is, the msbit of the second most significant 32-bit parameter byte) is repeated in the 8 most significant bits of the read value on all 32-bit reads and most significant 16- and 8-bit reads. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 855/1740 the same parameters written in the standard spram address space are read from the pse area with the same offsets, and vice-versa. see ta ble 55 7 for a reference of the address offsets in big and little endian machines. this feature reliefs the host from extending the signal of 24-bit etpu parameters before calculations, and from read-modify-write accesses to modify 24-bit parameters at the spram. spram organization the spram internal partition for channel allocation is dynamic and programmed in the channel registers (see section , etpu_cxcr ? etpu channel x configuration register ). the host application is responsible for allocating a different parameter base address to each channel during the initial etpu configuration, and to allocate enough parameters for the selected function, with no unintentional overlapping between parameters of different functions. besides channel parameters, global areas may have to be allocated for parameters that are shared by more than one channel, in one or both engines. also, temporary parameter areas should be reserved to be used by the coherent parameter transfer mechanisms described in section 24.5.4, parameter sharing and coherency , if necessary. enhanced time processing unit (etpu2) RM0029 856/1740 doc id 15177 rev 8 figure 521. spram organization example a single-engine etpu or dual-engine etpu system may require less parameters than the maximum number provided by the spram. since the spram partition is fully dynamic, there is no limitation of fixed channel addresses, and the reduced array can be fully utilized. host service requests host cpu can request immediate service from a channel by writing a non-zero value to the host service request register field hsr (see section , etpu_cxhsrr ? etpu channel x etpu 2 etpu 1 spram 0x000 etpu_c0cr[cpba]->0x014 etpu_c1cr[cpba]->0x018 etpu_c2cr[cpba]->0x168 etpu_c3cr[cpba]->0x172 etpu_c30cr[cpba]->0x180 etpu_c31cr[cpba]->0x16e etpu2 channel 3 parameters etpu2 channel 0 parameters etpu1 channel 0 parameters etpu1 channel 1 parameters etpu2 channel 30 parameters etpu2 channel 2 parameters etpu1 channel 2 parameters etpu1 channel 31 parameters etpu1 channel 3 parameters etpu1 channel 30 parameters etpu2 channel 31 parameters 0x200 real parameter number 0x014 0x020 0x028 0x030 0x2a0 0x2c0 0x1b0 0x2d0 0x2dc 0x2e4 0x300 host parameter offset 0x000 0x800 0x050 0x080 0x0a0 0x0c0 0xa80 0xb00 0x6c0 0xb40 0xb70 0xb90 0xc00 host etpu2 channel 1 parameters parameters 0x000 - 0x07f can be used as ?shared pool? for etpu absolute addressing mode. 0x3ff 0xffc etpu_c0cr[cpba]->0x010 etpu_c1cr[cpba]->0x150 etpu_c2cr[cpba]->0x160 etpu_c3cr[cpba]->0x00a etpu_c30cr[cpba]->0x100 etpu_c31cr[cpba]->0x0d8 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 857/1740 host service request register ). there is one hsr field for each channel, so that writing to it generates a service request to the respective channel only. a zero value in hsr means no host service request is pending for the channel. hsr value turns to 000 automatically at the end of microengine service for that channel, but only if the thread started due to an hsr. the meaning of a non-zero hsr value depends on the function assigned for the channel. these bits are part of the conditions which select the function entry point, and cannot be tested by microcode. for more details, refer to section , entry points . if host writes hsr = 000 when a thread for the same channel is already running, the thread runs until the end and is not aborted. if host writes hsr>000 when an hsr thread for the same channel is already running, hsr value resets at the end of the thread, and no new hsr will be pending. if hsr is written before its value is resolved by the scheduler during tst, the entry point will obey the new hsr value, and if this new value is 000, no service thread is executed for the hsr. the scheduling of hsrs is completely asynchronous with host accesses, and there is no race-free manner to change an hsr value before service thread execution, so generally the safe way is: write hsr>0 only when hsr = 0. error recovery or emergency host procedures may require one to the safely abort service and reset channel state when an hsr is already pending or executing. in these cases, the procedure below should be followed: 1. disable the channel, writing cpr = 00 in register etpu_cxcr. that will prevent any pending hsr to be serviced. 2. check if the channel is currently being serviced, reading its service status bit in register etpu_cssr. if it is, wait for the time necessary to finish the service pending, or check again until hsr == 0, or channel service bit in etpu_cssr is cleared. 3. write hsr with the error recover value. this value should, possibly combined with other host-defined flags in spram or fm bits, initiate a channel reset or error recovery procedure. 4. re-enable the channel, writing cpr value > 0 in register etpu_cxcr. scm access only host can access scm as data. depending on the specific device, scm may be implemented as a ram or rom. this determines host accesses to the scm as shown below. scm ram implementations when scm is implemented as ram, the host may read or write to scm by setting etpu_mcr bit vis = 1. if vis = 0 and host tries to access scm space, a bus error is issued, writes are ineffective and read data is meaningless. both engines must be stopped or halted to set vis = 1. only 32-bit aligned writes are allowed to scm from the host. write accesses of other sizes store unpredictable values into scm. note: it is necessary to turn vis bit on to set software breakpoints (see section , software breakpoints ). scm low power scm turns off its internal clocks when both engines are stopped (etpu_ecr bit stf asserted), vis = 0 at etpu_mcr, and misc is not enabled (scmmisen = 0). the scm enhanced time processing unit (etpu2) RM0029 858/1740 doc id 15177 rev 8 clocks are automatically turned on if either one of the stf bits is negated or vis turns to 1, or scmmisen turns to 1. scm clocks are not turned off if any of the engines is not stopped, even if they are both halted. the conditions for scm clocks and misc activation are summarized in ta ble 46 7 . scm off-range data when read accesses are made, either by the host or by a microengine, to addresses above the limit corresponding to the scmsize value in etpu_mcr, the value read comes from the register etpu_scmoffdatar. the host can program the register at initialization with an opcode value with operations that try to protect or recover the system from runaway code, for instance: terminate the thread, clear channel flags, disable match and transition service requests, issue an interrupt, jump to an error recovery procedure (v) . writes to unimplemented addresses do not return error and can write on unspecified mirror addresses, so they should be avoided. 24.5.3 scheduler every function is composed of one or more threads. a thread consists of a group of instructions that, once begins execution, cannot be interrupted by host or channel events. each active channel intents to be serviced, being granted time for thread execution. since one microengine handles several channels operating concurrently, the function threads must be executed serially. table 467. scm clocks and misc activation etpu_ecr_1 stf etpu_ecr_2 stf etpu_mcr vis etpu_mcr scmmisen scm clocks misc 0x0 (1) 1onon 0x0 (1) 0onoff x00 (1) 1onon x00 (1) 0onoff 1100offoff 1 1 0 1 on on 1 (2) 1 (2) 10onoff 1 (2) 1 (2) 11onoff (3) 00x0onoff 0 0 x 1 on on 1. vis cannot be written 1 if etpu_ecr_1 bit stf = 0 or etpu_ecr_2 bit stf = 0, and both hltf bits are 0. 2. if vis = 1, neither mdis can be written 0 nor the engine leave stop mode, regardless of device stop request. 3. misc resets and stays so when vis = 1, restarti ng automatically when vis goes 0 if scmmisen = 1. v. only part of these suggested operations can be parallelized in a single instruction, see section , microinstruction formats . RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 859/1740 the task of the scheduler is to recognize and prioritize the channels needing service and to grant execution time to each channel. the time given to an individual thread for execution or service is called a time slot . the duration of a time slot is determined by the number of instructions executed in the thread plus spram wait-states received, and varies in length. at any time, an arbitrary number of channels can require service. to request service, channel logic, etpu microcode or host application notifies the scheduler by issuing a service request. channel enabling and priority assignment every channel is assigned one of three priority levels?high, middle, or low?by the host cpu, through the channel configuration register field cpr (see section , etpu_cxcr ? etpu channel x configuration register ). these registers are also used to disable the channel, which is equivalent to assigning it a ?null? priority. in this case, the scheduler does not grant any of its service requests. it is possible to change the channel priority level or disable it dynamically. if the host disables a channel when it is currently being serviced, channel service thread will complete. this means that it is possible for the output level of a channel signal to change, or a host interrupt occur, even after its priority register was written to ?null?. for instance, if an output transition is scheduled, the transition will occur even after the channel is disabled. service requests previously pending or that occur while a channel is disabled remain asserted while the channel is disabled, and are serviced if the channel is enabled again, in due time determined by the priority scheme and concurrent requests from other channels. channels are disabled after reset, and it is recommended to configure a host service request for initialization of a channel before that channel is enabled to active priority (see section 24.6, initialization/application information ). channel priority schemes the scheduler holds a service grant register with one bit for each channel. once the scheduler grants a time slot to channel, the service grant bit for that channel is asserted in the service grant register. when the service grant bit of a channel is set, the channel may request new service but is not serviced again before its service grant bit is cleared. when all channels in a same priority level are serviced, their service grant bits are cleared at the end of the thread, one system clock before the next serviced channel is calculated, according to the scheme below (w) : clear all grant bits of priority high if all channels of that priority that are requesting have their grant bits in 1. clear all grant bits of priority medium if all channels of that priority that are requesting have their grant bits in 1. clear all grant bits of priority low if all channels of that priority that are requesting have their grant bits in 1. clear all grant bits of disabled channels. this scheme assures that no channel is left with its grant bit forever asserted (preventing it from being serviced again), even if the channel priorities are reassigned during the execution. w. grant bits are also cleared in the next clock, when t he service channel is chosen, or when the microengine is idle, using the same scheme. enhanced time processing unit (etpu2) RM0029 860/1740 doc id 15177 rev 8 priority level is determined based on the maximum latency desired for each channel. a channel having a function that requires the most frequent or more immediate service should be allocated a high priority level. the etpu employs a primary and a secondary priority scheme . these two schemes ensure frequent servicing of high-demand functions and ensure a minimum time allocation to all channels requesting service, regardless of their priority level. the primary scheme prioritizes requesting channels that have different priority levels; the secondary scheme prioritizes requesting channels that have the same priority level. initially, a channel requests service and is granted a time slot by the scheduler: service grant bit is asserted. if only high-level channels constantly receive service first because of their priority level, middle- and low-level channels would only be serviced by default, i.e., if no high-level channels request service. to ensure that each priority level receives an opportunity for servicing, every time slot has a fixed priority level that the scheduler honors first. divided into sets of seven, time slots are numbered from one to seven. figure 522 illustrates the numbered time slots in sets of seven (fields a and b) and identifies their assigned default priority level. the high level has more time slots than the middle and low levels. out of every seven time slots available, four are assigned to honor high-level channels first, two are assigned to honor middle-level channels first, and one is assigned to honor low-level channels first. only one request (in each engine) is serviced per time slot. when no channel requests service and the microengine is idle the priority scheme is initialized to time slot one, to prevent priority inversion on the next request (x) . figure 522. time slot priority levels primary scheme ? priority among channels on different levels although time slot priority assignment is fixed, the servicing priority is not. the primary scheme acknowledges the priority level assigned to a time slot, granting service first to a channel having the same priority. in figure 522 , time slot one has a high-level assignment; x. priority inversion would occur in the following situation: no channel is requesting service, and the current time slot is primarily assigned to a low-priority channel. if the scheduler was not reset to time slot one and two channels requested service at the same time, one with high priority and the other with low priority, the channel to be serviced would be the low-priority channel. 1 234567 1 23 h mhl hmhhmh 45 lh high middle low a b RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 861/1740 therefore, a high-level channel requesting service is recognized first. however, if no high- level channel requests service, the scheduler recognizes a requesting middle-level channel. if this level has no request, the scheduler continues to the low-level. if no requests occur, the scheduler truncates the seven state cycle and starts a new cycle at time slot one, waiting for the first request. granting service to a different-level channel is called priority passing. the order of passing always gives the highest priority to the assigned level, and the second priority to the higher of the remaining requesting priority levels as shown in ta ble 46 8 . when priority is passed to another level, that level is serviced and the fixed-priority-level sequence is resumed with the next time slot. figure 523. priority passing example examples of priority passing are shown in figure 523 . each cycle contains seven time slots (or less if no service request exist). in cycle b, no high-level or middle-level service requests are present before time slot three which is assigned by default to high-level priority. thus, time slot three is passed to the low level. in cycle b there are also no middle-level service requests before time slot six, so it passes the priority to a requesting high-level channel. table 468. priority passing assigned priority level next priority level next priority level high middle low middle high low low high middle slot number 67123456 123 1 mhhmh l hmhh mh h high pend count service high 21 01 0 2 0 - x new service requests arrive at a specific priority level 20 x 2 22 1 1 1 0 0 0 1 2 2 1 0 2 2 7 dh dm dh h>l dl dh m>h dm h>m h>m m>l h>l 1 0 dh, dh, dl - default service high, middle or low h>l, h>m, m>h, m>l - priority passing scheme id - idle (no service request) id slot assignment slot assignments: reset slot fixed priority level middle pend count service middle low pend count service low number cycle a cycle b cycle c (truncated) cycle d 23 mh 1 1 1 1 0 1 1 0 0 1 h h>m dm dh 1 h id enhanced time processing unit (etpu2) RM0029 862/1740 doc id 15177 rev 8 during time slot six no more high level requests are left, but two new middle-level requests arrive, and there are also three low level pending service requests. thus, time slot seven of cycle b and time slot one of cycle c are passed to the middle-level which is the next priority level after high. time slots two and three of cycle c are passed to the low level which contains the three remaining channel service requests. at time slot three of cycle c the last low level request is serviced, and the scheduler passes to idle state. at this point the cycle c is truncated and the scheduler passes to time slot one of cycle d. priority passing disabling the priority passing scheme allows a case where a high priority channel looses to a lower priority one right after another lower priority has been serviced, exemplified in the cycle d on figure 523 . a middle priority channel wins time slot 1 due to priority passing from high to middle. while it is being serviced, two new service requests arrive, one high and one middle priority. the high priority request looses to the middle one on next time slot 2 by default priority assignment. this priority inversion can be avoided by setting the etpu_ecr bit sppdis (see section , etpu_ecr ? etpu engine configuration register ), which disables the priority passing mechanism. when priority passing is disabled, at the end of the thread the slot number is incremented until a time slot that matches the priority of one of the requesting channel(s). the time slot advance takes no extra clocks. if no channel requests service, the time slot counter stays at time slot 1. the priority selection scheme with disabled priority passing is summarized in table 469 . an example of the priority passing disabling scheme is illustrated in figure 524 . the sequence of service requests is the same as in the example of figure 523 , and although the time slot incrementing differs, the priorities granted are the same for cycle b. cycle c has one of the low priority channels serviced before the second middle one. cycle d, however, no longer has the priority inversion. in cycle b, after the time slot 2 only a low priority request remains, so the time slot count advances directly to 4, which has a low priority assigned. time slot keeps on 4 for the next service, as only a low priority request remains also, and only time slot 4 is assigned to low. two high priority services contend for the next time slot 5 (assigned to high). the second high priority channel is serviced on the next time slot, jumped to 7 because there is no middle request, ending cycle b. cycle c starts with time slot 2, as there are no high priority table 469. priority passing disabling at the end of time slot servicing priority if any request of priority service it on time slot else if any request of priority service it on time slot else if any request of priority service it on time slot 1 high medium 2 high 3 low 4 2 medium high 3 low 4 medium 6 3 high low 4 high 5 medium 6 4 low high 5 medium 6 low 4 5 high medium 6 high 7 low 4 6 medium high 7 medium 2 low 4 7 high high 1 medium 2 low 4 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 863/1740 requests and two middle and two low ones. after the first middle service, time slot count skips 3 assigned to high (no high requests), and services a low priority channel on time slot 4. it follows the same scheme until there are no other requests and cycle c is truncated, resetting the time slot counter to 1. cycle d begins with a middle request, jumping to time slot 2. during this service two requests arrive, one high and one middle. unlike what happened with priority passing, the next serviced is the high priority channel, as the time slot increments to 3. the second middle priority channel request in cycle d is finally serviced next, on time slot 5. figure 524. priority passing disabling example secondary scheme ? priority among channels on the same level because channels can randomly request service, channels having the same priority level will inevitably request service simultaneously. a secondary scheme prioritizes these requests. the scheduler services channels on each of the three priority levels, beginning with the lowest numbered channel on that level. priority scheme example the overall priority scheme simultaneously incorporates both primary and secondary schemes. combining both schemes in the following example conveys their correlation. 1. one high-priority and one low priority channels request service, while the scheduler is in time slot one. having its service request bit asserted, a single high-level channel is granted the time slot, which has high-level priority (primary scheme) and its service slot number 67124457 4641 2 mhhmllhhmlmlhm high pend count service high 21 01 0 2 0 - x new service requests arrive at a specific priority level 20 x 2 22 1 1 1 0 0 0 1 2 2 1 0 2 2 2 dh dm dh dl dl dh dh dm dm dl dm dl 1 id 0 dh, dh, dl - default service high, middle or low id - idle (no service request) id slot assignment slot assignments: fixed priority level middle pend count service middle low pend count service low cycle a cycle b cycle c (truncated) cycle d 35 hm 1 1 1 1 0 1 1 0 0 1 h dm dh dm reset slot number enhanced time processing unit (etpu2) RM0029 864/1740 doc id 15177 rev 8 grant bit is asserted. at the end of the thread, the service grant bit is negated (no more requests of high priority level channels). 2. the scheduler proceeds to time slot two, which has middle-level priority; however, no middle-level channel is requesting service. priority is passed to the high level, but no high-level channel is requesting service; therefore, priority is passed again, and service is granted to the single requesting low-level channel. once serviced, this channel?s grant bit is negated (no more low-level requests). 3. the scheduler resumes with the fixed-priority sequence on time slot three; however, no channels are requesting service. the scheduler returns to time slot one, waiting for requests. 4. two high-level and two middle-level channels simultaneously request service. being in time slot one which is assigned high priority, the scheduler finds the lowest numbered high-level channel (secondary scheme) and selects it for service. this channel?s service grant bit is asserted. 5. the scheduler continues to time slot two, which has middle priority (primary scheme), and allocates the slot to the lowest numbered middle-level channel requesting service (secondary scheme). the scheduler notes the still unserviced middle-level channel and proceeds to time slot three. 6. time slot three is allocated for high priority. the slot is allocated to the remaining unserviced high-priority channel, and the channel?s service grant bit is asserted. the scheduler checks again at the end of the thread. all service grant bits of high-level requested channels are asserted; therefore, all high-priority channels that requested have been allocated execution time. under this condition, all service grant bits of the high-level serviced channels are negated. the scheduler proceeds to time slot four. 7. time slot four is allocated for low-priority channel; however, no low-level channel is requesting service. priority is passed to the high level, but no high-level channel is requesting service; therefore, priority is passed again, and service is granted to the remaining middle-level channel which requests service. this channel?s service grant bit is asserted. the scheduler checks again at the end of the thread. all grant bits of middle-level requested channels are asserted; therefore, all middle-priority channels have been allocated execution time. under this condition, all service grant bits of the middle-level serviced channels are negated. the scheduler proceeds to time slot five. meanwhile a low priority channel requests service. 8. time slot five is allocated for high-priority channels, but there are no more requests from high-priority or middle priority channels. the single low-level channel which required service is granted time slot five. once serviced, the channel?s service grant bit is asserted. next, the service grant bit is negated (no more requests of low priority level channels). 9. the scheduler resumes with the fixed-priority sequence on time slot six; however, no channels are requesting service. the scheduler returns to time slot one and waits for requests. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 865/1740 time slot latency latency is the amount of time between a service request and the beginning of service on that channel. the following factors affect latency: number of active channels number of channels on a priority level number of available time slots on a priority level number of microcycles required to execute a thread of a function number of parameter ram accesses during execution of a function thread system clock frequency. each time slot may require a different number of microcycles, depending on the thread of a function to be executed. this variation is shown in figure 525 . for more details on latency evaluation, see section 24.6.5, estimating worst-case latency . figure 525. time-slot variation 24.5.4 parameter sharing and coherency spram can be concurrently accessed by host and microengines (two in a dual etpu engine system). in general, there is no guaranteed order by which a group of parameters is accessed, which may lead to a lack of internal consistency if two or more related parameters are read when only part of them is updated. etpu provides mechanisms to guarantee parameter coherency. the most generic mechanisms for host-etpu coherency, suitable for any number of parameters, are: the use of transfer service thread mechanism. the mailbox (or ?software semaphore?) mechanism. these mechanisms, described in section 24.6.3, multiple parameter coherency methods , use microcode to transfer parameters from temporary buffers in spram to their definitive locations (or vice-versa). these methods have the disadvantage of wasting processing and code memory resources. etpu also provides a coherent dual-parameter controller (cdc) mechanism. it is used by host to coherently transfer pairs of parameters from/to a parameter buffer located on spram to/from the locations on spram where parameters are accessed directly by the channels. coherency is guaranteed by spram access arbitration. although limited to two parameters only, it has lower latency and wastes no microengine resources (y) . cdc usage is described in section , coherent dual-parameter controller (cdc) . microcycles time slot fixed priority level 1 2345 h mhlh 6 m enhanced time processing unit (etpu2) RM0029 866/1740 doc id 15177 rev 8 for parameters shared by both engines, etpu provides hardware semaphores . coherency is assured given the semaphores are used to prevent concurrent access to the changing parameters. microengine can request semaphores using specific microinstructions (see section , semaphore operations ). hardware semaphores are described in detail in section , hardware semaphores . neither host nor cdc have access to the hardw are semaphores, but they can be combined with microcode transfer mechanisms if host must coherently access parameters which are also shared by both engines. in order to ensure coherent access to a group of parameters by two or more contenders, each contender must have atomic access to the shared parameters. atomicity conditions are discussed in section , host side atomic access , and section , microengine side atomic accesses . host side atomic access host side atomic accesses can be achieved by either of following ways: for one parameter, the spram should be accessed by 32-bit-wide data transfers to ensure coherency for two parameters only, using the coherent dual-parameter controller. indirectly, for any number of parameters, by requesting microcode to coherently access spram in its behalf. the host side atomicity problem becomes, then, a microengine side atomicity problem. some methods that use this approach to achieve coherency are described in section 24.6.3, multiple parameter coherency methods . microengine side atomic accesses microengine single-parameter atomicity spram should be accessed by 32-bit-wide data transfers to ensure atomicity for 32-bit parameters. this applies either to host-microengine coherency or microengine-microengine coherency in a dual etpu engine system. microengine dual-parameter atomicity microengine has the ability to access two parameters coherently in back-to-back accesses, at random addresses: once it accesses spram, it has priority over host for another access in the next microcycle (see section , spram arbitration ). note that it applies only to microengine-host coherency . for microengine-microengine coherency in a dual etpu engine system, one must use hardware semaphores (see section , hardware semaphores ). microengine dual back-to-back accesses are guaranteed to be atomic in relation to host slave accesses or coherent dual-parameter controller, regardless of semaphore usage: host or cdc accesses cannot break-up a ba ck-to-back microengine access, neither microengine can break a cdc transfer, due to the spram arbitration mechanism described in section , spram arbitration . y. a microengine access to the spram in the moment cdc is performing the transfer may suffer a maximum of two wait-states. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 867/1740 atomicity is not guaranteed if microengine enters halt state in the middle of a back-to-back access (see section , microengine halt state ): host can access spram while microengine is halted in the middle of a back-to-back access. microengine side multiple atomicity hardware semaphores must be used for microengine-microengine coherency (more than 1 parameter) since two or more accesses from one microengine are not atomic with respect to the other. for multiple microengine-host coherency, the software methods described in section 24.6.3, multiple parameter coherency methods , or similar ones, must be used. some of these methods rely on the fact that parameter access of a thread is atomic in relation to another thread in the same engine, since a thread cannot be suspended (pre- empted). for 1 parameter coherent access, or dual-parameter coherency between only one microengine and host, the alternatives shown in previous sections apply. coherent dual-parameter controller (cdc) dual-parameter coherency is supported by a coherent dual-parameter controller hardware (cdc), which contends with microengine fo r spram access. cdc atomically transfers, upon host?s command, two parameters from one area of the spram to another. one area is a temporary (buffer) area, where the two parameters are directly read or written by the host. this temporary area has to begin in an spram address multiple of 2 words, and the two parameters must be sequential. the other area is the channel parameter area where the microcode normally accesses the parameters, usually with the channel relative address mode (see section , spram addressing modes ). in this area, the parameters transferred by cdc don?t have to be sequential. a transfer from the temporary area to the channel area, when the host sends data to the channel, is called a write transfer . inversely, in a read transfer the parameters are copied from the channel area to the temporary area (channel to host). coherency is guaranteed by the spram access contention rules implemented in the spram arbiter (see section , spram arbitration ). cdc transfers are cohe rent in respect to the two engines, so the target parameters in the channel area may be shared by channels on them both. during cdc operation, the host may suffer from 3 up to 11 system clocks wait states (z) , and the microengine(s) may suffer up to 2 microcycle wait-states (aa) . cdc accesses are atomic with respect to microengine(s) accesses to the spram. even when neither engine is in tst, cdc may suffer up to 4 system clock internal wait-states from spram arbiter, meaning 9 slave wait-states to host, so that it does not break atomic back- to-back accesses from microengine(s). cdc also cannot break tst preload accesses. host can initiate cdc back-to-back transfers: there is no need of idle slave cycles between two transfers. z. the maximum number of host wait states on cdc occurs when both microengines overlap their tsts, delayed 3 system clocks from each other. aa. one microcycle takes two system clocks. microengines get wait-states in multiples of microcycles, while host and cdc wait-states are multiples of system clocks. enhanced time processing unit (etpu2) RM0029 868/1740 doc id 15177 rev 8 cdc programming the coherent dual-parameter controller register (see section , etpu_cdcr ? etpu coherent dual-parameter controller register ) is used to configure and initiate cdc transfers between the temporary area and channel parameter area. host asserts sts bit in order to start the data transfer. cdc then contends for the spram and starts the transfer. when the data transfer is complete, sts returns to 0. host receives wait-states for writing sts = 1 while cdc contends for spram and during the transfer. the write access ends when cdc finishes the transfer. host receives wait-states during the cdc transfer. if host writes etpu_cdcr with sts = 0 or does not write the sts byte, the cdc transfer does not occur. cdc programming can be summarized as follows: 1. if it is a write transfer, i.e., from host to channel, write the two parameters into temporary area. 2. write etpu_cdcr with sts = 1 and the remaining cdc programming parameters: parameter width (32 or 24 bits, field pwidth), transfer direction (read or write, field wr), temporary parameter area base address (field pbbase), and the absolute addresses of the parameters to be transferred (concatenation of the fields ctbase and param0/1). 3. if it is a read transfer, i.e., from channel to host, read the two parameters from the temporary area into host memory/registers. hardware semaphores etpu provides hardware semaphores accessible by the microengine only. it is the responsibility of the application to ensure proper use of the semaphores (i.e., agree upon a specific semaphore and use it properly, to ensure coherency). the etpu microinstruction set has support for locking and freeing the semaphores, described in section , semaphore operations , and this is the only way to access them. there are four semaphores available, which reduces the amount of collisions by assigning unrelated data transfers to different semaphores. semaphores are used for parameters which can be shared by channels in different engines, and for engine-to-engine synchronization. semaphores are also the only way to ensure coherent access to parameters shared between the two microengines. attempting to lock one semaphore (even not successfully) frees the other locked by the same engine, ensuring one can lock just one semaphore at a time. that prevents deadlock conditions between the two engines. microcode end command or engine being in idle state (no thread executing) automatically releases all semaphores from one engine side, even if a semaphore lock is done in parallel. however, it is recommended to write the microcode in a way which locks semaphores for the shortest required period, and frees them without waiting for the end command, to improve the performance of the other microengine. semaphores are free after reset. an engine can only free a sempaphore locked by itself. semaphore lock requests are always non-blocking , in the sense that they do not suspend the requester in case the semaphore is already locked. the semaphore status after the lock request?indicating if it was successfully locked or not?must be tested through the smlck microengine branch condition (see section , branch conditions ). RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 869/1740 spram arbitration up to four entities can access spram: two microengines (in a dual etpu engine system) the coherent dual-parameter controller (cdc) the host cpu (direct memory-mapped access) the following rules specify the access priorities for contended access. they keep compatibility with the tpu3 dual-parameter access atomicity, but only between the microengine and cdc (not host accesses through slave bus). 1. microengine accesses from the two etpu engines are interleaved between each other, but not with host or cdc accesses; 2. the etpu microengine(s) gives priority for spram accesses to either the host cpu or the cdc under any of the following conditions: a) the microengine has completed accessing the second parameter in a back-to- back spram access (ab) . b) the spram was not accessed during the last arbitration slot for the microengine and the host does not loose the access to the other engine in the current arbitration slot (ac) . c) cdc is transferring data, after its first (read) access. note that the cdc can be in middle of a data transfer of another pair of parameters, unrelated to the ones that microengine tries to access. 3. the etpu microengine takes priority for spram accesses under either of the following conditions: a) the host cpu or cdc has done a data trans fer during the last access arbitration slot for the engine ac . also, the host cpu does not hold a pending access against the other etpu microengine. b) the microengine is arbitrating for the access of its second parameter in a back-to- back access ab . all pairs of back-to-back parameter accesses are coherent with respect to host and cdc (not to the other microengine). the direction (read or write) of any individual access by host or microengine is irrelevant to the arbitration. the use of normal or pse spram area by the host is also irrelevant to the arbitration. the first parameter preloading in a tst is considered first access by the arbiter, regardless of any access made at the end microinstruction of the previous thread, i.e.: the last access of a thread and the first preload are never considered a back-to-back access. on the other hand, the tst preload accesses are considered back-to-back and are, therefore, atomic with respect to host or cdc. note: the zero spram operation (see section , zero spram operation ) is considered an spram access for arbitration purposes both on writes and reads; the fact that read spram data is discarded is irrelevant for arbitration. ab. if microengine tries to access the spram in the following microcycles, the third and fourth consecutive accesses are considered the first and second of a new back-to-back dual access. ac. the microengine access slot is between its own t4 and t2 edges (see section 24.7.1, microcycle and i/o timing ). enhanced time processing unit (etpu2) RM0029 870/1740 doc id 15177 rev 8 24.5.5 enhanced channels enhanced channels comprise hardware support for input digital signal processing and output signal generation. each channel is associated with one input and one output signal. enhanced channel logic is combined with function microcode (and optionally angle mode logic) to implement channel i/o functionality. etpu?s enhanced channels are capable of dual action , meaning that each channel logic can handle two events at different times and/or cause two separated actions?these actions and events can be mutually dependent (with the first either blocking or enabling the other), or both independent, depending on the programmed channel mode . each enhanced channel contains event logic containing two event register sets , each set supporting one input and/or output action, the pair implementing dual-action support. each event register set contains two 24 bit registers: match and capture. the match register holds the pending match value which is compared against one of the two time bases by an equal-only/greater-equal comparator. the capture register captures one of the two time bases as a result of a match or transition detection. service requests are issued on particular combination of match and capture events, defined by the selected channel mode. in the context of the etpu channels, a match is a comparison between a time base value and a channel match register. if those two values are coincident, or the time base value is greater than the value of the match register, a match event occurs . depending on the channel mode of operation and current state of the channel logic, the match event may be recognized, i.e., change the state of the channel, or be ignored. a match event recognized by the channel logic is called a match recognition . match recognitions can cause, also depending on channel mode and current state, the channel to request service, configuring a match service request . etpu uses two kinds of comparator to assert a match event: an equal comparator , in which both the match register and the value of the selected time base must match exactly, and a greater-equal comparator . the greater-equal comparator considers any time base value between the range [n: n+0x800000-1] as a valid match against the value of n in the match register, even when the value n+0x800000-1 wraps around the point of origin (0x0). refer to figure 526 for an illustration of the matching values on a greater-equal comparator. the second source of events for the etpu channel is a transition detected at the corresponding channel?s input signal. two distinct transition detections can be programmed individually for each channel, allowing recognition of all possible combinations of edge detection. it is also possible to check the sampled state of an input signal upon the occurrence of a match: the sampling of the expected value is treated as a transition, even if the input signal did not necessarily toggled at the time of the match, or at any time at all. like match events, transitions events may or not be recognized by the channel logic. when they are, a transition detection occurs. as well as match recognitions, transition detections can issue a channel service request, depending on channel mode and current state. transition detections and match recognitions are sometimes simply called transitions and matches throughout this document, for short. input and output signals can be processed separately by the channel logic and microcode, and can also be combined such that matches and transitions are used to cause output signal actions . the output signals can also be directly controlled by microcode. many event combinations are allowed for a channel, given the possibility of configuring pairs of RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 871/1740 matches and transitions for the dual-action logic, where each event is able to block or enable the next one. there is a full set of channel modes described in section , channel modes , exploring all the capabilities mentioned here. each channel has its own set of registers and flags. they are selected, and made accessible to the microengine, according to the value written into the microengine chan register that points to the desired channel. every time the chan register is written, even if with the same previous value, a channel is selected and its flags and registers are updated. for further detail, see section , channel selection register ? chan . figure 526. greater-equal comparator beyond the request of services due to the signal and timing internal to each channel, one etpu channel microcode can explicitly request service from another channel through the microengine link register . a microcode write to the link register asserts a service request to the channel whose number matches the contents of link. refer to section , channel link for a complete description of this mechanism. these service requests originated in the etpu enhanced channels (either time base match, input signal transition, or link service request) result in a call to the corresponding channel service routine, which is the sequence of microinstructions that is called a thread . for further detail, refer to section 24.5.1, functions and threads . in addition to event logic, each channel has an output buffer enable signal, controlled by microcode, and an enhanced digital filter, which eliminates spurious glitches on input pin signal. output buffer enable is meant to control output mcu pad signal driver. a high level diagram of channel logic and registers is shown in figure 527 . note: the value opposed to n (n+0x800000) does not cause a match. greater-equal area 0 n n + 0x800000 tcr1/2 enhanced time processing unit (etpu2) RM0029 872/1740 doc id 15177 rev 8 figure 527. channel logic block diagram input signal tcr1 tcr2 capturea matcha tbsa[0] tbsa[1] er1 bus tbsa[2] 0: >= 1: == mrlea mrla tdla ucode erwa & cmw=1 set rst ucode mrla rst set rst ucode mrle set action logic 1 trans.a match a to service request transition event logic opaca ipaca capture 2 matchb tbsb[0] tbsb[1] er2 bus tbsb[2] 0: >= 1: == mrleb mrlb tdlb ucode erwb set rst ucode mrlb rst set rst ucode mrle set action logic 2 trans.b match b opacb ipacb edf output ff output logic set rst obe ff ucode tbsa[2:0] pdcm sri sri ucode mtd rst set ucode pdcm ucode ipaca ucode ipacb ucode opaca ucode opacb output signal output buffer enable etpu_tbcr[cdcf] to branch psti to branch psto psc, pscs ucode channel flags flag0 flag1 ucode flc comparator comparator odis opol microengine microengine mef (filter) ucode tdl ucode tdl to service request to branch tdlb to branch mrlb to branch tdla to branch mrla control transition event logic match recognition match recognition etpu_ecr[fpsck] tcrclk filter input signal = channel 0 only am ipp_obe_etpuch am synchr. synchr. udcm mode decoding ucode erwa & cmw=0 tcrclk channel input channel output tccea ucode mtd RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 873/1740 channel registers and flags channel configuration and control registers can be divided in the following groups: host configuration and control registers , which define channel function and parameter allocation in spram, input signal filtering, manage host interrupts, and are used for host service requests; they can only be accessed by host, except for the function mode bits which can be also tested by microcode. event registers , which can only be accessed by etpu microengine, through dedicated channel control microinstruction operations (see section , channel control and configuration microoperations ); these registers are directly used to implement channel functionality, and include channel event status latches which can be directly tested by microengine branch instructions. pin control registers , which basically define pin state and transition polarity (but not input signal filtering); they are accessible only by dedicated channel control microinstruction operations. link registers , which implement the channel link mechanism that allows one channel to request service to another one; they are accessible only by microinstruction operations. general channel registers : chan, sri, flag0/1, pdcm, udcm. most of those registers are channel exclusive, i.e., there is one copy of them for each channel. microcode can access registers from only one channel at a time. the channel selection (chan) register (see section , channel selection register ? chan ), accessible only by microcode, defines the channel whose registers are being accessed, with exception of link register and function mode. chan register assumes the value of the channel to be serviced at the beginning of tst. the service request inhibit (sri) register controls the generation of service requests on matches and transitions, also affecting channel logic behavior. for a full description see section , sri ? match/transition service request inhibit latch . flag0/1 are used to select channel service threads based on channel software state. see section , flag1,flag0 ? channel ?state resolution? flags , for more details. host configuration and control registers are described in section 24.4.7, channel configuration and control registers . time base configuration is common to all channels, and described in section 24.5.6, time bases . time base selection for matches and captures, however, is individual to each channel, and is part of the event registers. link registers are described in section , channel link . the following sections describe the event registers and pin control registers. enhanced time processing unit (etpu2) RM0029 874/1740 doc id 15177 rev 8 er ? event registers each channel contains two identical event register sets, named era and erb, corresponding to the two actions supported. each event register set contains: a 24-bit match register (match a or match b), which holds a match value. this value is compared against the selected match time base (tcr1 or tcr2). a 24-bit capture register (capturea or captureb), which samples the selected capture time base (tcr1 or tcr2) a time base selection register (tbsa or tbsb) a match recognition status flag (or latch) (mrla or mrlb) a match recognition enable latch (mrlea or mrleb) a transition detection flag (or latch) (tdla or tdlb) a transition continuous capture enable (tccea only) era and erb are associated with the first and second events in double action modes, not necessarily in that order. the order of match events associated with era and erb depends on the programmed channel mode, the matcha and matchb values, and the timebases selected by tbsa and tbsb. similarly, the order of transition events associated with era and erb depends on the programmed channel mode, and the transition detection selected by ipaca and ipacb. these registers are directly or indirectly accessed by the microcode. tbsa and tbsb registers are defined in section , tbsa and tbsb ? time base selection registers . the other registers are explained in section , match recognition and section , transition detection and time base capture . access to the event registers is qualified by the channel currently selected by the microengine (i.e., the channel value currently in the chan register). during the channel transition period (automatic chan assignment), or whenever chan is written by microcode, capture values of the new selected channel are sampled into microengine registers erta and ertb, therefore becoming visible to the microcode. at the same time, updated values of mrla, mrlb, tdla and tdlb are sampled into the branch logic, making the register values and the flags coherent with respect to each other and with the thread selected by the scheduler (ad) . note: the function mode bits are also sampled from the host interface on time slot transition, so that they remain constant to microengine even when host changes them. during service, the microcode can access updated values of the event registers of any channel by writing the channel number to chan. writing chan with the same value (chan := chan) updates erta and ertb with the new captured values, the branch logic with updated mrla/b and tdla/b flags. writing chan with a different value does the same with the values from the newly selected channel. match values are also accessed through erta and ertb microengine registers, which are copied to/from the channel matcha and matchb registers by specific microinstruction operations. microcode writes to the flags and selections (mrla/b, tdla/b and tbsa/b) are immediately effective to the channel. the mrla/b and tdla/b branch conditions are also ad. the thread selected is determined by the entry point which, in turn, is determi ned partially by the channel latches. see section , entry point address generation . RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 875/1740 immediately reset when their correspondent flags are reset by microcode. match registers are indirectly written by microcode through erta/b. mrlea/b is unconditionally asserted when respective match register is updated from erta/b, and its negation is immediate. ta ble 47 0 summarizes event registers accesses. matcha and matchb registers matcha and matchb registers hold a match value to be compared against the selected channel time base. a match value can only be written into the match register by microcode, through erta/b microengine registers (see section , write channel match and udcm registers ). microcode can also read the match register as a special t4abs source operation, when t4abs = 0101, and the source for t4abs is selected from the second register set. in this operation, matcha/b registers are copied into erta/b registers (see section , selecting sources and destination ). for more information on time base matches, see section , match recognition . capturea and captureb registers capturea and captureb registers capture the selected channel time base. capturea/b registers cannot be directly written or read by microcode. during the time slot transition (tst) or during chan assignment, capturea/b registers are copied into erta/b microengine registers. for more information, see section , transition detection and time base capture . table 470. event registers microcode accesses register access type sampled from channel update to channel microcode fields (1) reset value (2) capturea, captureb read through erta/b to erta/b on chan assignment no t2abd n.a. matcha, matchb read and write through erta/b to erta/b by microcode from erta/b by microcode erwa, cmw, erwb, t4abs n.a. mrlea, mrleb write to 0 (negate) directly; write to 1 (assert) upon matcha/b update from erta/b no immediate mrle, erwa, erwb 0, 0 tbsa, tbsb write only no immediate tbsa, tbsb 000, 000 mrla, mrlb flag test on branch, write to 0 (negate) only on chan assignment immediate bcc (test) mrla, mrlb (reset) 0, 0 tdla, tdlb flag test on branch, write to 0 (negate) only on chan assignment immediate bcc (test) tdl (reset) 0, 0 tccea write only no immediate mtd 0 1. see section 24.5.9, microinstruction set . 2. n.a. means that value of the register is undetermined after reset. enhanced time processing unit (etpu2) RM0029 876/1740 doc id 15177 rev 8 tbsa and tbsb ? time base selection registers tbsa/b are 3-bit registers which have the following effect on channel configuration: selection of the timebase (tcr1 or tcr2) to be compared against the match values in matcha and/or matchb registers. selection of the timebase (tcr1 or tcr2) to be captured in the capturea and/or captureb registers by a match or transition detection event. selection of comparator mode to be used with matcha and matchb registers: equal- only or greater-equal. after reset tbsa/b are 000. table 471 shows values of tbsa and tbsb for configuration selection. note that the time base selection for capture is independent of the time base selected for matches. tbsa/b are written through the microcode fields tbsa/b (see section , comparator and time base selection ). note that microcode field tbsa is also used to control the obe pin control register (see section , pin control registers ), which is separate from the tbsa register. mrla/b ? match recognition latches see section , mrla/b ? match recognition latches . mrlea/b ? match recognition latch enable see section , mrlea/b ? match recognition latch enable . tdla/b ? transition detection latch see section , tdla/b ? transition detect latches . tccea ? transition continuous capture enable see section , tccea ? transition continuous capture enable . pin control registers pin control registers are replicated one per channel, accessed only by microcode and qualified by the chan register in the same way as event registers. table 472 lists pin control registers, explained in following subsections, and their accesses. table 471. tbsa/b programming states tbs bit 2 1 0 bit value comparator selection capture time base selection match time base selection 0 greater or equal tcr1 tcr1 1 equal-only tcr2 tcr2 table 472. pin control registers microcode accesses register access type sampled from channel update to channel microcode fields (1) reset value ipaca, ipacb write only no immediate ipaca, ipacb 000,000 opaca, opacb write only no immediate opaca, opacb 000,000 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 877/1740 ipaca,ipacb and opaca,opacb ? input and output pin action control registers these registers determine the transition detections and output pin actions which takes place due to match or transition events. each field is three bit wide. after reset, the ipaca/b and opaca/b registers are set to 000. ipaca and ipacb registers are mutually independent and have identical encoding, and so do opaca and opacb. table 473 shows ipac and opac encoding. note that transition detections are independent from the output actions, but some options of output actions are triggered by transition detections. output actions can also be triggered by matches. for a detailed definition of transition detections, see section , transition detection and time base capture . ipaca/b define the transition events treated by channel logic. although the name ?transition? is generically used for the transition detections, ipac options 100 and 101 do not really detect transitions: they actually sample the state of the input signal at the occurrence of the corresponding match (match a used for ipaca, match b used for ipacb). psti flag test on branch no no bcc 0 psto flag test on branch, write no immediate bcc (test) psc, pscs (set) 0 obe write only no immediate tbsa values 1000,1001 0 (negated) pss flag test on branch on chan assignment no bcc n.a. (2) prss flag test on branch on chan assignment no bcc n.a. (3) 1. see section 24.5.9, microinstruction set . 2. pss is psti or psto sampled on chan assignments and at thread start. 3. prss is psti sampled on channel service request. table 472. pin control registers microcode accesses register access type sampled from channel update to channel microcode fields (1) reset value enhanced time processing unit (etpu2) RM0029 878/1740 doc id 15177 rev 8 output pin control logic and pin state output register ? psto the output signal control logic uses opaca/b, the pre-defined channel mode (pdcm) and the user defined channel mode (udcm), and the microcode pin state control (psc and pscs) fields. it is responsible for setting the pin state output (psto) register to the specified logic value required by microcode, by input events, or by match a and/or match b events. the psto register stores the driven pin state determined by the pin control logic. the output buffer enable signal, if used at mcu integration, must be set by microcode (using tbsa field) to make the pad propagate the psto register output to the actual pin. psto register output also goes to the microengine branch logic, enabling branching on the driven pin state (see figure 528 ). psto is set to 0 on reset. the psc and pscs microcode fields are used for setting the psto register to a fixed value, or to the value specified by the opaca or opacb microcode field, as shown in ta ble 47 4 . for details refer to section , channel control and configuration microoperations . on occurrence of match recognitions or transition detections, the pin control logic sets psto value according to the event number (match a/transition a or match b/transition b) and the contents of opaca/ipaca or opacb/ipacb registers. there are cases in which two match or transition events may occur at the same time, each of them trying to force a different pin action. the resolution of the selected match event which sets the value table 473. ipaca/b and opaca/b encoding value ipac meaning opac meaning 000 do not detect transitions do not change output signal 001 detect rising edge only match (1) sets output signal high 010 detect falling edge only match (1) sets output signal low 011 detect either edge match (1) toggles output signal 100 detect input signal = 0 on match (1) 1. match a is used for ipaca/opaca, and match b for ipacb/opacb. transition sets output signal low 101 detect input signal = 1 on match (1) transition detection sets output signal high 110 reserved transition detection toggles output signal 111 n.a. (2) 2. on the microinstruction fields ipaca/b and opaca/ b this value is neutral, meaning that ipac/opac register values are not changed. n.a. (2) table 474. psc and pscs encoding psc output pin action 00 force pin state according to opaca (pscs = 0) or opacb (pscs = 1). 01 force pin high. 10 force pin low. 11 do not change pin state. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 879/1740 depends on the pre-defined channel mode (pdcm) register and the user defined channel mode (udcm). for details refer to section , match/transition pin action conflict resolution . psti and pss ? pin state input and pin sampled state registers during the time slot transition period, or whenever the chan register is written by microcode, the filtered (ae) input signal psti or output signal psto (selected by the etpu_cxcr bit etpd) is sampled into the branch logic as the pss flag (see figure 528 and table 542 ). the microcode can then branch on either the currently driven (psto) or input (psti) pin state, or on sampled pin state (pss, which is stable as long as chan does not change). note: if a transition occurs simultaneously (after the filter) with the chan assignment, pss samples the new pin value. therefore, if tdla/b is cleared simultaneously with the assignment chan := chan, the occurrence of a transition at this very moment can still be tested with pss. prss ? pin request service sample channel logic can, depending on its state and programmed mode, request service to the etpu microengine (see section 24.5.1, functions and threads ). when the channel logic issues a service request, the filtered input signal psti is sampled into an internal channel flag prss. there is one such prss flag for each channel (see figure 528 ). channel prss keeps its value until all its service request sources are cleared and until a new service request rises. the channel prss flag is sampled into the branch logic as the prss flag (see table 542 ) during the time slot transition period, or whenever the chan register is written by microcode. obe ? output buffer enable control latch obe latch drives the output buffer enable signal, which can be used (depending on mcu integration) to control the output signal pad driver. channel output comes disabled from reset. if ipp_obe_[1|2]([0-31]) (af) from etpu is used on mcu integration and a signal is desired to be output in a channel, obe signal must be set by microcode. microcode field tbsa is used to set/reset the output buffer enable control when microcode field tbsa bit 3 is 1, according to table 475 . ae. the filter can be bypassed. af. output buffer enable: there is one independent obe signal for each channel. table 475. tbsa output buffer control microcode tbsa[2:0] meaning when tbsa[3] = 1 000 enable output buffer 001 disable output buffer 111 do nothing other values reserved enhanced time processing unit (etpu2) RM0029 880/1740 doc id 15177 rev 8 figure 528. pin state input/output logic general channel registers these registers control other aspects of channel logic. except for chan, they are unique per channel. table 476 summarizes the registers and access options. digital filter qd chan transition q s r from output logic to branch logic psto pss to branch logic psti input pad psti q s r from tbsa etpu mcu integration output pad and etpu_cxcsr obe to etpu_cxcsr odis opol frometpu_cxcr 0 0 1 1 set reset 0 1 frometpu_cxcr etpd synch. 1 0 cdfc==01 obe channel input channel output odis q d chan transition prss to branch logic q d channel service request RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 881/1740 channel selection register ? chan chan is the register that holds the number of the channel that qualifies the context of most channel registers, including pin control and er accesses, and is common to all channels in a same engine. when a thread starts to be executed, the contents of chan register is automatically updated on time slot transition to the number of the channel to be serviced. serviced channel is constant during channel servicing, but the selected channel can be changed any time by microengine writing into chan register. some microinstructions are affected by the serviced channel instead of chan. these are: conditional branch using lsr (see section , link register ) or function mode ( section , etpu_cxscr ? etpu channel x status control register ). negate channel flag lsr, interrupt cpu and data transfer request (see section , channel interrupt and data transfer requests ). when chan register is written, accesses are qualified by the new chan register value from the instruction following chan assignment on, except capturea/b sampling into erta/b and match register writing from erta/b (see section , chan assignment, read match and erwa/b ). writing chan (including with the same value, chan:= chan) updates erta and ertb with the new captured values, the branch logic with updated mrla/b and tdla/b flags. ta ble 47 7 shows the commands, flags and registers selected by the chan register value table 476. general channel registers microcode access register access type sampled from channel update to channel microcode fields (1) reset value chan read/write n.a. (2) n.a. (2) t4abs, t4bbs, t2abd defaults to serviced channel at thread start pdcm write only no immediate pdcm 1100 (sm_st) udcm write only no from erta by microcode cmw, erwa parameter value defined at integration sri write only no immediate mtd 1 flag1,flag0 branch flag test, write no immediate bcc,flc 0, 0 1. see section 24.5.9, microinstruction set . 2. chan is common to all channels in the engine. table 477. chan-selected features feature used selected by chan channel-relative spram access yes branch using pss, prss, psti and psto channel flags yes enhanced time processing unit (etpu2) RM0029 882/1740 doc id 15177 rev 8 pdcm ? predefined channel mode pdcm determines the channel mode assigned to the channel. channel mode defines much of the channel logic behavior, specially how matches blocks and enables transitions and vice-versa, as well as occurrence of time base captures and service requests based on matches and transitions. for a complete description see section , channel modes . pdcm is a 4-bit register set by the microcode field of the same name (see section , predefined channel modes ), and cannot be read or tested in branch instructions. ta ble 47 8 relates the pdcm value with channel modes. the second column specifies the mnemonic used to reference the mode, introduced in section , channel modes overview . there is one pdcm for each channel, initialized with 1100 on reset. pdcm is also used to select the user programmable channel mode. if this selection is made, the channel behavior is defined by the settings of the udcm register (see section , udcm ? user defined channel mode ). branch using mrla/b, tdla/b, flag0/1 (1) yes branch on all other conditions (2) no erta/b value yes configure (selected) channel yes channel commands applied to: mrla/b, tdla/b, tbsa/b, ipaca/b,opaca/b, psc, pscs, obe, pdcm, mrle, flag0/1 yes channel command: set/reset sri yes channel command: write to match registers (erwa/b) yes (3) channel command: read match registers into erta/b yes clear lsr no channel interrupts and data transfer requests (circ) optionally 1. in tpu, these conditions retained the old values. 2. refer to section , branch operations 3. if write match (erwa/b) occurs at the same time of a chan assignment, the channel which is target of the write is the one selected by the new chan value. see section , chan assignment, read match and erwa/b . table 477. chan-selected features feature used selected by chan RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 883/1740 udcm ? user defined channel mode udcm holds the control signals that define the channel logic behavior in terms of match and transition blocking and enabling, captures and service requests triggered by events. the register layout is defined in figure 529 . the individual fields are defined in section , channel mode logic and event flags . there is one udcm register for each channel, which can be independently programmed. udcm can only be written into the match register by microcode, through erta/b microengine registers (see section , write channel match and udcm registers ). figure 529. udcm register sri ? match/transition service request inhibit latch sri blocks channel service requests due to the assertion of mrla/b and/or tdla/b. sri does not affect recognition of link service requests or host service requests, neither table 478. pdcm encoding pdcm channel mode 0000 em_b_st 0001 em_b_dt 0010 em_nb_st 0011 em_nb_dt 0100 m2_st 0101 m2_dt 0110 bm_st 0111 bm_dt 1000 m2_o_st 1001 m2_o_dt 1010 user defined channel mode 1011 reserved 1100 sm_st (1) 1. this is the reset value, also compatible with tpu channel behavior. 1101 sm_dt 1110 sm_st_e 1111 n.a. (2) 2. this value is used as a neutral (do not change) value in the pdcm microinstruction field. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r rese rved rese rved msr mca p m1e t m1em 2 m1bm 2 m2bm 1 m2b t t1bm 1 t2bm 1 tbm 2 t1et 2 tsr tca p w enhanced time processing unit (etpu2) RM0029 884/1740 doc id 15177 rev 8 mrla/b or tdla/b microcode branch tests nor entry table selection (ag) . sri is asserted during reset and is controlled by microcode field mtd. to unburden the microengine, sri asserted configures a channel ?dumb? regarding the servicing of match and capture channel service requests. even with sri = 1, tdla/b and mrla/b can still be asserted, and the level specified by the opac (output pin action control) registers will be output to the pin. flag1,flag0 ? channel ?state resolution? flags each channel has a pair of flags, simply called flag0 and flag1, that can be set/reset by microcode through microinstruction field flc. flc sets/resets flag0/1 of the channel selected by chan. these flags can be tested by microcode, and are also used to resolve the microcode entry point for the channel service (see section , entry points ). flag0 and flag1 are, so, typically used for fast state resolution. flc microinstruction field also allows flag1,flag0 to be copied from selected bits of p register high byte, which is also meant to be used to hold application state. flag0 and flag1 are both zero out of reset. match recognition the match operation is performed every microcycle by comparing the channel matcha and matchb registers against the value of the tcr bus specified for each match. tcr1 or tcr2 bus is selected according to tbsa and tbsb fields. both results have effect on the next clock cycle (see section 24.7.1, microcycle and i/o timing ). a match a/b event is qualified by a set of match enabling conditions to the match recognition registers mrla/b. to recognize the match and assert these registers, the following match enabling conditions are required: for ipaca/b = 0xx, match enable flag (mef), qualified by the channel currently being serviced must be asserted. for ipaca/b = 1xx, match a/b is always enabled (even during time slot transition (tst)), regardless of the state of the match enable flag (mef). see section , mef ? match enable flag for the conditions of mef assertion. match recognition latch enable 1/2 (mrlea/b) is asserted. a match event recognition may only occur if its corresponding mrlea/b bit is set, which only happens upon a write to a channel match register by the microcode, copied from erta/b. mrlea/b is negated when the respective match occurs or, in some double match channel modes, when a match for the other match register occurs. it ensures that the greater-equal comparison will not cause additional matches (ah) . in selected modes (see section , channel modes ), the particular conditions of mrl and tdl flags of the other event, i.e: ? mrla, tdla enable or block mrlb; ? mrlb, tdlb enable or block mrla. the respective mrl is negated. in selected modes (see section , channel modes ), the state of its respective tdl flag. if the match a and/or match b conditions are met, the channel immediately forces the pin state if specified by the appropriate opaca/b registers (output pin action control 1/2) and, in some cases, by ipaca/b registers. refer to section , ipaca,ipacb and opaca,opacb ? input and output pin action control registers . ag. in tpu, sri also blocked tdl and mdl branches and enabled any transition to capture time base. ah. microcode can also negate mrlea/b. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 885/1740 if both match a and match b events occur at the same time, with conflicting pin actions, the priority over the pin action is mode dependent. for further details on pin action resolution refer to section , match/transition pin action conflict resolution . mrla/b ? match recognition latches mrla/b indicate the recognition of a match event detected by the comparator. they can be asserted either on t2 or t4 (see section 24.7.1, microcycle and i/o timing ). assertion of mrla/b issues a match service request in specific channel modes, depending on previous events and state of sri. after reset mrla and mrlb are both negated. when mrla or mrlb is asserted, it may change the output signal level according to the input and output pin action control registers (refer to section , ipaca,ipacb and opaca,opacb ? input and output pin action control registers ). assertion of mrla/b causes a capture of one or two time bases, according to the selected mode capturing scheme (see section , transition detection and time base capture ). a match recognition is self-blocking, regardless of channel mode: once mrla (mrlb) has been asserted, it negates its associated mrlea (mrleb) register, preventing future match recognitions, until the associated match register is rewritten by microcode. the microcode has to enable new matches by updating the new match value in the matcha (matchb) register (ai) . in addition, assertion of mrla/b can block its twin mrlb/a, depending on the channel mode. in some double match blocking channel modes, match a/b event blocks the occurrence of match b/a in a ?first win? scheme. it is the transition from 0 to 1 in mrl that causes the match actions: apart from mrlea/b negation(s), no action due to a match occurs if mrl was already set to 1, even if the other mrl assert conditions are satisfied. however, if a match and a microoperation negating its corresponding mrl occur at the same time, mrl negation by microcode overrides its assertion, but any dependable captures and pin action occurs anyway (if mrl was already negated before), and also the negation of mrle(s) (the respective one and, in some channel modes, the other, regardless of mrl state before). note that mrle must have been set before (by writing a new match value). mef ? match enable flag mef is a one-bit latch that is unique for all channels in an engine. mef can selectively enable assertion of mrla/b, depending on the ipaca/b field. for ipaca/b = 0xx, mef = 1 enables assertion of mrla/b for the scheduled channel during service. for ipaca/b = 1xx, match a/b is always enabled, regardless the state of the mef, but it still depends on the other match recognition conditions. matches of channels not being serviced are never disabled by mef. mef is not accessible by microengine or host. mef is negated for one microcycle in the middle of the time slot transition period. after two microcycles (plus wait-states) into tst, the me bit in the entry point is copied to mef to allow selective enabling of mrl for each thread (refer to section , time slot transition ). mef is asserted unconditionally soon after a thread ends. if a channel service needs to postpone a programmed match, mef assures that microcode wins the race against match event after time slot transition (only for ipac = 0xx). ai. before that, microcode should also negate mrla (mrlb), otherwise an old match may be recognized by the scheduler and serviced as a new one enhanced time processing unit (etpu2) RM0029 886/1740 doc id 15177 rev 8 note that a match event may be lost during the periods when mef is negated only if: the match comparator is configured for ?equal-only? behavior, and ipaca/b = 0xx, and tcr increments at the rate of system clock divided by 2 or faster. when the comparator is configured as ?greater-equal?, the match event that occurred when mef was negated may be recognized after mef is asserted again, due to the ?greater than? condition. mrlea/b ? match recognition latch enable mrlea/b is negated upon the assertion of its respective mrla/b. in blocking match channel modes it may also be negated together with the assertion of the twin mrlb/a. the mrlea/b bits ensure that data captured due to the first match event will not be overwritten when mrla/b is negated: due to greater-equal comparison, the match condition continues to be true, but should not cause another capture event. in addition to negation by local match event, the microcode can negate both mrlea and mrleb, to block pending matches, and also mrla/b, individually. this action will prevent future match events from the selected channel. writing the matcha/b registers by microcode to schedule the next match values sets mrlea and/or mrleb and enables new matches. this setting overrides the mrle negation conditions due to channel logic or microcode (see section , channel modes ). by combining write to match a/b with mrlea/b negation microinstructions, the microcode can negate one mrle while asserting the other. note: if the mrle negation conditions continue after writing matcha/b registers, the respective mrle does not keep asserted. for instance, if mrl = 1 and a match is programmed for a time value in the past during a thread with mef = 1, then mrle will be cleared soon after matcha/b is written, even though a match does not occur (because mrl was already asserted, neither captures nor pin toggles occur). when the match register is updated (with mrle already asserted before) and field mrla/b = 1 (no clear, see section , clear transition/match event registers ) and mrla/b flag is zero, the etpu behaves exactly as the tpu, that is: a match that comes concurrently with the rewrite of the match register, matching the old value, sets the mrl, as if the setting of the mrle due to match register write had precedence over its clear by the match at that moment. after this simultaneous operation, the mrle value stays at 1, and the captured time base value, if any, reflects the match value. when the match register is updated (with mrle already asserted before) and field mrla/b = 0 (clear mrl, see section , clear transition/match event registers ) and mrla/b flag is zero, the match captures will occur, the mrla/b flag will keep negated, and mrle will stay asserted. if a match is reprogrammed on tcr1 running at t2/t4 timing (tcr1cs = 1, see section , etpu_tbcr ? etpu time base configuration register ), a match can occur after mrla/b is cleared, together with the set of mrle. in this case, both mrl and mrle will be set, and a match service request will occur if enabled. however, the match happened on the old match value, not on the new (reprogrammed) one. in order to prevent this ambiguity to the code that services the match, it is advisable to clear the mrle (besides mrl) together with the match reprogramming, avoiding the match on the old value to occur while the new match value is being written. the set of the mrle due to match reprogramming prevails over the mrle clear, thus allowing the new programmed match to occur. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 887/1740 transition detection and time base capture time base capture(s) occur when the value of a specified tcr is sampled into the capturea and/or captureb register. tbsa[1] and tbsb[1] select which tcr will be captured in capturea and captureb, respectively. a capture event may occur due to either of the following events: the assertion condition of match recognition latch (mrl), even if mrl is simultaneously negated by microcode the assertion condition of transition detection latch (tdl), even if tdl is simultaneously negated by microcode. any transition event specified by ipaca if both the transition detection latch tdla and transition continuous capture enable tccea are asserted. a capture event occurs together with the assertion of mrl or tdl either on t2 or t4 positive edges, and captures the time-base value that caused the match, even if tcr1/2 increments concurrently with the assertion (see section 24.7.1, microcycle and i/o timing ) (aj) . mrla/b and tdla may, depending on the channel mode, inhibit the capture of the second event?s tcr into capturea/b. as a general rule, values captured by signal transitions are not overwritten by values captured by match events. when the enable bit tccea is asserted, captures due to transition events also occur after tdla is asserted. those captures happen on transition events specified by ipaca, and the tcr value is saved into capturea register only. the capturing scheme is defined by the channel mode programmed at register pdcm, or at register udcm when user defined channel mode is selected. for more information on mode-dependent capture schemes refer to section , channel modes . tdla/b ? transition detect latches tdla/b indicate detection of specific transition occurrences on a channel input signal. tdla and tdlb assertion causes service request in single and double transition predefined modes, respectively. tdlb assertion does not cause service request in single transition predefined modes, and tdla assertion does not cause service request in double transition predefined modes. in single transition channel predefined modes tdlb can be asserted on the second transition, but does not generate service request. yet on predefined modes, tdlb assertion is enabled only if tdla is asserted to detect an ordered input signal double transition. all the restrictions above, however, may be overridden by using the user defined channel mode. the ipaca and ipacb registers indicate the programmed edges of the first and second detected transition, respectively. the sampling of a determined value (0 or 1) on the input signal due the occurrence of a match is also treated as a ?transition?, depending on ipaca/b programming (see section , ipaca,ipacb and opaca,opacb ? input and output pin action control registers ). when using a channel mode where the transition1 is initially blocked and ipaca is programmed to detect such ?transitions?, the occurrence of a match a only unblocks the transition after the sampling. it means that the transition on the first match (ipaca configurations 100 and 101) is not effective on predefined modes where transition a is enabled by match a (m2_st, m2_dt, m2_o_st and m2_o_dt) or user-defined modes with udcm bit m1et asserted. a aj. in tpu3, when tcr1 was counting at maximum rate of system clock divided by 2, the next value was captured. enhanced time processing unit (etpu2) RM0029 888/1740 doc id 15177 rev 8 transition a can still happen after the match a, however, if matcha register is reprogrammed without clearing mrla. tdla/b assertion conditions initiates a capture event of one or both selected tcr buses. tdla or tdlb transition event generates a service request, depending on channel mode, previous events and the state of sri. for more information on the service request scheme, refer to section , entry point address generation , and section , channel modes . assertion of tdla/b occurs on either t2 or t4 positive edges. the capture event occurs on the same clock, and captures the time base value present when tdla/b was asserted aj . tdla and tdlb are negated during reset and may also be negated independently by microcode. tdla/b is reset by no way other than reset and microcode. it is the transition from 0 to 1 in tdl that causes the transition actions: even if tdl assert conditions are satisfied, no action due to a transition occurs if tdl was already set to 1. however, if a transition and a microoperation negating tdls occur at the same time and tdl was already negated, tdl negation by microcode overrides its assertion, but any dependable captures and pin action occurs anyway. tccea ? transition continuous capture enable tccea enables capture from transitions after the tdla flag is set. tccea is negated on reset, so that a capture occurs only when tdla asserts. tccea can be set and reset by microcode only, through the instruction field mtd (see section , disable match and transition service requests ). it can only be set together with inhibiting of the channel service requests (sri = 1) (ak) . when tccea is asserted, the transition events specified by ipaca that occur after tdla is set also cause captures into the capturea register only. however, output actions related to transition events are still blocked by tdla. channel modes the enhanced channels support various modes of operation combining match a/b recognition and transition detection events which set mrla/b and tdla/b. the channel mode is individually set for each channel by etpu microcode, through the pdcm register (see section , pdcm ? predefined channel mode ). the pdcm register selects among a set of 13 predefined channel modes, and also a user-defined channel mode. the order in which events occur, combined with assigned channel mode, establish which following event detections are inhibited and/or enabled, as well as the actions taken: time base capture, flag setting (mrla/b, tdla/b), match disabling (mrlea/b), output signal transition, and service request. those channel mode characteristics are fixed in the predefined modes, but can be individually programmed in the user-defined channel mode. a generic description of channel modes from the usage point of view can be found in section , channel modes overview . each mode is named with a mnemonic acronym for terse reference. the individual programmed attributes of the user-programmable channel mode are also described. the modes are used differently for input and output signals, as explained in section , predefined channel modes on input signal processing , and section , channel modes on output signal generation . modes also allow combining input processing and output ak. tccea provides compatibility with tpu when service request is inhibited. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 889/1740 generation in a single channel, as exemplified in section , combining input and output signals . section , channel mode logic and event flags , shows a structural definition of channel logic and its relation to channel modes. a dynamic, event-oriented view of each channel mode can be found in section 24.7.3, predefined channel mode summary . channel mode logic and event flags figure 530 shows a more detailed diagram of channel mode logic. the logic shown here is not necessarily identical to the actual channel logic implementation, but is equivalent with respect to conditions for event blocking, enabling, capture, and service requests. signals msr, tsr, mcap, tcap, m1et, m1em2, m1bm2, m2bm1, m2bt, t1bm1, t2bm1, tbm2 and t1et2 are decoded from programmed channel mode pdcm in predefined modes, and come directly from th e udcm register when user-defined mode is selected: tsr (1 bit) defines service requests issued by transitions, as shown in table 480 . msr (2 bits) defines service requests issued by matches, as shown in table 479 . tcap (1 bit) defines time base captures caused by transitions, as shown in table 480 . mcap (1bit) defines time base captures caused by matches, as shown in table 481 . m1et, m1em2, m1bm2, m2bm1, m2bt, t1bm1, t2bm1, tbm2, t1et2 (1 bit each) define match and transition reciprocal blocking and enabling, as well as transition ordering, as shown in ta ble 48 2 and ta ble 48 3 . ta ble 48 4 shows the decoded values of those control signals for each predefined channel mode. the first column shows the mnemonic reference for the predefined channel modes described in the following sections. changing pdcm or the udcm when user mode is selected may set or reset any of the channel flags, or issue captures and service requests, so it is advisable to switch channel modes only in a quiescent channel state, with channel flags mrlea/b, tdla/b, mrla/b cleared. furthermore, an event flag asserted in one mode may keep asserted after the mode programming change, even if the flag is impossible to be set in the new mode. table 479. msr[1:0] signals ? match service requests value msr 00 issue no service requests on matches 01 issue service request on match b only 10 issue service request on 2nd (1) match 1. 2nd match means the match that happens after the 1st match in time, either match a or match b. 11 issue service request on both matches enhanced time processing unit (etpu2) RM0029 890/1740 doc id 15177 rev 8 table 480. tcap and tsr signals ? transition captures and service requests value tcap tsr 0 1st (1) transition captures time bases corresponding to transition a and transition b (2) transition a captures corresponding time base if it is the second transition; transition b captures corresponding time base if it is the second transition. issue service request on the 1st (1) transition 1 transition a captures corresponding time base. transition b captures corresponding time base. issue service request on the 2nd (3) transition 1. 1st transition means the transitio n that happens first in time, either transition a or transition b. 2. match capture(s) never overwrites a transition capture. transition captures can al ways override a match capture. 3. 2nd transition means the transition that happens second in time, either transition a or transition b table 481. mcap signal ? match capture value mcap 0 match a captures corresponding time base; match b captures corresponding time base 1 either match captures time bases corresponding to match a and match b (1) 1. match capture(s) never overrides a transition capture. transition capt ures can always override a match capture. table 482. tbm2 signal ? transition blocks match b value tbm2 0 transition a blocks match b 1 transition b blocks match b table 483. m1et, m1em2, m1bm2, m2bm1, m2bt signals signal active value meaning m1et (match a enable transitions) transitions are initially blocked, and match a enables transitions m1em2 (match a enables match b) match b is initially blocked (1) , and match a enables match b m1bm2 (2) (match a blocks match b) match b is initially enabled (1) , and match a blocks match b (3) m2bm1 (2) (match b blocks match a) match a is initially enabled, and match b blocks match a (3) m2bt (match b blocks transitions) match b blocks transitions t1bm1 (transition a blocks match a) transition a blocks match a RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 891/1740 t2bm1 (transition b blocks match a) transition b blocks match a t1et2 (transition a enables transition b) transition b is initially blocked, and transition a enables transition b 1. the initial condition of m1em2 prevails over m1 bm2, while m1bm2 blocking prevails over m1em2 enabling, so that match b stays always blo cked when both m1bm2 and m1em2 are active. this combination is used in single-match modes (sm_*). 2. blocking of one match by the other is done through mrles. 3. matches always block themselves by resetting their own mrles (match a always blocks match a, match b always blocks match b) table 483. m1et, m1em2, m1bm2, m2bm1, m2bt signals signal active value meaning table 484. predefined channel mode control signals decoding predefined mode msr mcap m1et m1em2 m1bm2 m2bm1 m2bt t1bm1 t2bm1 tbm2 (1) t1et2 tsr (1) tcap (1) em_nb_st 11 0 off off off off off on off 0 on 0 0 em_nb_dt 11 0 off off off off off on off 1 on 1 1 em_b_st 11 1 off off on on off on off 0 on 0 0 em_b_dt 11 1 off off on on off on off 1 on 1 1 bm_st 10 0 off off off off off on off 0 on 0 0 bm_dt (2) 10 0 off off off off off off on 1 on 1 1 m2_st 01 0 on off off on off on off 0 on 0 0 m2_dt 01 0 on off off on off on off 1 on 1 1 m2_o_st 01 0 on on off off on on off 0 on 0 0 m2_o_dt 01 0 on on off off on on off 1 on 1 1 sm_st 11 1 off on on on off on off 0 on 0 0 sm_dt (2) 11 1 off on on on off off on 1 on 1 1 sm_st_e (3) 11 0 off on on on off on off 0 on 0 0 1. signals tsr, tcap and tbm2 replace the signal dtm used in previous etpu versions. 2. bm_dt and sm_dt are exceptions in the match blocking logic by transitions. see section , both match request modes (bm_st, bm_dt) , and section , single match modes (sm_st, sm_dt) . 3. sm_st_e is an exception in the capture scheme. see section , single match enhanced mode (sm_st_e) . enhanced time processing unit (etpu2) RM0029 892/1740 doc id 15177 rev 8 figure 530. channel mode logic and event flags s r q tdla sysclk s r q mrla sysclk t4s r q mrlea sysclk comparator a ucode erwa m2bm1 sri ucode tdl trans. event a m1et m2bt s r q tdlb sysclk s r q mrlb sysclk t4s r q mrleb sysclk comparator b ucode erwb m1bm2 ucode tdl ucode mrla ucode mrlb m1em2 match a sr match b sr transa sr transb sr msr[1] msr[0] msr[0] msr[1] tcap captureb mcap note: all flip-flops but mrle reset-dominant load enable capturea mcap load enable sm_st_e mef channel service non-filtered trans. detection b 1 0 tbm2 t1bm1 all control signals active high. ipaca[2] mef channel service ipacb[2] ucode clr mrlea clr mrleb sm_st_e tse1 1 0 tsr tse1 tse2 angle tooth detection window (channel 0 only) trans. event b tse2 ts2 ts1 ts1 ts2 (see figure 59) t2bm1 t1et2 tcap tsr tsr tcap tcap s r q tccea t2 ucode mtd ucode mtd 1 0 tsr ts1 ts2 tooth detection (see figure 59) (channels 1, 2 only) trans. event a RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 893/1740 channel modes overview predefined channel modes are divided according to the way they treat transitions in two basic modes: single transition modes (mnemonic suffix _st ): in these modes the first transition (flagged in tdla) issues a service request, and captures both time bases (selected by tbsa[1] and tbsb[1]) except on sm_st_e. the second transition (flagged in tdlb) does not issue a service request, but it captures time base selected by tbsb[1], except on sm_st_e. double transition modes (mnemonic suffix _dt ): in these modes the second transition (flagged in tdlb) issues a service request, and each transition captures its own selected time base (transition a and transition b capture time bases selected by tbsa[1] and tbsb[1], respectively). in predefined modes, transition b is always (but not only) enabled by transition a, so that transitions are always ordered: tdla is set on the first transition and tdlb on the second. unordered transitions are possible with user-defined mode, when udcm bit t1et2 = 0. matches are generally not ordered, except on specific ordered match modes m2_o_st and m2_o_dt. match capture(s) never overrides a transition capture, while transition captures can always override a match capture, either in predefined or user-defined modes. the following general rules apply to both predefined and user-defined modes: blocking of one match by the other, when it occurs, is done through mrles. matches always block themselves by resetting their own mrles (match a always blocks match a, match b always blocks match b). predefined modes differ mostly by the way matches affects and are affected by other matches and transitions, as explained in next sections. however, some general rules on match blocking apply: match b is blocked by first transition (tdla) in single transition modes, and by second transition (tdlb) in double transition modes. both matches are blocked by first transition in single transition modes. note: the rules above and in following sections may be overruled by the state of the channel latches if they are set/reset by microcode or if channel mode is changed. care must be taken to change channel modes, and is advisable to reset channel flags mrla/b, tdla/b and mrlea/b before writing pdcm, or to udcm when user-defined mode is selected. either match, blocking modes (em_b_st, em_b_dt) in these modes the first match recognition that occurs blocks the other match recognition and generates a service request. they end up with one service request for two programmed match recognitions where only the first match recognition has an actual effect. if both match recognitions occur at the same time, both mrla and mrlb are set, before the mutual blocking takes effect. enhanced time processing unit (etpu2) RM0029 894/1740 doc id 15177 rev 8 figure 531. either match, blocking modes (em_b_st, em_b_dt) either match, non blocking modes (em_nb_st, em_nb_dt) in these modes both match recognitions are independent and each of them generates service request. each match recognition captures its related time base and does not block the other. s r q tdla t2 s r q mrla t2 t4s r q mrlea sysclk comparator a ucode erwa sri trans. event a s r q tdlb t2 s r q mrlb t2 t4s r q mrleb sysclk comparator b ucode erwb ucode tdl trans. event b ucode mrla ucode mrlb match a sr match b sr transa sr transb sr captureb load enable capturea load enable mef channel service double trans. 1 0 double trans. double trans. note: all flip-flops but mrle reset-dominant; all control signals active high. ipaca[2] mef channel service ipacb[2] ts1 ts2 ts1 ts2 ucode tdl trans.event a tccea ucode clr mrlea ucode clr mrleb RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 895/1740 figure 532. either match, non blocking modes (em_nb_st, em_nb_dt) match b request modes (m2_st, m2_dt) in these modes transitions are initially blocked, and are enabled by match a. match b recognition generates the match service request and disables match a recognition. each match recognition captures its own programmed timebase. in case of simultaneous match recognition, both mrla and mrlb are set, and opacb register has priority over opaca for selecting the pin action. s r q tdla t2 s r q mrla t2 t4s r q mrlea sysclk comparator a ucode erwa sri trans. event a s r q tdlb t2 s r q mrlb t2 t4s r q mrleb sysclk comparator b ucode erwb ucode tdl trans. event b ucode mrla ucode mrlb match a sr match b sr transa sr transb sr captureb load enable capturea load enable double trans. 1 0 double trans. double trans. note: all flip-flops but mrle reset-dominant; all control signals active high. mef channel service ipaca[2] mef channel service ipacb[2] ts1 ts1 ts2 ts2 ucode tdl trans.event a tccea ucode clr mrlea ucode clr mrleb enhanced time processing unit (etpu2) RM0029 896/1740 doc id 15177 rev 8 figure 533. match b request modes (m2_st, m2_dt) both match request modes (bm_st, bm_dt) in these modes, match service request is generated only after both match recognitions occurred. by definition this is a non-blocking match mode: match recognitions do not block each other, implementing a last-served scheme. unlike other double transition modes, bm_dt blocks match a with transition b (not with transition a), so that the second transition blocks both matches. s r q tdla t2 s r q mrla t2 t4s r q mrlea sysclk comparator a ucode erwa sri trans. event a s r q tdlb t2 s r q mrlb t2 t4s r q mrleb sysclk comparator b ucode erwb ucode tdl trans. event b ucode mrla ucode mrlb match b sr transa sr transb sr double trans. captureb load enable capturea load enable double trans. 1 0 double trans. note: all flip-flops but mrle reset-dominant; all control signals active high. mef channel service ipaca[2] mef channel service ipacb[2] ts1 ts1 ts2 ts2 ucode tdl trans.event a tccea ucode clr mrlea ucode clr mrleb RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 897/1740 figure 534. both match request modes (bm_st, bm_dt) ordered modes with match b request (m2_o_st, m2_o_dt) these are ordered match modes on which match a recognition must precede match b recognition (ordered 1->2). match a asserts mrla and enables match b and transitions. match b asserts mrlb, generates a match service request, and blocks both transitions. s r q tdla t2 s r q mrla t2 t4s r q mrlea sysclk comparator a ucode erwa sri trans. event a s r q tdlb t2 s r q mrlb t2 t4s r q mrleb sysclk comparator b ucode erwb ucode tdl trans. event b ucode mrla ucode mrlb match a sr match b sr transa sr transb sr captureb load enable capturea load enable double trans. 1 0 double trans. double trans. 1 0 double trans. note: all flip-flops but mrle reset-dominant; all control signals active high. mef channel service ipaca[2] mef channel service ipacb[2] ts1 ts1 ts2 ts2 ucode tdl trans.event a tccea ucode clr mrlea ucode clr mrleb enhanced time processing unit (etpu2) RM0029 898/1740 doc id 15177 rev 8 figure 535. ordered modes with match b request (m2_o_st, m2_o_dt) single match modes (sm_st, sm_dt) single match modes support single or double transition with single match recognition. mrlb is never set, and mrleb has no effect. 1 0 double trans. s r q tdla t2 s r q mrla t2 t4s r q mrlea sysclk comparator a ucode erwa sri trans. event a s r q tdlb t2 s r q mrlb t2 t4s r q mrleb sysclk comparator b ucode erwb ucode tdl trans. event b ucode mrla ucode mrlb match b sr transa sr transb sr double trans. captureb load enable capturea load enable double trans. note: all flip-flops but mrle reset-dominant; all control signals active high. mef channel service ipaca[2] mef channel service ipacb[2] ts1 ts1 ts2 ts2 ucode tdl trans.event a tccea ucode clr mrlea ucode clr mrleb RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 899/1740 figure 536. single match modes (sm_st, sm_dt) single match enhanced mode (sm_st_e) this is an enhanced single transition and single capture mode, which provides non-filtered input captures in addition to the single capture, allowing one to measure the delay of the digital filter. in an output channel, it has the same functionality of sm_st (captures both time bases at once due to a match recognition). s r q tdla t2 s r q mrla t2 t4s r q mrlea sysclk comparator a ucode erwa sri trans. event a s r q tdlb t2 t4s r q mrleb sysclk ucode erwb ucode tdl trans. event b ucode mrla match a sr match b sr transa sr transb sr captureb load enable capturea load enable double trans. double trans. s r q mrlb t2 ucode mrlb 0 note: all flip-flops but mrle reset-dominant; all control signals active high. mef channel service ipaca[2] 1 0 double trans. ts1 ts1 ts2 ts2 ucode tdl trans.event a tccea ucode clr mrlea ucode clr mrleb enhanced time processing unit (etpu2) RM0029 900/1740 doc id 15177 rev 8 figure 537. single match enhanced mode (sm_st_e) s r q tdla t2 s r q mrla t2 t4s r q mrlea sysclk comparator a ucode erwa sri trans. event a s r q tdlb t2 t4s r q mrleb sysclk ucode erwb ucode tdl ucode mrla match a sr match b sr transa sr captureb load enable capturea load enable s r q mrlb t2 ucode mrlb 0 0 non-filtered trans. event note: all flip-flops but mrle reset-dominant; all control signals active high. mef channel service ipaca[2] ts1 ts1 ucode tdl trans.event a tccea ucode clr mrlea ucode clr mrleb RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 901/1740 predefined channel modes on input signal processing when processing an input signal, the predefined channel modes can be classified in the following primary mode groups: single transition, single match: em_b_st, sm_st, sm_st_e single transition, double match: em_nb_st, bm_st, m2_st, m2_o_st double transition, single match: em_b_dt, sm_dt double transition, double match: em_nb_dt, bm_dt, m2_dt, m2_o_dt in single transition modes, tdla assertion may capture both time bases at once, while in double transition modes each transition captures its related time base in its related capture register. double transition is always ordered, i.e tdlb is enabled by tdla and generates the service request. the channel logic supports various input modes with combinations of single/double transition and single/double match, explained in the following subsections. either match, blocking, single transition (em_b_st) on an input signal, this mode provides double timeout mechanism on a programmed transition edge with two timebases. the signal transition blocks both pending matches, indicating that no timeout condition occurred. the two match recognitions block each other, giving good separation in the entry table as to which match recognition caused the first timeout condition, and generating only one service request. either match performs timebase captures which do not overwrite captures by transitions. either match, blocking, double transition (em_b_dt) in double transition mode each transition is related to one match recognition. tdla assertion captures its related timebase, blocks match a and enables tdlb. tdlb assertion blocks match b, captures its related timebase and generates a service request. match recognitions block each other, so if there is a match timeout condition on tdla, only one match service request is generated. this mode is good for qualifying two signal transitions by match timeout mechanisms, with one service request. note that although tdla assertion does not block match b recognition, the value captured in capturea by tdla assertion is not overwritten by this recognition. the second transition blocks match b. either match performs timebase captures which do not overwrite captures by transitions. either match, non blocking, single transition (em_nb_st) on an input signal, this is a double timeout mechanism of independent match recognitions of two different timebases. the match recognitions do not block each other, such that the microcode can check if one or two match recognitions occurred before their related signal transition. the signal transition detection (by ipaca) asserts tdla, blocks both matches, captures both time bases and generates a transition service request, indicating that none of the two timeout conditions occurred. any combination can be easily resolved by microcode (for example, signal transition after match a and before match b, or signal transition after both match a and match b). another possible use of this mode is allocating one match recognition for transition timeout and the other for another non-critical timed task, adding functionality to a single channel. since the transition detection blocks both match recognitions, the match recognition of the other timed task is based on the fact that the comparator checks greater-equal conditions. it may be delayed if it occurs in the period between the signal transition detection (which blocks it) and the time tdla is negated by microcode. if matches are enabled during the enhanced time processing unit (etpu2) RM0029 902/1740 doc id 15177 rev 8 service, the same code can check if the match recognition of the timed task occurred in this period, by negating tdla and writing to the chan register its own value (in order to update the mrla flag in the branch logic). either match, non blocking, double transition (em_nb_dt) in this mode each transition is related to one match recognition, and the match recognitions are independent of each other. this mode can be used to give independent timeout conditions for the first and the second signal transition recognitions, and call service in any case of any timeout condition. the first transition detection programmed in ipaca sets tdla, captures its related timebase, blocks match a recognition and enables tdlb assertion. the second transition detection programmed in ipacb sets tdlb, blocks match b recognition, captures its related timebase and generates a service request. any match recognition that occurs captures its related time base and generates a match service request, independent on the other match recognition. match b request, single transition (m2_st) on an input signal, this mode provides an open window filter for a single signal transition. mrla assertion opens the window, and enables transition detection on tdla from this time on. mrlb assertion blocks match a (by negating mrlea), providing conditional window opening, because transitions are indirectly blocked. it also generates service request, but if it happens after match a it does not block transitions, providing a non-blocking timeout mechanism for the estimated signal transition time (typically it indicates a missing transition, or mis-prediction of the transition time). transitions can be detected from the microcycle following mrla assertion. the transition a detection asserts tdla, blocks both matches, captures both timebases and generates service request. using this mode, the channel can replace software open window filtering of qualified transitions with the channel hardware window. the window opening and timeout can be scheduled for any of the two time bases or combination of them. typically, match a will be used to open a prediction window, and match b will be used as a timeout condition which does not close the prediction window. this configuration improves noise immunity from early signal transitions, and reduces the probability for blocking late signal transitions due to timeout mis-prediction. using these conditions, the microcode can easily resolve the state: if tdla and mrla are asserted and mrlb negated, signal transition is in the expected range. if mrla and mrlb are both asserted, and tdla is asserted, the signal transition had a timeout condition due to match b mis-prediction. if mrlb is asserted and tdla negated, a timeout condition occurred, and the expected signal transition had not occurred yet. if mrla is negated and mrlb is asserted, the conditional window did not open at all (for example: a time window is open only after a specific angle, otherwise it is not opened). match b request, double transition (m2_dt) this mode is used as an open window filter for two signal transitions. in this case the match a recognition opens the window (unless match b recognition occurred first), and match b recognition blocks match a and generates a match service request. it is similar to m2_st, but in this case, it is the second transition that blocks match b. mrlb assertion is a global RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 903/1740 timeout condition for the two pulses. like m2_st, mrlb can conditionally eliminate the window from opening. using the tdla, tdlb, mrla and mrlb conditions, the microcode can easily resolve the state, in a similar manner as m2_st, with additional information on the second transition (tdlb). both match request, single transition (bm_st) on an input signal, this is a double timeout mechanism on two different time bases. both match recognitions must occur before the signal transition to generate a match timeout service request. assertion of tdla blocks both match a and match b recognitions, and captures both time bases, indicating there was no double timeout condition from both time bases. using the same timebase implements two timeout conditions, the first only sets its related mrl and the second generates a service request. using these flags allows the microcode to check if one or both match recognitions precede the signal transition. both match request, double transition (bm_dt) in this mode the first transition detection does not block matches, since both match recognitions are required to generate a match service request. the second transition detection asserts tdlb, blocks match a and match b, captures its related timebase and generates transition service request. in this mode, a match a recognition which occurs after the assertion of tdla does not capture a new value in capturea, to preserve the actual signal transition time. assertion of tdla, however, always captures its related timebase. this mode allows putting a double match timeout condition on the second transition. typically, a pulse trailing edge timing can be checked against two time bases, to indicate if the pulse has not ended when both mrla and mrlb are asserted. when a transition service request is generated by tdlb assertion, the state of mrla and mrlb indicates which timeout condition occurred, if any. ordered mode with match b request, single transition (m2_o_st) on an input channel, this mode provides a closing window filter for a single signal transition. match a assertion captures its programmed time base in capturea, opens the filter window (enables assertion of tdla), and enables assertion of mrlb. match b recognition captures its related timebase, closes the window (disables assertion of tdla) and generates a service request. due to match a and match b ordering, the window is opened for at least one microcycle. match b recognition indicates a window timeout condition which blocks late signal transitions, outside the prediction window. transition detection blocks both matches, indicating the transition occurred inside the estimated window. transitions can be detected from the microcycle following mrla assertion until the microcycle on which mrlb is asserted. when tdla is asserted inside the window range it disables both matches, captures both time bases and generates a transition service request. using this mode, the channel can replace software window filtering of qualified transitions with the channel hardware window. the window opening and closing time can be scheduled for any of the two time bases or a combination of them. ordered mode with match b request, double transition (m2_o_dt) in this mode the channel logic implements a window filter for two detected signal transitions. mrla assertion captures its related timebase and enables the assertion of both tdla and tdlb. mrlb assertion captures its related timebase and disables the assertion of both tdla and tdlb. transitions can be detected from the microcycle following mrla assertion until the microcycle on which mrlb is asserted. the first signal transition (following mrla enhanced time processing unit (etpu2) RM0029 904/1740 doc id 15177 rev 8 assertion) asserts tdla, captures its related timebase and enables assertion of tdlb. the second signal transition detection asserts tdlb, blocks match b, captures its related timebase and generates the service request. if both signal transitions occur inside the scheduled window, match b recognition is blocked. if one or both signal transitions do not occur inside the scheduled window, match b recognition generates a match service request and blocks further transition detections. the microcode can resolve the state using mrla, mrlb, tdla and tdlb, which affect the entry point selection. single match enhanced mode (sm_st_e) this is an enhanced single transition and single match channel mode which provides timing information of the digital filter delay. the capturea register captures the timebase selected by tbsa due to transition detection specified by ipaca or match recognition, as in sm_st mode. initially, the captureb register continuously captures the unfiltered ipacb-selected signal transitions from the digital filter input, directly from the signal synchronizer. when an ipaca-qualified, filtered transition detection occurs, tdla is set, mrla assertion is blocked, and, in addition, captures into captureb are also blocked. on service, capturea and captureb (copied into erta and ertb) holds the time of the qualified transition detection (erta), and the time of the last signal transition at the input of the digital filter (ertb). subtracting the time in ertb from the time in erta provides the delay of the digital filter. in a quiet environment, the two captures provide the accurate delay of the digital filter in granularity of two system clocks. in a noisy environment, false transitions may be detected at the input of the digital filter due to the noise, and the delay measurement may be reduced, especially if ipacb selects both edge detection. the microcode can do sanity checks on this value to recognize noise effects (for example: calculated delay is less than the minimum delay of the digital filter). note: in channel 0, if etpu_tbcr field am = 01 (angle mode), the unfiltered input comes from tcrclk input and the filtered input comes from the tcrclk filter output. the edge is selected by ipaca/b, and is independent of the edge selection by etpu_tbcr field tcr2ctl. single match, single transition (sm_st) in this mode the channel logic is functionally back-compatible to a tpu3 single action channel, but a match or transition detection captures at once both timebases. the mode recognizes a single transition with single match timeout. either tdla or mrla generates service request and captures both timebases. assertion of tdla blocks future assertions of mrla. single match, double transition (sm_dt) in this mode, the first transition detection asserts tdla, captures a timebase in capturea and enables tdlb. the second signal transition asserts tdlb, blocks match a, captures a timebase in captureb and generates a service request. match a (before tdlb) captures into captureb the timebase selected by tbsa, in order not to overwrite the captured value of tdla. this mode is used for scheduling one timeout condition on two input signal transitions (pulse timeout). RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 905/1740 channel modes on output signal generation since channel logic can generate output signal transitions based on matches, the channel can be viewed as working in the following primary mode groups for signal generation: single match: em_b_st, sm_st, sm_st_e, em_b_dt, sm_dt double match: em_nb_st, bm_st, m2_st, m2_o_st, em_nb_dt, bm_dt, m2_dt, m2_o_dt the channel logic supports various match channel modes with single/double match, as explained in the following subsections. either match, blocking modes (em_b_st, em_b_dt) on an output signal these modes are useful when using two different time bases to set a required signal transition. the first match condition which is met sets a required pin action, captures both time bases, blocks any effects of the other recognition, and generates a service request. because the first match recognition blocks the other, the microcode can get good separation in the function entry table as to which match caused the timeout first, and both time bases are captured, enabling the microcode to compare one timebase to the other at the moment of the match recognition. these modes can be used for: scheduling a required pin action to the first match recognition of two different time bases. cancelling a programmed pin action scheduled on one time base by match on another timebase (as a consequence of ta ble 48 5 ). microcode has to set the opac register of the cancelling match to no-action and the opac register of the other match to the required pin action which may be blocked. if match a is the cancelling match, it blocks the pin action also in case of two matches at the same time, since it has priority in this case. if match b is the cancelling match, it does not block the pin action in case of two matches at the same time. either match, non blocking modes (em_nb_st, em_nb_dt) on an output signal these modes are useful in combination with the me bit set on the entry point, to define an interlaced operation. for example, each match recognition can set a pin action, and the second pin action is not sensitive to microcode latency (me bit asserted). example for usage is pwm interlaced function on which the latency is determined by the period and not the duty cycle. another possibility is using one match for pin actions and the other match for an unrelated timed task without pin action (double the functionality of a single channel). match b request modes (m2_st, m2_dt) on an output signal, these modes can generate narrow pulses or do conditional pin actions. a conditional pin action means that the pin state is changed only if the match recognitions occurred in the correct order, since the match b recognition which generates the service request also has priority over the pin action and blocks future match a recognitions. setting opaca to a desired pin action and opacb to no-action, and using different time bases for match a and match b defines a conditional opaca pin action which can be blocked by match b recognition. for example, setting match a on time and match b on angle can limit the pin action to a maximum angle value. when pulses are generated, the service is requested at the trailing edge of the pulse, after mrlb is asserted. both match request modes (bm_st, bm_dt) on an output signal, each match recognition can affect the pin state, and capture its programmed time base. this way the pin action can be programmed separately for both enhanced time processing unit (etpu2) RM0029 906/1740 doc id 15177 rev 8 match recognitions. for example, both match recognitions can negate the signal, and service request is generated after both conditions are met. this mechanism can set two conditions to do a required pin action, and the first recognition changes the signal, but service is called only after both conditions occur. when using the same time base, these modes can generate narrow pulses in any required order. for example, in a pwm function, when duty cycle is below 50% the function can get service on the low time and program the pulse to the required duty cycle of the high time. when duty cycle is equal or above 50%, the function can get service on the high time and program a negative pulse with the width of the required low time. to switch between the two states the function can program once the same transition time to matcha and match b with a required pin action, and on the next service program double match for the new state. another usage is generating a required pin action on one programmed time and service request later on another time, after the second match recognition occurs, or capturing some timebase on one time and generating a required signal transition and service request later. ordered modes with match b request (m2_o_st, m2_o_dt) the order of the match recognitions imply that opaca register programmed pin action always precede the opacb register pin action. setting opaca to no-action, based on the greater-equal comparator, enables using match a on one time base to delay the signal effect of match b on the other time base. this method implements a conditional pulse extension or conditional delay on signal transition. these modes can also be used for deferred pulse generation with microcode service request after its trailing edge (if match a condition comes after match b condition). another option is having match a recognition associated with output pin actions and match b recognition for a timed microcode task which has to be scheduled at a programmed time which may be delayed by the match a pin action. single match modes (sm_st, sm_dt, sm_st_e) there is no difference between plain and enhanced single match modes on an output signal. in this mode the channel logic is functionally back-compatible to a tpu3 single match output channel. match a recognition generates service request and sets the pin state according to opaca register. it captures at once the timebase selected by tbsa in capturea and the timebase selected by tbsb in captureb. match/transition pin action conflict resolution in output signals, matches and/or transitions automatically cause pin actions defined by the opaca/b and/or ipaca/b channel control registers (see section , pin control registers ). simultaneous matches/transitions may be associated with different, possibly contradictory, pin actions. these conflicts are resolved according to the table 485 . if an opaca/b = 000 (no action) prevails over non-zero opac according to table 485 , then if match a/transition a and match b/transition b occur simultaneously, no output pin action occurs, that is: a match on the action logic with opac = 000 inhibits simultaneous actions of the other opac, if prevailing according to ta ble 48 5 . that also applies when output actions are caused by inputs (opac = 1xx). RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 907/1740 combining input and output signals the processing of input signal can be combined with output signal generation. a detected input transition can trigger an output signal edge, even without microcode intervention, by using opac options 1xx. the channel set-up examples below show these two capabilities combined (see figure 538 ). the first example implements a fast (no microcode intervention) short-circuit protection feedback mechanism for driving high-current output devices. the signal after the high- current driver feeds back to the channel input. the input signal is normally delayed from the output signal by the device turn-on delay. after the channel output turns on, the channel logic must check if the driver output (connected to the channel input) follows the driven value after the maximum device turn-on delay. if it does not, the driver output is probably shorted, and the channel output must be turned off immediately to avoid damaging the device. match a causes the output to be driven high (for simplicity the output and input signals are shown as positive logic). it also causes a transition a, because ipaca = 100 and the input is still low. match b occurs after the expected driver delay, and causes a service request. if the output is shorted, a transition b occurs on match b because ipacb = 100. this will cause the output to go low immediately, because opacb = 100. in the second example , an output pulse is generated from an input transition without microcode intervention. match a opens a window for transitions and also enables match b. a rising edge on input sets output high. on match b the window closes, and input signal is checked: if sampled high, the output resets; otherwise it stays high. in the third example , a pulse is generated depending on the value sampled on the input signal at a predetermined time. match a samples the input signal, causing a transition. low level on input sets output low, otherwise it stays high. match b sets output high. in both cases a service request is issued (microcode intervention), at the beginning and at the end of the pulse (match b), if required (sri := 0). note: when ipac = 1xx, a match event can cause simultaneously a match recognition and a transition detection. depending on the channel mode, these match and transition may have conflicting effects on other transition/match blocking or enabling. in these cases, blocking always prevails over enabling, effective on the next microcycle. table 485. simultaneous match pin action priority channel mode priority em_nb_st / em_nb_dt opaca em_b_st / em_b_dt opaca bm_st / bm_dt opaca m2_st / m2_dt opacb m2_o_st / m2_o_dt in these modes there is no possibility of simultaneous matches user-defined opacb if m2bm1 = 1 and m1bm2 = 0, opaca otherwise enhanced time processing unit (etpu2) RM0029 908/1740 doc id 15177 rev 8 figure 538. input/output combination input signal output signal match a match b ipaca := 001; opaca := 101; matcha:= window open time; ipacb:= 101; opacb:= 100; matchb:= window close time, input sampling; pdcm:= m2_o_dt; enables match a match b input signal output signal ipaca:= 100; opaca:= 100; matcha:= window open time,input sampling; ipacb:= 000; opacb:= 001; matchb:= window close time = matcha + pulse width; pdcm:= em_nb_dt; example 2: pulse generation on windowed input transition example 3: pulse generation on input sampling example 1: short-circuit protection feedback ipaca:= 100; opaca:= 001; matcha:= output activate time; ipacb:= 100; opacb:= 100; matchb:= matcha + max. high-current driver turn-on delay; pdcm:= bm_dt; match a match b input signal output signal output short enables RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 909/1740 channel link a channel can issue service requests to other channels through microcode, by assigning to the write-only microengine register link (refer to section , link register ) a value which specifies the target channel of the link service request, as shown in figure 539 . writing to the link register issues a link request to the target channel, setting its lsr flag. each channel has its own lsr flag, which can be tested as a microcode branch condition (see section , conditional/unconditional branch ) and reset through the microcode field lsr (see section , clear link service request ). the link branch condition samples, at the tst start, the value used to calculate the entry point. writing link with another channel target value in the same thread issues a link service request to the new target, without negating the service request to the former one. this allows a channel to issue service requests to any number of channels, including itself. neither link nor lsr microengine accesses are qualified by the chan register, i.e., they always access the serviced channel link and lsr, regardless of the value written in chan. if microcode executes an instruction with field lsr = 0 (clear link service request), the link branch condition is cleared. however, the link service request itself is cleared only if no link was received by the serviced channel during the same thread (al) . if microengine clears lsr of its channel and, simultaneously, link service request is issued to the current serviced channel, the branch condition is cleared but the link service request remains pending. figure 539. microengine link register a channel can issue link service requests to channels in any of two engines, determined by the link register field engine selection (2 bits), as shown in ta ble 48 6 . in a single- engine etpu, link is ignored when sent to the other engine, or engine 2. the engine which receives the link cannot distinguish where the link comes from, except by some user-programmed protocol using spram parameters. all links are negated on reset. al. that can only happen if the link service request came from the other engine or from the serviced channel itself. 7 6 5 4 3 2 1 0 engine selection reserved (1) channel number 1. reserved bit must be written 0. table 486. link engine selection engine selection description 00 this engine 01 engine 1 10 (1) 1. ignored in single-engine etpu engine 2 11 (1) the other engine enhanced time processing unit (etpu2) RM0029 910/1740 doc id 15177 rev 8 enhanced digital filter ? edf the edf eliminates passing of signal transitions which are caused by noise. its purpose is to eliminate false transition service requests caused by noise pulses which are shorter than a programmed width. the edf has three modes of operations, selected by the cdfc field in the etpu_ecr (see section , etpu_ecr ? etpu engine configuration register ). these modes offer selections of trade-off between noise immunity and signal latency. cdfc also allows the filter to be bypassed. table 487 gives an example of minimum detected signal pulse and maximum filtered noise pulse in the three edf operation modes. in angle mode, if am = 01, the edf in channel 0 is replaced with the digital filter and synchronizer of the tcrclk signal. in this mode, channel 0 works in combination with the angle counter logic, and their operation is fully synchronized. following subsections provide the functional description of the etpu channel digital filter. two-sample mode in this mode the edf works like the tpu2/3 digital filter. it uses the filter clock which is the system clock divided by (2, 4, 8,.., 256) as a sampling clock. the filter clock is selected by the fpsck field in the engine configuration register (etpu_ecr) (see section , etpu_ecr ? etpu engine configuration register ). the edf compares two consecutive samples. if both samples have the same value, the input signal state is updated. note that when the fpsck field selects the system clock divided by two, the edf works like the tpu1 four-clock digital filter. three-sample mode in this mode, like in the tpu2/3 mode, the edf uses the filter clock as a sampling clock. the edf compares three consecutive samples. if all three samples have the same value, the input signal state is updated. the three-sample mode gives more signal latency than the two-sample mode, but also better noise immunity and better ratio between minimum detected signal pulse to maximum filtered noise pulse. when a certain filter clock frequency is selected for two-sample mode, double filter clock frequency can be selected to get better latency in three-sample mode. continuous mode in this mode the edf compares all the values sampled at the rate of system clock divided by two, between two consecutive filter clock pulses. if the signal is continuously stable for the entire digital filter clock period (i.e all the samples have the same signal value), the input signal state is updated. this method gives the same latency and the same ratio between minimum detected signal pulse to maximum filtered noise pulse, as the two-sample mode, as long as there is no noise. each sampled noise delays the signal transition detection by at least a whole digital filter clock period. the continuous mode gives the best noise immunity by comparing multiple samples of the noise. on the other hand, when a short noise pulse appears in the middle of the filter clock period at the same time of a real signal transition, the continuous mode may reject a real signal transition and delay the response to the first filter clock period in which the signal is continuously stable. this may add to the latency and also to the minimum detected signal pulse in a noisy environment. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 911/1740 bypass mode in bypass mode the signal that feeds the edge detection comes directly from the output of the synchronizer, not filtered. bypass mode automatically makes the channel logic work in t2/t4 timing mode (see section , channel timing modes ). filter clock prescaler the tcrclk signal and each channel conf igured as an input have an associated synchronizer followed by a digital filter connected to the signal that samples signal transitions. after reset, the digital filter filters out high and low pulse widths smaller than the period of two system clocks with etpu_ecr bit fcss = 0, or 1 system clock with fcss = 1, preventing these transitions from being input to the transition detect logic. for fpsck = 0 and fcss = 0, the synchronizer and digital filter are guaranteed to pass pulses that are as wide as or wider than four system clocks, meaning a minimum period of eight system clocks. these figures are halved by setting fcss = 1. by changing the fpsck field in register etpu_ecr the user can select a lower clock rate for the filter signal to define wider valid pulses and filter out wider noise pulses. the filter prescaler clock control is a division of the system clock. to guarantee pulse detection by the digital filter, the pulse must cover at least the stated number of samples at the filter clock rate. for example, a two sample digital filter must sample two points in the pulse to detect it. table 487 shows the minimum guaranteed detected pulse width and the maximum filtered noise pulse width. the table refers only to the digital filter operation. the external pulses may have to be wider (to ensure detection) or narrower (to ensure filtering) depending on the rise/fall delay differences in the mcu receivers and internal logic. delays introduced by synchronizer, filter and edge detection logic are explained in section , input/output signal delays . note: if the etpu_tbcr field tcrcf selects the filter clock of the channels (see section , etpu_tbcr ? etpu time base configuration register ), the tcrclk filter will be clocked as if fcss = 0 always dividing system clock /2 using fpsck, regardless if fcss is 0 or 1. table 487. pulse widths and delays filter control (fpsck) sample on system clock divided by: min. width guaranteed detected / max. width filtered (min. filter delay / max. filter delay) (1) fcss = 0 fcss = 1 two-sample or continuous mode three-sample or integrator (2) mode not avail. 000 1 2 / 1 (2 / 3) 3 / 2 (3 / 4) 000 001 2 4 / 2 (3 / 3) 6 / 4 (5 / 5) 001 010 4 8 / 4 (5 / 7) 12 / 8 (9 / 11) 010 011 8 16 / 8 (9 / 15) 24 / 16 (17 / 23) 011 100 16 32 / 16 (17 / 31) 48 / 32 (33 / 47) 100 101 32 64 / 32 (33 / 63) 96 / 64 (65 / 95) 101 110 64 128 / 64 (65 / 127) 192 / 128 (129 / 191) 110 111 128 256 / 128 (129 / 255) 384 / 256 (257 / 383) 111 not avail. 256 512 / 256 (257 / 511) 768 / 512 (513 / 767) 1. this table shows pulse widths and delays in number of periods of the system clock. 2. integrator mode is available for tcrclk filtering only, see section , tcrclk digital filter . enhanced time processing unit (etpu2) RM0029 912/1740 doc id 15177 rev 8 channel timing modes channels can work on two different timing schemes, defining the period of channel clocking, tied to t2 and t4 microengine phases, as explained in subsections below. microengine t2 and t4 phases are shown in section 24.7.1, microcycle and i/o timing . t2 channel timing in t2 timing mode the channel event state can only be updated every two system clocks (see figure 566 ). pin state, tdls, mrls and capture registers are updated on the microengine?s t2 clock phase. mrle clears also happen on t2, but mrle setting occurs on t4, together with the match register write by microcode (see section , write channel match and udcm registers ). channels work in t2 timing mode when all the following conditions are true: etpu_tbcr bit tcr1cs is 0 (see section , etpu_tbcr ? etpu time base configuration register ). the enhanced digital filter is not configured as bypass (see section , enhanced digital filter ? edf ). etpu_ecr bit fcss is 0 (see section , filter clock prescaler ). t2/t4 channel timing in t2/t4 timing mode the channel event state can be updated on any system clock (see figure 567 ). pin state, tdls, mrls, mrles, and capture registers are updated either on microengine?s t2 or t4 clock phases. mrle clears can happen on t2 or t4, but mrle setting occurs on t4 only, together with the match register write by microcode (see section , write channel match and udcm registers ). channels work in t2/t4 timing mode when either one the following conditions are true: etpu_tbcr bit tcr1cs is 1 (see section , etpu_tbcr ? etpu time base configuration register ). the enhanced digital filter is configured as bypass (see section , enhanced digital filter ? edf ). etpu_ecr bit fcss is 1 (see section , filter clock prescaler ). 24.5.6 time bases each etpu engine has two time counter registers, tcr1 and tcr2. they provide 24-bit time bases, shared by all 32 channels. any channel can use both time bases to: match channel?s internal registers matcha or matchb; capture time base value to channel?s internal registers, capturea and/or captureb, when a match recognition or an input transition detection occurs. for more information on channel events refer to section 24.5.5, enhanced channels . the tcr1 and tcr2 counters are accessible by the microcode for read and write operations. its current value is used for getting the current time, and the captured values are used for channel relative time calculations of future events. when they are written at the same time they are incremented from any clock source, the written value prevails. tcr1 with etpu_tbcr[tcr1cs] = 0 and tcr2 values are updated in t2 and read in t4 (see section 24.7.1, microcycle and i/o timing ). tcr1 can also work at full-speed system clock, and so be updated on both t2 and t4, when etpu_tbcr[tcr1cs] = 1. both tcr1 and tcr2 values can be imported from or exported to the stac bus. when their values are RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 913/1740 imported (stac clients), these registers are written from the stac bus and can only be read by microcode. for information on stac bus protocol and definition of stac modules refer to ipi stac and section , stac interface . the tcr2 counters between the two engines are out of phase by 1 system clock, even when time bases are shared between them through stac. it also applies to tcr1 counters if etpu_tbcr[tcr1cs] = 0, but they can be in phase otherwise. timer count register 1 ? tcr1 tcr1 can be used in the following modes: internally clocked mode externally clocked mode stac bus client mode the host program can read tcr1 time base through the etpu_tb1r (see section , etpu_tb1r ? etpu time base 1 (tcr1) visibility register ). the tcr1 bus runs through all the local engine channels. in channels which select tcr1 as matcha and/or matchb source, when its value is greater or equal to the programmed match value, a match a and/or match b event occurs on that channel. a recognized match event sets its related match recognition latch 1 or 2, and according to the predefined channel modes (pdcm) it may generate a channel service request. for details on etpu channels refer to section 24.5.5, enhanced channels . externally clocked mode tcr1 can be driven externally by the tcrclk input, after the digital filter. the tcr1 clock source is configured by the tcr1ctl bit, as shown in figure 540 . for more information on clock source selection, please refer to section , etpu_tbcr ? etpu time base configuration register . figure 540. tcr1 clock selection internally clocked mode tcr1 can be driven by the system clock or system clock divided by 2, before the prescaler. tcr1 can also be clocked by a peripheral timebase clock generated within the mcu, also selected by tcr1ctl. the maximum frequency of the peripheral timebase clock is system clock divided by two. tcr1 advances only on the rising edges of the peripheral timebase clock. the use of this clock is mcu-dependent. tcr1ctl can also be used to freeze tcr1 clock independently of tcr2 (unlike gtbe). tcr1ctl tcr1 system 10 00 tcrclk prescaler input originated tcr1 prescaler in tcrclk pin, after the filter 1,2,3,..,256 tcr1p 8 01 peripheral timebase clock red line (stac) bus 11 no clock 0 1 div 2 tcr1cs clock enhanced time processing unit (etpu2) RM0029 914/1740 doc id 15177 rev 8 tcr1 clock prescaling any clock source selected by tcr1ctl is prescaled by a factor of 1 to 256, selected by etpu_tbcr field tcr1p. for more information on prescaler configuration refer to section , etpu_tbcr ? etpu time base configuration register . the tcr1 prescaler resets when etpu_gtbe_in is negated. after reset, it starts counting up to tcr1p when etpu_gtbe_in is asserted. when tcr1 increments (etpu_gtbe_in = 1), the prescaler starts a new count and the new tcr1p becomes effective. when tcr1 is written by microcode, the prescaler is reloaded with tcr1p and it becomes effective, if etpu_gtbe_in is asserted. stac bus client mode in this mode the tcr1 register is continuously updated from the stac bus, and the clock selection and prescaling logic becomes ineffective. it is not writable by the microcode, and when read, it reflects the stac bus imported value. the use of eac is forbidden in client mode. this mode is configured through the register etpu_redcr (see section , etpu_redcr ? etpu stac configuration register ). stac bus server mode tcr1 bus can be exported to the stac bus as a server, providing time information to other peripherals. this mode is configured through the register etpu_redcr (see section , etpu_redcr ? etpu stac configuration register ). timer count register 2 ? tcr2 the tcr2 is a 24-bit counter which can be used in the following modes: pin transition mode: count the rise, fall or both transitions of tcrclk signal. angle clock mode: count internal tooth angle in combination with the etpu angle counter (eac) hardware which implements an angle pll, and generates angle information to the channels. this mode is targeted for angle based applications. stac (stac) bus client mode: tcr2 is driven by an external source (see section , stac bus client mode ). gated mode: count with rate derived from the system clock divided by eight. the tcrclk signal is used to gate this count, enabling pulse accumulator operations. internally clocked modes: tcr2 is driven by internal clock, with count rate either system clock divided by eight or driven from the rising edge of a peripheral timebase clock defined at mcu integration. the use and rate of the peripheral timebase clock is mcu-dependent, but must not exceed system clock divided by two. all clock sources pass through a prescaler. in addition, the tcr2 count can be originated from the eac which is a hardware angle clock and angle counter. figure 541 shows the diagram for tcr2 clock control. when tcr2 is not driven by the eac or stac, the etpu_tbcr field tcr2ctl selects the clock source, also allowing tcr2 to be frozen independently of tcr1 (see section , etpu_tbcr ? etpu time base configuration register ). when in angle mode, tcr2ctl selects the tcrclk edge sensitivity. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 915/1740 figure 541. tcr2 clock control the tcrclk signal input is passed through a synchronizer and a programmable digital filter. in angle mode with am = 01, synchronizer and filter are also used in channel 0, replacing its input synchronizer and filter, to get the same timing in the eac and channel 0. the tcrclk synchronizer is an improved filter th at provides best latency while maintaining proper noise filtering (see section , etpu_tbcr ? etpu time base configuration register , field tcrcf[1:0]?tcrclk signal filter control). the tcr2 bus runs through all the local engine channels. it transitions on clock t2 (see section 24.7.1, microcycle and i/o timing ). in channels which select tcr2 as matcha and/or matchb source, tcr2 value is compared against matcha and/or matchb registers. a recognized match event sets its related match recognition latch 1 or 2, and according to the predefined channel modes (pdcm) it may generate a channel service request. for details on etpu channels refer to section 24.5.5, enhanced channels . the tcr2 counter is accessible by the microcode for read and write operations. its current value is used for getting the current counter value (representing signal transitions, time or angle), and the captured values are used for channel relative count calculations of future events. the tcr2 value is readable to the host through the etpu_tb2r (refer to section , etpu_tb2r ? etpu time base 2 (tcr2) visibility register ). when the tcr2 bus value is imported from the stac bus (stac client mode), tcr2 is not writable by the microcode, and read access from the microcode or from the host reflect the imported tcr2 value. tcr2 clock prescaling except in angle mode, any clock source selected by tcr2ctl is prescaled by a factor of 1 to 64, selected by etpu_tbcr field tcr2p. for more information on prescaler configuration refer to section , etpu_tbcr ? etpu time base configuration register . the tcr2 prescaler resets when etpu_gtbe_in is negated. after reset, it starts counting up to tcr2p when etpu_gtbe_in is asserted. when tcr2 increments (etpu_gtbe_in = 1), the prescaler starts a new count and the new tcr2p becomes effective. when tcr2 is written sync. system clk / 8 etpu_tbcr tcr2 023 tcr2 presc. tcrclk programmable digital filter etpu_tbcr 000 001 010 011 1, 2, . . . , 64 filter clock system clock/2 0 1 6 2 samp integr. 3 etpu_ecr[fpsck] etpu_tbcr[tcrcf1] gen. filter clock etpu angle angle mode etpu_tbcr[am] 1 0 counter pin [tcr2ctl] 3 [tcr2p] (eac) to channel 0 input on angle mode (am = 01) 101 peripheral timebase clock filtered signal for tcr1 clock etpu_tbcr[tcrcf0] 1 0 to all channel filter clocks 111 no clock 100 stac bus enhanced time processing unit (etpu2) RM0029 916/1740 doc id 15177 rev 8 by microcode, the prescaler is reloaded with tcr2p and it becomes effective, if etpu_gtbe_in is asserted. the counter that divides the system clock by 8 before the prescaler also resets when etpu_gtbe_in is negated, or when tcr2 is written by microcode. tcr2 gated mode tcr2 gated mode is selected in field tcr2ctl of register etpu_tbcr. in this mode the tcrclk signal enables or disables transfer of the system clock divided by 8 to the tcr2 prescaler. by programming the prescaler, tcr2 can run at rates from system clock divided by eight down to system clock divided by 512, in steps of eight system clock divisions. for more information refer to section , etpu_tbcr ? etpu time base configuration register . tcr2 signal transition modes these modes are selected when the tcr2ctl field in etpu_tbcr is set to rise, fall or ?rise-and-fall?. in these modes the tcrclk si gnal is the tcr2 clock source, and its maximum transition rate depends on the tcrclk digital filter mode of operation. the tcrclk digital filter can be programmed to use the system clock divided by two, or use the same filter clock of the channels, controlled by the tcrcf field in etpu_tbcr. it contains an up-down counter which operates as a digital integrator, optimizing signal latency in the selected mode and clock rate. when system clock divided by two is selected, the synchronizer and the digital filter are guaranteed to pass pulses that are wider than four system clocks (two filter clocks). otherwise the tcrclk is filtered with the same filter clock as the channel input signals. for details on tcrclk and channels digital filter control refer to section , etpu_tbcr ? etpu time base configuration register , and section , enhanced digital filter ? edf . stac bus client mode in this mode the tcr2 register is continuously updated from the stac bus, and the clock selection and prescaling logic becomes ineffective. it is not write accessible for the microcode, and when read, it reflects the stac bus imported value. the use of eac is forbidden in client mode. this mode is configured through the register etpu_redcr (see section , etpu_redcr ? etpu stac configuration register ). stac bus server mode when tcr2 bus is exported to the stac bus as a server, it can provide either time or angle bus to other peripherals, according to its operation mode. this mode is configured through the register etpu_redcr (see section , etpu_redcr ? etpu stac configuration register ). to provide sequential update of the stac clients, the angle tick rate must not be faster than the stac programmed update rate. this requirement puts a limitation on the angle clock count rate on high rate mode. in this case the angle and angle fraction accumulator (see section , angle tick generator , and figure 547 ) are advanced at rate of system clock divided by eight. therefore, the stac update rate for the angle bus must not be slower than eight system clocks. tcr2 bus in angle clock mode in this mode the tcr2 counter operates as part of the etpu angle counter (eac). the tcr2 bus value reflects this angle representation in which it counts angle ticks. angle mode is selected when the am bit is set in etpu_tbcr. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 917/1740 note that when tcr2 works in angle mode, it does not count directly from the tcr2 clock input which indicates tooth signal transition. its angle counter is controlled by the count control and high rate logic (see section , count control and high rate logic ), which provides the interpolated pin position, and handle cases of missing tooth, acceleration, de- acceleration and mechanical corrections. the eac uses the tcrclk signal to get the to oth transition indicati ons. the tcr2ctl field in etpu_tbcr has to be set for the appropriate tooth edge detection rise, fall, ?rise-and- fall? or none. tcr2 count clock comes from the eac control and not directly from the physical tooth. this way the eac control processes the signal transitions and handles missing teeth and flywheel mechanical corrections. note that when tcr2ctl selects ?none? for tooth edge selection, the tcr2 is not necessarily frozen, but can still be incremented by the eac logic. in angle mode, etpu channel 0, 1 or 2 operation is combined with the eac operation. when channel 0 is selected for eac operation, the tcrclk digital filter is used both by the eac and by channel 0 to get full synchronization between the two logics. the etpu angle counter (eac) logic runs continuously and updates the tcr2 angle counter, eliminating the microcode latency in updating the tcr2 value. stac interface both time bases tcr1 and tcr2 can be shared between the engines and with other blocks in the same mcu. each one of both etpu engines can drive their time bases to the stac (shared time and count) bus, acting as a server, while any other block can capture the value into its resources and behave like a client. for further reference about the stac bus operation refer to section , etpu_redcr ? etpu stac configuration register . the etpu can export to the stac bus or import from the stac bus the following internal resources: tcr1: can be exported to or imported from the stac bus. tcr1 can only be imported from stac bus when the engine is not in angle mode. when tcr1 is imported from the stac bus, it becomes read-only for the microcode and reflects the imported values. for details refer to section , timer count register 1 ? tcr1 . tcr2: can be exported to or imported from the stac bus. tcr2 can only be imported from the stac bus when engine is not in angle mode. when tcr2 is imported from the stac bus, it becomes read-only for the microcode, and reflects the imported values. when exported to the stac bus, tcr2 can work in either angle mode or as a free running counter associated with the tcrclk signal. for details refer to section 24.5.7, eac ? etpu angle counter . proper configuration of the following bits is necessary to determine what can drive the stac bus: etpu_tbcr[am] and etpu_redcr[ren2, rsc2], according to table 488 . table 488. stac bus and host read sources am (etpu_tbcr) ren2,rsc2 (etpu_redcr) tcr2 bus source (host read of etpu_tb2r) stac bus driver 00 0x (disabled) tcr2/time x 01, 10 or 11 0x (disabled) tcr2/angle x 00 11 (server) tcr2/time tcr2/time enhanced time processing unit (etpu2) RM0029 918/1740 doc id 15177 rev 8 note that angle mode is not available for stac bus clients: configuring both at the same time brings unpredictable results. when tcr2 is a stand-alone counter or a stac bus server, the same value that is driven to the internal tcr2 bus is also exported to the stac bus (either time count or angle). stac bus configuration is provided by the etpu_redcr bits ren1/2 and rsc1/2. ren1/2 enable the stac interface to interact with the resource (either tcr1 or tcr2 bus). rsc1/2 configure the resource (either tcr1 or tcr2 bus) as server or client. each time base / angle count resource from each engine receives a unique 4-bit hard-wired address that identifies it as a potential server. this address is used by the stac controller to coordinate which resource will drive the bus at a given stac time-slot. for any time-slot there is a server driving the bus upon selection of the stac controller, and there may be a client linked to that server by the etpu _redcr bits srv1/2 on each engine. when the server address on the stac bus matches the value in srv1/2, the client will load the stac information into the appropriate resource. for information on etpu stac bus configuration refer to section , etpu_redcr ? etpu stac configuration register . the etpu does not include a stac controller module, which is instantiated once in the system integration. note: setting a timebase as client of itself is forbidden, and results are unpredictable. gtbe ? global time base enable the gtbe bit in etpu_mcr enables time bases in both engines, allowing them to be started synchronously. gtbe is divided in two block interface signals: etpu_gtbe_out and etpu_gtbe_in. gtbe bit sets etpu_gtbe_out, and etpu_gtbe_in enables time bases to start. the etpu_gtbe_out signal can be used by mcu integration for synchronization between etpu time bases and time bases from other modules. if the gtbe bit in etpu_mcr must enable only the etpu time bases, etpu_gtbe_out is simply connected to etpu_gtbe_in. these two cases are shown in figure 542 . synchronization logic can be as simple as an or or an and logic gate. once etpu_gtbe_in transitions to 1, the engine 1 time bases start one system clock earlier than time bases in engine 2, except when t crclk is selected as clock source or tcr1 when etpu_tbcr[tcr1cs] = 1. this happens independently of prescaler values as long as they are the same for both engines, because the prescalers also freeze when etpu_gtbe_in = 0. microcode can always write to tcr1/2 registers, with either value of etpu_gtbe_in. note: the timebase prescalers are reset when the gtbe input is negated. 01, 10 or 11 11 (server) tcr2/angle tcr2/angle 01, 10 or 11 10 (client) forbidden (1) 1. stac client configuration in angle mode is also forbidden for tcr1. table 488. stac bus and host read sources am (etpu_tbcr) ren2,rsc2 (etpu_redcr) tcr2 bus source (host read of etpu_tb2r) stac bus driver RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 919/1740 figure 542. time base synchronization tcrclk digital filter the tcrclk signal has an improved integrating digital filter with a 2-bit up-down counter. the counter counts up to 3 when a high signal level is detected, or down to 0 when a low level is detected. the signal state is updated to one when the counter stops at 3, or zero when the counter stops at 0. the field tcrcf in register etpu_tbcr (see section , etpu_tbcr ? etpu time base configuration register ) determines whether the tcrclk signal input (after a synchronizer) is filtered with the same filter clock as the channel input signals (see section , enhanced digital filter ? edf ) or uses the system clock divided by 2, and also whether the tcrclk digital filter works in integrator mode or the same two sample mode as the channel filters (see table 444 ). the tcrclk filter delay and prescaling determines the minimum detectable tcrclk pulse widths and, therefore, its maximum frequency, as shown in section , filter clock prescaler , and table 487 . the tcrclk signal delay from the module input to tcr1/tcr2 incrementing or detection in the eac logic is explained in section , input/output signal delays . 24.5.7 eac ? etpu angle counter general the eac logic contains a mechanism which follows the flywheel angle, based on the tooth rate. this hardware works in combination with the tcrclk signal, the tcr2 counter and channel 0, 1 or 2 (depending on the etpu_tbcr field am) to generate angle information on the tcr2 bus which is passed to all the local engine channels. the eac helps to implement a digital angle pll (see table 546 ), which combines hardware with microcode processing at channel 0, 1 or 2. the angle measurement is based on history knowledge of etpu system etpu_gtbe_out etpu_gtbe_in etpu_mcr[gtbe] etpu system etpu_gtbe_out etpu_gtbe_in module x gtbe_out gtbe_in synchronization logic synchronization between etpu time bases only synchronization between etpu time bases and other module time bases etpu_mcr[gtbe] enhanced time processing unit (etpu2) RM0029 920/1740 doc id 15177 rev 8 the tooth period, for predicting the period of the next tooth. the tooth period is partitioned into a programmable number of angle ticks . the etpu application will use the divider in the mac/divide unit to calculate an integer and a fraction part of the angle tick such that the full tooth period gets the correct programmed number of angle ticks with no accumulated error. each single tooth can be divided in angle ticks, up to 1024. in a 60-tooth flywheel, 128 angle ticks per tooth provide resolution of ~0.05 degrees per tick, which meets the accuracy requirement of 0.1 degrees in current automotive applications. the measurement of one tooth in angle ticks is independent on engine rpm; it is the tooth period itself (and the corresponding tick period) that is re-calculated for each new tooth, based on the difference between the estimated tooth and the actual detection. for these applications, one of the etpu channels 0, 1 or 2 is dedicated to service the physical tooth detection. channel 0 shares the same filtered input as the tcrclk signal to get the same timing as the eac. the tcrclk edge detection is selected by etpu_tbcr field tcr2ctl for the eac, and by ipaca/b on channel 0, which must be set to detect the same edge(s). when channels 1 or 2 are selected to work with the eac, ipaca/b is used to select the tooth signal edge detection for both the channel and the eac, and the tooth signal that feeds the eac is the same filtered input which feeds the channel. channel 0, 1 or 2 generates the signal transition service request, and can also be used for generation of a window filter on this transition, to qualify tcr2 clocks. for this purpose, the selected channel should be configured with double match window filtering mode (refer to section , channel modes ). depending on the channel mode set for the channel, match a recognition opens the window, and match b recognition may close it or leave it open. see section , angle logic and channel modes , for details. match b also generates a time-out service request. its input signal transition comes from the tooth. the window can be defined by microcode to open at a predefined point inside the tooth period, and stay open for a desired percentage to the tooth period. the window can be measured in angle or time this method improves the noise immunity by allowing transition detection only on an expected period, a feature which was software responsibility in previous tpu versions. the eac supports deceleration, acceleration, last tooth and missing tooth scenarios. the large range of angle ticks per tooth can be used to cover longer tick counts caused by one or more missing teeth, or to provide extra resolution for future application requirements. in case of a missing tooth, the eac can be configured to insert a dummy tooth or to simply measure a longer tooth. figure 547 shows the block diagram of the angle counter system. tcr1 is used as a time base which measures the tooth period and is used for partitioning the period to angle ticks. angle mode registers in angle mode, the registers described below control etpu angle operations. they are accessible only by microengine as source and destination registers in microinstructions. when etpu is not in angle mode (am bit is negated in etpu_tbcr), all angle mode registers can be used as general purpose registers. tpr ? tooth program register tpr provides configuration for the angle counter circuit. in this register, the microcode can properly adjust the tooth count (controlling last tooth, missing teeth, dummy tooth insertion, halt until tooth detection) and the number of angle ticks per tooth (field ticks). note that this register is sampled into a temporary register in the eac logic when the high rate mode RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 921/1740 is detected (see section , high rate mode (acceleration) , and section , tpr buffering ), which means that changes to this register may take effect only for the next tooth. refer to section , count control and high rate logic , and to section , special cases of missing teeth and last tooth , until section , handling false tooth detection , for a detailed explanation about the use of this register. figure 543 provides a detailed description of the tpr. several conflict issues on tpr writes are explained in section , special tpr write cases . figure 543. tpr register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r last miss cnt iph hold tpr 10 tick s w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 field description [9:0] ticks angle ticks number in the current tooth this field defines the number of angle ticks in the current physical tooth. it partitions the tooth period to the required number of angle ticks. the actual number of angle ticks in a tooth is (ticks+1). in high rate mode (see section , high rate mode (acceleration) ), tpr writes are immediately effective only for bits iph and hold. all other fields changes are ?buffered? and become effective when eac leaves high rate mode. see also section , special tpr write cases . bits last, iph and hold must not be asserted all at once. 10 tpr tpr register reserved bit. in angle mode, must always be written 0 by the user, but holds the value written, so that tpr can be used as a general purpose register bit when angle mode is off. 11 hold force eac hold this bit forces the eac to halt its operation in a special eac freeze mode until a new physical tooth (a real one or emulated with iph = 1) is detected . assertion of this bit immediately freezes the eac in the middle of the tooth period. when a new physical tooth is detected, the bit is automatically negated by the eac. the hold bit can be used for synchronizing the eac tooth count, in case that a false physical tooth is detected due to noise. normal operation. force eac to halt until detection of a physical tooth. enhanced time processing unit (etpu2) RM0029 922/1740 doc id 15177 rev 8 tcr2 ? timer counter 2 in angle mode tcr2 counts angle ticks instead of time. 12 iph insert physical tooth this bit generates a dummy physical tooth which has the same effect as a real physical tooth, and resets itself subsequently. if eac is in halt mode, it switches back to normal mode (1) . if eac is in normal mode, it switches to high rate mode. if angle logic is frozen by hold = 1 (see below), it returns to the state it was at the freezing moment. no operation. insert dummy physical tooth. iph reads as 1 in the next microinstruction after it is asserted, negating subsequently. however, it can be set twice in two consecutive microinstructions to generate two teeth and make the eac go from halt to normal to high rate mode. 13-14 misscnt missing tooth counter decremented on each estimated tooth, stops at zero. used for generation of ?dummy tooth? whenever it holds a non-zero value. 00no missing tooth 01one missing tooth 10two missing teeth 11three missing teeth if the tooth is detected or inserted before the missing tooth tick count completes (going high rate mode, see section , high rate mode (acceleration) ), misscnt resets immediately, but missing teeth count continues in high rate mode (see section , tpr buffering ). 15 last last tooth indication asserted by microcode and negated when a tooth is detected or inserted via iph. not last tooth. last tooth - reset tcr2 counter at the end of the tooth tick count (after physical tooth or iph = 1) when misscnt = 0. if the tooth is detected or inserted before the tooth tick count completes (going high rate mode, see section , high rate mode (acceleration) ), last resets immediately, but tcr2 resets only when the tooth count completes and misscnt = 0 1. missing a physical tooth naturally causes eac to get into halt mode. field description RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 923/1740 figure 544. tcr2 in angle mode this 24-bit free-running counter is used to generate an accumulated angle fraction value. it is updated by the angle tick generator (refer to section , angle tick generator , for more details). refer to section , count control and high rate logic , for a detailed explanation about the use of this register in angle mode. tcr2 provides continuous count of the angle in units of angle ticks. the angle tick counter in tcr2 can be reset due to ?last tooth? microcode indication. tcr2 prescaling is disregarded in angle mode: physical tooth detection is done by eac regardless of the value set in tcr2p. trr ? tick rate register the exact period of the angle tick is programmed in the tick rate register by microcode. the period of the angle tick is given in units of tcr1 clocks as system clocks divided by 2*(tcr1p + 1), even if tcr1cs = 1 (see section , etpu_tbcr ? etpu time base configuration register ). refer to section , calculating the angle tick period integer and fraction , for a complete description about the mechanism to calculate the value to be written into this register. figure 545. trr register integer[14:0]?the integer part of tcr1 clocks in one angle tick. this number, decremented by one, works as a down-counter preload value. a value of integer = 0 represents an integer of 32768. a new value written is reloaded into the counter (becoming effective) when a new tick starts or a tooth is detected or inserted via iph. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000 angle tick counter[23:16] w reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r angle tick counter[15:0] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 30 29 26 27 26 25 24 23 22 21 20 19 18 17 16 r00000000 integer[14:7] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r integer[6:0] fraction w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enhanced time processing unit (etpu2) RM0029 924/1740 doc id 15177 rev 8 fraction[8:0]?nine-bit fractional part of tcr1 clocks in one angle tick. the fraction value is accumulated in the eac fraction accumulator, and whenever the result overflows (i.e., the accumulated fraction added up to an integer), the tick prescaler is halted for one tcr1 clock. figure 546. eac ?pll? ?filter? tcr1 clock divided by trr tick counter + - microcode estimated tooth time new trr tick clock tcr1 clock physical tooth (captured tcr1) ticks tooth ticks tcr2 time eac channel capture1:=tcr1 eac channel capture1:=tcr1 eac channel capture1:=tcr1 eac channel capture1:=tcr1 tcr1>estimated tooth time estimated tooth time (end of ticks) estimated tooth time (end of ticks) 00 00 n n n n ticks halt mode high rate mode tcr1>estimated tooth time --> deceleration tcr1 enhanced time processing unit (etpu2) RM0029 926/1740 doc id 15177 rev 8 acceleration and deceleration acceleration and deceleration affect the new tooth period relative to the known period of the last tooth. changes in tooth period may be extreme at very low engine rpm (such as cold start and warm start). the worst case of tooth period changes is caused during missing teeth, since there is more time for changes in angular velocity to be unnoticed by the eac hardware. for example, on cold start (~20 rpm) there may be extreme acceleration: the ratio between a known tooth period before two missing teeth and the new tooth period after the missing teeth can be very high (up to a factor of 75). acceleration and deceleration effects from tooth to tooth are less extreme as the engine climbs to high rpm. in case of deceleration, the estimated tooth period ends before the actual tooth detection arrives. in this case, the eac hardware waits at the end of the current tooth period, when it is said to be in halt mode , until the real tooth indication is received, then continues with normal operation ( normal mode ). see tab le 5 46 . in case of acceleration, the actual tooth period is shorter than the estimated tooth period. as a result, a new physical tooth indication arrives before the end of the estimated tooth period. in this case the eac closes the gap on high rate mode by counting on system clock divided by eight to the end of the tooth, advances to the next tooth, and switches back to normal operation mode. see table 546 . the reason that the eac does not jump directly to the next tooth is the need to provide sequential angle count throughout the whole tooth period, for channels or external stac clients (if tcr2 is a stac server) which compare angle in ?equal? mode. these peripherals must get all the valid angle values in a sequential manner, to avoid missing angle matches. tcr2 advancing from one tooth to another is a continuous count, and can be optionally reset at the end of the tooth. an estimated tooth is generated after the tooth tick counter reaches the ticks programmed value. the eac works continuously and switches automatically between normal, halt and high rate modes. it relies on the microcode to calculate the estimated tooth period on every tooth, and to update the correct angle tick and tooth parameters in the eac control registers. on high rpm, tooth period changes are reduced from tooth to tooth, and the eac may follow the angle with good accuracy for several teeth without microcode intervention. the eac handles missing teeth by insertion of ?dummy? teeth, or by enlarging the expected tooth period. it is a good practice to locate the flywheel missing teeth in non-critical angles, since a missing tooth may increase the angle measurement error (acceleration and deceleration is detected late). angle tick generator the angle tick generator is responsible for generating a programmed number of angle ticks in the tooth period. it generates the ticks in an average rate which ensures completion of the correct number of angle counts in the estimated period of the tooth, since the count of one tooth in angle ticks is independent on engine rpm. the main output of the angle tick generator is the tick clock that feeds tcr2 in angle mode, as well as the internal tooth tick counter (see figure 547 ). the tooth tick counter counts ticks within a tooth, from 0 up to ticks, is controlled by the angle tick generator logic and cannot be accessed by microcode. refer to figure 548 for a generic presentation of the angle tick count and the measurement of a single tooth period. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 927/1740 calculating the angle tick period integer and fraction on each tooth the microcode has to update the exact period of a single angle tick used for counting the internal angle in the tooth. the period of an angle tick or a tooth is measured in units of tcr1 clocks (if tcr1cs = 0) or tcr1 clocks divided by 2 (if tcr1cs = 1). the microcode can use the etpu mac divider unit (see section , mac and divide unit (mdu) ) to divide the tooth period by the number of angle ticks per tooth, which is stored in the ticks field of tpr (refer to section , angle mode registers ). this division yields the integer part of the angle tick period and the remainder. dividing again the remainder shifted left nine positions, by the number of angle ticks per tooth translates the remainder to a 9-bit fraction. the microcode concatenates the 15-bit integer and the 9-bit fraction to a 24-bit value and writes it to trr. the new rate is effective immediately after the next angle tick is generated by the angle tick generator (am) . for high rpm, note that shifting the tooth period value nine positions to the left prior to the first divide operation would calculate, in one operation, the integer and the fraction. for example: on 60-tooth flywheel running at 1000 rpm, tooth period is 1 ms. if tcr1 counts @ 25 mhz, it counts 25,000 times in a tooth, which can be represented by 15 bits. therefore the tooth period can be shifted nine positions to the left prior to divide operation, and be represented with 24 bits. using shift left nine positions and one divide operation would get the result in macl register (in mdu) which holds the integer and nine bits of the fraction: angle_tick_rate {integer[14:0], fraction[8:0]} = (tcr1toothperiod (an) <<9) / ticks trr = angle_tick_rate {integer[14:0], fraction[8:0]} on low rpm the initial tooth period, measured in tcr1 counts, may be too big to be shifted nine positions to the left. for lower rpm (for example 500 rpm) the tooth period cannot be represented by 15 bits, and shifting it nine positions to the left would lose the msb. in this case, two divide operations are required as follows: first divide the tooth period by the number of ticks?the integer is stored in macl and remainder in mach. macl is saved in another register. mach is shifted 9 positions to the left and divided again by ticks. in parallel with the second divide, the register which saved the original macl is shifted left 9 positions. after the divide macl contains the 9 bits fraction and the other register contains the 15-bit integer, shifted left nine times. the logical or of the two registers is written to the trr: angle_tick_rate {integer[14:0]} = (tcr1toothperiod) / ticks remainder[9:0] = tcr1toothperiod) mod ticks angle_tick_rate {fraction[8:0]} = (remainder[9:0] << 9) / ticks trr = angle_tick_rate {integer[14:0], fraction[8:0]} = (integer[14:0] << 9) | fraction[8:0] am.in high-rate mode, the tick keeps being updated at the rate of system clock/8 until it goes back to normal mode, when the new trr value is used. an. the tooth period (tcr1toothperiod) is not, in general, the value of estimated tooth time. it is obtained by microcode by subtracting tcr1 values between two teeth detections. its comparison with the estimated tooth time indicates acceleration (if minor) or deceleration (if greater) to the microcode. enhanced time processing unit (etpu2) RM0029 928/1740 doc id 15177 rev 8 figure 548. angle ticks generation generating the angle ticks the integer part of trr is preloaded to a prescaler, which counts down at input clock rate equals to the tcr1 clock rate (tcr1cs = 0) or tcr1 clock rate divided by 2 (tcr1cs = 1) (see figure 547 ). when the down counter reaches zero, it generates an angle tick pulse to the angle counter logic and a load pulse to the fraction accumulator. it is then preloaded with most updated trr integer part. due to the load pulse, the 9-bit fraction is accumulated in a 9-bit fraction accumulator. if a fraction overflow condition occurs (the 9-bit adder asserts carry out), the accumulator saves the lower 9 bits of the addition result, which is the remaining fractional part. the carry out bit indicates an accumulated integer ?one? which means that the angle tick is early by one input clock. it halts the prescaler operation for one input clock to compensate the accumulated error generated by the integer prescaler. as a result, the average angle tick period takes into account both the integer and the fraction parts. the accuracy depends on the bit count of the fraction. using 9-bit fraction part while the width of the field ticks in register tpr is 10 bits provides accuracy of two lsb on a full scale (ticks = 1023) or one lsb on lower scale (ticks<=511). when the tick prescaler gets high rate mode indication from the angle counter logic, it generates angle ticks at a rate of system clock divided by eight. in this case it does not generate load pulses to the fraction accumulator, ignores its ?hold? input and preloads internally to a fixed period of eight system clocks. when high rate mode is entered, the prescaler is preloaded to a period of eight system clocks before its first angle tick generation, ensuring separation of at least eight system clocks between the last normal mode angle tick and the first high rate mode angle tick. the fraction accumulator resets when the tick count advances to the next tooth, or when trr is written by the microcode. count control and high rate logic the count control and high rate logic controls tcr2 operation in angle mode, using the angle ticks generated by the angle tick generator. count control logic is responsible for advancing, holding and resetting the tcr2 and tooth tick counter in the proper timing, such that the tcr2 time base will reflect the correct estimated angle. this logic also includes the tooth program register (tpr, see section , angle mode registers , for more information). tooth signal angle tick p1 p2 p3 acceptance window from eac channel 2 4 6 9 11 13 16 18 20 23 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 tcr1 clocks eac channel capture tcr2 0 1 2 glitch rejected tcr1 = 1000 tcr1 = 1023 1046 3 6 9 2 5 8 1 4 7 0 3 6 9 2 5 8 1 4 7 0 3 6 0 fraction accumulator (modes m2_o_st/dt) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 tooth tick counter RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 929/1740 the count control and high rate logic handles deceleration, acceleration, missing teeth and last tooth. on high rate (acceleration) it ensures that the angle bus scans all valid angle values in a rate which can be traced by the stac bus. this operation enables external stac clients (if tcr2 is a stac server) or channels working in ?equal-only? comparator mode to match the tcr2 exported angle information in ?equal? mode, in an exact match. because the etpu channels are capable of capturing either tcr1 or tcr2 due to signal transition, the microcode can get either the angle or time of the physical pin transition. since the eac channel (0, 1 or 2) is connected to the physical tooth, the microcode can get the eac error in angle domain (tooth appears at the wrong angle) or time domain (physical tooth captured time into the eac channel, relative to the estimated tooth time). note that in angle mode, the transition detect logic of the channel 0, if selected as the eac channel, is fed from the digital filter of the tcrclk signal, and not from the channel 0 internal digital filter. this ensures synchronous operation of channel 0 and the eac hardware. another feature of the etpu channel, when working in single match and single transition enhanced mode (refer to section , single match enhanced mode (sm_st_e) ), is capturing a single time base due to signal transition before and after the digital filter. this option allows subtracting the digital filter delay to get accurate signal transition timing on the channel. this way, the tcrclk signal may be programmed with a slow and reliable digital filter, and get accurate time measurement of the digital filter delay. to assert the end of the estimated tooth period the count control and high rate logic compares the ticks field in tpr (refer to section , angle mode registers ) with the current value of the tooth tick counter. when the tooth tick value is greater or equal to ticks, it determines the end of the estimated tooth period. on acceleration this event occurs during high rate mode operation, after the arrival of a physical tooth. in deceleration, this event occurs during normal mode, before the arrival of a physical tooth. on constant angular velocity, this event appears together with the arrival of a physical tooth. the following sections describe the operation of the counter control and high rate logic. normal mode in normal mode the counter control logic advances tcr2 and the tooth tick counter as if the engine has a constant speed during the tooth period. it receives the angle ticks from the angle tick generator in an average rate which is determined by the tooth rate register (trr). this is the reset mode. when the tooth tick counter is about to reach the last value effectively stored in tpr field ticks plus one, the hardware detects the end of the estimated tooth period. if the physical tooth and the estimated tooth arrive at the same time the eac stays in normal mode, the tooth tick counter is reset, and tcr2 is incremented (depending on tpr bits last and misscnt). if the physical tooth and the estimated tooth do not arrive at the same time, either acceleration or deceleration is detected, and the eac switches to the proper mode. see figure 549 for a detailed diagram of normal mode behavior. the microcode which services the eac channel physical tooth transition may update trr according to various conditions to give the best estimation of the current tooth period, according to the previous tooth period and other engine parameters. enhanced time processing unit (etpu2) RM0029 930/1740 doc id 15177 rev 8 figure 549. normal mode halt mode (deceleration) in case of deceleration, the tooth tick counter reaches the ticks value before the arrival of the next tooth. the count control logic does not reset neither advances tcr2 and tooth tick counters. the count control logic halts tcr2 and tooth tick counters at the end of the tooth, waiting for the physical tooth to arrive. when the physical tooth is detected the eac switches back to normal mode and releases tcr2 to count the angle ticks of the new tooth, also resetting the tooth tick counter. only then tcr2 may wrap to 0, if tpr bit last is asserted. see figure 550 for a detailed diagram of halt mode behavior. the microcode service caused by the physical tooth determines the deceleration, calculates the new tooth period and angle tick period and updates trr. this operation slows the angle tick rate generated by the angle tick generator on-the-fly, to the rate required for the new tooth period. since the microcode service is initiated by the physical tooth edge, microcode latency may introduce a small angle error caused by using the trr value of the previous tooth at the beginning of the current tooth. on high rpm, deceleration is relatively small but the microcode latency may take a significant percentage of the tooth period. on low rpm microcode service latency takes little percentage of the tooth period, but there may be cases of extreme acceleration and deceleration. the microcode latency can be calculated knowing tcr1 value during the service time, and tcr1 value captured in the eac channel due to the physical tooth pin transition. the duration of the halt mode is obtained using the estimated tooth time. tooth signal angle tick trr p1 p2 p3 p4 tooth tick count eac channel service time slot eac channel capture tcr1 tcr1 tcr1 tcr1 p1/ n p2/ n p3/ n y y+n y+n+1 ch0 ch0 ch0 *service request **microcode updates trr * * ** ** tcr2 - continuous 0 0 0 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 931/1740 figure 550. halt mode ? deceleration high rate mode (acceleration) in case of acceleration, the next tooth arrives before the tooth tick counter reaches the ticks value. in this case the high rate logic is responsible for closing the gap and advancing the tooth on the correct timing. the high rate mode operates as follows: when the acceleration is detected (physical tooth arrives before the tooth tick counter reaches the ticks value), the count control and high rate logic switches to high rate mode in which both the tooth tick counter and tcr2 count at rate of system clock divided by eight, until the tooth tick counter reaches the current ticks value. to ensure correct operation, the ticks value is sampled in the logic at the beginning of the mode. at this point, which represents the estimated tooth edge, the logic resets the tooth tick counter and advances tcr2 (or resets it if last is asserted and misscnt = 0). the control logic switches back to normal mode, using the most updated trr value as input to the angle tick generator. the logic samples the updated ticks value for the tooth estimation, last tooth indication and number of missing teeth from tpr. in high rate mode the angle ticks are provided at high speed until the end of the current tooth. this operation is required to scan all the valid angle values of the current tooth, in a rate which is not too high for the stac bus continuous update, but much higher than the rate dictated by trr. eac channel microcode, which services the physical tooth transition detection, can start its service either before high rate mode operation is complete (the tooth tick counter has not reached the ticks value) or after the eac switched back to normal mode. any physical teeth received while the eac is in high rate mode does not alter the immediate eac state, but it is still detected by the eac channel logic and can, therefore, alter future eac behavior (for instance, closing the tooth detection window (see section , angle logic and channel modes ). at the beginning of high rate mode operation, the tpr value is preloaded into a temporary register in the counter control logic, used for scanning all the valid values to the end of the tooth signal angle tick trr p1 p2 p3 p4 eac channel service time slot eac channel capture tcr1 tcr1 tcr1 tcr1 p1/ n ch0 y y+n y+n+1 ch0 ch0 p2/ n halt mode *service request **microcode updates trr ** ** ** tcr2 - continuous tooth tick counter 0 0 0 enhanced time processing unit (etpu2) RM0029 932/1740 doc id 15177 rev 8 current tooth, with its appropriate last and misscnt attributes. while the eac is in high rate mode operation, the effect of microcode update of tpr fields last, misscnt and ticks is delayed to the next estimated tooth, after the high rate mode operation is complete (ao) (see section , special tpr write cases ). this is because the current physical tooth represents the next estimated tooth. if the microcode updates this field after high rate mode operation is complete, the current physical tooth and estimated tooth are the same, and the effect is immediate. either in high-rate mode or not, the value read by microengine is the same written, even if not yet effective, until the eac resets last and/or iph, or decrements misscnt. typically the microcode service may occur during the high rate mode on extreme acceleration situation at low rpm. therefore, the microcode operations are always related to the real physical tooth. from the above it can be seen that the microcode updates of the ticks field in tpr affect the end time of the current physical tooth. for correct operation, this field should be updated before the tooth tick counter has reached either the old or the new ticks value. during high rate mode operation, trr is ignored and the angle tick generator uses system clock divided by eight. therefore, the trr update by microcode will take effect only after the eac switches back to normal mode. if microcode service occurs after the tooth tick counter has been reset, the eac is already back in normal mode, and some angle ticks may have been counted at the rate of the previous tooth. in this case the new trr value will have immediate effect on the angle tick period, and the microcode should take into consideration the delay from the physical tooth to the estimated tooth in calculation of the next tooth period. see figure 551 for a detailed diagram of high rate mode behavior. an angle error may be introduced by the duration of the high rate mode. also, the scheduler latency may introduce a small accumulated error by using trr value of the previous estimated tooth at the beginning of the current tooth. after the estimated tooth has advanced, the duration of the high rate mode operation is the actual delay from the physical tooth edge to the estimated tooth edge. this delay can be obtained by comparing the estimated tooth time with the eac channel capture register which captured tcr1 on the physical pin transition. ao. the effect of microcode writes to fields hold and iph is immediate in high rate mode. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 933/1740 figure 551. high rate mode ? acceleration special cases of missing teeth and last tooth the eac handles cases of up to three missing teeth and the last tooth in the engine cycle. the following paragraphs describe these functions. handling the last tooth the microcode can set the tcr2 counter to work in engine periods (wrap-around count) or continuous angle measurement. for periodic operation, during the last engine cycle tooth the eac microcode has to set the last flag in tpr. as a result, when the tooth period is ended, the counter control logic generates a reset command to both the tooth tick counter and tcr2 instead of an advance command. the operation resets the tcr2 based angle count, indicating a new period of the engine cycle. this implementation provides an engine cycle based periodic angle measurement. handling missing teeth the eac can handle up to three missing teeth in two ways: count the angle ticks relative to the last physical tooth. the microcode should update the tpr ticks field to the number of angle ticks included in two, three or four teeth, according to the flywheel type (one, two or three missing teeth). eac hardware works in its regular manner. insert a ?dummy? tooth instead of the missing tooth, at the estimated point in time. after the ?dummy? tooth, the angle tick counter is incremented as if there was a physical tooth. a ?dummy? tooth can be inserted only during normal or high rate operation modes. the microcode inserts ?dummy? teeth by writing to the misscnt field in tpr. in the first option the missing tooth is not counted on the angle measurement. for example, a flywheel with 59 physical teeth and one missing tooth can be considered as 58 identical teeth numbered (0-57) and tooth number 58 has a double number of angle ticks. in this tooth signal angle tick trr p1 p2 p3 p4 eac channel service time slot eac channel capture p1/ n p2/ n p3/ n y y+n+1 ch0 ch0 ch0 high rate mode tcr1 tcr1 tcr1 tcr1 *service request **microcode updates trr * * ** ** tcr2 tooth tick counter enhanced time processing unit (etpu2) RM0029 934/1740 doc id 15177 rev 8 case a 720 degrees engine cycle has 118 teeth. tcr2 reflects the real angle, since it counts angle ticks continuously. in the second option, the missing teeth are counted as ?regular? teeth by automatic insertion of ?dummy? teeth. the microcode has to write a non-zero value to the misscnt field in tpr. this field is a 2-bit down counter which affects the operation of the counter control logic. for example, a flywheel with 59 physical teeth (0-58) and one missing tooth (59) can be considered as 60 teeth numbered (0-59), all having the same number of angle ticks. the microcode has to write ?01? to the misscnt bits during the period of tooth number 58 to indicate that next tooth (59) is missing. when the tooth tick counter reaches the ticks value, tcr2 is incremented as if a physical tooth has been detected. in addition, the misscnt value initializes a ?dummy tooth counter? which is decremented to indicate the number of left ?dummy teeth? which still need to be generated. because a dummy tooth was counted, eac does not enter halt mode and tooth tick counter continues incrementing in the absence of a physical tooth detection. in case of extreme acceleration on very low rpm (cold start) there can be a situation that the first physical tooth after one or two missing teeth appears even before the ?dummy? tooth is generated. due to the acceleration the eac switches to high rate mode in order to run through all the valid angle values, including the dummy teeth. when the tooth tick counter reaches the ticks value on high rate mode, and the ?dummy tooth? down counter is not zero, the generated ?dummy tooth? advances to the next tooth and decrements the ?dummy tooth? counter, but does not switch the eac back to normal mode. the last ?dummy tooth? decrements the counter to zero, indicating that no more dummy teeth are to be inserted, and the next tooth is an estimated physical tooth. the eac continues at high rate mode until the tooth tick counter reaches the ticks value again, then advances to the next tooth while switching back to normal mode. when in high rate mode, the tpr does not reflect the misscnt downcounting; see section , tpr buffering , for details. misscnt can be rewritten before it reaches 0, allowing it to count more than three missing teeth, as long as no physical tooth arrives between the first misscnt write and the rewrite. combining missing teeth and last tooth the last tooth indication takes effect when there are no more missing teeth to be generated, i.e the ?dummy tooth? counter value is zero. if, for example, the microcode sets the missing teeth counter to ?10? (two missing teeth) and sets the last flag, the first and the second dummy teeth will increment tcr2, and the third estimated tooth, which correlates with the physical tooth (the first of the next cycle), will reset tcr2, because last was set. this scheme enables the microcode to define one or more missing teeth to be replaced by ?dummy tooth? insertion, and the end of the engine cycle in one service request. it is assumed that the two missing teeth must come together in the same engine cycle, and not split between two engine cycles (either the missing teeth are both last in an engine cycle or both not last, but not last in one engine cycle and first in the next). RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 935/1740 figure 552. missing teeth and last tooth combination handling mechanical tooth correction the eac can handle tooth edge detection errors caused by flywheel mechanical errors. the etpu application can hold a vector of tooth mechanical errors with one entry per tooth. this error can be measured in angle ticks which are independent of engine rpm. the trr can be updated to the fixed period of any tooth, including its mechanical error. because tcr2 counts continuously, without being reset, the mechanical correction is transparent. though the tooth has its own programmed ticks value, tcr2 simply counts angle ticks, disregarding the boundary between two adjacent teeth. handling mis-detected tooth when a physical tooth signal is missed by the engine sensor, the eac may get into halt mode at the end of the estimated tooth period, expecting the physical arrival. in this case, a match timeout event of eac channel will call service which detects extreme deceleration. the microcode can assert the iph bit in tpr, to force the detection of the missed physical tooth. it can also calculate the accumulated angle bus error, and fix the next estimated tooth period, to close the gap. handling false tooth detection most of the false tooth detection, caused by noises on the engine tooth sensor, can be eliminated by the window blanking filtering, timed by eac channel match recognitions. the eac also provides means of fixing false detection of an additional tooth which passed the window filter. when such an event occurs, the eac switched to high rate mode (advancing to the next tooth) and when the next physical tooth arrives, an extreme acceleration is detected: the eac sees the remaining portion of the current tooth period as another tooth period. the microcode can detect the situation when the acceleration in not realistic, or when immediately after the detection of this extreme acceleration, the following tooth indicates extreme deceleration back to the original rpm. when the microcode detects such a case, the tooth counter has been advanced by mistake to the next tooth. the microcode can set the hold bit in the tpr, forcing the eac tooth signal angle tick tcr2 p1 p2 p3 p4 tooth tick counter eac channel service time slot tooth count ch0 tpr[misscnt] ?dummy teeth? tpr[last] 00 10 01 00 56 57 58 59 0 dummy teeth **microcode sets tpr *service request ** 0 n*(ticks+1) (for reference only) enhanced time processing unit (etpu2) RM0029 936/1740 doc id 15177 rev 8 to freeze and wait for the next physical tooth to close the gap. when the next physical tooth arrives, hold is automatically negated and the eac proceeds from that point to the remaining portion of the tooth period, in the same mode it was when hold bit was asserted. angle logic and channel modes the tcrclk transition detection is qualified by a signal that comes from channel 0 (see figure 547 ) and depends on the particular mode (pdcm) programmed for that channel. this configures a window for tcrclk detection for the angle logic which is the same (except on high rate mode, see section , high rate mode (acceleration) ) used to set the tdla flag on single transition modes, and tdlb on double transition modes (see signals tse1,tse2 in figure 530 ). the same applies when channels 1 or 2 are used to control eac (see signals ts1, ts2 in figure 530 ). as a consequence, the window depends on the channel mode as follows: on all modes, the window closes upon a tooth edge detection: tdla asserted on single transition modes, tdlb asserted on double transition modes. on mode m2_st: the window opens on match a (which enables transition a) and does not close with match b. if match b comes before match a, it blocks match a and, hence, transition a. on mode m2_o_st: the window opens on match a (which enables transition a) and closes on match b. match b is enabled by match a, so it cannot come before. on all other single transition modes, the window is ?always open?, independently of matches. on mode m2_dt: the window opens on transition a, which is enabled by match a. the window does not close with match b, but if it comes before match a the later gets blocked and, hence, blocks transitions. match a is also a condition for the window, so the microcode closes it by clearing mrla. on mode m2_o_dt: the window opens on transition a, which is enabled by match a. the window closes on match b, which is enabled by match a. match a is also a condition for the window, so the microcode closes it by clearing mrla. on all other double transition modes, the window opens on transition a. restarting angle logic it is not advisable to toggle the etpu_tbcr bit am while gtbe = 1. however, if the angle logic must be restarted without interfering with the timebase count running on tcr1, the procedure below must be followed: 1. write etpu_tbcr setting am = 00 and tcr2ctl = 111 at once. that prevents tcr2 from incrementing while the angle logic is disabled. the angle logic state-machine resets to normal mode and the tick prescaler to the initial count by am = 00, but not the microengine registers tpr and trr. 2. start a thread to reconfigure the eac. the thread must set the eac controlling channel (0, 1 or 2) flags in a state, depending on the channel mode, that lets the channel tooth detection window open (see section , angle logic and channel modes ). it can optionally write tcr2 with an angle preset value equivalent to the first tooth expected after restart. the thread must also set tpr bit hold = 1. the tpr bit iph must be 0. 3. after the thread is finished, write etpu_tbcr setting am = 01, 10 or 11, and tcr2ctl according to the desired tooth edge selection if am = 01. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 937/1740 the first tooth detected after this procedure restarts the tcr2 counting, unfreezing the angle mode logic into normal mode. special tpr write cases this section describes how simultaneous modification of tpr fields are resolved, and how the effect of tpr writes depend on the eac mode. tpr buffering in high rate mode (see section , high rate mode (acceleration) ), tpr writes are immediately effective only for bits iph and hold. writes to all other fields are ?buffered? and become effective when eac leaves high rate mode. however, if tpr is written a second time right after iph is asserted in normal mode, this second write behaves as if eac is still in normal mode. only in the next microcycle (after execution of a nop, for instance) the tpr writes are buffered, acknowledging high rate mode. misscnt and last can be written any value during high rate mode, and the value that prevails for the next tooth is the one sampled when eac goes back to normal mode (or the value written in normal or halt mode thereafter). if misscnt and/or last are not zero when high rate mode begins, they are sampled into the internal eac logic and are effective while high rate lasts (missing teeth count continues and tcr2 is reset at the end of high rate if last = 1). however, their values in tpr are reset when high rate mode starts. after that and until the end of high rate mode, the value read by microcode is the same written. this behavior prevents read-modify-writes to tpr from unwillingly rewriting last or misscnt. iph and last if both iph and last are asserted in the same microinstruction, the eac acts as if last was set first and then iph right after, so that: in normal mode, it goes to high rate with last = 1; in halt mode, it goes to normal mode resetting last (and tcr2); in high rate mode, iph is ignored and last becomes effective in the next tooth (physical or inserted) after it goes back to normal mode. iph and ticks because of different results depending on the eac mode at the time of tpr write, it is not advisable to write 1 to iph and change ticks at the same microinstruction. a consistent behavior is obtained if iph is written fist and ticks on the second microinstruction after (for instance with a nop between them), making the new ticks value valid for the next tooth regardless of the mode. the mode-dependent behavior is: in normal mode, the new ticks value becomes valid before eac goes high rate due to the iph; in halt mode, the eac goes to normal mode, and new ticks is valid for the next tooth; in high rate mode, the new ticks value is effective when eac leaves high rate mode, and iph is ignored; enhanced time processing unit (etpu2) RM0029 938/1740 doc id 15177 rev 8 iph and misscnt if both iph and misscnt are written non-zero values: in normal mode, at the next microcycle the eac goes to high rate mode, the misscnt field in tpr goes to 0, and the missing teeth are counted in high rate mode. in halt mode, the eac goes to normal mode for one microcycle and then, yet another microcycle later, goes to high rate mode, counting the missing teeth. the tpr fields iph and misscnt are zeroed on the transition from normal to high rate mode. in high rate mode, iph is ignored (resetting at the next microcycle) and misscnt is buffered (see section , tpr buffering ). iph and hold if iph and hold are asserted at once, iph cancels the hold and both reset. the eac is not frozen, regardless of the mode. last and hold if last and hold are written 1 at once, last asserts and eac is frozen. when a physical tooth is detected or iph is asserted, the eac is unfrozen in the same state it was before, and last is kept asserted. 24.5.8 microengine each etpu engine has a microengine that fetches, decodes and executes microinstructions. the microengine only works when there are service requests to be attended, otherwise it turns to idle state, controlled by hardware scheduler (see section 24.5.3, scheduler ). microcode is stored in shared code memory (scm) that is 32-bit wide. microengine can access spram using a different bus from the one used to accesses code memory, so that code and data can be accessed at the same time (harvard architecture). some of etpu functionality can only be made through the microengine, like configuring channels and interrupting host. microengine gives etpu a high degree of flexibility, since any desired treatment for channel?s events can be implemented; however, that flexibility comes at the cost of channel service?s latency. latency is worsened when channels from a same etpu engine contend for microengine service. in figure 553 a block diagram of microengine architecture is shown. microengine features are summarized as follows: p, diob, a, b, c, d, sr, rar, link, chan, macl, mach, erta, ertb, tcr1, tcr2, tpr, trr registers are accessible by microcode. 24-bit alu and post-alu shifter performs basic arithmetic and logical operations described in section , alu and post-alu shifter . mdu (mac/divide unit) performs integer mac, multiply and divide operations. fixed microinstruction size of 32 bits. fixed-length instruction execution (2 system clocks) static superscalar operation RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 939/1740 figure 553. microengine block diagram diob p a bin alu post-alu control code memory bus spram d.bus 32 32 imm.data chan* 8 24 sr c ad (dest.) bs (source) erta ertb flags to to branch logic 4 24 24 24 24 24 24 etpu channels er1 bus er2 bus 24 spram a.bus 24 24 24 32 24 1 mach macl mac 24 24 24 divide unit 24 ain n, v, z, c mb flags to to branch logic mn, mv, mz, mc 5 rar* channels + tcrs microengine?s datapath shifter eau shifter result result address & size calc. chan 8, 16 or 24 24 as (source) 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 link* tcr1 tcr2 6 tdlb, psti, psto to branch logic mrla, mrlb, tdla, 24 24 1 5 5 5 1 1 1 b 24 24 fetch and scm address 14 branch logic pc 1 rar d 24 24 enhanced time processing unit (etpu2) RM0029 940/1740 doc id 15177 rev 8 registers etpu microengine accesses a total of 18 registers. fourteen of them are special purpose (registers a, b, c and d are for general use). special purpose registers except chan and link can also be used as general use if the operation that use their contents are not performed. register description is intended to just introduce their functionalities and not to provide detailed explanation of it since it will be described in section 24.5.9, microinstruction set . registers less than 24 bits in size are right-justified. none of the registers have guaranteed reset values. however, some are initialized just before the thread starts (see section , time slot transition ). p register p register is the only one that is 32-bit wide. it can be used as source and destination for arithmetic/logical operation, and as source and destination for spram read/write operations. for p source/destination possibilities in alu/mdu microoperations, see section , selecting sources and destination . when p is used as spram read/write operations source or destination there are only 3 possibilities of access: all 32 bits, lower 24 bits and upper 8 bits. spram operations are explained in detail in section , spram microoperations . p is automatically loaded with one parameter before the thread starts (parameter preload). for more information see section , entry point format , and section , time slot transition . upper 8 bits of p register can be used as application state, since these bits can be tested as branch conditions. p[31:24] is also used in dispatch microoperation (see section , dispatch microoperation ), and bit pairs p[29:28], p[27:26], p[25:24] can be directly copied into channel flags 1 and 0 using field flc. together with entry table condition encoding, it provides fast state resolution without code execution. diob ? data input/output buffer register the diob register is 24-bit wide and can be used as source and destination for arithmetic/logical operations as well as spram data source and destination. the diob only can be accessed as 24 bits, both in arithmetic/logical and spram read/write operations. when using the diob to perform an spram access, only the lower 24 bits of spram will be accessible (spram upper 8 bits always remain unchanged). the diob can also be used as spram addressing register, when the diob contents are used as absolute spram address (14-bit wide). in this case the diob can also be pre- decremented or post-incremented (see section , indirect addressing mode ). the diob is automatically loaded with one parameter before the thread starts (parameter preload). for more information see section , entry point format , and section , time slot transition . erta and ertb registers erta/b registers are 24-bit wide and can be used as source or destination in arithmetic/logical operations. erta/b are the only source for channel?s match registers write (see section , write channel match and udcm registers ). erta can also be the source for udcm write. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 941/1740 when a thread starts to be executed, erta and ertb are loaded with a copy of capturea and captureb registers respectively. erta/b can be used to receive a copy of matcha and matchb registers. erta/b are the only destination of matcha/b read operation (see section , special t4abs source operation: read match registers ). erta and ertb also receive a copy of capturea and captureb registers when chan register is written (see section , chan register ). for more information about capture and match registers see section , matcha and matchb registers , and section , capturea and captureb registers . sr ? shift register the sr is a 24-bit wide register that can be used as source and destination register for arithmetic/logical operations. the sr can shift right its contents by 1 bit at time and, at the same time, receive in its bit 23 the lost bit of a shift-right operation in post-alu shifter ( section , alu and post-alu shifter ), allowing the sr to be used to perform 48-bit shift right (see section , shift operations ). mach and macl registers both mach and macl are 24-bit registers, part of mac/divide unit (see section , mac and divide unit (mdu) ). they can be used as source and destination in most arithmetic/logic operations. when multiply or divide operations are used (multiply-accumulate included), mach and macl have special purpose and some restrictions apply, see section , mac and divide unit (mdu) , for more information. link register link register is an 8-bit wide register and can be used only as destination in arithmetic operations. link is a write-only command register, which precludes its use as a source register for alu operations. when link register is written, it issues a service request for the channel number and etpu engine equal to the number written in link register (see section 24.5.1, functions and threads , and section , channel link , for information about link service request). rar ? report address register the rar is a 14-bit register and can be used as source and destination in arithmetic operations. the rar also receives the contents of pc register when a subroutine call is executed. the contents of the rar are loaded into pc when a return from subroutine is executed. the rar is loaded with value 0x3fff during tst. for more information about subroutine call and return see section , branch operations , and section , return from subroutine , respectively. chan register chan is a 5-bit register that can be used as source and destination in arithmetic operations. the contents of chan register affects the execution of many channel-related microinstructions, because its number indicates the selected channel . chan register must not be used to store temporary values in arithmetic operations. for more details, refer to section , channel selection register ? chan . counter registers: tcr1, tcr2, tpr and trr all these registers are 24-bit wide except tpr, which is a 16-bit register. they can be read or written in arithmetic/logical operations, and have special-purpose uses for time base and enhanced time processing unit (etpu2) RM0029 942/1740 doc id 15177 rev 8 angle mode operations. for more information about those registers see section 24.5.6, time bases , and section 24.5.7, eac ? etpu angle counter . general purpose registers: a, b, c and d a, b, c and d are 24-bit general purpose registers, which can be used to store intermediate values and do not have other specific uses with any etpu feature. alu and post-alu shifter the alu executes 24-bit arithmetic and logical operations. alu?s output goes directly to a 1-bit shifter, called post-alu shifter, so it is possible, for example, to add and shift using only one microinstruction. in some microinstruction formats, it is not possible to specify the operation executed by alu. in these cases alu will always perform addition. in formats which have the field aluop for alu operation selection, all of them can be performed, including add/subtract using c (carry) flag as alu?s carry-in, bitwise and/or/not/xor, and shift/rotate of 2, 4, 8 and 16 bits. see section , alu/mdu operation selection . subtraction, inversion, increment and decrement can be performed by combinations of source inversion and setting alu?s carry-in to 1. alu always performs 24-bit operations on its inputs, called a-source and b-source , and outputs a 24-bit result. 8-, and 16-bit inputs are zero padded to 24 bits. likewise, alu 24-bit output is always truncated to the destination register size. alu flags four flags?carry, negative, overflow, zero?described below, are related to alu and post- alu shift operations. operation size and shifting affect flags generation logic. operation size determines the result boundary to be used for flags generation. operation size is determined by size of sources and destination (see section , flags sampling control ). for more information about flag generation, see section , flags sampling control . alu flags can be used as branch condition (see section , conditional/unconditional branch ) or conditional alu/mdu operation (see section , conditional alu/mdu operation execution ). field ccs/ccsv in microinstructions can force no update of all flags. not all flags are updated in all alu operations: overflow is updated only on addition and absolute value operations, carry flag is updated in most alu operations, and only zero and negative are updated in all alu operations. alu flags are never updated when microinstruction starts an mdu operation, regardless of ccs/ccsv, but are updated normally afterwards, on alu operations that are executed in parallel with an ongoing mdu operation (mdu has its own flags). note: operation size can be smaller than destination register. for example: 0xffff + 0x0001 (both 16-bit sources) stores 0x10000 in a 24-bit register and sets zero and carry flags because operation size is 16 bits. carry flag (c) in an unsigned addition without shifting, carry flag is the alu carry from bit 7 to 8, 15 to 16, or 23 to 24 on 8, 16 and 24-bit operation sizes respectively. in an unsigned subtraction without shifting, carry flag represent the sign of alu?s result considering operation size (carry flag equal to 0 means a negative result). RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 943/1740 carry flag definition is operation-dependent. the carry flag in add/subtraction with post- alu shift is defined in table 493 . find the definitions for other operations in the following sections. negative flag (n) negative flag indicates the sign of result based on the operation size, regardless of the operation performed, as shown in table 489 . note: the n flag may not reflect the sign of the value actually written into the destination register, if it does not have the same size of the operation (see section , flags sampling control ). this is always the case for registers rar (14 bits) and chan (5 bits). overflow (v) overflow is updated only on addition (with or without carry) and absolute value operations. in signed operations, overflow flag indicates that the result of arithmetic operation (add or subtraction) can not be represented by a word of the size of the operation. overflow flag behavior for addition is defined in table 490 . overflow flag for absolute operation is explained in section , absolute value operation . v flag is calculated using alu adder output (that is, it is not affected by 1-bit shift/rotate operations). zero flag (z) zero flag equal to 1 indicates that the result from the alu, limited to the operation size, is zero, regardless of the operation performed, whether the result is written, or where it is written. it depends on the operation size, as shown in table 491 . table 489. negative (n) flag behavior operation size value 8 bits n = result[7] 16 bits n = result[15] 24 bits n = result[23] table 490. overflow flag on addition (1) ? v 1. for v-flag definition on the absolute operation, see section , absolute value operation . operation size value (2) 2. bs is taken after any inversi on by the binv field, but not added to the carry bit (cin field) 8 bits (as[7] & bs[7] & !alu_adder_output[7]) | (!as[7] & !bs[7] & alu_adder_output[7]) 16 bits (as[15] & bs[15] &!alu_adder_output[15]) | (!as[15] & !bs[15] & alu_adder_output[15]) 24 bits (as[23] & bs[23] &!alu_adder_output[23]) | (!as[23] & !bs[23] & alu_adder_output[23]) table 491. zero flag ? z operation size value 8 bits z = (result[7:0] == 0x00) enhanced time processing unit (etpu2) RM0029 944/1740 doc id 15177 rev 8 alu add operation with and without shifting add operation is selected by aluop or aluopi fields and when none of them is available in a microinstruction format (ap) . optionally, result can be shifted or rotated right by 1 bit, which is selected by shf, aluop or aluopi fields. see section 24.5.9, microinstruction set , for more details. table 492 describes how cin and binv fields change add operation behavior. alu adder output can be 1-bit shifted or 1-bit rotated right as follows: shift right: if binv==1 result[23:0] = adder_output[24:1] else result[23:0] = adder_output[24:1] xor 0x800000 endif shift left: result[23:1] = adder_output[22:0] result[0] = 0 rotate right: case(opsize/ccsv) 8-bit: result[6:0] = adder_output[7:1] result[7] = adder_output[0] result[23:8] = adder_output[23:8] 16-bit: result[14:0] = adder_output[15:1] result[15] = adder_output[0] result[23:16] = adder_output[23:16] 24-bit: result[22:0] = adder_output[23:1] result[23] = adder_output[0] 16 bits z = (result[15:0] == 0x0000) 24 bits z = (result[23:0] == 0x000000) ap. alu operations only occur on formats where a destination field is found (t2abd/t2d). table 492. types of add operations binv cin operation (adder output) 1 1 as + bs 1 0 as + bs + 1 0 0 as - bs 0 1 as - bs - 1 table 491. zero flag ? z operation size value RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 945/1740 note: only for the post-alu rotate right, the operation size is determined by the field ccsv (see section , flags sampling control ). for example: if ccsv = 00, t4abs = p (24-bits), t4bbs = a (24 bits), t2abd = b (24 bits), and aluop = ?add ror?, then b gets a+ p with bits 7:0 rotated, even though the operation size is 24 bits. ta ble 49 3 describes carry flag behavior. flags n and z on shift are updated according to the result after shift. flag v with shift is updated according to the add operation only, the same way as without shift. adc operation adc operation is selected by the aluop field. cin field is ignored when this operation is selected. table 494 describes how binv change adc operation behavior. table 493. carry flag update on add operation binv (1) operation size shift/rotate value 1 8 bits none adder carry from bit 7 to bit 8 1 16 bits none adder carry from bit 15 to bit 16 1 24 bits none alu_adder_output[24] 0 8 bits none !adder carry from bit 7 to bit 8 0 16 bits none !adder carry from bit 15 to bit 16 0 24 bits none !alu_adder_output[24] 0 or 1 8 bits shift left alu_adder_output[7] 0 or 1 16 bits shift left alu_adder_output[15] 0 or 1 24 bits shift left alu_adder_output[23] 0 or 1 x shift right alu_adder_output[0] 1 8 bits rotate right adder carry from bit 7 to bit 8 1 16 bits rotate right adder carry from bit 15 to bit 16 1 24 bits rotate right alu_adder_output[24] 0 8 bits rotate right !adder carry from bit 7 to bit 8 0 16 bits rotate right !adder carry from bit 15 to bit 16 0 24 bits rotate right !alu_adder_output[24] except on max-constant generation (see section , max constant generation with t4bbs = 111 ) 1. binv has no effect on carry-out when used to code max constant (see section , max constant generation with t4bbs = 111 ). table 494. types of adc operations binv cin operation 1 x as + bs + c flag 0 x as - bs - c flag enhanced time processing unit (etpu2) RM0029 946/1740 doc id 15177 rev 8 flags behave exactly the same way as for add operation without shift/rotate. bitwise operations bitwise and, or and xor are selected by aluop field. on these operations cin field is ignored and binv field inverts (bitwise not) bs. c and v flags are never updated on these operations. table 495 describes and, or and xor bitwise operations. set bit / clear bit operations these operations set or clear the as bit determined by bs[4:0]. if the bit number resolves to a value greater than 23, no bit is set or cleared (i.e., result is equal to as). on these operations cin field is ignored and binv field inverts (bitwise not) bs. c and v flags are never updated for set/clear bit operations. these operations override b-source size to 8 bits. set bit (binv = 1): result = as | (1 << bs[4:0]) clear bit (binv = 1): result = as & ~(1 << bs[4:0]) set bit (binv = 0): result = as | (1 << (31 - bs[4:0])) clear bit (binv = 0): result = as & ~(1 << (31 - bs[4:0])) exchange bit exchange the as bit determined by bs[4:0] with c flag. if the bit number resolves to a value greater than 23, no exchange is performed (i.e., result is equal to as and c flag is not updated). this operation overrides bs size to 8 bits. on this operation, cin field is ignored and binv field inverts (bitwise not) bs. v flag is never updated on exchange bit operation. c flag is always updated, regardless of ccsv, unless bs[4:0] > 23. exchange bit (binv = 1): if bs[4:0] <= 23 begin temp_c_flag = as[bs[4:0]] if c_flag == 1 result = as | (1 << bs[4:0]) table 495. types of bitwise operations aluop binv operation 10000 1 as | bs 10000 0 as | (~bs) 10001 1 as ^ bs 10001 0 as ^ (~bs) 10010 1 as & bs 10010 0 as & (~bs) RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 947/1740 else result = as & ~(1 << bs[4:0]) c_flag = temp_c_flag end exchange bit (binv = 0): if (31 - bs[4:0]) <= 23 begin temp_c_flag = as[31 - bs[4:0]] if c_flag == 1 result = as | (1 << (31 - bs[4:0])) else result = as & ~(1 << (31 - bs[4:0])) c_flag = temp_c_flag end multibit shift/rotate operations these operations shift or rotate as by 2, 4, 8 or 16 bits. size of shift/rotate is determined by bs[1:0]. table 496 describes the number of shifted/rotated bits depending on bs[1:0] value. shift right is a logical operation (i.e., zeros are inserted on left). multibit shift and rotate operations overrides bs size to 8 bits. the shifts and rotate operate on 24 bits, independently of the operation size. v flag is never updated for multibit shift or rotate operations. carry flag behavior is described on table 497 . cin is ignored in these operations, but binv is effective. table 496. number of shifted/rotated bits for each bs[1:0] value bs[1:0] bits shifted/rotated 02 14 28 316 table 497. carry flag value on multibit shift/rotate operations aluop bs[1:0] c flag value (1) 11001 (shift left) 0 as[22] 11001 (shift left) 1 as[20] 11001 (shift left) 2 as[16] 11001 (shift left) 3 as[8] 11010 (shift right) 0 as[1] 11010 (shift right) 1 as[3] 11010 (shift right) 2 as[7] 11010 (shift right) 3 as[15] 11011 (rotate right) 0 as[2] enhanced time processing unit (etpu2) RM0029 948/1740 doc id 15177 rev 8 absolute value operation absolute value operation is selected by aluop field. on this operation, as is interpreted as a signed number and its absolute value is the result. v and n flags are updated with the result signal determined by the operation size. as bit 23 after size override and sign extension (if any, see section , a-source size override ), regardless of a-source register size, is used to check the operand signal and is copied to c-flag. note that if as is 8-bit or 16-bit, its sign is taken into account and copied to c only if sign-extension is performed. ta ble 49 8 summarizes flag updating for absolute value operation. this operation is independent of b-source. instruction fields t4bbs, binv and cinv are ignored in this operation. the absolute value operation size is the minor between a-source size and destination size. mac and divide unit (mdu) mdu is an autonomous resource in the microengine which can carry out sequential multiply, multiply-accumulate, fractional multiplication and divide operations, selected through the microinstruction fields aluop or aluopi. the unit supports signed and unsigned multiply and fractional multiplication of any combination of 8, 16 or 24-bit operands (aq) , and also signed and unsigned 24-bit multiply-accumulate. divide operation is unsigned, and both operands are always 24-bit wide. depending on the size of operands and the type of operation, mdu can take more than one microcycle to execute the operation, but microengine continues to execute microinstructions in parallel. when the microcode issues an end command, any mdu executing operation terminate immediately and is left incomplete. when selecting an operation that uses mdu, the result is always placed in mach and macl registers, and the register selected as destination does not have its value changed ( section , selecting sources and destination ). 11011 (rotate right) 1 as[4] 11011 (rotate right) 2 as[8] 11011 (rotate right) 3 as[16] 1. ccs/ccsv can disable flag update on multibit shift/rotate, but the specified flag size in ccsv is ignored for the c flag. table 497. carry flag value on multibit shift/rotate operations aluop bs[1:0] c flag value (1) table 498. alu flags in absolute value operation operation size v, n (1) 1. v, n can be 1 on 8- and 16-bit absolute value, because the operand sign is always taken from bit 23. v, n can also be 1 in 23-bit absolute value (or 8-bit and 16-bit with sign extension), if the operand is 0x800000 (0x80, 0x8000). cz 8 alu_output[[7] as[23] alu_output[7:0] == 0 16 alu_output[15] alu_output[15:0] == 0 23 alu_output[23] alu_output[23:0] == 0 aq. there is no distinct selection of 24-bit fractional mu ltiplication, for it works exactly as a 24-bit ordinary multiplication. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 949/1740 during calculations, mach and macl holds temporary values and should not be written, otherwise the result is unpredictable. one must not start an mdu operation while mdu is already busy: the result is unpredictable for both the ongoing operation and the started one. mdu operations update its own set of five flags, described in section , mdu flags . mdu operations never update c, n, v and z flags. cin and binv microinstruction fields affect mdu operations according to table 499 . multiply and multiply-accumulate operation length mdu needs two sources, a source and b source, to perform an operation. the time needed to perform a multiply or multiply-accumulate is: on 24-bit x 8 bit multiplies: 2 microcycles (one start-mdu plus one execution microcycle) on 24-bit x 16 bit multiplies: 3 microcycles (one start-mdu plus two execution microcycles) on 24 bit x 24 bit multiplies/macs: 4 microcycles (one start-mdu plus three execution microcycles) an internal pipeline in mdu allows multiply-accumulate (or even non-fractional multiply) operations to start one microinstruction before a multiplication or multiply-accumulate (signed or unsigned) has been completed (e.g., one can start one multiply or multiply- accumulate once every three microinstructions). however, by doing that it is not possible to read the result in mach and macl (although the mdu flags can be tested), so this is intended to be used in a multiply-accumulate sequence. it is also allowed to mix different sizes in multiply/mac sequences. multiply-accumulate operations are similar to multiply operations, except that the contents of mach and macl registers are added to the multiplication result. when multiply or multiply accumulate operations finish, macl and mach hold the least and the most significant 24-bit words, respectively. divide operation length the divide operation is always unsigned. the division completes in 13 microcycles, meaning that after the start divide microinstruction, one has to wait for 12 microcycles and then read the result and the remainder in mach and macl registers. during the 12 execution microcycles, microengine can execute microinstructions unrelated to the mdu. table 499. cin and binv with mdu operations b-source operand binv cin operation performed signed 1 1 as mdu_op bs 0 0 as mdu_op (-bs) 1 0 reserved 0 1 reserved unsigned (1) 1. includes the b-source (unsigned) in fmults (signed) operations. 1 1 as mdu_op bs 1 0 as mdu_op (bs+1) 0 x reserved enhanced time processing unit (etpu2) RM0029 950/1740 doc id 15177 rev 8 signed multiplication (mults) mdu signed multiplication is defined as follows: (signed) mach,macl = (signed) as * (signed) bs mc and mv flags are reset. mz is set if result is 0, resets otherwise. mn is set if result is negative. unsigned multiplication (multu) mdu unsigned multiplication is defined as follows: (unsigned) mach|macl = (unsigned) as * (unsigned) bs mc and mv flags are reset. mz is set if result is 0, resets otherwise. mn is a copy of the most significant bit of result. signed multiply-accumulate (macs) mdu signed multiply-accumulate is defined as follows: (signed/unsigned) {mach,macl} += (signed) as * (signed) bs mc is not altered. mv is set if result can not be represented by a 48-bit signed number. macs never resets mv flag: it is left as is if no overflow occurs, or set it otherwise. this allows checking the overflow flag only once at the end of a series of multiply-accumulate operations in a scalar product calculation. if (({mach,macl} += as * bs < -2 47) || ({mach,macl} += as * bs > 2 47 - 1)) mv = 1 mz is set if result is 0, resets otherwise. mn is a copy of the most significant bit of result. note that only 24-bit multiply-accumulate is available. unsigned multiply-accumulate (macu) mdu unsigned multiply-accumulate is defined as follows: (signed/unsigned) {mach,macl} += (unsigned) as * (unsigned) bs mc is set if result can not be represented by a 48-bit unsigned non-negative number. macu never resets mc flag: mc flag is left as is if no carry occurs, or set otherwise. this allows checking the carry flag only once at the end of a series of multiply-accumulate operations in a scalar product calculation. if (({mach,macl} += as * bs < 0) || ({mach,macl} += as * bs > 2 48 - 1)) mc = 1 mv is not altered. mz is set if result is 0, resets otherwise. mn is a copy of the most significant bit of result. note that only 24-bit multiply-accumulate is available. signed fractional multiplication (fmults) mdu signed fractional multiplication takes the b-source as an unsigned 8- or 16-bit fraction between 0 and (2 8 - 1)/2 8 (inclusive) for the 8-bit operation, or between 0 and (2 16 - 1)/2 16 (inclusive) for the 16-bit operation. only a-source is taken as a signed number. the RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 951/1740 value of b-source is considered the unsigned numerator of a fraction with denominator 2 8 or 2 16 for the 8- and 16-bit operations, respectively. the integer part of the result is stored in mach, and the fractional part in macl. the result is signed, so that the concatenation of mach and macl form a 48-bit fixed point number with a 24-bit mantissa, both for 8- and 16-bit operations. to calculate the unsigned numerator of the fractional part (with denominator 2 24 ) of the result, one must take the absolute value of macl considering the signal of the result (not macl alone), i.e.: if flag mn = 1, invert macl and add 1. mdu flags are updated in the same way as in the signed multiplication. unsigned fractional multiplication (fmultu) mdu unsigned fractional multiplication takes both a-source and b-source as unsigned operands. b-source is taken as an 8- or 16-bit fraction between 0 and (2 8 - 1)/2 8 (inclusive) for the 8-bit operation, or between 0 and (2 16 -1)/2 16 (inclusive) for the 16-bit operation. the value of b-source is considered the numerator of a fraction with denominator 2 8 or 2 16 for the 8 and 16-bit operations, respectively. the integer part of the result is stored in mach, and the fractional part in macl. the fractional part in macl is the numerator of a fraction with denominator 2 24 . the concatenation of mach and macl form a 48-bit fixed point number with a 24-bit mantissa, both for 8 and 16-bit operations. mdu flags are updated in the same way as in the unsigned multiplication. unsigned divide (div) at the end of a divide operation macl holds the result of the division, taking a-source as numerator and b-source as denominator, while mach holds the remainder. if a divide by 0 is executed, macl holds the maximum unsigned number (0xffffff) as result and flag mv is set to indicate division by 0 (otherwise reset). the contents of mach become indetermined. mc flag is always reset. mz flag is set if macl equals 0, and reset otherwise. mn receives a copy of mach bit 23 (msb from the remainder). note that signed division is not available. mdu flags mdu has its own flags to indicate the result and status of an mdu operation. they are: mc, mz, mv, mn and mb. all mdu flags are updated with the final result at the end of the operation, and do not change until the next operation finishes. therefore it is possible to start a new mdu operation and test the flags of the previous one in parallel, except for mult/mac with 8-bit operand (takes only 1 microcycle). mdu negative flag ? mn mn flag is always a copy of mach bit 23 at the end of the operation, either in signed or unsigned ones. note that mach holds the rest of a division operation, which is always unsigned. enhanced time processing unit (etpu2) RM0029 952/1740 doc id 15177 rev 8 mdu carry flag ? mc mdu carry flag indicates if the result cannot be represented by a 48-bit number, in signed and unsigned multiply accumulates. it is reset in the other operations. mdu zero flag ? mz in multiply and multiply-accumulate operations, mdu zero flag is asserted if mach and macl are equal to zero at the end of an operation. in divide operations, zero flag is asserted if macl (result) is equal to 0. mdu overflow flag ? mv in multiply operations, mv flag is negated and keeps negated in the end, because the result of a multiplication can always fit in a 48-bit result (mach and macl concatenated). in a multiply-accumulate operation, mv is asserted if the result size is wider than 48 bits. mv flag work in both signed and unsigned operations. in divide operations it is only asserted if a divide-by-zero operation was executed. mdu busy flag (mb) mb tests as true at the next microinstruction after the mdu start operation, and as false at the last microcycle of any mdu operation execution. branch conditions microengine allows conditional branch. there are five sets of flags that can be tested in a conditional branch: alu flags, mdu flags, p flags, channel flags, and semaphore flag (flag smlck). when a thread starts to be executed, the values in mdu and alu flags are not initialized. alu flags are described in section , alu flags . mdu flags are described in section , mdu flags . mdu and alu flags are updated during execution of microinstructions. p flags are actually the upper byte of p register, which optionally can work as user defined flags (see section , p register ). channel flags flags0, flag1, mrla, mrlb, tdla, tdlb, pss, psti and psto are obtained from the selected channel (value in chan register), while channel flags, lsr, fm[0] and fm[1] are selected by the serviced channel, regardless of the chan value (ar) . flags tdla/b, mrla/b, lsr, fm[1:0] and pss, are sampled at the beginning of a thread. flag pss does not change during its execution while chan register is not written. when a write in chan register is performed, all flags except lsr and fm[1:0] are updated according to the channel specified by chan value. flags mrla/b and tdla/b are reset when their respective latches in channel are cleared by microcode. ar. serviced channel does not change during execution of a thread, and it is the channel that requested a service (initial value of chan register when a thread starts). table 500. channel flags as branch condition flag description service or selected channel flag0 state resolution flag reflects the selected channel (chan) flag1 state resolution flag reflects the selected channel (chan) RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 953/1740 semaphore condition smlck always indicates if a semaphore is locked for the engine, resolving as false before any lock attempt. for each trial, the smlck flag is updated. the smlck value set in one thread is not meaningful to the other. after a free, the smlck condition tests as false until a new lock attempt on the same thread. branch conditions are selected through instruction fields bcc and bcf (see section , conditional/unconditional branch ). 24.5.9 microinstruction set each microinstruction can execute up to three microoperations in parallel. microinstructions are grouped into formats, and there are four types of microoperations : alu/mdu operations spram operations channel configuration/control operations flow control operations each microinstruction format is defined by a set of microinstruction fields, which determine the operations, each belonging to one of the groups above (there may be several in one group). complete microinstruction formats are shown in section , microinstruction formats . parallelism conflicts may arise when two operations are executed in the same microinstruction. these situations are explained in section , microinstruction parallelism issues . spram microoperations the access to spram is made by providing an address and a register to perform a data transfer, except semaphore operations, which are also classified in the spram group. only mrla match a recognition latch these flags reflect the selected channel (chan) see section , mrla/b ? match recognition latches , and section , tdla/b ? transition detect latches , for more information. mrlb match b recognition latch tdla transition a detection latch tdlb transition b detection latch lsr link service request reflects the serviced channel. pss sampled input pin state reflects the selected channel (chan). does not change if chan is not changed (see section , pin control registers ). psti current input pin state. reflects the selected channel (chan). changes any time. psto current output pin state reflects the selected channel (chan). changes any time. fm[1:0] function mode bits reflects the function mode for serviced channel ( section , etpu_cxscr ? etpu channel x status control register ) table 500. channel flags as branch condition (continued) flag description service or selected channel enhanced time processing unit (etpu2) RM0029 954/1740 doc id 15177 rev 8 p and diob registers can exchange data with spram. microengine always addresses spram in 32-bit boundaries, for 8, 24, or 32-bit wide data. direction is determined by the field rw in all addressing modes: rw = 0 selects read and rw = 1 selects write. spram addressing modes the etpu has four addressing modes: absolute selected channel relative indirect engine relative the addressing modes absolute and selected channel relative use immediate bits to form the physical address of spram, which is identified in microinstruction as a field called aid. aid field can be 3, 7, or 8-bit wide depending on the addressing mode. absolute addressing mode in absolute addressing mode, the address range is 256 parameters, addressed by field aid, which in this mode is 8-bit wide. these parameters are located in spram addresses from 0 to 255. physical_address = aid[7:0] selected channel relative addressing mode in selected channel relative addressing mode, only the first 8 (with 3-bit aid) or 128 (with 7-bit aid) parameters of the selected channel are accessible, depending on the microinstruction format. physical address is calculated using the channel parameter base address that is specified in field cpba of etpu_cxcr (see section , etpu_cxcr ? etpu channel x configuration register ). aid field is added to channel parameter base address to compose the physical address. the equation is: physical_address = selected_channel_parameter_base_address + aid[6:0], or physical_address = selected_channel_parameter_base_address + aid[2:0] indirect addressing mode in indirect addressing mode the physical address is taken from diob register. only diob bits 13 to 2 are relevant. since the spram word address is shifted two bits up in diob, its contents hold the same parameter address value used by host. the equation is: physical_address = diob[13:2], or physical_address = (truncated) diob / 4 indirect addressing mode can have post-increment or pre-decrement on diob, allowing stack operations. see section , diob stack operation , for more information. engine relative addressing mode in engine relative addressing mode the physical address is the concatenation of the etpu_ecr field erba (see section , etpu_ecr ? etpu engine configuration register ) with the 7-bit aid instruction field. this allows the same function microcode, when running on distinct engines, to access different address spaces, global to the engine only. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 955/1740 spram source/destination registers when performing an spram operation, only diob or p can be used as data source or destination. p is 32-bit wide, and diob is 24-bit wide. microinstruction field p/d (1 bit) is used to choose between p and diob as data the source or destination. when the p/d field is not available in microinstructions that support spram access, the source/destination is p. spram operation size when using diob register to perform spram data transfers, the operation size is always 24-bit wide (lower 24 bits of spram). when using p register, the operation size can be 8, 24 or 32-bit wide, which is controlled by microcode rsiz field (2 bits). rsiz meaning is shown in table 502 . rsiz is not available in all microinstructions that support spram access. in microinstructions where rsiz field is not available, spram access will be 24 bits by default. when performing a zero spram write operation (see section , zero spram operation ), rsiz defines the size of operation regardless of the p/d field ( section , spram source/destination registers ). spram access direction rw field defines the direction of the access in the spram. the access direction is summarized in table 503 . table 501. spram source/destination register selection p/d meaning 0 p access 1 diob access table 502. spram p access size rsiz p access diob access 00 full 32-bit access (i.e. p[31:0]=spram[addr] [31:0]) reserved 01 only upper 8 bits are transferred (i.e. p[31:24] = spram[addr] [31:24]) reserved 10 only lower 24 bits are transferred (i.e. p[23:0] = spram[addr] [23:0]) diob = spram[addr] [23:0] 11 reserved reserved table 503. spram access direction r/w meaning 0 read spram parameter into p or diob registers 1 write spram parameter from p or diob registers enhanced time processing unit (etpu2) RM0029 956/1740 doc id 15177 rev 8 zero spram operation zero spram operation is controlled by microcode field zro (1 bit). when zro field is 0, the data portion written in spram or in p/diob (spram read) registers will always be 0x0. when performing a zero spram write operation, the rsiz is relevant regardless of the p/d field (usually rsiz is meaningful only for p/d = 0), which means that zero spram write operation can be performed with 32, 24 or 8 bits according to spram operation size. these conditions are summarized in table 504 . note: when field stc is present, stc = 11 also disables zero spram operation (see table 505 ). the conflicts with diob operations (see section , diob stack operation ) and alu operations are resolved like a normal spram operation (see table 546 ). diob stack operation spram indirect addressing mode (see section , indirect addressing mode ) is used if stc field (2 bits) exists in the microinstruction, controlling automatic increment/decrement of diob register, as shown in table 505 , thus allowing stack operations. diob is incremented and decremented in word addresses, only from bits 15 downto 2, i.e.: the bits 23 to 16 and 1 to 0 are left untouched by stc pre-decrement and post-increment. semaphore operations semaphore lock and free operations are available through etpu microcode. for more information about semaphores see section , hardware semaphores . two microinstruction fields control semaphore operations: fl (1 bit) and smpr (2 bits). serviced channel sees four semaphores, selected by field smpr. table 504. zero spram operation zro rw p/d meaning 0 0 0 clear p register. size is determined by rsiz field. see section , spram operation size . 0 0 1 clear diob (all 24 bits), independently of rsiz 01x clear spram parameter. size is determined by rsiz field. see section , spram operation size . 1 rw p/d regular spram operation table 505. diob post-increment / pre-decrement ? stc stc meaning 00 post-increment of diob 01 pre-decrement of diob 10 no increment/decrement (normal access) 11 no spram access (1) 1. also disables zero spram operation RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 957/1740 when freeing a semaphore, the field smpr has no meaning. this is because only one semaphore can be locked at a time by each engine, so when freeing a semaphore it is not necessary to specify its number. note: if microcode tries to lock a semaphore already locked for the same engine, the semaphore continues locked for the engine and the smlck branch condition resolves as true. alu/mdu operations alu/mdu microoperations mostly comprises two sources, one destination and one operation. the operation is generally selected through fields aluop, aluopi or shf. in formats where there is no operation selection field (aluop, aluopi or shf), the operation performed is always addition; however, it is possible to perform subtraction, increment or decrement using fields binv (see section , b-source inversion ) and cin (see section , carry-in control ). source and destination register set selection microcode field t4abs allows selection of a source from either one of two register sets, shown in table 510 . the same applies to t2abd, used for alu destination selection with other two register sets, as shown in tab le 5 11 . microinstruction fields abse and abde control the register set selection for source and destination, respectively, when available at the format. in formats without abse/abde, the field t4bbs determines the register sets used by t2abd and t4abs, as shown in section , microinstructions without fields abse and abde . microinstructions with fields abse and abde in microinstructions where abse and abde fields are available (1 bit each), abse controls register set selection for t4abs and abde controls register set selection for t2abd. ta ble 50 7 shows the meaning of values for abse and abde fields. microinstructions without fields abse and abde when abse and abde are not available in a microinstruction format, register set is selected by t4bbs field. table 508 explains how to select a register set either for t4abs and t2abd. table 506. semaphore operations fields field meaning fl 0 = free semaphore, 1 = lock semaphore smpr semaphore number selector table 507. register set selection by abse or abde abse or abde register set selected 0 second 1first enhanced time processing unit (etpu2) RM0029 958/1740 doc id 15177 rev 8 selecting sources and destination all alu/mdu operations need two sources (called as and bs) and one destination (called ad), except for some of those that use immediate data (see section , operations with immediate data ). fields t4abs (4 bits), abse (1 bit), t4bbs (3 bits) select sources, while t2abd (4 bits) and abde (1 bit) select the destination. when mdu is used (multiply/divide), t2abd destination selection is ignored and results are stored in mach and macl (see section , mac and divide unit (mdu) ). abse and abde are not available in some microinstruction formats that support alu/mdu operations. however, in all formats where abse is available, abde is also available and vice-versa. the existence of abse/abde fields changes the meaning of t4bbs field, as shown in table 509 . on instructions with immediate data, it is used as b-source (see section , operations with immediate data ). all sources and destinations have a size associated to them, and these sizes are used to select flag sample position (see section , flags sampling control ). sizes can be 8, 16 or 24 bits. registers that are not exactly of one of these sizes are treated as the immediately upper size (e.g., chan[4:0] is an 8-bit source). see section , flags sampling control , for more information. some parallelism issues arise when selecting p, diob, erta or ertb as destination registers, since they can be modified by other microoperations in the same microinstruction (see section , microinstruction parallelism issues , for details). table 508. register set selection by t4bbs w/o abse, abde t4bbs register set for t2abd register set for t4abs 0xx first first 100 second second 101 second first 110 first second 111 first first none (1) 1. refers to operations with immediate data as b-source, without abse, abde. first first table 509. b source selection ? t4bbs t4bbs meaning in microinstruction formats with abse/abde meaning in microinstruction formats without abse/abde (1) 000 bs[23:0] = p[23:0] 001 bs[23:0] = a[23:0] 010 bs[23:0] = sr[23:0] 011 bs[23:0] = diob[23:0] 100 reserved bs = 0 101 reserved bs = 0 110 reserved bs = 0 111 bs = 0, or max const., if cin = 0 and binv = 0 (see section , generating ?max? constant ). 1. t4bbs also selects a-source and destination register set in this case, according to table 508 . RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 959/1740 t4abs selects one source from two register sets, shown in table 510 . abse and t4bbs control which set t4abs field uses to select the source. for more information about how to select a register set for t4abs and t2abd see section , source and destination register set selection . all sources are zero-filled to 24 bits, unless sign-extension is specified (see section , a-source size override ). t2abd selects the destination from one of two register sets, shown in table 511 . abde and t4bbs control which set t2abd field uses to select the destination. table 510. a source selection ? t4abs t4abs first register set second register set selected register size selected register size 0000 as[7:0]=p[7:0] 8 as[7:0] = 0 8 0001 as[7:0]=p[15:8] 8 as[23:0]=c[23:0] 24 0010 as[7:0]=p[31:24] 8 as[15:0] = tpr[15:0] 16 0011 as[23:0] = ertb[23:0] 24 as[23:0] = b[23:0] 24 0100 as[23:0] = d[23:0] 24 as[23:0] = trr[23:0] 24 0101 as[15:0] = p[15:0] 16 as[7:0] = 0, read_match (1) 8 0110 as[15:0] = p[31:16] 16 as[13:0] = rar[13:0] 16 0111 as[7:0] = p[23:16] 8 as[23:0] = mach[23:0] 24 1000 as[23:0] = p[23:0] 24 as[23:0] = macl[23:0] 24 1001 as[23:0] = a[23:0] 24 as[4:0]=chan[4:0] 8 1010 as[23:0] = sr[23:0] 24 as[14:2] = chan_base (2) 16 1011 as[23:0] = diob[23:0] 24 as[13:0] = engine_base (3) 16 1100 as[23:0] = tcr1[23:0] 24 reserved - 1101 as[23:0] = tcr2[23:0] 24 reserved - 1110 as[23:0] = erta[23:0] 24 reserved - 1111 as[23:0] = 0 24 reserved - 1. t4abs = 0101 with second register set also reads matcha/b registers into erta/b (see section , special t4abs source operation: read match registers ). 2. chan_base is the selected channel?s base spram address in channel relative address mode (see section , chan_base as a source ). 3. engine_base is the etpu_ecr field erba shifted left nine positions. table 511. destination selection ? t2abd t2abd first register set second register set selected register size selected register size 0000 a[23:0] = ad[23:0] 24 c[23:0] = ad[23:0] 24 0001 sr[23:0] = ad[23:0] 24 link[7:0] = ad[7:0] 8 0010 erta[23:0] = ad[23:0] (1) 24 tpr[15:0] = ad[15:0] 16 enhanced time processing unit (etpu2) RM0029 960/1740 doc id 15177 rev 8 max constant generation with t4bbs = 111 when t4bbs = 111, binv = 0, and cin = 0, the value assigned to bs will be 0x800000, and not 0x0 as expected. see section , generating ?max? constant , for a detailed explanation. special t4abs source operation: read match registers when t4abs = 0101 and the source for t4abs is selected from the second register set, the constant 0x00 is used as as (8-bit size) and the following register transfer is performed in parallel as well: match registers of the selected channel (value in chan register) are copied to erta/ertb registers, where erta receives the value of matcha register and ertb receives the value of matchb register (see section , er ? event registers ). note that alu destination can still be chosen by t2abd in parallel. when erta or ertb is selected by t2abd, a parallelism issue arises (see section , alu operations and read match registers ). chan_base as a source each channel has a parameter base address in spram, which is configured in etpu_cxcr registers, cpba field (see section , etpu_cxcr ? etpu channel x configuration register ). chan_base, which represents a parameter address (cpba*2), can be used as a-source using t4abs = 1010 when t4abs selects a source from the second register set. in this case, chan_base is loaded into as[13:2] to form the byte address (as[23:14] = 0, as[1:0] = 0). for example, in indirect addressing mode, where the destination register is diob, chan_base is loaded into diob[13:2], which is the parameter address, and diob[13:0] represents the byte address. chan_base is the base address of the selected channel (given by chan register). 0011 ertb[23:0] = ad[23:0] (2) 24 b[23:0] = ad[23:0] 24 0100 diob[23:0] = ad[23:0] 24 chan[4:0] = ad[4:0] 8 0101 p[15:0] = ad[15:0] 16 d[23:0] = ad[23:0] 24 0110 p[31:16] = ad[15:0] 16 rar[12:0] = ad[12:0] 16 0111 p[23:0] = ad[23:0] 24 mach[23:0] = ad[23:0] 24 1000 tcr1[23:0] = ad[23:0] 24 macl[23:0] = ad[23:0] 24 1001 tcr2[23:0] = ad[23:0] 24 reserved - 1010 p[31:24] = ad[7:0] 8 reserved - 1011 p[23:16] = ad[7:0] 8 reserved - 1100 p[15:8] = ad[7:0] 8 reserved - 1101 p[7:0] = ad[7:0] 8 reserved - 1110 trr[23:0] = ad[23:0] 24 reserved - 1111 no destination selected (3) 24 reserved - 1. t2abd = 0010 with first register set also writes to matcha or udcm registers of the selected channel if field erwa = 0 (see section , write channel match and udcm registers ). 2. t2abd = 0011 with first register set also writes to ma tchb register of the selected channel if field erwb = 0. 3. if no destination is selected, alu flags are updated, although the result is lost. table 511. destination selection ? t2abd t2abd first register set second register set selected register size selected register size RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 961/1740 flags sampling control this section explains how the flags z (zero), c (carry), n (negative) and v (overflow) are updated in an alu operation. when there are post-alu shift operations, the alu carry out is not directly sampled in carry flag, but passed to the post-alu shifter (see section , shift operations ). since the size of source operands in alu operations is variable, flags can be sampled as an operation of 8, 16 or 24 bits wide. the operation size selection is automatic, based on defined sizes of sources and destination, using the equation: operation_size = minor(size_of(destination), greater(size_of(a-source), size_of(b-source))) operation size can also be shown with the following table: note: whenever bs = (constant) 0, its size is considered 8 bits, and all 24 bits in b-bus are set to 0. therefore, all operations with bs = (constant) 0 have their size determined by as and destination only. ccs field (1 bit) controls whether flags will be updated or not ( table 514 ). when ccs bit exists in a microinstruction, the operation size will be used to sample flags. in some microinstructions ccs field is replaced by ccsv (2 bits, table 513 ). flag sampling according to ccsv can be set as defined by the operation size, or fixed as 8 or 16-bit operations. note: for the post-alu rotate right operation, ccsv also determines the rotate size: whether 8- bit, 16-bit, or determined by the operation size. table 512. operation size determination a source b source destination operation size x x 8 bits 8 bits 8 bits 8 bits x 8 bits 16 or 24 bits x 16 bits 16 bits 16 bits 8 or 16 bits 24 bits 16 bits 8 or 16 bits 16 bits 24 bits 16 bits 24 bits x 24 bits 24 bits x 24 bits 24 bits 24 bits table 513. flag sampling using ccsv field ccsv meaning 00 sample flags as an 8 bit operation 01 sample flags as a 16 bit operation 10 sample flags as defined by operation size 11 do not sample flags enhanced time processing unit (etpu2) RM0029 962/1740 doc id 15177 rev 8 when neither ccs nor ccsv are present in the microinstruction, flags are not sampled. ccs and ccsv do not affect the carry update on exchange bit operation (see section , exchange bit ), but does control the n and z flags. b-source inversion the data selected as second source (t4bbs) can be inverted (bitwise boolean not) before operation. this is controlled by microinstruction field binv (1 bit, ta ble 51 5 ). a zero value for binv activates b-source inversion. binv also selects between adc or sbc enhanced alu operation, using inverted c flag as carry-in besides bs inversion for sbc . note that binv does not invert carry in fixed-carry operations (see table 516 ). when binv = 0, t4bbs = 111 and cin = 0, the value assigned to bs is 0x800000, instead of 0x0. see section , generating ?max? constant , for more details. carry-in control cin field (1 bit, ta ble 51 6 ) controls the carry-in for addition/subtraction operations. functionality of cin field depends on the arithmetic operation selected by aluop. when aluop is not available in microinstruction, the operation selected is add . for carry-in control in mdu operations, see table 499 . table 514. flag sampling using ccs field ccs meaning 0 sample flags as defined by operation size 1 do not sample flags table 515. b-source inversion ? binv binv meaning 0 invert b-source (1) 1. except on max-constant selection, see section , generating ?max? constant . 1 keep b-source bus unchanged table 516. alu carry-in control operation cin = 0 cin = 1 add (addition) carry-in used is 1 (1) carry-in used is 0 adc (addition with carry) (2) carry-in used is c flag sbc (subtraction with borrow) (3) carry-in used is inverted c flag 1. except on max-constant selection, see section , generating ?max? constant . 2. selected by aluop = 11000 and binv = 1 3. selected by aluop = 11000 and binv = 0 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 963/1740 generating ?max? constant when t4bbs = 111, cin = 0 and binv = 0, bs is assigned to 0x800000 (called ?max constant?) instead of 0x000000. this is an exception for cin and binv fields: when ?max constant? is selected, the carry in is 0 and b-source (?max constant? itself) is not inverted, neither the carry out. ?max constant? is the value which, added to a time base value minus 1, gives the farthest wrapped time base value that satisfies a channel greater-equal comparison. see section 24.5.5, enhanced channels , for more information. shift operations there are three types of shift operations: alu, post-alu and shift register. alu shift operations are covered in section , alu/mdu operation selection . post-alu and shift register are covered in the following sections. shift register operations sr can be used as a general purpose register and it can easily shift-right its contents, combined or not to post-alu shift operations. if field src (1 bit) in microcode is 0, sr will shift its contents 1 bit to the right according to the algorithmic description below. sr shifting operation depends also on shf or aluop fields. aluop and shf never exist both on the same microinstruction format. sr operation : sr[22:0] = sr[23:1]; if shf == ?01? or aluop == ?10110? then sr[23] = alu_out[0]; else sr[23] = 0; endif; post-alu shift operations post-alu shift can be selected by shf field (2 bits) or by some specific aluop field values. shf and aluop fields are never both available in the same microinstruction format. when selecting post-alu shift operation using aluop field, alu will always add the sources before shifting the result. table 517. shift register control ? src src meaning 0 shift right sr 1 bit 1 no shift table 518. post-alu shift operation post alu operation shf (1) 1. alu performs as+bs before shift/rotate for all shf values. aluop shift left (1 bit) 00 10101 shift right (1 bit) 01 10110 rotate right (1 bit) 10 10111 no shift/rotate 11 any other (2) enhanced time processing unit (etpu2) RM0029 964/1740 doc id 15177 rev 8 carry flag is only updated when ccs or ccsv[1:0] fields allow it (see section , flags sampling control ). algorithmic descriptions of post-alu shift operations are presented in section , alu add operation with and without shifting . conditional alu/mdu operation execution the 3-bit field as/ce allows conditional execution of arithmetic operation, as shown in ta ble 51 9 . the same field can also be used for overriding the size of a-source (see section , a-source size override ). other operations not related to alu/mdu in the same microinstruction are not affected by the as/ce field. if a conditional operation is selected, there is no a-source size override; similarly, when size override for a-source is selected, the alu/mdu operation executes unconditionally. when a conditional alu/mdu operation is not executed: the destination register is not updated. if the destination is chan, no actions associated with chan assignment occur (see section , channel selection register ? chan ). the alu and mdu flags are not updated. mdu does not start any operation, i.e., mach and macl are not updated. sr does not shift. t4abs-selected read-match does not occur. a-source size override some values if the as/ce field are used for a-source size override, as shown in table 520 . 2. some aluop combinations perform shift/rotate, but not using the post-alu shifter (see table 523 ) table 519. alu/mdu conditional execution as/ce meaning 000 used for a-source size override (see section , a-source size override ) 001 010 execute if c = 1 011 execute if c = 0 100 execute if z = 1 101 execute if z = 0 110 execute if n = 1 111 execute unconditionally/no size override table 520. a-source size override as/ce meaning 000 a-source size override to 8 bits 001 a-source size override to 16 bits RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 965/1740 register size override zero-pads an overridden source to 24-bits (if no sign extension is performed, see section , a-source sign extension ) and affects operation size calculation. when register source is wider than size override, most significant bits of selected register are not used as a source (zeros are used instead). when size override is wider than selected register, register value is padded to zeros.when size override is used with mdu operations, it affects only the operand values, but not the operation size: mdu operation size is fully determined by the operation definition (fields aluop, aluopi). a-source sign extension the sext microinstruction field forces sign extension of a source according to the size of a operand, either overridden or not by as/ce field, according to table 522 . the sign is taken from the size-overridden value, not the original one. a-source sign is not extended in microinstructions without sext field, even if as/ce field is present. 010 used for conditional execution (see section , conditional alu/mdu operation execution ) 011 100 101 110 111 execute unconditionally/no size override table 520. a-source size override (continued) as/ce meaning table 521. as/ce field a source size override funcionality size override size of selected register as value (1) 1. all values are zero-padded to 24 bits 8 bits 8 bits reg[7:0] 8-bits 16 bits reg[7:0] 8bits 24 bits reg[7:0] 16 bits 8 bits reg[15:0] 16 bits 16 bits reg[15:0] 16 bits 24 bits reg[15:0] table 522. a source sign extension sext meaning 0 extends sign of a source from its size to 24-bits 1 does not extend sign of a source enhanced time processing unit (etpu2) RM0029 966/1740 doc id 15177 rev 8 alu/mdu operation selection when field aluop is available in microinstruction, enhanced alu operations shown in ta ble 52 3 can be performed, otherwise addition is performed. the alu operations are defined in section , alu and post-alu shifter . the mdu operations are defined in section , mac and divide unit (mdu) . table 523. alu operation selection ? aluop aluo p operation comment 00000 as mults bs[7:0] signed multiplication 00001 as multu bs[7:0] unsigned multiplication 00010 as fmults bs[7:0] signed fractional multiplication 00011 as fmultu bs[7:0] unsigned fractional multiplication 00100 as mults bs[15:0] signed multiplication 00101 as multu bs[15:0] unsigned multiplication 00110 as fmults bs[15:0] signed fractional multiplication 00111 as fmultu bs[15:0] unsigned fractional multiplication 01000 as mults bs[23:0] signed multiplication 01001 as multu bs[23:0] unsigned multiplication 01010 as macs bs[23:0] signed multiply-accumulate 01011 as macu bs[23:0] unsigned multiply-accumulate 01100 as div bs[7:0] unsigned division by 8-bit value 01101 as div bs[15:0] unsigned division by 16-bit value 01110 as div bs [23:0] unsigned division by 24-bit value 01111 n.a. reserved 10000 as[23:0] | bs[23:0] 24 bit bitwise or 10001 as[23:0] ^ bs[23:0] 24 bit bitwise xor 10010 as[23:0] & bs[23:0] 24 bit bitwise and 10011 abs(as) absolute value of as 10100 as + bs arithmetic addition 10101 (as + bs) shl 1 arithmetic addition with 1-bit post-alu shift left. ( section , post-alu shift operations ) 10110 (as + bs) shr 1 arithmetic addition with 1-bit post-alu shift right ( section , post-alu shift operations ) 10111 (as + bs) ror 1 arithmetic addition with 1-bit post-alu rotate right ( section , post-alu shift operations ) 11000 as adc/sbc bs (1) addition/subtraction with c flag ( section , carry-in control ) 11001 as shl (2^(bs[1:0]+1)) as is shifted left: 2 bits for bs = 0; 4 for bs = 1; 8 for bs=2; 16 for bs=3 11010 as shr (2^(bs[1:0]+1)) as is shifted right: 2 bits for bs = 0; 4 for bs = 1; 8 for bs=2; 16 for bs=3 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 967/1740 operations with immediate data immediate data can be used with some specific microinstruction formats. etpu microcode allows 8-, 16- or 24-bit immediate data. immediate data is loaded as b-source, so t4bbs field is not available. when using 24-bit immediate, an add is performed with a-source = 0 and flags are not updated. alu operations are available with 8-bit immediate, although the field that selects alu operation in this case is aluopi. 24-bit immediate destination when using 24-bit immediate data, the destination register is selected by t2d field (2 bits), according to ta ble 52 4 . enhanced alu operations with immediate data enhanced operations with immediate data, selected by aluopi (5 bits) are allowed only with an 8 bit immediate operand (see table 525 ). 11011 as ror (2^(bs[1:0]+1)) as is rotated right: 2 bits for bs = 0; 4 for bs = 1; 8 for bs=2; 16 for bs=3 11100 as exch bs[4:0] exchange c flag and as bit determined by bs[4:0] ( section , exchange bit ) 11101 as setb bs[4:0] set bit in as determined by bs[4:0] (2) 11110 as clrb bs[4:0] clear bit in as determined by bs[4:0] (2) 11111 n.a. r eserved 1. addition/subtraction is selected by field binv (see section , b-source inversion ) 2. in setb and clrb operations, the register that drives a source is not changed, unless se lected as destination of the operation. table 523. alu operation selection ? aluop (continued) aluo p operation comment table 524. 24-bit immediate destination ? t2d t2d target register 00 p[23:0] 01 a[23:0] 10 sr[23:0] 11 diob[23:0] table 525. alu operation selection with immediate data ? aluopi aluopi operation comment 00000 as mults #imm8 signed multiplication 00001 as multu #imm8 unsigned multiplication 00010 as fmults #imm8 signed fractional multiplication 00011 as fmultu #imm8 unsigned fractional multiplication 00100 as div #imm8 unsigned division 00101 n.a. reserved enhanced time processing unit (etpu2) RM0029 968/1740 doc id 15177 rev 8 00110 n.a. reserved 00111 n.a. reserved 01000 ad[7:0] = as[7:0] | #imm8, ad[23:8] = as[23:8] bitwise or 01001 ad[7:0] = as[7:0] ^ #imm8, ad[23:8] = as[23:8] bitwise xor 01010 ad[7:0] = as[7:0] & #imm8, ad[23:8] = as[23:8] bitwise and 01011 ad[7:0] = as[7:0] & #imm8, ad[23:8] = 0x0 bitwise and with clear 01100 ad[15:8] = as[15:8] | #imm8, ad[23:16] = as[23:16], ad[7:0] = as[7:0] bitwise or 01101 ad[15:8] = as[15:8] ^ #imm8, ad[23:16] = as[23:16], ad[7:0] = as[7:0] bitwise xor 01110 ad[15:8] = as[15:8] & #imm8, ad[23:16] = as[23:16], ad[7:0] = as[7:0] bitwise and 01111 ad[15:8] = as[15:8] & #imm8, ad[23:16] = 0x0, ad[7:0] = 0x0 bitwise and with clear 10000 ad[23:16] = as[23:16] | #imm8, ad[15:0] = as[15:0] bitwise or 10001 ad[23:16] = as[23:16] ^ #imm8, ad[15:0] = as[15:0] bitwise xor 10010 ad[23:16] = as[23:16] & #imm8, ad[15:0] = as[15:0] bitwise and 10011 ad[23:16] = as[23:16] & #imm8, ad[15:0] = 0x0 bitwise and with clear 10100 as + #imm8 arithmetic addition 10101 (as + #imm8) shl 1 arithmetic addition with 1-bit shift left. 10110 (as + #imm8) shr 1 arithmetic addition with 1-bit shift right 10111 (as + #imm8) ror 1 arithmetic addition with 1-bit rotate right 11000 n.a. reserved 11001 as shl (2^(#imm8[1:0]+1)) as is shifted left: 2 bits for #imm8 = 0; 4 for #imm8 = 1; 8 for #imm8=2; 16 for #imm8=3 11010 as shr (2^(#imm8[1:0]+1)) as is shifted right: 2 bits for #imm8 = 0; 4 for #imm8 = 1; 8 for #imm8=2; 16 for #imm8=3 11011 as ror (2^(#imm8[1:0]+1)) as is rotated right: 2 bits for #imm8 = 0; 4 for #imm8 = 1; 8 for #imm8=2; 16 for #imm8=3 table 525. alu operation selection with immediate data ? aluopi (continued) aluopi operation comment RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 969/1740 channel control and configuration microoperations channel control and configuration fields set configuration values in the channel logic of the channel selected by the chan register, except fields lsr and circ. channel flags operations each channel has two associated hardware flags, called channel flag 0 and channel flag 1. microcode field flc (3 bits) allows them to be set or cleared, as shown in ta ble 52 6 . these flags can be tested by microcode as a branch condition, and may also influence in the entry point taken, allowing fast state decoding. for more details, see section , entry points . comparator and time base selection tbsa and tbsb fields (4-bit wide each) are used to configure the type of the comparator and the time bases used for match or capture (see table 527 and table 528 ). tbsa can also be used to control the output buffer enable signal (see table 475 ). 11100 as exch #imm8[4:0] exchange c flag and as bit determined by #imm8[4:0] (see section , exchange bit ) 11101 n.a. reserved 11110 n.a. reserved 11111 n.a. reserved table 525. alu operation selection with immediate data ? aluopi (continued) aluopi operation comment table 526. p flags operation ? flc flc meaning 000 clear flag0 001 set flag0 010 clear flag1 011 set flag1 100 copy flag1:flag0 from p[25:24] 101 copy flag1:flag0 from p[27:26] 110 copy flag1:flag0 from p[29:28] 111 no operation (nil) table 527. time base selection 1 ? tbsa tbsa bit 2 1 0 tbsa[3] = 0 bitfield comparator selection capture selection match tb selection 0 greater or equal tcr1 tcr1 1 equal-only tcr2 tcr2 enhanced time processing unit (etpu2) RM0029 970/1740 doc id 15177 rev 8 transition detection and pin action control ipaca/b and opaca/b fields are used to configure transition detection sensitivity (for the channel input signal) or output pin action control (for the channel output signal), as defined in ta ble 52 9 . ipaca and ipacb have the same format, where ipaca is related to match a and first transition detection, and ipacb to match b and second transition detection. the same applies in analogue way to opaca and opacb. for the output signal, configuring opac registers does not change the current signal state, but defines the action to be done when a match or transition detection occurs. see section , match recognition , and section , channel modes on output signal generation , for more information. ipaca/b = 1xx also enables assertion of mrla/b during time slot transition. see section , match recognition . tbsa[3] = 1 action 210 set obe = 1 0 0 0 set obe = 0 0 0 1 do nothing 1 1 1 reserved all other values table 527. time base selection 1 ? tbsa tbsa bit 2 1 0 table 528. time base selection 2 ? tbsb tbsb bit 2 1 0 tbsb[3] = 0 bitfield comparator selection capture selection match tb selection 0 greater or equal tcr1 tcr1 1 equal-only tcr2 tcr2 tbsb[3] = 1 action 210 do nothing 1 1 1 reserved all other values table 529. input and output pin action control ? ipaca/b and opaca/b value ipac meaning opac meaning 000 do not detect transitions do not change output signal 001 detect rising edge only match (1) sets output signal high 010 detect falling edge only match (1) sets output signal low 011 detect both edges match (1) toggles output signal 100 detect input signal = 0 on match (1) transition detection sets output signal low 101 detect input signal = 1 on match (1) transition detection sets output signal high RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 971/1740 immediate pin state control it is possible to change output signal state immediately by using psc (2 bits) and pscs (1 bit) fields. write channel match and udcm registers match registers can have their values changed using erwa and erwb fields (1 bit each). they also set their respective mrle register (see section , match recognition ). erwa can also be used to program the udcm register (see section , udcm ? user defined channel mode ). the field cmw selects where the contents of erta is copied when erwa is active (see table 531 ). if erta or ertb is a destination of an alu operation and, at the same time, the respective erwa/b field is active, the new erta value is the one written into the matcha/b register or the udcm register. 110 reserved transition detection toggles output signal 111 do not change ipac do not change opac 1. match a is used for ipaca/opaca, and match b for ipacb/opacb. table 529. input and output pin action control ? ipaca/b and opaca/b value ipac meaning opac meaning table 530. immediate pin state control ? psc and pscs psc pscs meaning 00 0 set signal as specified by opaca (see section , transition detection and pin action control ) 00 1 set signal as specified by opacb (see section , transition detection and pin action control ) 01 x set signal high 10 x set signal low 11 x don?t change signal state table 531. write matcha/b ? erwa/b field cmw value action erwa 1 0 write erta value in matcha. enable matches for matcha register (mrlea = 1) 0 0 write erta value into udcm 1 1 don?t change udcm, matcha and mrlea 0 1 reserved erwb 1 0 write ertb value in matchb. enable matches for matchb register (set mrleb = 1) 1 1 don?t change matchb and mrleb 0 0 0 reserved enhanced time processing unit (etpu2) RM0029 972/1740 doc id 15177 rev 8 clear transition/match event registers flags mrla, mrlb, tdla and tdlb (see section , er ? event registers ) indicate the state of matches and transitions detected in the selected channel, and it is possible to clear those flags using the microcode fields mrla, mrlb (1 bit each) and tdl (1 or 2 bits, depending on the format). the flags cleared by these microcode fields are the actual channel flags, and also the ones sampled into the branch logic. tdl can be one or two bits wide, depending on the microinstruction format (see section , microinstruction formats ). two-bit tdl allows independent clearing of tdla and/or tdlb. ta ble 53 3 defines the two-bit tdl field. disable matches microcode field mrle (1 bit) allows disabling matches on channel selected by chan register, for both matcha and matchb registers, by clearing their respective mrle bits. matches can be enabled for each match register using erwa and erwb fields (see section , write channel match and udcm registers ). some instruction formats have a two-bit mrle field (see section , microinstruction formats ) which allows independent disabling of matches 1 and 2, as shown in table 535 . table 532. clear transition/match event registers ? mrla/b, tdl field meaning mrla 0 = clear mrla event register, 1 = don?t change mrlb 0 = clear mrlb event register, 1 = don?t change tdl (1 bit) 0 = clear tdla and tdlb flags, 1 = don?t change table 533. independent tdla/b clear ? two-bit tdl value meaning 0 0 clear tdla 0 1 clear tdlb 1 0 clear both tdla and tdlb 1 1 do not clear tdla or tdlb table 534. disable matches ? mrle mrle meaning 0 disable matches for match a and match b 1 don?t change match enabling RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 973/1740 disable match and transition service requests microcode field mtd (2 bits) disables match and transition service requests for the selected channel. mtd does not disable link service request and host service request. mtd sets or resets register sri (for more details see section , sri ? match/transition service request inhibit latch ) and tccea (see section , tccea ? transition continuous capture enable ). predefined channel modes microcode pdcm field (4 bits) defines the channel mode (see section , channel modes ). pdcm coding is shown in ta ble 53 7 . note that pdcm bit 0 selects between single transition (pdcm[0] = 0) and double transition (pdcm[0] = 1) predefined modes. pdcm is also used to select the user-defined channel mode, defined by the channel register udcm (see section , udcm ? user defined channel mode ). table 535. two-bit mrle mrle meaning 0 0 disable match a (clear mrlea) 0 1 disable both matches (clear mrlea and mrleb) 1 0 disable match b (clear mrleb) 1 1 nop table 536. disable match and transition service request ? mtd mtd action on sri action on tccea 00 sri = 0: enable service requests for match and transition tccea = 0: disable transition captures (1) when tdla = 1 01 sri = 1: disable service requests for match and transition 10 sri = 1: disable service requests for match and transition tccea = 1: enable transition captures (2) when tdla = 1 11 don?t change 1. disables only captur es on transition events specified by ipaca. 2. enables only captures into capturea regi ster, on transition events specified by ipaca. table 537. predefined channel modes pdcm channel mode 0000 em_b_st 0001 em_b_dt 0010 em_nb_st 0011 em_nb_dt 0100 m2_st 0101 m2_dt enhanced time processing unit (etpu2) RM0029 974/1740 doc id 15177 rev 8 channel interrupt and data transfer requests microcode can issue interrupt requests, data transfer requests and global exception through circ field. for more information see section , interrupts and data transfer requests . clear link service request microcode lsr field (1 bit) is used to clear the link service request flag of the serviced channel (may not be the one selected by chan). the lsr branch condition is always cleared, but not the link service request, if another channel link was received by the serviced channel during the executing thread. see section , channel link , for more information. 0110 bm_st 0111 bm_dt 1000 m2_o_st 1001 m2_o_dt 1010 user-defined channel mode 1011 reserved 1100 sm_st 1101 sm_dt 1110 sm_st_e 1111 keep current channel mode table 538. channel and data transfer requests ? circ circ meaning 000 channel interrupt request from selected channel 001 data transfer request from selected channel 010 channel interrupt and data transfer requests from selected channel 011 channel interrupt and data transfer requests from serviced channel 100 channel interrupt request from service channel 101 data transfer request from service channel 110 global exception 111 don?t request interrupt table 537. predefined channel modes pdcm channel mode RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 975/1740 flow control microoperations etpu has jump and call microoperations to change microcode flow. besides, etpu has dispatch jump and dispatch call that can be used to implement a jump table. in call (or dispatch call ) microoperation, the return address is saved in the rar. if nested sub-routine calls are necessary, return address values have to be saved in a stack, usually implemented with diob register. flow control microoperations are also provided to repeat a given microinstruction, to finish the current thread execution, and to halt the microengine. ending current thread ? end microcode end field (1 bit) finishes current thread and allows other channels to be serviced. if end field is 0, the current instruction is completed and the thread is finished. end = 1 has no effect, and the next microinstruction is executed any mdu operation (see section , mac and divide unit (mdu) ) that could be still pending when the thread is finished is left incomplete. end also releases any semaphore locked by the engine. branch operations branch operations can be jump or call . the target address of jump or call microoperations is always immediate and absolute. branch microoperation is affected by fls field (refer to section , flush pipeline ). selecting jump or call microoperations the only difference between jump and call microoperations is that when a call is executed the value of pc or pc+1 (depending on flush, see section , flush pipeline ) is saved in the rar. the microcode field j/c (1 bit) selects whether jump or a call is executed, according to ta ble 54 0 . branch target address microcode baf field (14 bits) indicates the absolute address of a jump / call target. conditional/unconditional branch jump and call can be conditional or unconditional, depending on the bcc (6 bits) and bcf (1 bit) fields, as shown in table 541 and table 542 . bcf determines whether branch is taken when condition specified by bcc is true or false. when a branch condition uses the channel flags, the channel context is related to the channel number written in chan register. table 539. link service request negation control ? lsr lsr meaning 0 clear link service request (flag lsr) 1 don?t change table 540. jump / call selection ? j/c j/c meaning 0jump 1call enhanced time processing unit (etpu2) RM0029 976/1740 doc id 15177 rev 8 dispatch microoperation dispatch microoperation is an unconditional branch where the target address is always pc+p[31:24] (unsigned). dispatch is affected by fls field (refer to section , flush pipeline ). dispatch microoperation is defined by r/d field (2 bits, table 543 ). field r/d can also be used to define return from sub-routine (see section , return from subroutine ). table 541. branch condition inversion ? bcf bcf meaning 0 branch if condition determined by bcc is false 1 branch if condition determined by bcc is true table 542. branch condition selection ? bcc bcc meaning bcc meaning 001110 flag 0 001111 flag 1 100000 v alu flag 110000 pss channel flag 100001 n alu flag 110001 prss channel flag 100010 c alu flag 110010 ?less than? alu flag combination (signed) (1) 100011 z alu flag 110011 ?lower or equal? alu flag combination (unsigned) (2) 100100 mv mdu flag 110100 p[24] 100101 mn mdu flag 110101 p[25] 100110 mc mdu flag 110110 p[26] 100111 mz mdu flag 110111 p[27] 101000 tdla channel flag 111000 p[28] 101001 tdlb channel flag 111001 p[29] 101010 mrla channel flag 111010 p[30] 101011 mrlb channel flag 111011 p[31] 101100 lsr channel flag 111100 psto channel flag 101101 mb flag mdu flag 111101 psti channel flag 101110 fm[1] channel flag 111110 smlck semaphore flag 101111 fm[0] channel flag 111111 false all other values reserved 1. ?less than? is a signed comparison, equal to the xor between alu flags v and n; e.g., 0 < 0xffffff tests as false (0 < -1). 2. ?lower equal? is an unsigned comparison, equal to z or c; e.g., 0 < 0xffffff tests as true. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 977/1740 return from subroutine when a subroutine call or a dispatch call microoperation is executed, the return address is saved in the rar. to return from a subroutine a microoperation is available to load the contents of the rar back to the pc. fields r/d (2 bits) or rtn (1 bit, ta ble 54 4 ) can be used to return from subroutine. for r/d field, see table 543 . return from subroutine microoperation is affected by fls (see section , flush pipeline ) when field r/d is used. return execution through rtn always flushes the pipeline. flush pipeline when a branch, dispatch or subroutine return microoperation is executed, the next microinstruction can be executed unconditionally before the flow change takes effect, since microengine has a two-stage pipeline. executing the next microinstruction after a branch maximizes execution performance. this feature is controlled by field fls (1 bit, ta ble 54 5 ). when fls = 0 the pipeline is flushed, so the next microinstruction placed after a branch is decoded as nop if the branch is taken. if fls = 1, the microinstruction placed after the branch is executed, either if the branch is taken or not, as shown in figure 554 . flush also controls which value is stored in rar in a call: in case of no flush, it is the address of the branch/dispatch instruction + 2, even if rar is the alu destination of the instruction after the call; in case of a flush, it is the address of the instruction following branch/dispatch. if a branch with no flush is followed by another branch with no flush, the instructions are executed in the following order: 1. first branch 2. second branch 3. first branch?s destination instruction 4. second branch?s destination instruction, and the flow proceeds normally from then on the destination of the first branch must not be another flow changing instruction (branch, return or dispatch). similar flows apply when returns or dispatches are used instead of branches. this scheme can be used to implement quick table look-ups with a dispatch replacing the first branch, for instance. table 543. return and dispatch ? r/d r/d meaning 00 return from subroutine (see section , return from subroutine ) 01 dispatch jump 10 dispatch call 11 don?t change microinstruction flow table 544. return from sub-routine ? rtn rtn meaning 0 return with pipeline flush 1 do not return enhanced time processing unit (etpu2) RM0029 978/1740 doc id 15177 rev 8 figure 554. flush pipeline halt microinstruction halt is a microinstruction provided to implement software breakpoints (see section , software breakpoints ). note that halt is coded as a microinstruction format, not a field (see section , microinstruction formats ). the execution of this instruction puts the microengine in halt state. for more information about the implications of microengine halt state, see section , microengine halt state . halt is valid only if software breakpoints are enabled at the debug interface (signal ndedi_enable asserted). if software breakpoints are not enabled, halt executes as a nop and is treated as an illegal instruction (see section , illegal instructions ). nop microinstruction there is not a unique microinstruction with an assigned opcode to do no operation. nop microinstruction is achieved through any of the formats shown on section table 547., microinstruction formats where the user can assign to each individual field the corresponding value for ?no operation?. however, to prevent future impacts of instruction changes on object code compatibility, th e instruction value 0x 4fffffff should al ways be used for nop. illegal instructions an instruction is considered illegal if any reserved field value is used, including when the fields marked rsv in the instruction formats (see table 547 ) are assigned value 0. a halt table 545. flush pipeline ? fls fls meaning 0 flush pipeline when jump / call / dispatch jump / dispatch call / return is executed 1 do not flush pipeline when jump / call / dispatch jump / dispatch call / return is executed instr a no flush (fls = 1) flush (fls = 0 or rtn = 0) instr a branch dispatch return branch dispatch return branch/dispatch/ return executed branch/dispatch/ return executed RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 979/1740 instruction is exceptionally considered illegal when executed with software breakpoints disabled (see section , halt microinstruction ). global exception may be issued up to two microcycles after instruction fetch. the execution results of an illegal instruction on the microengine, channel logic or host interface are unpredictable, except for the halt case. if the microengine decodes an illegal instruction, the following actions are taken: a global exception is issued. flag ilf1/2 on register etpu_mcr is set to indicate this occurrence to the host. a breakpoint occurs, if ndedi is present and configured to do so. microinstruction parallelism issues this section clarifies parallelism issues that arise when two non-commutative microoperations appear in the same microinstruction. alu operations and read match registers alu operations have only one destination register, but there is one case where source selection determines destination: read match register in erta and ertb registers. in this case if alu destination is erta or ertb a conflict arises. the alu destination value overwrites the value read from the match registers. alu and spram operations p and diob registers can be selected as destination by both alu and spram (read) microoperations in the same microinstruction. since p and diob update from spram data happens after p and diob update for alu/mdu microoperations, the data read from spram remains in p or diob after an operation when one of them is specified as destination for both alu and spram microoperations in this case, the value loaded into p or diob is the one read from spram however, the alu operation is executed and its flags are updated accordingly when p or diob is destination of an spram read and also an alu source at the same microinstruction, the value before the read is used for the alu operation if diob is the alu destination and p is loaded from spram or vice-versa, no conflict occurs, and the result is the same as if operations occurred separately. all the above also applies to zero spram operations. when using p or diob as destination for alu operations and also as source for a spram write operation, the data written in spram is the one calculated by alu, which means it is possible to calculate a value and write it in an spram address using only one microinstruction. the old value of diob or the old value minus 4 (pre-decrement) is always used when diob is selected as address (indirect address mode), no matter if diob is selected as destination of either the spram or alu. for the value loaded into diob, refer to table 546 . enhanced time processing unit (etpu2) RM0029 980/1740 doc id 15177 rev 8 erta/b as alu destination and erwa/b the value in erta and ertb registers can be written in match registers of the selected channel by using fields erwa and erwb ( section , write channel match and udcm registers ). if, at the same microinstruction, erta or ertb is the destination of an alu/mdu microoperation, the value written in the match registers is the alu/mdu result. the same applies to udcm when erta is the destination of an alu operation and instruction fields erwa and cmw are active. if an alu operation occurs in parallel with erwa/b but erta/b are not the destination of an alu/mdu operation, then udcm and matcha/b receives the erta/b value. erwa/b and mrle erwa/b automatically sets the mrlea/b channel latch, respectively (see section , write channel match and udcm registers ). microinstruction fields erwa/b independently sets mrlea/b channel flags, regardless of mrle. chan assignment, read match and erwa/b when chan is a destination of an alu operation it causes a read of the capturea/b register values into erta/b. the capture registers loaded into erta/b are selected by the new chan value. the value of the capturea/b registers overwrites any read-match commanded simultaneously. if chan assignment happens with an erwa/b operation in the same instruction, the updated match register(s) belong to the new selected channel. read match and erwa/b if a read match operation is executed with erwa/b in the same microinstruction, the matcha/b registers receive the old values of erta/b, and the erta/b registers receive the old matcha/b values simultaneously, i.e.: erta/b and matcha/b swap their values. if erta/b is the destination of an alu operation at the same instruction, matcha/b gets the alu result (see section , erta/b as alu destination and erwa/b ), but the erta/b not being written still receives the old matcha/b values. table 546. diob load from spram and alu diob selected as spram read destination? diob selected as alu destination? diob load value no no diob, --diob (pre-decrement), or diob++ (post-increment) yes no spram read data (post-inc and pre-dec ignored) yes yes spram read data (post-inc, pre-dec and alu result ignored) no yes alu result (post-inc an pre-dec ignored) RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 981/1740 note: read match, erwa/b and chan assignment can be active at the same instruction. combining rules section , chan assignment, read match and erwa/b , and section , read match and erwa/b , the result is: erta/b receives the capturea/b values of the new chan value, and matcha/b of the new channel receives the old erta/b value(s). stack accesses and alu operations post-increment is ignored in a stack operation (field stc) if diob is loaded from spram: diob keeps the value read from spram. pre-decrement is ignored in a stack operation (field stc) if diob is destination of an alu operation, for diob load value, but not for diob as address. post-increment/pre-decrement remains valid in all other situations. these rules can be summarized in the following equivalent c code, and in ta ble 54 6 . diob = *diob[15:2]; // read without posinc/predec *diob[15:2] = diob; // write without posinc/predec diob = *(--diob[15:2]); // read with predec diob = *diob[15:2]; // read with posinc (ignored) *(--diob[15:2]) = diob; // write with predec *diob[15:2]++ = diob; // write with posinc (value written is before increment) src and alu/mdu operations if operation src is active (field src = 0) and register sr is selected as destination of an alu operation, the value of the alu operation prevails over the shifted value. the value of sr used as source in the alu/mdu operation is the one before the shift. semaphore lock/free and smlck branch condition when the smlck branch condition is tested at the same microinstruction of a semaphore lock or free, the condition is evaluated after the semaphore action (either free or lock) is taken. dispatch and spram read when the most significant byte of p is read from spram (read 8 msb bits or 32 bits) and a dispatch instruction is executed simultaneously, the dispatch target address is calculated upon the p value before the read. chan assignment, psc/pscs, and clear mrlea/b, mrla/b, tdla/b when clear mrles, mrla/b or tdls is done and a chan assignment is done at the same time, the flag selected by the old chan value is cleared in the channel, but the branch conditions receive the state of the flags selected by the new chan. when a pin action is commanded through pcs/pscs and a chan assignment is done simultaneously, the output signal affected is selected with the old chan value. microinstruction formats see table 547 . enhanced time processing unit (etpu2) RM0029 982/1740 doc id 15177 rev 8 table 547. microinstruction formats format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a1 0 0 0 imm[15:13] imm[7:2] imm[23:16] imm[12] rtn imm[11:9] imm[1:0] t2d imm[8] 0 0 a2 t4abs t2abd ccs ab se ab de 0 1 a3 aluop ccsv aluopi [3:2] as/ce aluopi [1:0] 01 0 a4 flc shf src ccs rsv flc [1:0] ab se ab de 1 b1 1 0 0 end cin binv t4bbs rw p/d ccs aid[7:0] (global param) b2 1 zro aid[6:0] (channel param) b3 0 0 0 stc ab se ab de rsv 1 1 b4 0 0 1 0 ccsv 1 as/ce aluop b5 fl 0 sext smpr b6 1 rsv src ab se ab de b7 0 1 1 end shf tdl psc mrla erwa mrlb erwb abse abde ccs mrle pscs c1 0 1 0 0 end opaca opacb tbsa tbsb lsr pdcm c2 1 ipaca ipacb d0 1 1 0 0 mrle 0 circ psc fls rw pscs flc circ[1:0] r/d 0 p/d rsiz zro aid[6:0] (engine param) d1 1 aid[7:0] (global param) d2 1 zro aid[6:0] (channel param) d3 1 1 1 1 mrle 1 stc 1 1 0 0 rsv d4 fl 0rsv smpr d5 1 1 0 1 mrle rsv cmw mtd tdl rw tdl mrla erwa mrlb erwb 0 p/d rsiz aid[7:0] (global param) d6 1 zro aid[6:0] (channel param) d7 1 1 1 1 mrle 1 stc 1 1 0 1 rsv d8 fl 0rsv smpr d9 1 1 0 0 mrle 0 rw 1 p/d rsiz zro aid[6:0] (engine param) RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 983/1740 e1 1 1 1 bcc[5] j/c bcc[4:0] fls rw bcf baf[13:0] 00 p/d stc e2 01 aid[2:0] e3 fl 10 rsv smpr e4 0 11 1 rsv f1 rsv 1 rsv 111 rsv format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 alu operations channel control/config operations ram operations flow control operations table 547. microinstruction formats (continued) format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 enhanced time processing unit (etpu2) RM0029 984/1740 doc id 15177 rev 8 24.5.10 test and development support overview following sections describe several features available to support development and test. most debug features, described in section , development support features , are accessible through a separate debug bus, and are not available through registers in the standard etpu memory map. the details of the access to this interface are mcu-dependent, but a separate ip block, called ndedi, is provided so that these features are accessible by a nexus interface. ip-bus green line device debug request can also be used to put microengines in halt state. conditions for the assertion of this line are also mcu-dependent. section , test support features , describes embedded test features: the multiple input signature calculator (misc) is an scm test feature accessible through registers etpu_mcr and etpu_misccmpr (see section 24.4.2, system configuration registers ). misc allows scm test ?on the fly, that is, while etpu is running, with no impact on etpu functionality or performance. development support features internal debug interface and nexus class 3 support etpu provides an internal debug interface that exports real-time microengine states and values, including breakpoint/watchpoint information. it also provides inputs for breakpoint request from other blocks or outside mcu. ndedi is an ip block designed to support nexus functionality for the etpu. when internal debug interface is connected to an ndedi block, the mcu can provide nexus class 3 debug interface. nexus is a development support external interface defined by the ieee standard isto 5001-1999 . some of the next subsections describe debug features provided by the internal debug interface combined with the ndedi block. ndedi can be replaced by other block providing a different programming interface, such as a register debug interface, for instance. microengine halt state halt is a microengine state where it suspends execution during a thread, or does not start executing a scheduled thread from idle state. while idle state is entered from end execution without any other scheduled thread, microengine enters halt state by any of the following events: execution of the halt microinstruction (software breakpoint). external halt request through the debug interface (includes nexus breakpoint request via evti input pin (see section , internal debug interface and nexus class 3 support ). the other engine enters halt state and they are configured to halt simultaneously (bit htwin is asserted via nexus interface). ipi green line device debug request assertion and ndedi register ndedietpux_dc field cbi = 1. if same register?s field cbt = 1, microengine halts at the next time-slot boundary, if cbt = 0 it halts immediately. as a particular case, microengines come halted out of reset if device debug request is asserted, since cbi reset value is 1. microengine does not execute out of reset, either in halt (device debug request RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 985/1740 asserted) or idle state (device debug request negated), but halt enables several other features (see below). occurrence of any of the hardware breakpoint conditions. see section , hardware breakpoints , for details. execution of a single-step microinstruction: microengine returns to halt state after executing a single microinstruction while in halt state. see section , single-step execution , and section , forced microinstruction execution , for details. when microengine enters halt state, it automatically triggers the following actions: suspends input signal sampling and filters (respective engine channels only), if signal ndedi_stop_pins is asserted at the debug interface. releases the spram arbitration for host or cdc accesses, no matter if microengine was halted in the middle of a dual-parameter (back-to-back) access. stops tcr1/2 clocks of the respective engine, if signal ndedi_stop_tcr is asserted at the debug interface. if the other engine is also in halt state or stopped, allows turning etpu_mcr vis bit to 1. if all halt conditions are cleared when vis = 1, microengine(s) keep on halt state until vis = 0, when it automatically exits halt state, except on single-step (see section , single- step execution ), so that single-step execution is ignored while vis = 1. mdu continues executing until it finishes any ongoing operation even if microengine is in halt state, except when the halted instruction is an end. there are two kinds of halt state, depending on the previous microengine state when halted: 1. halt_idle , if the engine was not executing a thread when halted; the engine cannot leave halt_idle to fetch instructions, so one cannot single-step or follow a program flow; it can, however, execute forced instructions (see section , forced microinstruction execution ). 2. halt_exec , if the engine was executing a thread when halted. the engine can single- step and continue a program flow from halt_exec. when microengine exits halt state, any dependable action is suspended and, if exiting halt_exec, the instruction pointed by the pc is fetched, while the instruction already fetched before halt is executed. note that both the pc and the prefetched instructions can be modified during halt state, with a forced execution of a branch instruction (see section , forced microinstruction execution ). enhanced time processing unit (etpu2) RM0029 986/1740 doc id 15177 rev 8 hardware breakpoints microengine can enter halt state through a command from the debug interface, configuring a hardware breakpoint. hardware breakpoints can halt the microengine on specific conditions, listed below. these conditions depend on ndedi configuration. chan register assignment (only by microcode, not by time slot transition). spram read and/or write to a given address and/or write data. the breakpoint is always qualified by the spram address, but the following variations are allowed: ? break on write only, read only, or read-and-write. ? break on higher-byte write data value, lower 24-bit write value, full word (32-bit) write value, or regardless of data. break on read data is not supported. pc (program counter) value. beginning of a thread with a host service request pending. beginning of a thread with a link service request pending. beginning of a thread with a match service request pending. beginning of a thread with a transition service request pending. end of a thread. illegal instruction execution. all these conditions can also be qualified by the value of the chan register. on any of these conditions, halt of one microengine does not depend on the halt of the other, unless the other engine is configured to do so, via nexus interface. occurrence of any of these conditions halts the microengine, i.e., the conditions are logically ?ored? together, and they can be individually enabled. while in halt state, the microengine can also execute any forced microinstruction not in the normal program flow (see section , forced microinstruction execution ) or, if in halt_exec, in single-step (see section , single-step execution ). there are situations when requests for stopping an engine, breakpoint and service can occur simultaneously. breakpoint requests always prevails over a stop request (etpu_ecr bit mdis = 1 or device debug request = 1). when the etpu is idle: stop request prevails over service request if there is not a hardware breakpoint request; a hardware breakpoint request leads to debug mode immediately if there is no service request, and after tst if there is service request (regardless of stop requests). the rules above are summarized in the ta ble 54 8 , showing the destination state of the microengine in each situation. table 548. breakpoint, stop and service requests resolution from idle breakpoint request mdis service request final state no 0 0 idle no 1 0 stop no 0 1 tst no 1 1 stop yes 0 0 halt_idle yes 1 0 halt_idle yes 0 1 tst (1) yes 1 1 tst (1) 1. breaks after tst, if signal ndedi_sync_break is still asserted. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 987/1740 when a thread is ending, it goes to idle or tst only if there is neither a hardware breakpoint request (signal ndedi_thread_break negated) nor a request to stop (mdis = 1 or device debug request = 1). when thread is ending and there are simultaneous hardware breakpoint (ndedi_thread_break active) and stop (mdis = 1 or device debug request = 1) requests, hardware breakpoint prevails and the engine enters debug mode (halt_idle state). if the engine entered debug mode after a thread finished (halt_idle state) and a ?go? command comes from the debug interface, the engine state machine goes to idle and the rules above apply. it means that if a ?go? is issued in halt_idle state with mdis = 1, the engine goes to idle for one microcycle and then stops (if mdis or device debug request keeps asserted and there is no other breakpoint request). note: hardware breakpoint requests are ignored for the first microinstruction executed when microengine leaves halt. hardware watchpoints debug interface allows watchpoints on the same conditions available for hardware breakpoints (see section , hardware breakpoints ). software breakpoints a software breakpoint occurs when microengine executes a halt microinstruction. any number of software breakpoints can be set in code, usually replacing an active microinstruction. like any other microinstruction, halt increments the pc and pre-fetches the next instruction. so, before the halt state is suspended, if the original program flow must be followed, the original instruction at the halt address must be executed, regardless if the software breakpoint is removed (replacing halt by the original microinstruction) or not. the following is the procedure to resume execution from a software breakpoint: 1. restore the original instruction in scm (replace halt). 2. force a jump with flush to the original instruction (see section , forced microinstruction execution ). 3. if the software breakpoint must be kept: single-step and replace the original instruction with a halt. 4. let the flow continue, issuing a go command (leaving halt state). special care must be taken if halt is followed by another halt, and the second halt is removed when microengine was halted by the first one. in this case, replacing the second halt with the original microinstruction is not enough to remove the second breakpoint, because the second halt was already prefetched and would be executed anyway when halt was suspended. the debugger must also do a forced execution of unconditional branch with flush to the original microinstruction address. that will clear the pipeline, replacing the prefetched instruction with a nop, and load pc with the address of the removed breakpoint. so, when halt state is suspended, the original microinstruction will be fetched while nop is executed, and program flow continues normally from then on. note: a halt instruction placed after a no-flushing branch, dispatch or return may be a problem from the debugger application standpoint: after the halt is executed, the etpu debug interface informs the address of the branch/dispatch/return destination, and the debugger application has no direct way to identify which halt instruction was executed, if multiple halts lead to the same address. this can be solved if the debug support block (ndedi) has a register holding the address of the last instruction executed, otherwise one should forbid non-flushed halt instructions. enhanced time processing unit (etpu2) RM0029 988/1740 doc id 15177 rev 8 software breakpoint setting and removal is possible only with scm ram implementations or rom implementations with scm ram emulation (see section , scm emulation ). there is only one way of inserting software breakpoints into scm ram: writing bit vis = 1 in register etpu_mcr, and then accessing scm as an ordinary ram from the slave bus. this can be done only if both engines are halted or stopped. single-step execution when microengine is already in halt_exec state, it can run the next microinstruction in the normal program flow and get back to halt state. pc is incremented, or assigned the baf value in a branch with satisfied condition. note that the executed instruction was already prefetched in the instruction pipeline, and a new microinstruction is fetched during its execution. the prefetched instruction may be cleared during halt state by the forced execution of a branch with flush (see section , forced microinstruction execution ), making single-step execute a nop instead of the next instruction in the program flow. single-step execution is controlled by the debug interface, and is a feature available from nexus if etpu is connected to the ndedi block.the single-step execution of a nop instruction can be useful to control input signal sampling and filtering, if signal ndedi_stop_pins = 1 at the debug interface. single-step does not happen if vis = 1. forced microinstruction execution when microengine is already in halt state (either halt_idle or halt_exec), it can run forced microinstructions through the debug interface. this feature is available from nexus if etpu is connected to the ndedi block. the microinstruction, specified by the user, is not fetched from scm and comes directly from the debug interface. mdu start commands issued by forced instructions are executed, and the mdu runs the operation until the end, independently of the halt state. the microinstruction field end is ignored. during forced execution of any instruction except branches, returns and dispatches, the pc does not change, and the prefetched instruction in the pipeline is bypassed, but not discarded. when halt state is suspended, the prefetched instruction is executed and the instruction pointed by the pc is prefetched in parallel (two-stage pipeline). forced execution of a branch, dispatch or return loads the pc with the baf field (if branch condition is satisfied), pc+p or rar, respectively. if branch condition is not satisfied, pc value stays unaltered. the flush control (field fls) also works, so that a successful forced branch with flush replaces the prefetched instruction with a nop. so, to clear the instruction pipeline during halt, all one has to do is an unconditional branch to the desired address with flush. halt instructions must not be executed as forced. forced operations that depend on the serviced channel are unpredictable when executed in halt_idle. microengine register access etpu provides no direct access to microengine and channel registers from the slave bus or any other interface. however, these registers can be read and written in halt state by executing forced microinstructions (see section , forced microinstruction execution ). immediate data microinstructions may be used to set register values. some registers are not selectable for immediate data destination, so intermediary register(s)?notably p?may have to be used to carry the desired new value to the target register in two or more microinstructions. usually the previous values of intermediary register(s) must be previously saved and restored after the whole operation. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 989/1740 similar procedures apply for register reads: their contents must be dumped to spram, where they can be read from the slave bus. microengine flag access microengine halt state allows reading the branch conditions flags through forced microinstructions or, more easily, through the ndedi register ndedi_enginex_cfsr. flag conditions set by the user are seen by microengine for the next microinstruction execution. the flag set options are limited by the possibilities of forced microinstruction execution. if the etpu runs (not single-stepping) after exiting the halted state, the conditions modified during halt may remain only for the first microcycle after the halted state. after the first microcycle, branch conditions are altered only according to their regular update scheme. microengine stall microengine can get into a stall state, attending a request from a debug interface signal assertion. the reason for a stall request from ndedi (or from any other debug support block) should be a temporary lack of resources, for instance queue full. during stall the microengine suspends execution, but all the other engine logic continues operating: time bases, angle logic, channel logic, input sampling and filters. stall differs from halt, not enabling any of the debug features that halt enables (see section , microengine halt state ). it also does not break an atomic microengine access, unlike halt. the microengine can be stalled when idle and from the moment tst ends, before executing the first thread microinstruction, until just before the last thread microinstruction is executed. stall requests are ignored in any other occasions. microengines in a dual-engine system can be independently stalled. if a forced end is issued when microengine is in stall coming from execution, the end is executed only when the microengine resumes execution from stall. scm emulation if scm is implemented as rom, an external ram may be used to replace it, allowing code patching and software breakpoint setting for debugging purposes. scm rom replacement by emulation ram is mcu-dependent. the scm may even be divided into a rom part and a ram part. in this case, both microengines can run code from both rom and emulation ram. it is possible to make one engine run code from ram and the other from rom, by using different entry tables. the scm visibility conditions also apply to emulation ram. all scm implementations, either ram, rom or emulation ram, are external to the etpu block. etpu provides a signal to enable the switching between external scm banks. the conditions for this switching are: 1. both engines stopped 2. vis bit = 0 note that these conditions also stop the clocks of the scm interface and misc logic. test support features scm test ? multiple input signature calculator the multiple input signature calculator (misc) comprises special hardware that sequentially reads all scm positions and calculates, in parallel, a 32-bit signature from a 32- input crc signature calculator with the following polynomial: enhanced time processing unit (etpu2) RM0029 990/1740 doc id 15177 rev 8 1 + x 1 + x 2 + x 22 + x 31 a complete description of the signature calculation procedure can be found in section 24.7.4: misc algorithm . once started by the host the misc runs continuously, restarting after the completion of each cycle, when it sets the etpu_mcr flag scmmisc (see section , etpu_mcr ? etpu module configuration register ). the average time for a misc calculation can be measured by checking scmmisc state at regular intervals, incrementing a counter and clearing scmmisc if it is set. misc accesses to the scm array are executed if none of the engines is accessing the scm, to avoid degradation of the microengine performance: it happens while no channel is being serviced. an ongoing misc operation can be aborted by writing 0 to scmmisen. the host must load the register etpu_misccmpr (see section , etpu_misccmpr ? etpu misc compare register ) with the expected value to be found at the end of the misc cycle, and then start the signature calculation writing bit scmmisen = 1 in register etpu_mcr (see section , etpu_mcr ? etpu module configuration register ). misc zeroes the signature accumulator and starts reading scm data and calculating the signature. after last scm position is read, misc compares the value in signature accumulator against the value in etpu_misccmpr: if there is a mismatch misc stops, a global exception is issued and the bit scmmisf in register etpu_mcr assumes value 1. if no mismatch is found, misc repeats the procedure automatically. when signature is being calculated, scm address starts at the last scm address and counts down to 0. the conditions for executing a misc operation are (see also ta ble 46 7 ): both microengines in idle state (no channel is being serviced) or stopped, in any combination (e.g., engine 1 idle with engine 2 stopped) etpu_mcr bit vis = 0 etpu_mcr bit scmmisen = 1 note that misc can run regardless of scm implementation type (ram or rom). if scmmisen = 0 or vis = 1, the misc logic stays at its initial state, with address counter pointing to the last scm position and accumulator reset. performance monitoring features idle counter the idle counter register etpu_idle (see section , etpu_idle ? etpu idle register ) continuously counts microcycles in which the microengine is not busy with channel service. it can be used to measure the microengine utilization by rating the count measured during a period of time to the number of microcycles contained in the period. the idle counter does not count microcycles when the engine is stopped, or is in tst or halt states. 24.6 initialization/application information 24.6.1 configuration sequence after initial power-on reset the etpu remains in an idle state (as) , requiring initialization of several registers before any function can begin execution. also, if the scm is implemented RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 991/1740 in ram, it should be initialized with the etpu application code prior to configuring the etpu. configuration procedures are summarized as follows: if scm is implemented as ram, load the etpu application code (see section , scm access ). initialize the scm misc logic (optional, see section , scm test ? multiple input signature calculator ). initialize the etpu time base configuration registers (etpu_tbcr) to setup: ? tcr1 and tcr2 prescalers and clock sources. ? select digital filtering mode. ? tcrclk signal filter control. ? angle mode operation (if necessary). initialize the etpu engine configuration register(s) (etpu_ecr) to setup: ? entry table base. ? filter prescaler clock control. initialize etpu stac configuration regist er(s) (etpu_redcr), if one needs to setup tcr1/2 resource client/server operation. write to the channel configuration registers (etpu_cxcr) to choose the function to be performed by each channel, and its parameter base address. write to channel status control register (etpu_cxscr) to choose among the possible variations within the function flow (fm bits). write to spram for parameter initialization of each configured channel. write to register(s) etpu_wdtr if one needs to enable and setup the watchdog(s) mode and timeout. write to channel x host service request registers (etpu_cxhsrr) to initialize the active channels. (at) write to the channel interrupt enable register (etpu_cier) if interrupts are to be enabled from the appropriate channels. likewise for data transfer requests (etpu_cdtrer). this can also be done through etpu_cxcr. write to channel x configuration registers (etpu_cxcr) to enable each channel by assigning it a high, middle, or low priority (cpr field). at monitor the host service request registers (etpu_cxhsrr) for completion of initialization. write etpu_mcr bit gtbe = 1 to start tcr1/tcr2 time base counting at same time in both engines (may be done before or never, depending on the particular application and use of red line bus). see section 24.7.2, initialization code example . as. except when device debug request is asserted on power-on reset: in this case, the microengines wake-up in halt state. at. this operation is done before enabling active channels to avoid time events happening before the channel initialization. enhanced time processing unit (etpu2) RM0029 992/1740 doc id 15177 rev 8 24.6.2 reset options hardware reset hardware reset is achieved by assertion of device synchronous reset. both engines and common logic is reset, and even the system configuration and global channel registers assume their reset values. note: all etpu input clocks must pulse during reset so that both engines are reset, even if they are in module disable or stop mode. software reset etpu has no software reset. to abort infinite microcode loops, the force end mechanism must be used (see field fend in section , etpu_ecr ? etpu engine configuration register ). 24.6.3 multiple parameter coherency methods follows a description of two methods for coherent transfer of multiple parameters between host and etpu. both methods involve the use of two parameter areas: the transfer parameter area (hereafter called tpa), which is the spram area directly accessed by the host for reads and writes, and the permanent parameter area (hereafter called ppa), which are the spram positions where channel parameters are normally accessed by the function microcode. note that parameters in either tpa or ppa do not have to be in sequential addresses. tpas and ppas allocation are completely defined by the application, and there may be any number of them, independently of the channels. the methods described here are not the only solutions for the coherent transfer problem, and both can co-exist in etpu and even used in combination. also note that for transfers of a pair of parameters, the coherent dual-parameter controller is faster and have less impact on both etpu and host performance. that said, the methods are: transfer service a microengine thread transfers, upon host service request, data from/to a tpa to/from a ppa. coherency is guaranteed by the fact that a thread is atomic with respect to other threads in the same engine, and so are its transfers. if parameters in ppa are shared by both engines, hardware semaphores have to be used to access them. mailbox for host to etpu transfers, the microcode checks a flag, set by the host, indicating the existence of new parameter data in the tpa. it can, then, either access tpa data directly or copy it to the ppa. for etpu to host transfers, when microcode changes ppa, it copies them to the tpa and flags updated tpa data to host, possibly using an interrupt or a data transfer request. the mailbox flag is reset when data is copied: by the etpu microcode, when it transfers tpa to ppa (possibly followed by an interrupt); by the host, when it reads data from the tpa. this indicates that tpa is free for another transfer. transfer service has the advantage of separating the task of data transfer from the functional service thread that accesses the parameters, with less impact to the latter. compared to the mailbox method, however, it has bigger average latency, because the transfer service thread has to contend for a time slot to execute. this latency can be minimized if transfer service thread is assigned to a separate channel with higher priority, but even so it does not guarantee that ppa is updated before the next execution of the functional thread that uses it. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 993/1740 mailbox method, on the other hand, makes the functional thread check for the existence of new data (host to etpu). it does not have to be responsible for the transfer, though: it may access the tpa directly, and a transfer service can then be used to copy data from tpa to ppa. 24.6.4 programming hints and caveats atomic dual access after a call, return a dual, back-to-back parameter access is not atomic after a call, a jump, or a return if they occurred in parallel with an odd spram access. it is safer to make a pair of parameter accesses that must be coherent begin at the second instruction after a call/jump/return. resource polling the use of polling while waiting for a condition or a resource (except semaphore lock) should be avoided in order not to hang the microengine in long loops. this general programming guideline is greatly enforced in etpu, as a thread cannot be preempted for any reason. safer polling, albeit with long and indeterministic latency, can be obtained if one issues a channel link to itself and terminates the thread. the microengine is then free to other tasks, and the next poll happens at the next time the channel is serviced. this mechanism can be combined with finite (timed out) loops for better latency. changing channel function, parameter base, or entry table scheme channel function, parameter base address and entry table scheme are determined by the etpu_cxcr fields cfs, cpba and etcs. they cannot be changed when the channel is enabled. if the channel is disabled first, one may still have service requests from the previous function, so before the channel is enabled again one must be sure that: the first thread executed in the new function is the initialization one. the initialization thread of the new function clears any previously pending service request. follows a safe procedure for function changing: 1. disable the channel (write etpu_cxcr field cpr = 00). 2. change the function configuration (etpu_cxcr fields cfs and/or cpba and/or etcs). 3. request the initialization thread, writing etpu_cxhsrr with the initialization hsr (channel still disabled). 4. enable the channel (write etpu_cxcr field cpr > 0); the initialization hsr is serviced before any other formerly pending service requests, clearing them. checking and clearing interrupts of a stopped engine an engine may be stopped with interrupts (or dma requests) pending. this includes the case when the engine?s mdis bit is set and a thread is still running: the thread will complete execution, possibly issuing an interrupt or dma request before the engine stops, setting the stf bit. as soon as the engine stops the channel registers become inaccessible, issuing bus errors when accessed. interrupts and dma requests can still be checked and cleared through the global channel registers, though. dma requests can also be cleared by the hardware handshaking with the dma controller when the engine is stopped. enhanced time processing unit (etpu2) RM0029 994/1740 doc id 15177 rev 8 24.6.5 estimating worst-case latency reliable systems are designed to work under worst-case conditions. this section explains how to estimate worst-case latency (wcl) for any etpu function in any system. the appendix covers the following topics: introduction to worst-case latency using worst-case latency estimates to evaluate performance priority scheme details used in wcl analyses first-pass wcl analysis second-pass wcl analysis the first-pass wcl analysis is based on a deterministic, generalized formula that is easy to apply. because of the generalizations in the formula, the first analysis result is almost always much worse than the real worst case. if the desired system performance is within the limits of this first analysis, then no further analysis is required; the system is well within the performance limits of the etpu. if the desired system performance exceeds that indicated by the first analysis, the second-pass wcl analysis should be applied. the second-pass analysis is not a generalized formula, but rather uses specific system details for a realistic worst-case estimation. introduction to worst-case latency note: in this appendix the latency calculation and examples refer to old tpu functions such as pwm, dio etc. these functions use single action channels which have single transition and single match functionality. they are not optimized for the etpu hardware enhancement which support various double action modes. these examples are for reference only. new etpu functions which are optimized for the new hardware will impose different latency calculations. worst-case latency for a channel is the longest amount of time that can elapse between the execution of any two function threads on that channel. for example, if in a particular system, channel 5 is running pwm, the worst-case latency for channel 5 is the longest possible time between the execution of two pwm threads. the worst-case time includes the time the execution unit takes to execute threads for other active channels, and other delays described later in this section. refer to figure 555 . figure 555. worst-case latency for pwm additional channel threads and other delays. worst-case latency for channel 5 pwm thread executed for channel 5 next pwm thread executed for channel 5 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 995/1740 worst-case latency for a channel depends both on the function running on that channel and on the activity on other channels. since the 32 etpu channels must all share the same execution unit, execution speed of a particular function varies with each system. the pwm thread response is faster if there are no other active channels than if other channels are also active. in addition, changing the priority scheme and channel number assignments can change performance for a function even if the same set of functions are still active. each function is divided into treads, as shown in figure 556 (see also section 24.5.1, functions and threads ). the etpu microengine executes one thread of a function at a time. for example, the microengine might execute thread 1 of pwm, then thread 3 of dio, then thread 2 of pwm, then thread 2 of sm, and so on. the amount of time the etpu microengine grants a function to execute a thread varies with the number of microcode instructions in the thread. since there is only one etpu microengine (in each etpu engine), the etpu cannot actually execute the software for multiple functions simultaneously. however, the hardware for each of the channels is independent. this means that, for example, all 32 channel signals can change thread at the same moment, provided that the function software sets up the channel hardware to do so beforehand. with host cpu code, the system designer assigns functions to channels and initializes the functions. after initialization, functions typically run without host intervention, except for etpu channel interrupts to the host to give or receive information. most functions can run continuously with periodic servicing from the etpu microengine. as required, the channels request service from the etpu microengine, and the etpu scheduler determines the order in which the channels are serviced. worst-case latency for a channel can be derived from the details of the priority scheme that the scheduler uses (see section 24.5.3, scheduler ). figure 556. function threads dio function threads pwm function threads sm function threads s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 s1 s2 s3 s4 enhanced time processing unit (etpu2) RM0029 996/1740 doc id 15177 rev 8 using worst-case latency estimates to evaluate performance once wcl is found for a channel, the user must determine how to use this number to analyze performance. to analyze the performance of a channel running the pwm function, for example, some information about what happens in each thread is necessary. the following example refers to old tpu pwm function, which is not optimized to the etpu enhanced hardware. for pwm, thread 1 is the initialization thread, and threads 2 and 3 are used during normal function execution. (pwm threads 4, 5, and 6 are for special modes and will be assumed to be unused on channel 5). thread 2 writes a time into the channel 5 match register and performs other operations that will cause the channel 5 signal to go from low to high at the time indicated in the match register (match time). at match time, the signal goes high and channel 5 requests service from the etpu microengine to execute thread 3. thread 3 writes a time into the channel 5 match register and performs other operations that will cause the channel 5 signal to go from high to low at match time. at match time, the signal goes low and channel 5 requests service from the etpu microengine to execute thread 2. a pwm wave is kept running on the system by the etpu executing thread 2, then thread 3, then thread 2, then thread 3, and so on. since the definition of worse-case latency assumes a fully loaded running system, initialization threads are not part of worst-case calculations. for the channel 5 example, the two pwm threads in figure 555 are thus the two normal running threads, threads 2 and 3. figure 555 does not define which thread is thread 2 and which is thread 3. since the worst- case latency derived from the first-pass analysis is the worst case between any two threads (not counting initialization threads), it is safe to say that the worst-case latency shown in figure 556 represents both the worst-case high time and the worst-case low time. notice in figure 555 that worst-case latency is drawn from the end of the execution of the first pwm thread to the end of the execution of the next pwm thread. it is drawn from end to end because the microcode instructions that make up the threads control the channel hardware. to make sure that all the microcode instructions needed to change the pin thread have been executed, it is necessary to include the execution time of the second thread. thread information for each function is found in the programming notes for individual tpu functions. priority scheme details used in wcl analysis the user assigns functions to channel numbers and gives each active channel a priority level of high, middle, or low. the scheduler uses the channel number and channel priority level to determine the order in which to grant service. the scheduler allocates time slots to specific priority levels of high, middle, or low. one function thread is executed in each time slot. the length of a time slot varies according to the length of the executing thread. when fully loaded, the scheduler always assigns time slots in a seven-slot sequence (see figure 557 ). after a seven-slot sequence is completed, another seven-slot sequence begins (see figure 558 ). note that in etpu, when no service request exists, the scheduler goes to thread 1, but wcl calculation considers full load. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 997/1740 figure 557. time-slot sequence this sequence scheme gives higher-priority channels more service time than lower-priority channels. high-priority channels are allocated four of seven time slots, middle-priority channels are allocated two of seven time slots, and low-priority channels are allocated one of seven time slots. figure 558. multiple time-slot sequences priority passing if no channel of the priority level assigned to the time slot is requesting service, the etpu scheduler can pass priority to other levels. if no high-level channel is requesting service during a high level time slot, a middle-level channel is granted service; or, if no middle level- channel is requesting service, a low-level channel is granted service. if no middle-level channel is requesting service during a middle-level time slot, a high-level channel is granted service; or, if no high-level channel is requesting service, a low-level channel is granted service. if no low-level channel is requesting service during a low-level time slot, a high-level channel is granted service; or, if no high-level channel is requesting service, a middle-level channel is granted service. if no channel is requesting service, the time slot sequence is reset to state 1 and the scheduler idles until a request is received. priority passing is implemented in hardware and does not contribute to worst-case latency. time-slot transition after each time slot, the etpu must prepare for the next time slot. this preparation time between each time slot is called a time-slot transition. see section , time slot transition . time-slot transitions can take from six up to ten system clocks. h m h l h m h time slot transitions (10 cpu clock cycle each) time slots of varying lengths h m h l h m h new 7-slot sequence h m h l h m h h m h new 7-slot new 7-slot sequence sequence enhanced time processing unit (etpu2) RM0029 998/1740 doc id 15177 rev 8 channel number priority if more than one channel of a priority level is requesting service, the lowest numbered channel is granted service first. for example, if channels 0, 5, and 9 are all high-level channels requesting service during a high time slot, channel 0 is granted service first. continuing this example, if channel 0 requests service again immediately after being serviced, it is not serviced again until channels 5 and 9 are serviced. this scheme is implemented so that continuously-requesting low numbered channels do not take all the time on the etpu execution unit and leave no time for other channels. the scheduler uses registers to keep track of which channels have been serviced and which require servicing. each channel has two register bit: a service request register (srr) and a service grant register (sgr). the srr is set when a channel requests service. after the channel has been granted service, the sgr is set and the srr is cleared. sgrs are not cleared individually by channel, but rather as priority level groups. the clearing of a group of sgrs begins a new cycle for that priority level. an sgr group is cleared on the condition that a channel of that priority level has just been serviced, and no other channel of that priority level is requesting service (has a set srr) and has not been granted service (has a clear sgr). for example, if a middle-priority channel has just been serviced (either in a middle-priority time slot or a high or low-priority time slot gained by priority passing), the srrs and sgrs of all middle-priority channels are compared. if there is no middle-priority channel with its srr set and sgr cleared, the scheduler clears all middle-level sgrs. if there is a middle- level channel with its srr set and sgr cleared, the scheduler does not clear the sgr group, and the requesting middle-level channel is serviced on the next middle-level time slot (or possibly sooner by priority passing). spram collision rate most function threads read or write to the etpu spram at least once. because both the etpu microengine and host can access the spram but not at the same time, the microengine may suspend execution during the spram access while waiting for the host to finish accessing the spram. at other times the host may wait for the microengine. wait states can take up to two system clocks, when the host accesses the spram directly, without using cdc. microengine(s) wait-states must be added into the worst-case latency calculation. the system designer should estimate the percentage of spram accesses in the system that will result in microengine wait-states. this percentage is called the ram collision rate (rcr). in each collision with direct host accesses to the spram the microengine(s) wait for two system clocks. in etpu the coherent dual-parameter contro ller (cdc) may also access the spram for atomic transfers of two parameters. etpu microengine may wait on this operation (if it is in service time) until the transfer is complete. cdc always transfers two parameters, making four consecutive accesses (read, write, read, write) of one system clock each. the system designer should estimate the percentage of spram accesses in the system that will result in a microengine wait due to coherent transfer, and multiply it with the average number of system clocks the microengine waits for each transfer. this percentage is called coherent parameter collision rate (cpcr). in addition, microengine to microengine multiple parameter coherent communication, using the hardware semaphores, may hold one microengine which waits to lock the semaphore while the other microengine is holding it. this waiting is due to a software loop, not hardware wait-states. note that single parameter access of one microengine does not affect the timing of the other microengine due to spram time interlace. this implies that single parameter RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 999/1740 microengine to microengine communication does not affect the performance. the microengine which waits for the semaphore will loop until it is freed by the other microengine. this time depends on the etpu application. the system designer should estimate the percentage of microengine to microengine coherent parameter communication that will result in etpu semaphore loops, and multiply it with the average number of system clocks the microengine loops for each such transfer. this percentage is called ccr (communication collision rate). a 100% collision rate for a system is the theoretical worst case. in many systems, however, the rcr, cpcr and ccr would be very low, sometimes even near 0%. this is because the etpu is an independent processor capable of servicing most function needs, so that the host rarely needs to access the etpu parameter ram. also coherent microengine to microengine communication of more than one parameter may be rare. to find a realistic rcr, cpcr the system designer should evaluate the host code and find the percentage of time it accesses the etpu parameter ram with or without using the cdc. this percentage gives a good rcr and cpcr. the etpu application provides a good estimation of ccr. note: the programming practice of polling a fl ag in the etpu spram causes a ve ry high rcr and should be avoided in high-performance systems. after the collision rate for a system is found, it can be applied to the wcl calculations for each channel. the system designer can use the collision percentage and the number of spram accesses (with and without semaphores) to estimate the etpu loop time for a function. note that in old tpu functions cpcr and ccr are both zero. the estimation of etpu wait time is as follows: variables: n1 = number of simple ram accesses in the longest thread rcrwait = maximal system clocks wait time for simple ram collision = 2 cpcrwait = average system clocks for coherent parameter transfer (using cdc). n2 = number of etpu-etpu semaphore ram accesses in the longest thread ccrwait = average system clocks for microengine-microengine communication transfer. estimated wait time: function etpu maximal wait time = n1 * (rcr * rcrwait + cpcr * cpcrwait) + n2 * ccr * ccrwait first-pass worst-case latency analysis following is the first-pass calculation of worst-case latency for a channel. remember that this analysis uses generalizations that usually produce a result much worse than the real worst case. if the worst-case result from the first analysis is too long for the desired performance, use the second analysis for a more realistic worst-case analysis. worst-case assumptions and formula to estimate worst-case latency for a channel, assume this worst-case condition: the channel has just been serviced in a time slot of its priority level, and all other channels in the system are continuously requesting service and have cleared sgrs. the worst-case latency is the time from the end of the channel?s service until the end of the channel?s next service. see figure 559 . enhanced time processing unit (etpu2) RM0029 1000/1740 doc id 15177 rev 8 figure 559. first-pass worst-case latency to estimate worst-case latency: find the worst-case service time for each active channel. using the h-m-h-l-h-m-h time-slot sequence, map the channels that are granted for each time slot. add time for six-clock time-slot transitions. finding the worst-case service time for each active channel a table for etpu functions should list the longest threads (not counting initialization threads) for the functions, and the number of etpu spram accesses in the longest thread (semaphored and non semaphored). these figures will be used for estimating microengine wait time. ta ble 54 9 is an example for old tpu functions in which there are only simple parameter ram accesses. it does not take into consideration the cdc operation and microengine to microengine communication. the worst-case service time for each channel is: (cpcr = ccr = 0) longest thread + ((number of ram accesses in longest thread+1) * rcr * 2 clocks). note that the formula adds 1 ram accesses for the parameter preload that occurs during tst. there are actually three accesses during tst, but only the first one can receive wait- states. channel x serviced worst-case latency channel x other channels serviced channel x serviced next table 549. longest threads and ram accesses for old tpu functions function longest thread ram accesses dio 10 4 itc 40 (no linking) 42 (linking) 7 oc 40 7 pwm 24 4 spwm mode 0 mode1 mode 2 14 18 20 (no linking) 22 (linking 4 4 4 4 pma 94 8 pmm 94 8 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 1001/1740 mapping the channels for each time slot to determine when a channel will be serviced again, it is necessary to determine which other channels will be serviced first. do this by assuming all channels are continuously requesting service and mapping the channels into the time-slot sequence. adding time for time-slot transitions add six system clocks for time-slot transitions which occur after each time slot. first-pass analysis worst-case latency examples the examples in this section assume the system configuration shown in table 550 . finding the wcl for pwm on channel 0 the following shows how to find the wcl for pwm on channel 0. psp angle-angle mode angle-time mode 76 50 6 3 sm (1) 160 21 ppwa mode 0 mode 1 mode 2 mode 3 44 50 (2) 44 50 9 10 9 10 1. assumes one master and one slave. for each additional slave a) add 32 clocks and 2 ram accesses, and b) add (step_rate_cnt ? two clocks) 2. with one channel linked. add two clocks for each additional channel linked. table 549. longest threads and ram accesses for old tpu functions (continued) function longest thread ram accesses table 550. system configuration example channel priority function (1) , (2) 1. 9% ram collision rate (rcr) 2. cpu clock rate = 40 mhz, or 25 ns per clock period 0 high pwm (driving a dc motor) 1 middle ppwa (mode 0, measuring the dc motor speed) 2 low dio (input) enhanced time processing unit (etpu2) RM0029 1002/1740 doc id 15177 rev 8 1. find the worst-case service time for each active channel. a) longest thread of pwm is 24 cpu clocks with four ram accesses. 24 + ((4 ram accesses+1) * 0.09 * 2 cpu clock waits) = 24.9 cpu clocks, rounded up to 25 cpu clocks (since there are no partial clock periods) channel 0 worst-case service time = 25 cpu clocks. b) longest thread of ppwa in mode 0 is 44 cpu clocks with nine ram accesses. 44 + ((9 ram accesses+1) * 0.09 * 2 cpu clock waits) = 45.8 cpu clocks, rounded up to 46 cpu clocks channel 1 worst-case service time = 46 cpu clocks. c) longest thread of dio is ten cpu clocks with four ram accesses. 10 + ((4 ram accesses+1) * 0.09 * 2 cpu clock waits) = 10.9 cpu clocks, rounded up to 11 cpu clocks channel 2 worst-case service time = 11 cpu clocks. 2. assume channel 0 has just been serviced and that channels 1 and 2 are continuously requesting service. using the h-m-h-l-h-m-h time-slot sequence, map the channels that are granted for each time slot. see figure 560 . figure 560. next servicing for channel 0 channel 1 will be serviced in the middle-priority time slot before channel 0 is serviced again. 3. add time for the six-clock cpu time-slot transitions. see figure 560 and table 551 . a four-clock nop occurs after each channel is serviced since there is one channel in each priority level, i.e., a new cycle for a priority level is started after each channel is serviced. time-slot transitions occur after each time slot. tpu ch0 wcl tim tpu ch0 wcl tim channel 0 serviced worst case latency channel 0 h m h l h m h h channel 1 serviced channel 0 serviced = 10-cycle time slot transition = 4-cycle nop instruction RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 1003/1740 83 clocks * 25 ns/clock = 2075 ns conclusion: in this system configuration pwm can run with a minimum high time or low time of 2075 ns. note that in double match etpu system the pwm can be serviced once in each period, and there is no latency for minimum high time. the latency in etpu pwm function will represent the minimum pwm period. finding the wcl for ppwa on channel 1 the following shows how to find the wcl for ppwa on channel 1. 1. find the worst-case service time for each active channel. see step 1 of previous example. 2. assume channel 1 has just been serviced and that channels 0 and 2 are continuously requesting service. using the h-m-h-l-h-m-h time-slot sequence, map the channels that are granted for each time slot. see figure 561 . figure 561. next servicing for channel 1 channel 0 will be serviced twice and channel 2 once before channel 1 is serviced again. 3. add time for the six-clock cpu time-slot transitions. see figure 561 and table 552 . table 551. worst-case latency for channel 0 channel 0 worst-case service time 25 clocks channel 1 worst-case service time 46 clocks two 6-clock time-slot transitions 12 clocks total clocks 83 clocks tpu ch1 wcl tim tpu ch1 wcl tim channel 1 serviced worst case latency channel 1 h m h l h m h h channel 0 serviced channel 2 serviced = 10-cycle time slot transition = 4-cycle nop instruction channel 0 serviced channel 1 serviced enhanced time processing unit (etpu2) RM0029 1004/1740 doc id 15177 rev 8 131 clocks * 25 ns/clock = 3275 ns conclusion: in this system configuration ppwa can measure a period or pulse of minimum 3275 ns. note that ppwa function optimized for etpu hardware can use double transition mode to measure very narrow pulses with one service after the second transition, and latency will affect only the minimum gap between two input pulses. also the function threads would have more efficient coding. finding the wcl for dio on channel 2 the following shows how to find the wcl for dio on channel 2. 1. find the worst-case service time for each active channel. see step 1 of previous examples. 2. assume channel 2 has just been serviced and that channels 0 and 1 are continuously requesting service. using the h-m-h-l-h-m-h time-slot sequence, map the channels that are granted for each time slot. see figure 562 . figure 562. next servicing for channel 2 channel 0 will be serviced four times and channel 1 twice before channel 2 is serviced again. 3. add time for the ten-clock cpu time-slot transitions and the four-clock nops. see figure 562 and table 553 . table 552. worst-case latency for channel 1 two channel 0 worst-case service times 50 clocks channel 1 worst-case service time 46 clocks channel 2 worst-case service time 11 clocks four 6-clock time-slot transitions 24 clocks total clocks 131 clocks tpu ch2 wcl tim tpu ch2 wcl tim channel 2 serviced worst case latency channel 2 h m h l h m h h channel 0 serviced channel 1 serviced = 10-cycle time slot transition = 4-cycle nop instruction channel 0 serviced channel 0 serviced m h l h channel 1 serviced channel 0 serviced channel 2 serviced RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 1005/1740 245 clocks * 25 ns/clock = 6125 ns conclusion: in this system configuration dio can keep track of the input level at a minimum of every 6125 ns. note that dio function optimized for etpu hardware can use double transition mode to measure two pin transitions at a time and reduce the service time, improving the overall system performance and latency. second-pass worst-case latency analysis following is an example of a second-pass analysis for calculating worst-case latency for a channel. the second-pass analysis is useful for higher-performance systems, since it gives a more realistic worst-case latency result than first-pass analysis. this example uses a relatively simple system in order to illustrate the basic principles of second-pass analysis. for a more complex example of second-pass analysis, refer to multiphase motor commutation tpu function (comm)(tpupn09/ d). second-pass analysis guidelines rather than use a fixed formula, a second-pass analysis relies on the application of the following guidelines. 1. the first-pass analysis makes the assumption that all channels in the system are continually requesting service. for many systems this is an unrealistic assumption. for example, if tcr1 is counting at a rate of 2 mhz (500 ns per count) and a channel is running the dio function with a match rate of 20,000 tcr1 counts, the dio will request service every 10 ms (20,000 * 500 ns = 10,000,000 ns or 10 ms). it is therefore unrealistic to assume that the channel running this dio function is continuously requesting service. figure out a realistic service request rate for each channel. time slots can then be mapped to each channel at the real rate of request. 2. if a function is active during system initialization but not during the high-speed running mode of the system, then that system does not need to be included in the high-speed worst-case latency calculations. 3. use a realistic spram collision rate. 4. be careful when assigning functions priority levels and channel numbers. decide which function or functions will be most difficult to make perform at the desired level. assign those channels high priority and low channel numbers. try different priority and channel assignments to see how it affects the system. table 553. worst-case latency for channel 2 four channel 0 worst-case service times 100 clocks two channel 1 worst-case service time 92 clocks channel 2 worst-case service time 11 clocks seven 6-clock time-slot transitions 42 clocks total clocks 245 clocks enhanced time processing unit (etpu2) RM0029 1006/1740 doc id 15177 rev 8 5. the seven-slot sequence of || h | m | h | l | h | m | h || is asymmetrical when put back- to-back with other seven-slot sequences. note that in the following sequence there are two high-priority slots next to each other: || h | m | h | l | h | m | h |||| h | m | h | l | h | m | h || 6. make sure that when mapping out channels to the sequence, you choose a worst-case slot to start the mapping. for example, when estimating wcl for a high-priority channel, do not start the mapping in the last high-priority slot in a seven-slot sequence, as that is a best case for a high-priority channel since another high-priority time slot is next. 7. instead of always using the longest thread in the function as the worst-case thread, evaluate the threads in the function that will be used in the system and use the appropriate worst-case threads. for example, in the preceding example of first-pass analysis, the pwm was shown to be able to achieve a high time and low time of 2475 ns under worst-case conditions. this was derived using the longest pwm thread of 24 cpu clocks. this longest thread is actually thread 2, the thread that is entered after the pin has just gone high. thread 3, the thread that is entered after the pin has just gone low, requires only two cpu clocks. therefore, in the first-pass example, the high time was correctly derived, but the low time is actually shorter than was estimated. second-pass analysis example this example requires three 50% pwm waveforms: one 5 khz (200 ms/period) and two 50 khz (20 ms/period), each running dc motors. (remember that the pwm function requests service from the etpu after each high time and after each low time, so the etpu must handle a request every 100 ms for the 5 khz pwm and every 10 ms for the 50 mhz pwm.) note: this example uses square waves for simplicity. notice that to use a pwm waveform in the typical way, in which the pulse is modulated, the pulse must not be modulated in a way that violates the worst-case latency requirements. this example also uses one dio channel monitoring a signal level every millisecond and one ppwa channel in mode 0 monitoring the speed of the 5-khz dc motor. the ppwa must measure periods of 5 khz (200 ms/period). the cpu is interrupted by the channel running the ppwa function after measuring 200 periods (every 40 ms). the interrupt service routine performs an averaging of the period accumulation and checks it against a known parameter. the interrupt service time is so short and infrequent that it is a tiny fraction of total system time. the interrupt service routine contains no polling of the parameter ram. therefore a realistic rcr = 0%. first-try system configuration try a system configuration that seems likely to work. if it does not, change priority levels or channel numbers. the 5 khz and 50 khz pwms are the most time-critical functions. those are assigned high priority. ppwa is assigned middle priority. the dio is low performance and is assigned low priority. refer to tab le 5 54 . table 554. first-try system configuration channel priority function (1) , (2) 0 high pwm at 50 khz (needs a 4-s wcl) 1 high pwm at 50 khz (needs a 4-s wcl) RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 1007/1740 with this system configuration, worst-case service time for each active channel is determined as follows: a) longest thread of pwm is 24 cpu clocks with four ram accesses. 24 + ((4 ram accesses+1) * 0 * 2 cpu clock waits) = 24 cpu clocks channels 0-2 worst-case service time = 24 cpu clocks. b) longest thread of ppwa in mode 0 is 44 cpu clocks with nine ram accesses. 44 + ((9 ram accesses +1)* 0 * 2 cpu clock waits) = 44 cpu clocks channel 8 worst-case service time = 44 cpu clocks. c) longest thread of dio is ten cpu clocks with four ram accesses. 10 + ((4 ram accesses+1) * 0 * 2 cpu clock waits) = 10 cpu clocks channel 15 worst-case service time = 10 cpu clocks. to find the wcl for channel 0, assume channel 0 has just finished service. map the channels in the h-m-h-l-h-m-h sequence. see figure 563 . figure 563. worst-case latency for channel 0 (first try) conclusion: with this system configuration, worst-case latencies for channels 0 and 1 are too high (wcl for channel 1 is the same as wcl for channel 0). try a different system configuration. second-try system configuration the second-try system configuration is shown in table 555 . 2 high pwm at 5 khz (needs a 40-s wcl) 8 middle ppwa at 5 khz (needs an 80-s wcl) 15 low dio as input at rate of 1 ms 1. 0% ram collision rate 2. cpu clock rate = 40 mhz, or 60 ns per clock period table 554. first-try system configuration channel priority function (1) , (2) tpu ch0 wcl tim 1 tpu ch0 wcl tim 1 = 10-cycle time slot transition = 4-cycle nop instruction channel 0 serviced worst case latency h m h l h m h h channel 8 serviced channel 1 serviced channel 15 serviced channel 2 serviced m h l channel 0 serviced enhanced time processing unit (etpu2) RM0029 1008/1740 doc id 15177 rev 8 to find the wcl for channel 0, assume channel 0 has just finished service. map the channels in the h-m-h-l-h-m-h sequence. see figure 564 . figure 564. worst-case latency for channel 0 (second try) conclusion: with this system configuration, the wcl of both channel 0 and channel 1 is 3.85 ms, which is within the limit of 4 ms needed for a 50-khz pwm. next, find the wcl for channel 2. assume channel 2 has just finished service. map the channels in the h-m-h-l-h-m-h sequence. see figure 565 . figure 565. worst-case latency for channel 2 conclusion: with this system configuration, the wcl for channels 2 and 8 is 4.7 ms, which is within the 40 and 80 ms wcl requirements. table 555. second-try system configuration channel priority function (1) , (2) 1. 0% ram collision rate 2. cpu clock rate = 40 mhz, or 60 ns per clock period 0 high pwm at 50 khz (needs a 4-s wcl) 1 high pwm at 50 khz (needs a 4-s wcl) 2 middle pwm at 5 khz (needs a 40-s wcl) 8 middle ppwa at 5 khz (needs an 80-s wcl) 15 low dio as input at rate of 1 ms tpu ch0 wcl tim 2 tpu ch0 wcl tim 2 = 10-cycle time slot transition = 4-cycle nop instruction channel 0 serviced worst case latency h m h l h m h h channel 2 or channel 8 serviced channel 1 serviced channel 15 serviced channel 0 serviced m h l tpu ch2 wcl tim 1 tpu ch2 wcl tim 1 = 10-cycle time slot transition = 4-cycle nop instruction channel 2 serviced worst case latency h m h l h m h h channel 0 serviced channel 15 serviced channel 1 serviced channel 8 serviced m h l channel 2 serviced RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 1009/1740 notice that channels 2 and 8 are well within their wcl requirements. the system could be reconfigured as shown in table 556 to give channels 0 and 1 a larger margin while still keeping channels 2, 8 and 15 within their wcl requirements. 24.6.6 endianness the address of the 24-bit parameters and the most significant byte depends on the endianness of the mcu. table 557 shows the parameter addresses for big and little endian machines. 24.7 appendices 24.7.1 microcycle and i/o timing execution and channel timing figure 566 shows the main timings related to microinstruction execution when channels and timebases run on t2 timing. table 556. second-try system with channel 0 and 1 reconfigured channel priority function (1) , (2) 1. 0% ram collision rate 2. cpu clock rate = 40 mhz, or 60 ns per clock period 0 high pwm at 50 khz (needs a 10-s wcl) 1 high pwm at 50 khz (needs a 10-s wcl) 2 middle pwm at 5 khz (needs a 40-s wcl) 8 low ppwa at 5 khz (needs an 80-s wcl) 15 low dio as input at rate of 1 ms table 557. parameter addresses and endianness parameter byte address offset (n = word address offset) big endian little endian 32-bit 4*n 24-bit 4*n + 1 4*n 32-bit parameter?s most significant byte 4*n 4*n + 3 24-bit parameter?s most significant byte 4*n + 1 4*n + 2 least significant byte 4*n + 3 4*n enhanced time processing unit (etpu2) RM0029 1010/1740 doc id 15177 rev 8 figure 566. execution, timebase and channel t2 timing tcr1/2* t2 t4 t2 t4 t2 t4 1 microcycle 1 microcycle 1 microcycle t n+1 t n mrla/b tdla/b cap1/2 pin action due match uinstr uinst n uinst n+1 uinst = set pin pin action due uinstr note: * tcr clock/prescaler selection = 4x system clock updated pin value updated pin value uinstr uinst n pre-fetch uinst n+1 uinst n+2 execution system clock t4 (match on t n ) t n t n-1 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 1011/1740 figure 567. execution, timebase and channel t2/t4 timing the sequential occurrence of the four t states (t1 ? t4) constitutes a microcycle. only t2 and t4 are taken as reference for timings, either internal or external. t2 and t4 have the timing of the positive system clock pulses, and are used in most of the etpu logic in an edge-triggered design style. two additional t states are derived from the system clocks: t2 and t4 . t2 occurs when the etpu loses spram arbitration to a bus master. t4 occurs in halt state (due to a breakpoint or device debug request assertion, for instance), or in stall state (due to an ndedi queue full); see section , development support features , for more details. t2 and t4 states are defined as microcycle timing states (not to be confounded with logic states) of one system clock in which the t clocks continue to run, but the control signals associated with the clocks are unaffected. that is, no operation occurs during these states. both t2 and t4 states occur in multiples of two system clocks to keep the microengine synchronized with the free running channels, which are unaffected and keep on working as in t2 and t4. tcr1/2* t2 t4 t2 t4 t2 t4 1 microcycle 1 microcycle 1 microcycle t n-1 t n t n-3 mrla/b tdla/b cap1/2 pin action due match uinstr uinst n uinst n+1 uinst = set pin pin action due uinstr note: * tcr clock/prescaler selection = 1 x system clock updated pin value uinstr uinst n pre-fetch uinst n+1 uinst n+2 execution system clock t4 (match on t n ) t n-2 t n+1 t n+2 t n+3 t n+4 t n updated pin value enhanced time processing unit (etpu2) RM0029 1012/1740 doc id 15177 rev 8 thus, the etpu has two types of timing states: t2 : hold execution for spram access, from clock pulse t2 until one of the next t2 clock pulses of another microcycle. t4 : hold execution in debug mode or stall, from clock pulse t4 until one of the next t4 clock pulses of another microcycle. figure 568 and figure 569 shows the timing of t2 and t4 timing states, respectively. figure 568. t2 timing figure 569. t4 timing t4 t2 t2 t2 t2 t2 1st 2nd t2 t4 t2 t4 t2 t clocks sys.clock nth t2 wait-t2 t4 pc a1 a2 t4 t4 a2 a3 t2 (a1) (a0) (a1) inst t2 t4 t4 t4 t4 t4 1st 2nd t4 t2 t4 t2 t4 t clocks sys.clock nth t4 wait-t4 t2 pc a1 a2 t2 t2 a2 t4 a3 t4 (a1) (a1) (a2) inst RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 1013/1740 input/output signal delays the synchronizer, filter and edge detection logic delay the input signal transitions. the filter delay varies with the filter clock (etpu_ecr field fpsck) and the filter mode used, as shown in the table 487 . for any given transition, it depends on the phase of the filter clock when the input transition happens. in integration mode (tcrclk filtering only), it also depends on the state of the integrator counter. the total delay is defined as the number of system clock rising edges between the input transition and the setting of tdla/b, tcr1/2 incrementing, or eac tooth sensing (tcrclk) in angle mode. the synchronizer delay is 2 or 3 system clocks, depending on the phase of the synchronizer when the input transition happens. the edge detection takes 1 more system clock. the total delays are, thus: min. total delay = min. synchronizer delay + min. filter delay + edge detection delay min. total delay = 3 + min. filter delay max. total delay = max. synchronizer delay + max. filter delay + edge detection delay max. total delay = 4 + max. filter delay the channel filters can be bypassed, so nullifying the filter delays in the equations above. the channel output flip-flops drive the etpu output signals directly, without any synchronous delays. consult the mcu reference manual for information on additional delays added at the integration. 24.7.2 initialization code example the code example below initializes etpu_1 engine and configures etpu uart function to perform the receiver at channel 1 and the transmitter at channel 0. the function works without parity and the data word is 8 bits in size. the initialization code assumes the microcode function previously loaded into scm. ************************************************************************** ********* // initilization program for etpu engine 1, function microcode previously loaded into scm. // no angle mode, etpu uart function configured to perform at channels 0 and 1. // channel0 - tx_uart // channel1 - rx_uart // uart specifications: // data word size: 8 bits // parity: disabled // ***************************** definitions *********************************** //bases #define etpu_base 0x000 //mcu-dependent #define spram_base 0x000 //mcu-dependent //general configuration registers #define etpu_mcr_offset 0x000 //module configuration register enhanced time processing unit (etpu2) RM0029 1014/1740 doc id 15177 rev 8 #define etpu_tbcr_1_offset 0x020 //time base configuration register #define etpu_ecr_1_offset 0x014 //engine configuration register #define etpu_cier_1_offset 0x240 //channel interrupt enable register #define etpu_cdtrer_1_offset 0x250 //data transf interrupt enable register //channel0 configuration registers #define etpu_c0cr_1_offset 0x400 //channel0 configuration register #define etpu_c0scr_1_offset 0x404 //channel0 status control register #define etpu_c0hsrr_1_offset 0x408 //channel0 host service req. register //channel1 configuration registers #define etpu_c1cr_1_offset 0x410 //channel1 configuration register #define etpu_c1scr_1_offset 0x414 //channel1 status control register #define etpu_c1hsrr_1_offset 0x418 //channel1 status control register // tx_uart spram parameters #define match_rate_tx_offset 0x004 //channel0 parameter 1 #define data_uart_tx_offset 0x008 //channel0 parameter 2 #define data_size_tx_offset 0x00c //channel0 parameter 3 // rx_uart spram parameters #define match_rate_rx_offset 0x024 //channel1 parameter 1 #define data_uart_rx_offset 0x028 //channel1 parameter 2 #define data_size_rx_offset 0x02c //channel1 parameter 3 // #define etpu_mcr (*((volatile unsigned int*)(etpu_mcr_offset + etpu_base))) #define etpu_tbcr_1 (*((volatile unsigned int*)(etpu_tbcr_1_offset + etpu_base))) #define etpu_ecr_1 (*((volatile unsigned int*)(etpu_ecr_1_offset + etpu_base))) #define etpu_cier_1 (*((volatile unsigned int*)(etpu_cier_1_offset + etpu_base))) #define etpu_cdtrer_1 (*((volatile unsigned int*)(etpu_cdtrer_1_offset + etpu_base))) #define etpu_c0cr_1 (*((volatile unsigned int*)(etpu_c0cr_1_offset + etpu_base))) #define etpu_c0scr_1 (*((volatile unsigned int*)(etpu_c0scr_1_offset + etpu_base))) #define etpu_c0hsrr_1 (*((volatile unsigned int*)(etpu_c0hsrr_1_offset + etpu_base))) #define etpu_c1cr_1 (*((volatile unsigned int*)(etpu_c1cr_1_offset + etpu_base))) #define etpu_c1scr_1 (*((volatile unsigned int*)(etpu_c1scr_1_offset + etpu_base))) #define etpu_c1hsrr_1 (*((volatile unsigned int*)(etpu_c1hsrr_1_offset + etpu_base))) #define match_rate_tx (*((volatile unsigned int*)(match_rate_tx_offset + spram_base))) #define data_uart_tx (*((volatile unsigned int*)(data_uart_tx_offset + spram_base))) #define data_size_tx (*((volatile unsigned int*)(data_size_tx_offset + spram_base))) #define match_rate_rx (*((volatile unsigned int*)(match_rate_rx_offset + spram_base))) RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 1015/1740 #define data_uart_rx (*((volatile unsigned int*)(data_uart_rx_offset + spram_base))) #define data_size_rx (*((volatile unsigned int*)(data_size_rx_offset + spram_base))) // macros #define tcr2_prescaler(x) ((x & 0x3f) << 8) #define tcr1_prescaler(x) (x & 0xff) #define channel_function(x) ((x & 0x1f) << 16) #define channel_param_base_addr(x) (x & 0xff) #define function_mode(x) (x & 0x3) #define match_rate_trans(x) (x & 0xffff) #define match_rate_rec(x) (x & 0xffff) #define data_word_tx(x) (x & 0x3fff) #define data_size_trans(x) (x & 0xf) #define data_size_rec(x) (x & 0xf) #define host_serv_req(x) (x & 0x7) #define entry_table_base(x) (x & 0x1f) //etpu_mcr fields - module configuration register #define pse 0x00000002 //parameter sign extension #define scmmisen 0x00000200 //scm misc enable #define vis 0x00000040 //scm visibility #define gtbe 0x00000001 //global time base enable //etpu_tbcr_1 fields - time base configuration register #define tcrclk_filter_twosample 0x00000000 //tcrclk filter in two sample mode #define tcrclk_filter_integrator 0x00800000 //tcrclk filter in integrator mode #define tcrclk_filter_div2clock 0x00000000 //tcrclk filter uses system clock divided by 2 #define tcrclk_filter_channelclock 0x00400000 //tcrclk filter uses channel clock #define tcr2_rise 0x00100000 //tcr2 inc rising edge #define tcr2_fall 0x00200000 //tcr2 inc falling edge #define tcr2_risefall 0x00300000 //tcr2 inc ris and fall #define tcr2_gateddiv8 0x00000000 //tcrclk gates system clock/8 #define tcr1clk_source_div2 0x00000000 //tcr1 source system clock/2 #define trc1clk_source_tcrclk 0x00040000 //tcr1 source is tcrclk pin #define channel_filter_twosamplemode 0x00000000 //filter:two sample mode #define channel_filter_threesamplemode 0x00008000 //filter:three sample mode #define channel_filter_contmode 0x0000c000 //filter:continuous mode //etpu_ecr fields - engine configuration register #define filter_prescaler_clock_div4 0x00010000 //system clock/4 //etpu_cxcr fields - channelx configuration register #define channel_int_enable 0x80000000 //channel interrupt enable #define channel_data_transf_req_enable 0x40000000 //channel data transfer req. enable #define channel_priority_disable 0x00000000 //channel disable enhanced time processing unit (etpu2) RM0029 1016/1740 doc id 15177 rev 8 #define channel_priority_low 0x10000000 //low priority channel #define channel_priority_middle 0x20000000 //middle priority channel #define channel_priority_high 0x30000000 //high priority channel //data_uart - spram #define clear_tdre 0x007fffff //tdre must be zero to signal new valid //data to be transmitted void init_etpu( ){ volatile int temp; //initialize etpu module configuration register(etpu_mcr) etpu_mcr = 0x00070000; //scmsize is 16k(7 2k blocks) //initialize etpu time base configuration register(etpu_tbcr) etpu_tbcr_1 = (tcr1clk_source_div2 | channel_filter_twosamplemode | tcr1_prescaler(8)); //initialize etpu engine configuration register(etpu_ecr) etpu_ecr_1 = (entry_table_base(0x1f) | filter_prescaler_clock_div4); //write to the channel configuration registers(etpu_cxcr) to choose the //function to be performed by the channel and its parameter base address.standard entry table //is selected. etpu_c0cr_1 = (channel_int_enable | channel_function(15) | channel_param_base_addr(0x00)); etpu_c1cr_1 = (channel_int_enable | channel_function(15) | channel_param_base_addr(0x02)); //write to the channel status control registers(etpu_cxscr) to choose //variations within the function flow. etpu_c0scr_1 = (function_mode(0)); // no parity for transmitter etpu_c1scr_1 = (function_mode(0)); // no parity for receiver //write to spram for parameter initialization of each configured //channel match_rate_tx = match_rate_trans(0x412); //setup match rate for transmitter data_uart_tx = data_word_tx(0x000000aa); //load first byte to be transmitted=aa data_size_tx = data_size_trans(8); //8-bit data word for transmitter match_rate_rx = match_rate_rec(0x412); //setup match rate for receiver data_size_rx = data_size_rec(8); //8-bit data word for receiver //write to channel host service request registers(etpu_cxhsrr) to //initialize active channels(channel 0 and 1) etpu_c0hsrr_1 = host_serv_req(3); etpu_c1hsrr_1 = host_serv_req(2); //write to channel priority field to enable each channel by //assigning it a high,middle or low priority etpu_c0cr_1 =(etpu_c0cr_1 | channel_priority_high); etpu_c1cr_1 =(etpu_c1cr_1 | channel_priority_high); //monitor channel host service request register for completion //of initialization RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 1017/1740 //hsr should be zero in the end of initialization do { temp = etpu_c0hsrr_1; } while (temp != 0); do { temp = etpu_c1hsrr_1; } while (temp != 0); //write gtbe bit to start tcr1 and tcr2 time bases counting //at the same time etpu_mcr = (etpu_mcr | gtbe); }// end of etpu_initialization routine ************************************************************************** ********* 24.7.3 predefined channel mode summary ta ble 55 8 explains channel double match predefined submode functionality by showing all event sequence possibilities. the initial state considered for all submodes is channel flags mrla, mrlb, tdla and tdlb reset. from initial state one can follow the table and verify how each submode behaves in a determined sequence of events. note that the actions performed by an event type depend on all previous events following the initial state, for a given channel submode. there are three columns for each event: one for event type, one for enable/disable actions and one for capture. event type column can be matcha, matchb, transa and transb (for double transition modes). enable/disable actions column (identified as ? [blocks](enables) ? in column head) specifies which other events are enabled or disabled. initially disabled events (specified in ?initially blocked? column) are usually enabled by other events. in double transition submodes, the first transition detected is always considered transa and the second is considered transb. this means that transa event actually enables the detection of transb event. this is not explicit in the table, since it is a general behavior for all double transition submodes. a sequence of four events (two matches and two transitions) are necessary to describe the behavior of some channel submodes. when a determined sequence of events has less than four events, the other event columns are left blank. cells in an ?event type? column that have light-grayed background indicate that a service request is generated. more than one event in the same event sequence can issue service request. note: the table does not exhaust all possibilities of channel logic event sequences, because it does not account for possible microcode interventions. for instance, if matches are blocked by first transition and microcode resets tdla, the matches become enabled again, and from this point on the channel behaves as if the first transition had never occurred. enhanced time processing unit (etpu2) RM0029 1018/1740 doc id 15177 rev 8 table 558. predefined channel mode summary mode initially blocked 1st event 2nd event 3rd event 4th event event type [blocks] (enables (1) ) capt. event type [blocks] (enables) capt. event type [blocks] (enables) capt. event type [blocks] (enables) capt. em_nb_st none matcha/b none 1/2 matchb/a none 2/1 transa [matches] both transb none 2 transa [matches] both transb none 2 transa [matches] both transb none 2 em_nb_dt none matcha/b none 1/2 matchb/a none 2/1 transa none 1 transb none 2 matcha none 1 transa none 1 matchb none 2 transb none 2 transb [matchb] 2 matchb none 2 transa [matcha] 1 transb [matchb] 2 transa [matcha] 1 matchb none 2 transb none 2 transb [matchb] 2 em_b_st none matcha [matchb] both transa [matches] both transb none 2 matchb [matcha] both transa [matches] both transb none 2 em_b_dt none matcha [matchb] both transa none 1 transb none 2 matchb [matcha] both transa [matcha] 1 matchb none 2 transb none 2 transb [matchb] 2 bm_st none matcha/b none 1/2 matchb/a none 2/1 transa [matches] both transb none 2 transa [matches] both transb none 2 transa [matches] both transb none 2 RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 1019/1740 bm_dt none matcha/b none 1/2 matchb/a none 2/1 transa none 1 transb [matches] 2 transa none 1 matchb/a none 2/ none transb [matches] 2 transb [matches] 2 transa none 1 matcha/b none none/ 2 matchb/a none 2/ none transb [matches] 2 transb [matches] 2 transb [matches] 2 m2_st transa matcha (transa) 1 matchb none 2 transa [matches] both transb none 2 transa [matches] both transb none 2 matcha and matchb (transa) both transa [matches] both transb none 2 matchb [matcha] 2 m2_dt transa matcha (transa) 1 transa none 1 transb [matchb] 2 matchb none 2 transb none 2 matchb none 2 transa none 1 transb none 2 matcha and matchb (transa) both transa none 1 transb none 2 matchb [matcha] 2 m2_o_st transa matchb matcha (matchb) (transa) 1 transa [matches] both transb none 2 matchb [transa] 2 m2_o_dt transa matchb matcha (matchb) (transa) 1 transa none 1 transb [matchb] 2 matchb [transb] 2 matchb [transa] 2 table 558. predefined channel mode summary (continued) mode initially blocked 1st event 2nd event 3rd event 4th event event type [blocks] (enables (1) ) capt. event type [blocks] (enables) capt. event type [blocks] (enables) capt. event type [blocks] (enables) capt. enhanced time processing unit (etpu2) RM0029 1020/1740 doc id 15177 rev 8 sm_st (2) matchb matcha none both transa none both transb none 2 transa [matcha] both transb none 2 sm_dt matchb matcha none both transa none 1 transb none 2 transa none 1 matcha none 2 transb none 2 transa none 1 transb [matcha] 2 sm_st_e (3) matchb transb matcha none 1 transa none 1 transa [matcha] 1 generates service request 1. transition a always enables transition b 2. sm_st is compatible with tpu3 channel logic. 3. it is not possible to include all functionality of this submode in table. see section , single match enhanced mode (sm_st_e) , for more details. table 558. predefined channel mode summary (continued) mode initially blocked 1st event 2nd event 3rd event 4th event event type [blocks] (enables (1) ) capt. event type [blocks] (enables) capt. event type [blocks] (enables) capt. event type [blocks] (enables) capt. RM0029 enhanced time processing unit (etpu2) doc id 15177 rev 8 1021/1740 24.7.4 misc algorithm the misc generator is based on the following polynomial: g(x) = 1 + x 1 + x 2 + x 22 + x 31 (equivalent to feedback mask = 0x80400007) the misc signature generation starts by clearing the misc accumulator value to 0 and preloading the misc counter with the highest scm address. it then steps through each address decrementing the counter, reading 32 bit values and following the algorithm below: if the least significant bit in misc is 1 then misc = misc right shifted by 1 bit misc = misc xor 0x80400007 else misc = misc right shifted by 1 bit end if misc = misc xor ram data the code example below shows an excerpt of c code that calculates the misc signature for a given array of data, based on the previous algorithm: #define scm_size (max_scm_address / 4) /* last byte address - converted to 32-bit word */ #define poly 0x80400007 /* g(x) = 1 + x 1 + x 2 + x 22 + x 31 */ /************************************************************************* ****** function : void calc_misc() purpose : this function calculates the misc value. inputs notes : none returns notes : misc value general notes : the array?unsigned int data[]? represents the actual memory array, organized in 32-bit words. ************************************************************************** *****/ unsigned int calc_misc (void) { int j; /* loop counter */ unsigned int misc = 0; for (j = (scm_size-1); j >= 0 ; j--) { /* scm_size has the number of 32- bit words in scm */ if (misc & 0x1) { misc >>= 1; misc ^= poly; } else { misc >>= 1; } misc ^= data[j]; /* data[j] is the actual 32-bit word taken from the scm array */ } return (misc); /* final signature calculated */ }; enhanced time processing unit (etpu2) RM0029 1022/1740 doc id 15177 rev 8 the value calculated by this algorithm must be loaded into register etpu_misccmpr prior to activating the scm misc calculator in etpu. once the misc calculator is activated (bit scmmisen in register etpu_mcr is written to 1) etpu itself will start this procedure (au) reading the scm whenever allowed by microengine. at the end of the cycle, when all the array has been read and the scm signature is calculated, the host cpu can be notified via global exception if the misc accumulator does not match the value in etpu_misccmpr. equation 12 shows how the average time taken by misc to complete the signature of the whole scm can be calculated. equation 12 average misc period = s / (4 * f * (1 - l)) in equation 12 , f = clock frequency s = scm size in bytes l = etpu load (as a percentage of execution clocks over a period of time, including tst clocks) further detail on misc calculation can be found on section , scm test ? multiple input signature calculator . au. etpu misc hardware is optimized to read 32-bit words from memory and to calculate this crc in parallel, rather than shifting one bit at a time. the actual implementation inside etpu, although bringing to the same results, does not match exactly the algorithm shown here. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1023/1740 25 enhanced queued analog-to-digital converter (eqadc) 25.1 information specific to this device this section presents device-specific parameterization and customization information not specifically referenced in the remainder of this chapter. 25.1.1 device-specific pin configuration features the following eqadc pins are multiplexed and configuration of the corresponding systems integration unit (siu) registers is necessary. an12/ma0/sds these pins are configured by setting the pad configuration register 215 (siu_pcr215) on the siu. note: attempts to convert the input voltage applied to this pin while the ma0 or the sds functions are selected will result in an undefined conversion result. as this pin is also used by digital logic, it has reduced analog to digital conversion accuracy when compared to the an[0:11,16:39] analog input pins. an13/ma1/sdo these pins are configured by setting the pad configuration register 216 (siu_pcr216) on the siu. note: attempts to convert the input voltage applied to this pin while the ma1 or the sdo functions are selected will result in an undefined conversion result. as this pin is also used by digital logic, it has reduced analog to digital conversion accuracy when compared to the an[0:11,16:39] analog input pins. an14/ma2/sdi these pins are configured by setting the pad configuration register 217 (siu_pcr217) on the siu. note: attempts to convert the input voltage applied to this pin while the ma2 or the sdi functions are selected will result in an undefined conversion result. as this pin is also used by digital logic, it has reduced analog to digital conversion accuracy when compared to the an[0:11,16:39] analog input pins. an15/fck these pins are configured by setting the pad configuration register 218 (siu_pcr218) on the siu. note: attempts to convert the input voltage applied to this pin while the fck function is selected will result in an undefined conversion result. as this pin is also used by digital logic, it has reduced analog to digital conversion accuracy when compared to the an[0:11,16:39] analog input pins. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1024/1740 doc id 15177 rev 8 external triggers the source of the eqadc external triggers can be the etpu, the emios, or an external signal. the source is selected by configuring the eqadc trigger input select register (siu_etisr) on the siu. 25.1.2 availability of analog inputs analog inputs anr, ans, ant and anu are not available on spc564a74xx, spc564a80xx devices. 25.2 introduction 25.2.1 module overview the enhanced queued analog-to-digital converter (eqadc) block provides accurate and fast conversions for a wide range of applications. the eqadc provides a parallel interface to two on-chip analog-to-digital converters (adcs), a single master to single slave serial interface to an off-chip external device, and a parallel side interface to one or more on-chip digital signal processing (dsp) modules (for example, a decimation filter). the two on-chip adcs are architected to allow access to all the analog channels. the eqadc transfers commands from multiple command fifos (cfifos) to the on-chip adcs or to the external device. the multiple result fifos (rfifos) can receive data from the on-chip adcs, from an off-chip external device or from an on-chip dsp module. data from the on-chip adcs can be routed to the side interface, processed by the on-chip dsp and then routed back through the side interface to the rfifos. the eqadc supports software and external hardware triggers from other blocks to initiate transfers of commands from the cfifos to the on-chip adcs or to the external device. it also monitors the fullness of cfifos and rfifos, and accordingly generates dma or interrupt requests to control data movement between the fifos and the system memory, which is external to the eqadc. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1025/1740 25.2.2 block diagram figure 570 is the block diagram for the eqadc. figure 570. eqadc block diagram figure 570 shows the primary components inside the eqadc. the eqadc consists of the fifo control unit which controls the cfifos and the rfifos, the adc control logic which controls the two on-chip adcs, the eqadc synchronous serial interface (eqadc ssi) which allows communication with an external device, and the eqadc parallel side interface (eqadc psi) which allows communication with on-chip eqadc companion modules (av) . there are 6 cfifos and 6 rfifos, each with 4 entries, except cfifo0 that can have 8 entries. an8/anw an9/anx/tbias an10/any an11/anz an0/dan0+ an1/dan0- an2/dan1+ an3/dan1- an4/dan2+ an5/dan2- an6/dan3+ an7/dan3- priority decoder external device sds fck sdo sdi adc0 adc1 bias gen refbypc cfifox note: x=0, 1, 2, 3, 4, 5 32 bits cqueue y rqueue y system rfifox 16 bits cbuffer0 cbuffer1 eqadc fifo control mux control logic synchronous serial channel vdda vssa vrh vrl ma0 ma1 ma2 y=0, 1, 2, 3, ... dma and requests number adc control interface (eqadc ssi) eqadc interrupt dma transaction done signals eqadc ssi transmit buffer unit logic an12/t50pvref an13/t25pvref an15 an14/t75pvref pre-charge ref gen parallel side interface (eqadc psi) eqadc on-chip digital signal processor abort cont abort cont memory result format and calibra- tion etrigx, atrig fil bypassx an16/ an17 an19 an18 an20-39 mux mux enhanced queued analog-to-dig ital converter (eqadc) RM0029 1026/1740 doc id 15177 rev 8 the fifo control unit performs the following functions: it prioritizes the cfifos to determine what cfifos will have their commands transferred. supports software and hardware triggers to start command transfers from a particular cfifo. decodes command data from the cfifos, and accordingly, sends these commands to one of the two on-chip adcs or to the external device. decodes result data from on-chip adcs or from the external device, and transfers data to the appropriate rfifo or to the parallel side interface. the adc control logic manages the execution of commands bound for on-chip adcs. it interfaces with the cfifos via two 2-entry command buffers (cbuffers) with abort control and with the rfifos and side interface via the result format and calibration sub-block . the adc control logic performs the following functions: buffers command data for execution. decodes command data and accordingly generates control signals for the two on-chip adcs. detects abort request, stores aborted commands and buffers immediate conversion commands. formats and calibrates conversion result data coming from the on-chip adcs. generates the internal multiplexer control signals and the select signals used by the external multiplexers. the eqadc ssi allows for a full duplex, synchronous, serial communication between the eqadc and an external device. the eqadc psi allows for a full duplex, synchronous, parallel communication between the eqadc and decimation filters a and b and reaction modules. figure 570 also depicts data flow through the eqadc. commands are contained in system memory in a user defined data structure. the most likely data structure to be used is a queue as depicted in the figure 570 (aw) . command data is moved from the command queue (cqueue) to the cfifos by either the host cpu or by the dmac. once a cfifo is triggered and becomes the highest priority cfifo using a certain cbuffer, command data is transferred from the cfifo to the on-chip adcs, or to the external device. the adc executes the command, and the result is moved through the result format and calibration sub-block to either the side interface or to the rfifo. data from the external device or on- chip companion module bypasses the result format and calibration sub-block and is moved directly to its specified rfifo. when data is stored in an rfifo, data is moved from the rfifo by the host cpu or by the dmac to a data structure in system memory depicted in the figure 570 as a result queue (rqueue). for users familiar with the qadc, the eqadc system upgrades the functionality provided by that block. refer to section 25.7.7, eqadc versus qadc , for a comparison between the eqadc and qadc. av. decimation filters a and b and reaction module aw. command and result data can be stored in system memory in any user defined data structure. however, in this document it will be assumed that the data structure of choice is a queue, since it is the most likely data structure to be used and because queues are the only ty pe of data structure supported by the dmac. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1027/1740 25.2.3 features the eqadc block includes these distinctive features: two independent on-chip rsd cyclic adcs ? 8, 10, and 12 bits ad resolution ? targets up to 10 bit accuracy at 500ksample/s (adc_clk=7.5 mhz) and 8 bit accuracy at 1m sample/s (adc_clk=15 mhz) for differential conversions ? selectable common mode conversion range (0 - 5v; 0 - 2.5v; 0 - 1.25v) ? differential conversions ? differential channels include variable gain amplifier for improved dynamic range (x1; x2; x4) ? differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics (200k ohms; 100k ohms; 5k ohms) ? sample times of 2 (default), 8, 64 or 128 adc clock cycles ? provides time stamp information when requested ? parallel interface to eqadc cfifos and rfifos ? supports both right-justified unsigned and signed formats for conversion results ? the refbypc pin stabilizes one of internal generated reference ? temperature sensor ? ability to measure directly vdd automatic application of adc calibration constants ? provision of reference voltages (25%vref and 75%vref) for adc calibration purposes 40 input channels available to the two on-chip adcs 4 pairs of differential analog input channels full duplex synchronous serial interface to an external device ? has a free-running clock for use by the external device ? supports a 26-bit message length ? transmits a null message when there are no triggered cfifos with commands bound for external cbuffers, or when there are triggered cfifos with commands bound for external cbuffers but the external cbuffers are full parallel side interface to communicate with several on-chip companion modules stac bus client interface to import an alternative timebase to the internal time stamp priority based cfifos ? supports six cfifos with fixed priority. the lower the cfifo number, the higher its priority. when commands of distinct cfifos are bound for the same cbuffer, the higher priority cfifo is always served first. ? immediate conversion command feature with conversion abort control ? streaming mode operation of cfifo0 to execute some commands several times ? supports software and several hardware trigger modes to arm a particular cfifo ? generates interrupt when command coherency is not achieved external hardware triggers ? supports rising edge, falling edge, high level and low level triggers ? supports configurable digital filter enhanced queued analog-to-dig ital converter (eqadc) RM0029 1028/1740 doc id 15177 rev 8 ? supports controls to bypass the trigger digital filters two triggers operation mode for queue0 ? additional internal trigger (not filtered) called advance trigger that is used to enable the external trigger of queue0 and to control the loop behavior of cfifo0 supports 4 to 8 external 8-to-1 muxes which can expand the input channel number from 40 to 96 upgrades the functionality provided by the qadc 25.3 modes of operation this section describes the operation modes of the eqadc. 25.3.1 normal mode this is the default operational mode when the eqadc is not in streaming mode or background debug or stop mode. 25.3.2 streaming mode this mode is characterized by two main aspects: the abort action by cfifo0 in any current conversion process started from another queue, and the loop behavior of the cfifo0. in some applications, there may be sequences of identical commands each spaced only by a few microseconds. to reduce the dma data transfer, in this mode a short command queue can be stored in cfifo0 and repeatedly be executed based on a timed trigger, but advance to the next (repeating) sequence of commands based on another device?s internal trigger. the cfifo0 delivers commands to the adc as before, but those commands are not ?invalidated? after they are sent (in fact, they are ?invalidated? only because the transfer next data pointer has moved on). when it encounters these repeated commands the cfifo0 only fills once, using the dma as usual, until either it is full or a command with end-of- queue is encountered. thereafter the sub-queue repeats/wraps. the number of commands loaded is unaffected by the delivery of commands once the streaming mode is configured, since no commands loaded are invalidated even if sent before all the queue is loaded. the number of entries in the cfifo0 is extended to eight (configurable). this is to facilitate the targeted applications. the repeating subqueue must be contained within the eight cfifo0 entries. to maintain compatibility, cfifo0 by default operates as it does before, without streaming and with four entries. streaming, and additional entries, can be enabled independently. streaming mode is selected as another mode for queue 0 using the configuration bits in the eqadc_cfcr register. streaming mode makes use of an additional bit in the conversion command word (ccw); this bit is called ?repeat?. the purpose of this bit is to mark in the command queue, where to start a repeating sequence. streaming mode requires two trigger inputs. the standard queue 0 trigger, in this mode referred to as ?repeat trigger? and a second internal trigger input to the eqadc called ?advance? trigger. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1029/1740 25.3.3 debug mode upon a debug mode entry request, eqadc behavior will vary according to the status of the dbg field in section , eqadc module configuration register (eqadc_mcr) . if dbg is programmed to 0b00, the debug mode entry request is ignored. if dbg is programmed to 0b10 or to 0b11, the eqadc will enter debug mode. in case the eqadc ssi is enabled, the free running clock (fck) output to external device will not stop when dbg is programmed to 0b11, but fck will stop in low phase, when dbg is programmed to 0b10. during debug mode, the eqadc will not transfer commands from any cfifos, no null messages will be transmitted to the external device, no data will be returned to any rfifo, no hardware trigger event will be captured, and all eqadc registers can be accessed as in normal mode. the latter implies that cfifos can still be triggered using software triggers, since no scheme is implemented to write-protect registers during debug mode. dma and interrupt requests continue to be generated as in normal mode. if at the time the debug mode entry request is detected, there are commands in the on-chip cbuffers that were already under execution, these commands will be completed but the generated results, if any, will not be sent to the rfifos until debug mode is exited. commands whose execution has not started will not be executed until debug mode is exited.the clock associated with an on-chip adc stops, during its low phase, after the adc ceases executing commands. the time base counter will only stop after all on-chip adcs cease executing commands. when exiting debug mode, the eqadc relies on the cfifo operation modes and on the cfifo status to determine the next command entry to transfer. the eqadc internal behavior after the debug mode entry request is detected differs depending on the status of command transfers. no command transfer is in progress. the eqadc immediately halts future command transfers from any cfifo. if a null message is being transmitted, eqadc will complete the serial transmission before halting future command transfers. if valid data (conversion result or data read from an adc register) is received at the end of transmission, it will not be sent to an rfifo until debug mode is exited. if the null message transmission is aborted, the eqadc will complete the abort procedure before halting future command transfers from any cfifo. the message of the cfifo that caused the abort of the previous serial transmission will only be transmitted after debug mode is exited. command transfer is in progress. eqadc will complete the transfer and update cfifo status before halting future command transfers from any cfifo. command transfers to the internal cbuffers are considered completed when a command is written to the buffers. command transfers to the external device are considered completed when the serial transmission of the command is completed. if valid data (conversion result or data read from an adc register) is received at the end of a serial transmission, it will not be sent to an rfifo until debug mode is exited. the cfifo status bits will still be updated after the completion of the serial transmission, therefore, after debug mode entry request is detected, the eqadc status bits will only stop changing several system clock cycles after the on-going serial transmission completes. if the command message transmission is aborted, the eqadc will complete the abort procedure before halting future command transfers from any cfifo. the message of enhanced queued analog-to-dig ital converter (eqadc) RM0029 1030/1740 doc id 15177 rev 8 the cfifo that caused the abort of the previous serial transmission will only be transmitted after debug mode is exited. command/null message transfer through serial interface was aborted but next serial transmission did not start. if the debug mode entry request is detected between the time a previous serial transmission was aborted and the start of the next transmission, the eqadc will complete the abort procedure before halting future command transfers from any cfifo. the message of the cfifo that caused the abort of the previous serial transmission will only be transmitted after debug mode is exited. 25.3.4 stop mode upon a stop mode entry request detection, the eqadc progressively halts its operations until it reaches a static, stable state from which it can recover when returning to normal mode. eqadc then asserts an acknowledge signal, indicating that it is static and that the clock input can be stopped. in stop mode, the free running clock (fck) output to external device will stop during its low phase if the eqadc ssi is enabled, and no hardware trigger events will be captured. the latter implies that, as long as the system clock is running, cfifos can still be triggered using software triggers, since no scheme is implemented to write-protect registers during stop mode. if at the time the stop mode entry request is detected, there are commands in the on-chip cbuffers that were already under execution, these commands will be completed but the generated results, if any, will not be sent to the rfifos until stop mode is exited. commands whose execution has not started will not be executed until stop mode is exited. after these remaining commands are executed, the clock input to the adcs is stopped. the adc clock stops during its low phase. the time base counter will only stop after all on-chip adcs cease executing commands. only then, the stop acknowledge signal is asserted. when exiting stop mode, the eqadc relies on the cfifo operation modes and on the cfifo status to determine the next command entry to transfer. the eqadc internal behavior after the stop mode entry request is detected differs depending on the status of the command transfer. no command transfer is in progress the eqadc immediately halts future command transfers from any cfifo. if a null message is being transmitted, eqadc will complete the transmission before halting future command transfers. if valid data (conversion result or data read from an adc register) is received at the end of the transmission, it will not be sent to an rfifo until stop mode is exited. if the null message transmission is aborted, the eqadc will complete the abort procedure before halting future command transfers from any cfifo. the message of the cfifo that caused the abort of the previous serial transmission will only be transmitted after stop mode is exited. command transfer is in progress eqadc will complete the transfer and update cfifo status before halting future command transfers from any cfifo. command transfers to the internal cbuffers are considered completed when a command is written to the buffers. command transfers to the external device are considered completed when the serial transmission of the command is completed. if valid data (conversion result or data read from an adc register) is received at the end of a serial transmission, it will not be sent to an rfifo until stop mode is exited. the cfifo status bits will still be updated after RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1031/1740 the completion of the serial transmission, therefore, after stop mode entry request is detected, the eqadc status bits will only stop changing several system clock cycles after the on-going serial transmission completes. if the command message transmission is aborted, the eqadc will complete the abort procedure before halting future command transfers from any cfifo. the message of the cfifo that caused the abort of the previous serial transmission will only be transmitted after stop mode is exited. command/null message transfer through serial interface was aborted but next serial transmission did not start. if the stop mode entry request is detected between the time a previous serial transmission was aborted and the start of the next transmission, the eqadc will complete the abort procedure before halting future command transfers from any cfifo. the message of the cfifo that caused the abort of the previous serial transmission will only be transferred after stop mode is exited. 25.4 external signal description 25.4.1 overview the following is a list of external pins. note: at chip integration level, some of the digital and analog signals listed here might share pins or not be available external to the chip. refer to the signals chapter for details. table 559. external signals name port function reset state type an0/dan0+ input single-ended analog input / differential analog input positive terminal ? analog an1/dan0- input single-ended analog input / differential analog input negative terminal ? analog an2/dan1+ input single-ended analog input / differential analog input positive terminal ? analog an3/dan1- input single-ended analog input / differential analog input negative terminal ? analog an4/dan2+ input single-ended analog input / differential analog input positive terminal ? analog an5/dan2- input single-ended analog input / differential analog input negative terminal ? analog an6/dan3+ input single-ended analog input / differential analog input positive terminal ? analog enhanced queued analog-to-dig ital converter (eqadc) RM0029 1032/1740 doc id 15177 rev 8 an7/dan3- input single-ended analog input / differential analog input negative terminal ? analog an8/anw input single-ended analog input / single- ended analog input from external multiplexers ? analog an9/anx input single-ended analog input / single- ended analog input from external multiplexers ? analog an10/any input single-ended analog input/single- ended analog input from external multiplexers ? analog an11/anz input single-ended analog input / single- ended analog input from external multiplexers ? analog an12 input / output single-ended analog input ? analog an13 input / output single-ended analog input ? analog an14 input / output single-ended analog input ? analog an15 input single-ended analog input ? analog an16 input single-ended analog input ? analog an17 input single-ended analog input ? analog an18 input single-ended analog input ? analog an19 input single-ended analog input ? analog an20 input single-ended analog input ? analog an21 input single-ended analog input ? analog an22 input single-ended analog input ? analog an23 input single-ended analog input ? analog an24 input single-ended analog input ? analog an25 input single-ended analog input ? analog an26 input single-ended analog input ? analog an27 input single-ended analog input ? analog an28 input single-ended analog input ? analog an29 input single-ended analog input ? analog an30 input single-ended analog input ? analog an31 input single-ended analog input ? analog an32 input single-ended analog input ? analog an33 input single-ended analog input ? analog an34 input single-ended analog input ? analog table 559. external signals (continued) name port function reset state type RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1033/1740 25.4.2 detailed signal descriptions an0/dan0+ ? single-ended analog input/differential analog input positive terminal an0 is a single-ended analog input to the two on-chip adcs. dan0+ is the positive terminal of the differential analog input dan0 (dan0+ - dan0-). an1/dan0? ? single-ended analog input/differential analog input negative terminal an1 is a single-ended analog input to the two on-chip adcs. dan0- is the negative terminal of the differential analog input dan0 (dan0+ - dan0-). an35 input single-ended analog input ? analog an36 input single-ended analog input ? analog an37 input single-ended analog input ? analog an38 input single-ended analog input ? analog an39 input single-ended analog input ? analog ma0 output external multiplexer control signal 0 digital ma1 output external multiplexer control signal 0 digital ma2 output external multiplexer control signal 0 digital fck output eqadc ssi free running clock 0 digital sds output eqadc ssi serial data select 1 digital sdi input eqadc ssi serial data in digital sdo output eqadc ssi serial data out 0 digital vdda input analog positive power supply ? power vssa input analog negative power supply ? power vrh input voltage reference high ? power vrl input voltage reference low ? power refbypc input external bypass capacitor pin ? power etrig0 input external trigger for cfifo0 ? digital etrig1 input external trigger for cfifo1 ? digital etrig2 input external trigger for cfifo2 ? digital etrig3 input external trigger for cfifo3 ? digital etrig4 input external trigger for cfifo4 ? digital etrig5 input external trigger for cfifo5 ? digital table 559. external signals (continued) name port function reset state type enhanced queued analog-to-dig ital converter (eqadc) RM0029 1034/1740 doc id 15177 rev 8 an2/dan1+ ? single-ended analog input/differential analog input positive terminal an2 is a single-ended analog input to the two on-chip adcs. dan1+ is the positive terminal of the differential analog input dan1 (dan1+ - dan1-). an3/dan1? ? single-ended analog input/differential analog input negative terminal an3 is a single-ended analog input to the two on-chip adcs. dan1- is the negative terminal of the differential analog input dan1 (dan1+ - dan1-). an4/dan2+ ? single-ended analog input/differential analog input positive terminal an4 is a single-ended analog input to the two on-chip adcs. dan2+ is the positive terminal of the differential analog input dan2 (dan2+ - dan2-). an5/dan2? ? single-ended analog input/differential analog input negative terminal an5 is a single-ended analog input to the two on-chip adcs. dan2- is the negative terminal of the differential analog input dan2 (dan2+ - dan2-). an6/dan3+ ? single-ended analog input/differential analog input positive terminal an6 is a single-ended analog input to the two on-chip adcs. dan3+ is the positive terminal of the differential analog input dan3 (dan3+ - dan3-). an7/dan3? ? single-ended analog input/differential analog input negative terminal an7 is a single-ended analog input to the two on-chip adcs. dan3- is the negative terminal of the differential analog input dan3 (dan3+ - dan3-). an8/anw ? single-ended analog input/ single-ended analog input from external multiplexers an8 is a single-ended analog input to the two on-chip adcs. anw is a single-ended analog input to one of the on-chip adcs in external multiplexed mode. an9/anx ? single-ended analog input/ single-ended analog input from external multiplexers an9 is a single-ended analog input to the two on-chip adcs. anx is a single-ended analog input to one of the on-chip adcs in external multiplexed mode. an10/any ? single-ended analog input/ single-ended analog input from external multiplexers an10 is a single-ended analog input to the two on-chip adcs. any is a single-ended analog input to one of the on-chip adcs in external multiplexed mode. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1035/1740 an11/anz ? single-ended analog input/ single-ended analog input from external multiplexers an11 is a single-ended analog input to the two on-chip adcs. anz is a single-ended analog input to one of the on-chip adcs in external multiplexed mode. an12 ? single-ended analog input an12 is a single-ended analog input to the two on-chip adcs. an13 ? single-ended analog input/ an13 is a single-ended analog input to the two on-chip adcs. an14 ? single-ended analog input an14 is a single-ended analog input to the two on-chip adcs. an15 ? single-ended analog input an15 is a single-ended analog inputs to the two on-chip adcs. an16 ? single-ended analog input/ an16 is a single-ended analog input to the two on-chip adcs. an17 ? single-ended analog input an17 is a single-ended analog input to the two on-chip adcs. an18 ? single-ended analog input an18 is a single-ended analog input to the two on-chip adcs. an19 ? single-ended analog input an19 is a single-ended analog input to the two on-chip adcs. an20-an39 ? single-ended analog input an20 through an39 are single-ended analog inputs to the two on-chip adcs. ina_adc0_0 - ina_adc0_9 ? single-ended analog input ina_adc0_0 through ina_adc0_9 are single-ended analog inputs to the on-chip adc0. ina_adc1_0 - ina_adc1_9 ? single-ended analog input ina_adc1_0 through ina_adc1_9 are single-ended analog inputs to the on-chip adc1. ma0-ma2 ? external multiplexer control signals ma0, ma1, and ma2 combined form a select signal associated with external multiplexers. fck ? eqadc ssi free-running clock fck is a free-running clock signal for synchronizing transmissions between the eqadc (master) and the external (slave) device. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1036/1740 doc id 15177 rev 8 sds ? eqadc ssi serial data select sds is the serial data select output. it is used to indicate to the external (slave) device when it can latch incoming serial data, when it can output its own serial data, and when it must abort a data transmission. sds corresponds to the chip select signal in a conventional spi interface. sdi ? eqadc ssi serial data in sdi is the serial data input signal from the external (slave) device. sdo ? eqadc ssi serial data out sdo is the serial data output signal to the external (slave) device. vrh, vrl ? voltage reference high and voltage reference low vrh and vrl are voltage references for the adcs. vrh is the highest voltage reference, while vrl is the lowest voltage reference. vdda, vssa ? 5v vdd and vss for the 5v analog components vdda is the positive power supply pin for the adcs and vssa is the negative power supply pin for the adcs. refer to electrical specifications. refbypc ? reference bypass capacitor the refbypc pin is used to connect an external bypass capacitor between refbypc and vrl. the value of this capacitor should be 100nf. this bypass capacitor is used to provide a stable reference voltage for the adc. etrig0?etrig5 ? external triggers the external trigger signals are for hardware triggering. the eqadc can detect rising edge, falling edge, high level and low level on each of the external trigger signals. etrigx triggers cfifox. the eqadc also supports configurable digital filters for these external trigger signals. these digital filters can be bypassed by individual input control signals called eqadc_intern_trig_selx. 25.5 memory map/register definition this section provides memory maps and detailed descriptions of all registers. data written to or read from reserved areas of the memory map is undefined. 25.5.1 eqadc memory map this section provides memory maps for the eqadc block. table 560. eqadc memory map address use access eqadc_base+0x000 eqadc module configuration register (eqadc_mcr) unrestricted eqadc_base+0x004 eqadc test register (eqadc_tst) test RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1037/1740 eqadc_base+0x008 eqadc null message send format register (eqadc_nmsfr) unrestricted eqadc_base+0x00c eqadc external trigger digital filter register (eqadc_etdfr) unrestricted eqadc_base+0x010 eqadc cfifo push register 0 (eqadc_cfpr0) write only eqadc_base+0x014 eqadc cfifo push register 1 (eqadc_cfpr1) write only eqadc_base+0x018 eqadc cfifo push register 2 (eqadc_cfpr2) write only eqadc_base+0x01c eqadc cfifo push register 3 (eqadc_cfpr3) write only eqadc_base+0x020 eqadc cfifo push register 4 (eqadc_cfpr4) write only eqadc_base+0x024 eqadc cfifo push register 5 (eqadc_cfpr5) write only eqadc_base+0x028 reserved - eqadc_base+0x02c reserved - eqadc_base+0x030 eqadc result fifo pop register 0 (eqadc_rfpr0) read only eqadc_base+0x034 eqadc result fifo pop register 1 (eqadc_rfpr1) read only eqadc_base+0x038 eqadc result fifo pop register 2 (eqadc_rfpr2) read only eqadc_base+0x03c eqadc result fifo pop register 3 (eqadc_rfpr3) read only eqadc_base+0x040 eqadc result fifo pop register 4 (eqadc_rfpr4) read only eqadc_base+0x044 eqadc result fifo pop register 5 (eqadc_rfpr5) read only eqadc_base+0x048 reserved - eqadc_base+0x04c reserved - eqadc_base+0x050 eqadc cfifo control regi ster 0 (eqadc_cfcr0) unrestricted eqadc_base+0x054 eqadc cfifo control regi ster 1 (eqadc_cfcr1) unrestricted eqadc_base+0x058 eqadc cfifo control regi ster 2 (eqadc_cfcr2) unrestricted eqadc_base+0x05c reserved - eqadc_base+0x060 eqadc interrupt and dma control register 0 (eqadc_idcr0) unrestricted eqadc_base+0x064 eqadc interrupt and dma control register 1 (eqadc_idcr1) unrestricted eqadc_base+0x068 eqadc interrupt and dma control register 2 (eqadc_idcr2) unrestricted eqadc_base+0x06c reserved - eqadc_base+0x070 eqadc fifo and interrupt status register 0 (eqadc_fisr0) unrestricted eqadc_base+0x074 eqadc fifo and interrupt status register 1 (eqadc_fisr1) unrestricted eqadc_base+0x078 eqadc fifo and interrupt status register 2 (eqadc_fisr2) unrestricted eqadc_base+0x07c eqadc fifo and interrupt status register 3 (eqadc_fisr3) unrestricted eqadc_base+0x080 eqadc fifo and interrupt status register 4 (eqadc_fisr4) unrestricted eqadc_base+0x084 eqadc fifo and interrupt status register 5 (eqadc_fisr5) unrestricted eqadc_base+0x088 reserved - eqadc_base+0x08c reserved - eqadc_base+0x090 eqadc cfifo transfer counter register 0 (eqadc_cftcr0) unrestricted eqadc_base+0x094 eqadc cfifo transfer counter register 1 (eqadc_cftcr1) unrestricted eqadc_base+0x098 eqadc cfifo transfer counter register 2 (eqadc_cftcr2) unrestricted eqadc_base+0x09c reserved - eqadc_base+0x0a0 eqadc cfifo status snapshot register 0 (eqadc_cfssr0) read only eqadc_base+0x0a4 eqadc cfifo status snapshot register 1 (eqadc_cfssr1) read only eqadc_base+0x0a8 eqadc cfifo status snapshot register 2 (eqadc_cfss2r) read only eqadc_base+0x0ac eqadc cfifo status register (eqadc_cfsr) read only table 560. eqadc memory map (continued) address use access enhanced queued analog-to-dig ital converter (eqadc) RM0029 1038/1740 doc id 15177 rev 8 eqadc_base+0x0b0 reserved - eqadc_base+0x0b4 eqadc synchronous serial interface control register (eqadc_ssicr) unrestricted eqadc_base+0x0b8 eqadc synchronous serial interface receive data register (eqadc_ssirdr) read only eqadc_base+0x0bc - eqadc_base+0x0cc reserved - eqadc_base+0x0d0 eqadc stac bus client configuration register (eqadc_redlccr) unrestricted eqadc_base+0x0d4 - eqadc_base+0x0fc reserved - eqadc_base+0x100 - eqadc_base+0x10c eqadc cfifo0 registers (eqadc_cf0rw) (w=0, .., 3) read only eqadc_base+0x110 - eqadc_base+0x11c eqadc cfifo0 extension registers (eqadc_cf0erw) (w=0, .., 3) read only eqadc_base+0x120 - eqadc_base+0x13c reserved - eqadc_base+0x140 - eqadc_base+0x14c eqadc cfifo1 registers (eqadc_cf1rw) (w=0, .., 3) read only eqadc_base+0x150 - eqadc_base+0x17c reserved - eqadc_base+0x180 - eqadc_base+0x18c eqadc cfifo2 registers (eqadc_cf2rw) (w=0, .., 3) read only eqadc_base+0x190 - eqadc_base+0x1bc reserved - eqadc_base+0x1c0 - eqadc_base+0x1cc eqadc cfifo3 registers (eqadc_cf3rw) (w=0, .., 3) read only eqadc_base+0x1d0 - eqadc_base+0x1fc reserved - eqadc_base+0x200 - eqadc_base+0x20c eqadc cfifo4 registers (eqadc_cf4rw) (w=0, .., 3) read only eqadc_base+0x210 - eqadc_base+0x23c reserved - eqadc_base+0x240 - eqadc_base+0x24c eqadc cfifo5 registers (eqadc_cf5rw) (w=0, .., 3) read only eqadc_base+0x250 - eqadc_base+0x2fc reserved - eqadc_base+0x300 - eqadc_base+0x30c eqadc rfifo0 registers (eqadc_rf0rw) (w=0, .., 3) read only eqadc_base+0x310 - eqadc_base+0x33c reserved - eqadc_base+0x340 - eqadc_base+0x34c eqadc rfifo1 registers (eqadc_rf1rw) (w=0, .., 3) read only eqadc_base+0x350 - eqadc_base+0x37c reserved - table 560. eqadc memory map (continued) address use access RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1039/1740 25.5.2 eqadc register descriptions eqadc module configuration register (eqadc_mcr) the eqadc module configuration register (eqadc_mcr) contains bits used to control how the eqadc responds to a debug mode entry request, and to enable the eqadc ssi interface. figure 571. eqadc module configuration register (eqadc_mcr) eqadc_base+0x380 - eqadc_base+0x38c eqadc rfifo2 registers (eqadc_rf2rw) (w=0, .., 3) read only eqadc_base+0x390 - eqadc_base+0x3bc reserved - eqadc_base+0x3c0 - eqadc_base+0x3cc eqadc rfifo3 registers (eqadc_rf3rw) (w=0, .., 3) read only eqadc_base+0x3d0 - eqadc_base+0x3fc reserved - eqadc_base+0x400 - eqadc_base+0x40c eqadc rfifo4 registers (eqadc_rf4rw) (w=0, .., 3) read only eqadc_base+0x410 - eqadc_base+0x43c reserved - eqadc_base+0x440 - eqadc_base+0x44c eqadc rfifo5 registers (eqadc_rf5rw) (w=0, .., 3) read only eqadc_base+0x450 - eqadc_base+0x7fc reserved - table 560. eqadc memory map (continued) address use access register address: eqadc_base+0x000 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 icea0 icea1 0 essie 0 dbg w reset: 0000000000000000 = unimplemented or reserved enhanced queued analog-to-dig ital converter (eqadc) RM0029 1040/1740 doc id 15177 rev 8 note: disabling the eqadc ssi (0b00 write to essie) or serial transmissions from the eqadc ssi (0b10 write to essie) while a serial transmission is in progress results in the abort of that transmission. note: when disabling the eqadc ssi, the fck will not stop until it reaches its low phase. eqadc test register (eqadc_tst) the eqadc test register (eqadc_tst) is used for test purposes only. this register can only be read/written in a test access, accessing the eqadc_tst register in any other way will result in a transfer error. in a non-test access to the eqadc_tst register, read data is undefined and written data is ignored. table 561. eqadc module configuration regi ster (eqadc_mcr) field description field description 24-25 icea n immediate conversion command enable adc n ( n =0,1) icea n enables the eqadc to abort on-chip adc n current conversion and to start the immediate conversion command from cfifo0 in the requested adc n . 1 enable immediate conversion command request. 0 disable immediate conversion command request. 27-28 essie[0:1] eqadc synchronous serial interface enable field the essie field defines the eqadc synchronous serial interface operation according to table 562 . 30-31 dbg[0:1] debug enable the dbg field defines the eqadc response to a debug mode entry request as in table 563 . table 562. eqadc ssi enable field essie[0:1] meaning 0b00 eqadc ssi is disabled 0b01 reserved 0b10 eqadc ssi is enabled, fck is free running, and serial transmissions are disabled. 0b11 eqadc ssi is enabled, fck is free running, and serial transmissions are enabled. table 563. debug enable field dbg[0:1] meaning 0b00 do not enter debug mode. 0b01 reserved 0b10 enter debug mode. if the eqadc ssi is enabled, fck stops while the eqadc is in debug mode. 0b11 enter debug mode. if the eqadc ssi is enabled, fck is free running while the eqadc is in debug mode. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1041/1740 figure 572. eqadc test register (eqadc_tst) eqadc null message send format register (eqadc_nmsfr) the eqadc null message send format register (eqadc_nmsfr) defines the format of the null message sent to the external device. figure 573. eqadc null message send format register (eqadc_nmsfr) register address: eqadc_base+0x004 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w reset: 0000000000000000 = unimplemented or reserved register address: eqadc_base+0x008 0123456789101112131415 r 000000 nmf w reset:0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r nmf w reset:0000000000000000 = unimplemented or reserved enhanced queued analog-to-dig ital converter (eqadc) RM0029 1042/1740 doc id 15177 rev 8 the eqadc null message send format register only affects how the eqadc sends a null message, but it has no control on how the eqadc detects a null message on receiving data. the eqadc detects a null message by decoding the message_tag field on the receive data. refer to page 1099 for more information on the message_tag field. note: writing to the eqadc null message send format register while the serial transmissions are enabled (essie field configured to 0b11 in section , eqadc module configuration register (eqadc_mcr) ) is not recommended. eqadc external trigger digital filter register (eqadc_etdfr) the eqadc external trigger digital filter register (eqadc_etdfr) is used to set the minimum time a signal must be held in a logic state on the cfifo triggers inputs to be recognized as an edge or level gated trigger. the digital filter length field specifies the minimum number of system clocks that must be counted by the digital filter counter to recognize a logic state change. however, there is a control signal that can be used to bypass the digital filter when this is not needed. figure 574. eqadc external trigger digi tal filter register (eqadc_etdfr) table 564. eqadc null message send format register (eqadc_nmsfr) field description field description 6-31 nmf[0:25] null message format the nmf field contains the programmable null message send value for the eqadc. the value written to this register will be sent as a null message when serial transmissions from the eqadc ssi are enabled (essie field configured to 0b11 in section , eqadc module configuration register (eqadc_mcr) ) and either ? there are no triggered cfifos with commands bound for external cbuffers, or; ? there are triggered cfifos with commands bound for external cbuffers but the external cbuffers are full. refer to section , null message format for external device operation , for more information on the format of a null message. register address: eqadc_base+0x00c 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 dfl w reset: 0000000000000000 RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1043/1740 table 565. eqadc external trigger digital filter register (eqadc_etdfr) field description field description 28-31 dfl[0:3] digital filter length the dfl field specifies the minimum number of system clocks that must be counted by the digital filter counter to recognize a logic state change. the count specifies the sample period of the digital filter which is calculated according to the following equation: minimum clock counts for which an etrig signal needs to be stable to be passed through the filter are shown in table 566 . refer to section , external trigger event detection , for more information on the digital filter. the dfl field must only be written when the modex of all cfifos are configured to disabled.when the digital filter is bypassed by using the input control, the dfl is not considered and the trigger input signal is not filtered. filterperiod s ( ystemclockperiod 2 dfl ) 1s ( ystemclockperiod ) + = table 566. minimum required time to valid etrig dfl[0:3] minimum clock count minimum time (ns) (system clock = 120 mhz) 0b0000 2 16.66 0b0001 3 25.00 0b0010 5 41.66 0b0011 9 75.00 0b0100 17 141.66 0b0101 33 275.00 0b0110 65 541.66 0b0111 129 1075.00 0b1000 257 2141.66 0b1001 513 4275.00 0b1010 1025 8541.66 0b1011 2049 17075.00 0b1100 4097 34141.00 0b1101 8193 68275.00 0b1110 16385 136541.66 0b1111 32769 273075.00 enhanced queued analog-to-dig ital converter (eqadc) RM0029 1044/1740 doc id 15177 rev 8 eqadc cfifo push registers (eqadc_cfpr) the eqadc cfifo push registers (eqadc_cfpr) provide a mechanism to fill the cfifos with command messages from the cqueues. refer to section 25.6.4, eqadc command fifos , for more information on the cfifos and to section , message format in eqadc , for a description on command message formats. figure 575. eqadc cfifo push register x (eqadc_cfprx) eqadc result fifo pop registers (eqadc_rfpr) the eqadc result fifo pop registers (eqadc_rfpr) provide a mechanism to retrieve data from rfifos. register address: eqadc_base+0x010 register address: eqadc_base+0x014 register address: eqadc_base+0x018 register address: eqadc_base+0x01c register address: eqadc_base+0x020 register address: eqadc_base+0x024 0123456789101112131415 r 0000000000000000 w cf_pushx reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w cf_pushx reset: 0000000000000000 table 567. eqadc cfifo push register x (eqadc_cfprx) field description field description 0-31 cf_pushx [0:31] cfifo push data x when cfifox is not full, writing to the whole word or any bytes of eqadc_cfprx will push the 32-bit cf_pushx value into cfifox. writing to the cf_pushx field also increments the corresponding cfctrx value by one in section , eqadc fifo and interrupt status registers (eqadc_fisr) . when the cfifox is full, the eqadc ignores any write to the cf_pushx. reading the eqadc_cfprx always returns zero. only whole words must be written to eqadc_cfpr. writing half-words or bytes to eqadc_cfpr will still push the whole 32-bit cf_push field into the corresponding cfifo, but undefined data will fill the areas of cf_push that were not specifically designated as target locations for the write. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1045/1740 figure 576. eqadc rfifo pop register x (eqadc_rfprx) eqadc cfifo control registers (eqadc_cfcr) the eqadc cfifo control registers (eqadc_c fcr) contain bits that affect cfifos. these bits specify the cfifo operation mode and can invalidate all of the cfifo contents. register address: eqadc_base+0x030 register address: eqadc_base+0x034 register address: eqadc_base+0x038 register address: eqadc_base+0x03c register address: eqadc_base+0x040 register address: eqadc_base+0x044 0123456789101112131415 r 00000000 00000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rf_popx w reset: 0000000000000000 = unimplemented or reserved table 568. eqadc rfifo pop register x (eqadc_rfprx) field description field description 16-31 rf_popx [0:15] result fifo pop data x when rfifox is not empty, the rf_popx contains the next unread entry value of rfifox . reading a word, a half-word, or any bytes from eqadc_rfprx will pop one entry from rfifox and cause the rfctrx field to be decremented by one in the section , eqadc fifo and interrupt status registers (eqadc_fisr) . when the rfifox is empty, any read on eqadc_rfprx returns undefined data value and does not decrement the rfctrx value. writing to eqadc_rfprx has no effect. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1046/1740 doc id 15177 rev 8 figure 577. eqadc cfifo control register 0 (eqadc_cfcr0) figure 578. eqadc cfifo control register 1 (eqadc_cfcr1) register address: eqadc_base+0x050 0123456789101112131415 r000 cfe ee0 str me0 000 mode0 amode0 w sse 0 cfin v0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 mode1 0000 w sse 1 cfin v1 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved register address: eqadc_base+0x054 0123456789101112131415 r 00000000 mode2 0000 w sse 2 cfin v2 reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 mode3 0000 w sse 3 cfin v3 reset: 0000000000000000 = unimplemented or reserved RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1047/1740 figure 579. eqadc cfifo control register 2 (eqadc_cfcr2) register address: eqadc_base+0x058 0123456789101112131415 r 00000000 mode4 0000 w sse 4 cfin v4 reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 mode5 0000 w sse 5 cfin v5 reset: 0000000000000000 = unimplemented or reserved table 569. eqadc cfifo control register x (eqadc_cfcrx) field description field description 3 cfeee0 cfifo0 entry number extension enable the cfeee0 bit is used to enable the extension of the cfifo0 entries. when in extended mode, the cfifo0 total entries is the sum of normal entries plus the defined value for extension. for more details, refer to section , cfifo0 streaming mode description . 1 enable the extension of cfifo0 entries. 0 cfifo0 has a normal value of entries. 4 strme0 cfifo0 streaming mode operation enable the strme0 bit is used to enable the streaming mode of operation of cfifo0. in this case, it is possible to repeat some sequence of commands of this fifo. for more details, refer to section , cfifo0 streaming mode description . 1 enable the streaming mode of cfifo0. 0 streaming mode of cfifo0 is disabled. 5 ssex cfifo single-scan enable bit x the ssex bit is used to set the sssx bit in section , eqadc fifo and interrupt status registers (eqadc_fisr) . writing a ?1? to ssex will set the sssx in section , eqadc fifo and interrupt status registers (eqadc_fisr) , if the cfifo is in single-scan mode. when sssx is already asserted, writing a ?1? to ssex also has no effect. if the cfifo is in continuous-scan mode or is disabled, writing a ?1? to ssex will not set sssx. writing a ?0? to ssex has no effect. ssex always is read as ?0?. 1 set the sssx bit. 0no effect. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1048/1740 doc id 15177 rev 8 6 cfinvx cfifo invalidate bit x the cfinvx bit causes the eqadc to invalidate all entries of cfifox. writing a ?1? to cfinvx will reset the value of cfctrx in section , eqadc fifo and interrupt status registers (eqadc_fisr) . writing a ?1? to cfinvx also resets the push next data pointer, transfer next data pointer to the first entry of cfifox in figure 629 . cfinvx always is read as ?0?. writing a ?0? has no effect. invalidate all of the entries in the corresponding cfifo. no effect. writing cfinvx only invalidates commands stored in cfifox; previously transferred commands that are waiting for execution, that is comm ands stored in the cbuffers, will still be executed, and results generated by them will be stored in the appropriate rfifo. cfinvx must not be written unless the modex is configured to disabled, and cfifo status is idle. modex [0:3] cfifo operation mode x the modex field selects the cfifo operation mode for cfifox, see table 570 . refer to section , cfifo scan trigger modes , for more information on cfifo trigger mode. if modex is not disabled, it must not be changed to any other mode besides disabled. if modex is disabled and the cfifo status is idle , modex can be changed to any other mode. 12-15 amode0 [0:3] cfifo0 advance trigger operation mode 0 the amode0 field selects the trigger mode for the atrig0 trigger signal in streaming mode, see table 571 . the use of reserved values drives to unknown behavior of the block. if amode0 is not disabled, it must not be changed to any other mode besides disabled. if amode0 is disabled and the cfifo0 status is idle, amode0 can be changed to any other mode. for the streaming mode of operation when the atrig0 is used to enable the etrig0 or to advance the command queue, the normal mode of oper ation is external trigger single scan. other settings are not fully tested. table 569. eqadc cfifo control register x (eqadc_cfcrx) field de scription (continued) field description table 570. cfifo operation mode table mode x [0:3] cfifo operation mode 0b0000 disabled 0b0001 software trigger, single scan 0b0010 low level gated external trigger, single scan 0b0011 high level gated external trigger, single scan 0b0100 falling edge external trigger, single scan 0b0101 rising edge external trigger, single scan 0b0110 falling or rising edge external trigger, single scan 0b0111 - 0b1000 reserved 0b1001 software trigger, continuous scan 0b1010 low level gated external trigger, continuous scan RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1049/1740 eqadc interrupt and dma control registers (eqadc_idcr) the eqadc interrupt control registers (eqadc_idcr) contain bits to enable the generation of interrupt or dma requests when the corresponding flag bits are set in section , eqadc fifo and interrupt status registers (eqadc_fisr) . figure 580. eqadc interrupt and dma control register 0 (eqadc_idcr0) 0b1011 high level gated external trigger, continuous scan 0b1100 falling edge external trigger, continuous scan 0b1101 rising edge external trigger, continuous scan 0b1110 falling or rising edge external trigger, continuous scan 0b1111 reserved table 570. cfifo operation mode table (continued) mode x [0:3] cfifo operation mode table 571. cfifo0 advance trigger operation mode table amode0[0:3] cfifo0 advance trigger operation mode 0b0000 disabled 0b0001 reserved 0b0010 reserved 0b0011 reserved 0b0100 falling edge external trigger, single scan 0b0101 rising edge external trigger, single scan 0b0110 falling or rising edge external trigger, single scan 0b0111 - 0b1111 reserved register address: eqadc_base+0x060 0123456789101112131415 r ncie 0 tori e0 pie0 eoqi e0 cfui e0 0 cffe 0 cffs 0 0000 rfoi e0 0 rfd e0 rfd s0 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ncie 1 tori e1 pie1 eoqi e1 cfui e1 0 cffe 1 cffs 1 0000 rfoi e1 0 rfd e1 rfd s1 w reset: 0000000000000000 = unimplemented or reserved enhanced queued analog-to-dig ital converter (eqadc) RM0029 1050/1740 doc id 15177 rev 8 figure 581. eqadc interrupt and dma control register 1 (eqadc_idcr1) figure 582. eqadc interrupt and dma control register 2 (eqadc_idcr2) register address: eqadc_base+0x064 0123456789101112131415 r ncie 2 tori e2 pie2 eoq ie2 cfui e2 0 cff e2 cff s2 0000 rfoi e2 0 rfd e2 rfd s2 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ncie 3 tori e3 pie3 eoq ie3 cfui e3 0 cff e3 cff s3 0000 rfoi e3 0 rfd e3 rfd s3 w reset: 0000000000000000 = unimplemented or reserved register address: eqadc_base+0x068 0123456789101112131415 r ncie 4 tori e4 pie4 eoq ie4 cfui e4 0 cff e4 cff s4 0000 rfoi e4 0 rfd e4 rfd s4 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ncie 5 tori e5 pie5 eoq ie5 cfui e5 0 cff e5 cff s5 0000 rfoi e5 0 rfd e5 rfd s5 w reset: 0000000000000000 = unimplemented or reserved RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1051/1740 table 572. eqadc interrupt and dma control re gister x (eqadc_idcrx) field description field description nciex non-coherency interrupt enable x nciex enables the eqadc to generate an interrupt request when the corresponding ncfx in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is asserted. 1 enable non-coherency interrupt request. 0 disable non-coherency interrupt request. toriex trigger overrun interrupt enable x toriex enables the eqadc to generate an interrupt request when the corresponding torfx in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is asserted. apart from generating an independent interrupt request for a cfifox trigger overrun event, the eqadc also provides a combined interrupt at which the result fifo overflow interrupt, the command fifo underflow interrupt, and the command fifo trigger overrun interrupt requests of all cfifos are ored. when rfoiex, cfuiex, and toriex are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes asserted: rfofx, cfufx, and torfx (assuming that all interrupts are enabled). see section 25.6.8, eqadc dma/interrupt request , for details. 1 enable trigger overrun interrupt request. 0 disable trigger overrun interrupt request. piex pause interrupt enable x piex enables the eqadc to generate an interrupt request when the corresponding pfx in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is asserted. 1 enable pause interrupt request. 0 disable pause interrupt request. eoqiex end of queue interrupt enable x eoqiex enables the eqadc to generate an interrupt request when the corresponding eoqfx in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is asserted. 1 enable end of queue interrupt request. 0 disable end of queue interrupt request. cfuiex cfifo underflow interrupt enable x cfuiex enables the eqadc to generate an interrupt request when the corresponding cfufx in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is asserted. apart from generating an independent interrupt request for a cfifox underflow event, the eqadc also provides a combined interrupt at which the result fifo overflow interrupt, the command fifo underflow interrupt, and the command fifo trigger overrun interrupt requests of all cfifos are ored. when rfoiex, cfuiex, and toriex are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes asserted: rfofx, cfufx, and torfx (assuming that all interrupts are enabled). see section 25.6.8, eqadc dma/interrupt request , for details. 1 enable underflow interrupt request. 0 disable underflow interrupt request. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1052/1740 doc id 15177 rev 8 cffex cfifo fill enable x cffex enables the eqadc to generate an interrupt request (cffsx is asserted) or dma request (cffsx is negated) when cfffx in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is asserted. 1 enable cfifo fill dma or interrupt request. 0 disable cfifo fill dma or interrupt request. cffex must not be negated while a dma transaction is in progress. cffsx cfifo fill select x cffsx selects if a dma or interrupt request is generated when cfffx in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is asserted. if cffex is asserted, the eqadc generates an interrupt request when cffsx is negated, or it generates a dma request if cffsx is asserted. 1 generate dma request to move data from the system memory to cfifox. 0 generate interrupt request to move data from the system memory to cfifox. cffsx must not be negated while a dma transaction is in progress. rfoiex rfifo overflow interrupt enable x rfoiex enables the eqadc to generate an interrupt request when the corresponding rfofx in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is asserted. apart from generating an independent interrupt request for an rfifox overflow event, the eqadc also provides a combined interrupt at which the result fifo overflow interrupt, the command fifo underflow interrupt, and the command fifo trigger overrun interrupt requests of all cfifos are ored. when rfoiex, cfuiex, and toriex are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes asserted: rfofx, cfufx, and torfx (assuming that all interrupts are enabled). see section 25.6.8, eqadc dma/interrupt request , for details. 1 enable overflow interrupt request. 0 disable overflow interrupt request. table 572. eqadc interrupt and dma control re gister x (eqadc_idcrx) field description field description RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1053/1740 eqadc fifo and interrupt status registers (eqadc_fisr) the eqadc fifo and interrupt status registers (eqadc_fisr) contain flag and status bits for each cfifo and rfifo pair. write ?1? to a flag bit to clear it. writing ?0? has no effect. status bits are read only. these bits indicate the status of the fifo itself. rfdex rfifo drain enable x rfdex enables the eqadc to generate an interrupt request (rfdsx is asserted) or dma request (rfdsx is negated) when rfdfx in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is asserted. 1 enable rfifo drain dma or interrupt request. 0 disable rfifo drain dma or interrupt request. rfdex must not be negated while a dma transaction is in progress. rfdsx rfifo drain select x rfdsx selects if a dma or interrupt request is generated when rfdfx in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is asserted. if rfdex is asserted, the eqadc generates an interrupt request when rfdsx is negated, or it generates a dma request when rfdsx is asserted. 1 generate dma request to move data from rfifox to the system memory. 0 generate interrupt request to move data from rfifox to the system memory. rfdsx must not be negated while a dma transaction is in progress. table 572. eqadc interrupt and dma control re gister x (eqadc_idcrx) field description field description enhanced queued analog-to-dig ital converter (eqadc) RM0029 1054/1740 doc id 15177 rev 8 figure 583. eqadc fifo and interrupt status register x (eqadc_fisrx) register address: eqadc_base+0x070 register address: eqadc_base+0x074 register address: eqadc_base+0x078 register address: eqadc_base+0x07c register address: eqadc_base+0x080 register address: eqadc_base+0x084 01234 5 6789101112131415 r ncfx tor fx pfx eoq fx cfuf x sssx cfff x 00000 rfo fx 0 rfdf x 0 w reset: 00000 0 1000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfctrx tnxtptrx rfctrx popnxtptrx w reset: 00000 0 0000000000 = unimplemented or reserved RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1055/1740 table 573. eqadc fifo and interrupt status re gister x (eqadc_fisrx) field description field description 0 ncfx non-coherency flag ncfx is set whenever a command sequence being transferred through cfifox becomes non coherent. if nciex in section , eqadc interrupt and dma control registers (eqadc_idcr) , and ncf x are asserted, an interrupt request will be generated. write ?1? to clear ncfx. writing a ?0? has no effect. for more information refer to section , command sequence non-coherency detection . 1 command sequence being transferred by cfifox became non-coherent. 0 command sequence being transferred by cfifox is coherent. 1 torfx trigger overrun flag for cfifox torfx is set when trigger overrun occurs for the specified cfifo in edge or level trigger mode. trigger overrun occurs when an already triggered cfifo receives an additional trigger. when torie x in section , eqadc interrupt and dma control registers (eqadc_idcr) , and torf x are asserted, an interrupt request will be generated. apart from generating an independent interrupt request for a cfifox trigger overrun event, the eqadc also provides a combined interrupt at which the result fifo overflow interrupt, the command fifo underflow interrupt, and the command fifo trigger overrun interrupt requests of all cfifos are ored. when rfoiex, cfuiex, and toriex are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes asserted: rfofx, cfufx, and torfx (assuming that all interrupts are enabled). see section 25.6.8, eqadc dma/interrupt request , for details. write ?1? to clear the torf x bit. writing a ?0? has no effect. 1 trigger overrun occurred. 0 no trigger overrun occurred. the trigger overrun flag will not set for cfifos configured for software trigger mode. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1056/1740 doc id 15177 rev 8 2 pfx pause flag x pf behavior changes according to the cfifo trigger mode. in edge trigger mode, pfx is set when the eqadc completes the transfer of an entry with an asserted pause bit from cfifox. in level trigger mode, when cfifox is in triggered status, pfx is set when cfifo status changes from triggered due to the detection of a closed gate. an interrupt routine, generated due to the asserted pf, can be used to verify if a complete scan of the cqueue was performed. if a closed gate is detected while no command transfers are taking place, it will have immediate effect on the cfifo status. if a closed gate is detected while a command transfer to an on-chip cbuffer is taking place, it will only affect the cfifo status when the transfer completes. if a closed gate is detected during the serial transmission of a command to the external device, it will have no effect on the cfifo status until the transmission completes. the transfer of entries bound for the on-chip adcs is considered completed when they are stored in the appropriate cbuffer. the transfer of entries bound for the external device is considered completed when the serial transmission of the entry is completed. in software trigger mode, pfx will never become asserted. if pie x in section , eqadc interrupt and dma control registers (eqadc_idcr) , and pfx are asserted, an interrupt will be generated. write ?1? to clear the pf x . writing a ?0? has no effect. refer to section , pause status , for more information on the pause flag. 1 entry with asserted pause bit was transferred from cfifox (cfifo in edge trigger mode), or cfifo status changes from triggered due to detection of a closed gate (cfifo in level trigger mode). 0 entry with asserted pause bit was not transferred from cfifox (cfifo in edge trigger mode), or cfifo status did not change from triggered due to detection of a closed gate (cfifo in level trigger mode). in edge trigger mode, an asserted pfx only implie s that the eqadc has finished transferring a command with an asserted pause bit from cfifox. it does not imply that result data for the current command and for all previously tr ansferred commands has been returned to the appropriate rfifo. in software or level trigger mode, when the eqadc completes the transfer of an entry from cfifox with an asserted pause bit, pfx will not be set and transfer of commands will continue without pausing. 3 eoqfx end of queue flag x eoqfx indicates that an entry with an asserted eoq bit was transferred from cfifox to the on-chip adcs or to the external device - see section , message format in eqadc , for details about command message formats. when the eqadc completes the transfer of an entry with an asserted eoq bit from cfifox, eoqfx will be set. the transfer of entries bound for the on-chip adcs is considered completed when they are stored in the appropriate cbuffer. the transfer of entries bound for the external device is considered completed when the serial transmission of the entry is completed. if the eoqiex bit in section , eqadc interrupt and dma control registers (eqadc_idcr) , and eoqfx are asserted, an interrupt will be generated. write ?1? to clear the eoqfx bit. writing a ?0? has no effect. refer to section , cqueue completion status , for more information on the end of queue flag. 1 entry with asserted eoq bit was transferred from cfifox. 0 entry with asserted eoq bit was not transferred from cfifox. an asserted eoqfx only implies that the eqadc has finished transferring a command with an asserted eoq bit from cfifox. it does not imply that result data for the current command and for all previously transferred commands has been returned to the appropriate rfifo. table 573. eqadc fifo and interrupt status re gister x (eqadc_fisrx) field description field description RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1057/1740 4 cfufx cfifo underflow flag x cfufx indicates an underflow event on cfifox. cfufx is set when cfifox is in triggered state and it becomes empty. no commands will be transferred from an underflowing cfifo, nor will command transfers from lower priority cfifos be blocked. when cfuiex in section , eqadc interrupt and dma control registers (eqadc_idcr) , and cfufx are both asserted, the eqadc generates an interrupt request. apart from generating an independent interrupt request for a cfifox underflow event, the eqadc also provides a combined interrupt at which the result fifo overflow interrupt, the command fifo underflow interrupt, and the command fifo trigger overrun interrupt requests of all cfifos are ored. when rfoiex, cfuiex, and toriex are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes asserted: rfofx, cfufx, and torfx (assuming that all interrupts are enabled). see section 25.6.8, eqadc dma/interrupt request , for details. write ?1? to clear cfufx. writing a ?0? has no effect. 1 a cfifo underflow event occurred. 0 no cfifo underflow event occurred. 5 sssx cfifo single-scan status bit x an asserted sssx bit enables the detection of trigger events for cfifos programmed into single-scan level- or edge-trigger mode, and works as trigger for cfifos programmed into single-scan software-trigger mode. refer to section , single-scan mode , for further details. the sssx bit is set by writing a ?1? to the ssex bit in section , eqadc cfifo control registers (eqadc_cfcr) . the eqadc clears the sssx bit when a command with an asserted eoq bit is transferred from a cfifo in single-scan mode, when a cfifo is in single-scan level-trigger mode and its status changes from triggered due to the detection of a closed gate, or when the value of the cfifo operation mode (modex) in section , eqadc cfifo control registers (eqadc_cfcr) , is changed to disabled. writing to sssx has no effect. sssx has no effect in continuous-scan or in disabled mode. 1cfifo in single-scan level- or edge-trigger mo de will detect a trigger event, or cfifo in single-scan software-trigger mode is triggered. 0cfifo in single-scan level- or edge-trigger mode will ignore trigger events, or cfifo in single-scan software-trigger mode is not triggered. 6 cfffx cfifo fill flag x cfffx is set when the cfifox is not full. when cffe x in section , eqadc interrupt and dma control registers (eqadc_idcr) , and cfffx are both asserted, an interrupt or a dma request will be generated depending on the status of the cffsx bit. when cffsx is negated (interrupt requests selected), software clears cfffx by writing a ?1? to it. writing a ?0? has no effect. when cffsx is asserted (dma requests selected), cfffx is automatically cleared by the eqadc when the cfifo becomes full. 1 cfifox is not full. 0 cfifox is full. writing ?1? to cfffx when cffsx is asserted (dma requests selected) is not allowed. when generation of interrupt requests is selected (cffsx=0), cfffx must only be cleared in the isr after the cfifox push register is accessed. table 573. eqadc fifo and interrupt status re gister x (eqadc_fisrx) field description field description enhanced queued analog-to-dig ital converter (eqadc) RM0029 1058/1740 doc id 15177 rev 8 12 rfofx rfifo overflow flag x rfofx indicates an overflow event on rfifox. rfof x is set when rfifox is already full, and a new data is received from the on-chip adcs or from the external device. the rfifox will not overwrite older data in the rfifo, and the new data will be ignored. when rfoiex in section , eqadc interrupt and dma control registers (eqadc_idcr) , and rfofx are both asserted, the eqadc generates an interrupt request. apart from generating an independent interrupt request for an rfifox overflow event, the eqadc also provides a combined interrupt at which the result fifo overflow interrupt, the command fifo underflow interrupt, and the command fifo trigger overrun interrupt requests of all cfifos are ored. when rfoiex, cfuiex, and toriex are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes asserted: rfofx, cfufx, and torfx (assuming that all interrupts are enabled). see section 25.6.8, eqadc dma/interrupt request , for details. write ?1? to clear rfofx. writing a ?0? has no effect. 1 an rfifo overflow event occurred. 0 no rfifo overflow event occurred. 14 rfdf x rfifo drain flag x rfdfx indicates if rfifox has valid entries or not. rfdfx is set when the rfifox has at least one valid entry in it. when rfdex in section , eqadc interrupt and dma control registers (eqadc_idcr) , and rfdfx are both asserted, an interrupt or a dma request will be generated depending on the status of the rfdsx bit. when rfdsx is negated (interrupt requests selected), software clears rfdfx by writing a ?1? to it. writing a ?0? has no effect. when rfdsx is asserted (dma requests selected), rfdfx is automatically cleared by the eqadc when the rfifo becomes empty. 1 rfifox has at least one valid entry. 0 rfifox is empty. writing ?1? to rfdfx when rfdsx is asserted (dma requests selected) is not allowed. when the generation of interrupt requests is selected (rfdsx=0), rfdfx must only be cleared in the isr after the rfifox pop register is accessed. 16-19 cfctrx [0:3] cfifox entry counter cfctrx indicates the number of commands stored in the cfifox. when the eqadc completes transferring a piece of new data from the cfifox, it decrements cfctrx by one. writing a word or any bytes to the corresponding section , eqadc cfifo push registers (eqadc_cfpr) , increments cfctrx by one. writing any value to cfctrx has no effect. 20-23 tnxtptrx [0:3] cfifox transfer next pointer tnxtptrx indicates the index of the next entry to be removed from cfifox when it completes a transfer. when tnxtptrx is zero, it points to the entry with the smallest memory-mapped address inside cfifox. tnxtptrx is only updated when a command transfer is completed. if the maximum index nu mber (cfifo depth minus one) is reached, tnxtptrx is wrapped to zero, else, it is incremented by one. for details refer to section , cfifo basic functionality . writing any value to tnxtptrx has no effect. table 573. eqadc fifo and interrupt status re gister x (eqadc_fisrx) field description field description RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1059/1740 eqadc cfifo transfer counter registers (eqadc_cftcr) the eqadc cfifo transfer counter registers (eqadc_cftcr) record the number of commands transferred from a cfifo. the eqadc_cftcr supports the monitoring of command transfers from a cfifo. figure 584. eqadc cfifo transfer counter register 0 (eqadc_cftcr0) 24-27 rfctrx [0:3] rfifox entry counter rfctrx indicates the number of data items stored in the rfifox. when the eqadc stores a piece of new data into rfifox , it increments rfctrx by one. reading the whole word, half-word or any bytes of the corresponding section , eqadc result fifo pop registers (eqadc_rfpr) , decrements rfctrx by one. writing any value to rfctrx itself has no effect. 28-31 popnxtptrx [0:3] rfifox pop next pointer popnxtptrx indicates the index of the entry that will be returned when eqadc_rfprx is read. when popnxtptrx is zero, it points to the entry with the smallest memory- mapped address inside rfifox. popnxtptrx is updated when eqadc_rfprx is read. if the maximum index number (rfifo depth minus one) is reached, popnxtptrx is wrapped to zero, else, it is incremented by one. for details refer to section , rfifo basic functionality . writing any value to popnxtptrx has no effect. table 573. eqadc fifo and interrupt status re gister x (eqadc_fisrx) field description field description register address: eqadc_base+0x090 0123456789101112131415 r 00000 tc_cf0 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000 tc_cf1 w reset: 0000000000000000 = unimplemented or reserved enhanced queued analog-to-dig ital converter (eqadc) RM0029 1060/1740 doc id 15177 rev 8 figure 585. eqadc cfifo transfer counter register 1 (eqadc_cftcr1) figure 586. eqadc cfifo transfer counter register 2 (eqadc_cftcr2) register address: eqadc_base+0x094 0123456789101112131415 r 00000 tc_cf2 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000 tc_cf3 w reset: 0000000000000000 = unimplemented or reserved register address:eqadc_base+0x098 0123456789101112131415 r 00000 tc_cf4 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000 tc_cf5 w reset: 0000000000000000 = unimplemented or reserved RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1061/1740 eqadc cfifo status snapshot registers (eqadc_cfssr) the eqadc cfifo status snapshot registers (eqadc_cfssr) contain status fields to track the operation status of each cfifo and the transfer counter of the last cfifo to initiate a command transfer to the internal/external cbuffers. eqadc_cfssr0-1 are related to the on-chip cbuffers (cbuffer0-1) while eqadc_cfssr2 is related to the external cbuffers. all fields of a particular eqadc_cfssr register are captured at the beginning of a command transfer to the cbuffer associated with that register. note that captured status register values are associated with previous command transfer. this means that the cfssr registers capture the status registers before the status registers change because of the transfer of the current command that is about to be popped from the cfifo. the eqadc_cfssr registers are read only. writing to the eqadc_cfssr registers has no effect. figure 587. eqadc cfifo status snapshot register 0 (eqadc_cfssr0) table 574. eqadc cfifo transfer counter regi ster x (eqadc_cftcrx) field description field description tc_cfx [0:10] transfer counter for cfifox tc_cfx counts the number of commands which have been completely transferred from cfifox. the transfer of entries bound for the on-chip adcs is considered completed when they are stored in the appropriate cbuffer. the transfer of entries bound for an external device is considered completed when the serial transmission of the entry is completed. the eqadc increments the tc_cfx value by one after a command is transferred. tc_cfx resets to zero after eqadc completes transferring a command with an asserted eoq bit. writing any value to tc_cfx sets the counter to that written value. if cfifox is in triggered state when its mode x field is programmed to disabled, the exact number of entries transferred from the cfifo until that point - tc_cfx - is only known after the cfifo status changes to idle, as i ndicated by cfsx. for details refer to section , disabled mode . register address: eqadc_base+0x0a0 0123456789101112131415 r cfs0_tcb 0 cfs1_tcb 0 cfs2_tcb 0 cfs3_tcb 0 cfs4_tcb 0 cfs5_tcb 0 0000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 lcftcb0 tc_lcftcb0 w reset: 0111100000000000 = unimplemented or reserved enhanced queued analog-to-dig ital converter (eqadc) RM0029 1062/1740 doc id 15177 rev 8 figure 588. eqadc cfifo status snapshot register 1 (eqadc_cfssr1) figure 589. eqadc cfifo status snapshot register 2 (eqadc_cfssr2) register address: eqadc_base+0x0a4 0123456789101112131415 r cfs0_tcb 1 cfs1_tcb 1 cfs2_tcb 1 cfs3_tcb 1 cfs4_tcb 1 cfs5_tcb 1 0000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 lcftcb1 tc_lcftcb1 w reset: 0111100000000000 = unimplemented or reserved register address: eqadc_base+0x0a8 0123456789101112131415 r cfs0_tssi cfs1_tssi cfs2_tssi cfs3_tssi cfs4_tssi cfs5_tssi 0 0 0 0 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ecb ni lcftssi tc_lcftssi w reset: 0111100000000000 = unimplemented or reserved RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1063/1740 table 575. eqadc cfifo status snapshot regi ster x (eqadc_cfssrx) field description field description cfsx_tcb n [0:1] cfifo status at transfer to cbuffer n (n=0,1) cfsx_tcb n indicates the cfifox status of previously completed command transfer. cfsx_tcb n is a copy of the corresponding cfsx in the section , eqadc cfifo status register (eqadc_cfsr) , captured at the time a current command transfer to cbuffer n is initiated. lcftcb n [0:3] last cfifo to transfer to cbuffer n (n=0,1) lcftcb n holds the cfifo number to have completed a previous command transfer to cbuffer n , see table 576 . tc_lcftcb n [0:10] transfer counter for last cfifo to transfer commands to cbuffer n tc_lcftcb n indicates the number of commands which have been completely transferred from cfifox when a current command transfer from cfifox to cbuffer n is initiated. tc_lcftcb n is a copy of the corresponding tc_cfx in the section , eqadc cfifo transfer counter registers (eqadc_cftcr) , captured at the time a current command transfer from cfifox to cbuffer n is initiated. this field has no meaning when lcftcb n is 0b1111. cfsx_tssi [0:1] cfifo status at transfer through the eqadc ssi cfsx_tssi indicates the cfifox status of previously completed serial transmission through the eqadc ssi. cfsx_tssi is a copy of the corresponding cfsx in the section , eqadc cfifo status register (eqadc_cfsr) , capture at the time a current serial transmission through the eqadc ssi is initiated. ecbni external cbuffer number indicator ecbni indicates to which external cbuffer the previous command was transmitted. 1 last command was transferred to cbuffer3. 0 last command was transferred to cbuffer2. lcftssi[0:3] last cfifo to transfer commands through the eqadc ssi. lcftssi holds the cfifo number to have completed a previous command transfer to an external cbuffer through the eqadc ssi, see table 577 . lcftssi does not indicate the transmission of null messages. tc_lcfssi [0:10] transfer counter for last cfifo to transfer commands through eqadc ssi tc_lcftssi indicates the number of commands which have been completely transferred from a particular cfifo when a command transfer from that cfifo to an external cbuffer is initiated. tc_lcftssi is a copy of the corresponding tc_cfx in the section , eqadc cfifo transfer counter registers (eqadc_cftcr) , captured at the time a current command transfer to an external cbuffer is initiated. this field has no meaning when lcftssi is 0b1111. table 576. lcftcb n description lcftcb n [0:3] lcftcb n meaning 0b0000 last command was transferred from cfifo0 0b0001 last command was transferred from cfifo1 0b0010 last command was transferred from cfifo2 0b0011 last command was transferred from cfifo3 0b0100 last command was transferred from cfifo4 enhanced queued analog-to-dig ital converter (eqadc) RM0029 1064/1740 doc id 15177 rev 8 eqadc cfifo status register (eqadc_cfsr) the eqadc cfifo status register (eqadc_cfsr) contains the current cfifo status. the eqadc_cfsr registers is read only. writing to the eqadc_cfsr register has no effect. figure 590. eqadc cfifo status register (eqadc_cfsr) 0b0101 last command was transferred from cfifo5 0b0110 - 0b1110 reserved 0b1111 no command was transferred to cbuffer n table 576. lcftcb n description (continued) lcftcb n [0:3] lcftcb n meaning table 577. lcftssi description lcftssi[0:3] lcftssi meaning 0b0000 last command was transferred from cfifo0 0b0001 last command was transferred from cfifo1 0b0010 last command was transferred from cfifo2 0b0011 last command was transferred from cfifo3 0b0100 last command was transferred from cfifo4 0b0101 last command was transferred from cfifo5 0b0110 - 0b1110 reserved 0b1111 no command was transferred to an external cbuffer register address: eqadc_base+0x0ac 0123456789101112131415 r cfs0 cfs1 cfs2 cfs3 cfs4 cfs5 0 0 0 0 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w reset: 0000000000000000 = unimplemented or reserved RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1065/1740 eqadc ssi control register (eqadc_ssicr) the eqadc ssi control register (eqadc_ssicr) configures the ssi sub-block. table 578. field description field description cfsx[0:1] cfifo status cfsx indicates the current status of cfifo x . refer to table 579 for more information on cfifo status. table 579. current cfifo status cfifo status field value explanation idle 0b00 cfifo is disabled. cfifo is in single-scan edge or level trigger mode and does not have sss asserted. eqadc completed the transfer of the last entry of the cqueue in single-scan mode. reserved 0b01 not applicable. waiting for trigger 0b10 cfifo mode is modified to continuous-scan edge or level trigger mode. cfifo mode is modified to single-scan edge or level trigger mode and sss is asserted. cfifo mode is modified to single-scan software trigger mode and sss is negated. cfifo is paused. eqadc transferred the last entry of the queue in continuous-scan edge trigger mode. triggered 0b11 cfifo is triggered enhanced queued analog-to-dig ital converter (eqadc) RM0029 1066/1740 doc id 15177 rev 8 figure 591. eqadc ssi control register (eqadc_ssicr) register address: eqadc_base+0x0b4 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000 mdt 0000 br w reset: 0000011100001111 = unimplemented or reserved table 580. eqadc ssi control register (eqadc_ssicr) field description field description 21-23 mdt[0:2] minimum delay after transmission mdt field defines the minimum delay after transmission time (t mdt ) expressed in serial clock (fck) periods. t mdt is minimum time sds should be kept negated between two consecutive serial transmissions. table 581 lists the minimum delay after transfer time according to how mdt is set. the mdt field must only be written when the serial transmissions from the eqadc ssi are disabled - see essie field in section , eqadc module configuration register (eqadc_mcr) . 28-31 br[0:3] baud rate field the br field selects system clock divide factor as shown in table 582 . the baud clock is calculated by dividing the system clock by the clock divide factor specified with the br field. the br field must only be written when the eqadc ssi is disabled - see essie field in section , eqadc module configuration register (eqadc_mcr) . table 581. minimum delay after transmission (t mdt ) time mdt t mdt (fck period) 0b000 1 0b001 2 0b010 3 0b011 4 RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1067/1740 eqadc ssi receive data register (eqadc_ssirdr) the eqadc ssi receive data register (eqadc_ssirdr) records the last message received from the external device. 0b100 5 0b101 6 0b110 7 0b111 8 table 582. system clock divide factor for baud clock br[0:3] system clock divide factor (1) 0b0000 2 0b0001 3 0b0010 4 0b0011 5 0b0100 6 0b0101 7 0b0110 8 0b0111 9 0b1000 10 0b1001 11 0b1010 12 0b1011 13 0b1100 14 0b1101 15 0b1110 16 0b1111 17 1. if the system clock is divided by a odd number then t he serial clock will have a duty cycle different from 50%. table 581. minimum delay after transmission (t mdt ) time mdt t mdt (fck period) enhanced queued analog-to-dig ital converter (eqadc) RM0029 1068/1740 doc id 15177 rev 8 figure 592. eqadc ssi receive data register (eqadc_ssirdr) eqadc stac client configuration register (eqadc_redlccr) the eqadc stac client configuration regi ster (eqadc_redlccr) contains bits used to control which time slots the eqadc selects to obtain pre-defined external time bases. register address: eqadc_base+0x0b8 0123456789101112131415 rrdv00000 r_data w reset: 0000000000001111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rr_data w reset: 0000000000000000 = unimplemented or reserved table 583. eqadc ssi receive data register (eqadc_ssirdr) field description field description 0 rdv receive data valid bit the rdv bit indicates if the last received data is valid. this bit is cleared automatically whenever the eqadc_ssirdr register is read. writes have no effect. 1 receive data is valid. 0 receive data is not valid. 6-31 r_data [0:25] eqadc receive data field the r_data contains the last result message that was shifted in. writes to the r_data have no effect. messages that were not completely received due to a transmission abort will not be copied into eqadc_ssirdr. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1069/1740 figure 593. eqadc stac client config uration register (eqadc_redlccr) s register address: eqadc_base+0x0d0 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r redbs2 srv2 redbs1 srv1 w reset: 0000000000000000 = unimplemented or reserved table 584. eqadc stac client configuration register (eqadc_redlccr) field description field description redbs m [0:3] stac timebase bits selection, where m ( m =1,2) the redbs m field selects 16 bits from the total of 24 bits that are received from the stac interface as described in below. consider tbase m [0:23] the selected time base from slot srv m: srv m [0:3] stac bus server data slot selector m ( m =1,2) the field srv m indicates the slot number that contains the desired time base value sent by the stac server. it is possible to have up to 16 different sources to be selected. table 585. stac bus timebase bits selection redbs m [0:3] selected bits 0b0000 tbase m [0:15] 0b0001 tbase m [1:16] 0b0010 tbase m [2:17] 0b0011 tbase m [3:18] 0b0100 tbase m [4:19] 0b0101 tbase m [5:20] 0b0110 tbase m [6:21] 0b0111 tbase m [7:22] 0b1000 tbase m [8:23] others reserved enhanced queued analog-to-dig ital converter (eqadc) RM0029 1070/1740 doc id 15177 rev 8 eqadc cfifo registers (eqadc_cfxrw) (x=0, ..,5; w=0, .., 3) the eqadc cfifo registers (eqadc_cfxrw) (x=0, .., 5; w=0, .., 3) provide visibility of the contents of a cfifo for debugging purposes. each cfifo has four registers which are uniquely mapped to its four 32-bit entries. refer to section 25.6.4, eqadc command fifos , for more information on cfifos. these registers are read only. data written to these registers is ignored. figure 594. eqadc cfifo0 registers (eqadc_cf0rw) (w=0, .., 3) table 586. srvm valid values srv m [0:3] time base 0b0000 etpu engine a, tcr1 0b0001 reserved 0b0010 etpu engine a, tcr2 0b0011 reserved 0b0100?0b1111 reserved register address: eqadc_base+0x100 register address: eqadc_base+0x104 register address: eqadc_base+0x108 register address: eqadc_base+0x10c 0123456789101112131415 r cfifo0_dataw w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfifo0_dataw w reset: 0000000000000000 RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1071/1740 figure 595. eqadc cfifo1 registers (eqadc_cf1rw) (w=0, .., 3) figure 596. eqadc cfifo2 registers (eqadc_cf2rw) (w=0, .., 3) register address: eqadc_base+0x140 register address: eqadc_base+0x144 register address: eqadc_base+0x148 register address: eqadc_base+0x14c 0123456789101112131415 r cfifo1_dataw w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfifo1_dataw w reset: 0000000000000000 register address: eqadc_base+0x180 register address: eqadc_base+0x184 register address: eqadc_base+0x188 register address: eqadc_base+0x18c 0123456789101112131415 r cfifo2_dataw w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfifo2_dataw w reset: 0000000000000000 enhanced queued analog-to-dig ital converter (eqadc) RM0029 1072/1740 doc id 15177 rev 8 figure 597. eqadc cfifo3 registers (eqadc_cf3rw) (w=0, .., 3) figure 598. eqadc cfifo4 registers (eqadc_cf4rw) (w=0, .., 3) register address: eqadc_base+0x1c0 register address: eqadc_base+0x1c4 register address: eqadc_base+0x1c8 register address: eqadc_base+0x1cc 0123456789101112131415 r cfifo3_dataw w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfifo3_dataw w reset: 0000000000000000 register address: eqadc_base+0x200 register address: eqadc_base+0x204 register address: eqadc_base+0x208 register address: eqadc_base+0x20c 0123456789101112131415 r cfifo4_dataw w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfifo4_dataw w reset: 0000000000000000 RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1073/1740 figure 599. eqadc cfifo5 registers (eqadc_cf5rw) (w=0, .., 3) eqadc cfifo0 extension registers (eqadc_cf0erw) (w=0, .., 3) the eqadc cfifo0 extension registers (eqadc_cf0erw) (w=0, .., 3) provide visibility of the contents of the extended portion of cfifo0 for debugging purposes. there are four registers which are uniquely mapped to its four 32-bit entries. refer to section 25.6.4, eqadc command fifos , for more information on cfifos. these registers are read only. data written to these registers is ignored. register address: eqadc_base+0x240 register address: eqadc_base+0x244 register address: eqadc_base+0x248 register address: eqadc_base+0x24c 0123456789101112131415 r cfifo5_dataw w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfifo5_dataw w reset: 0000000000000000 table 587. eqadc cfifox registers (eqadc_cfxrw) (w=0, .., 3) field description field description 0-31 cfifox_dataw [0:31] cfifox data w (w = 0, .., 3) reading cfifox_dataw returns the value stored on the wth entry of cfifox. each cfifo is composed of four 32-bit entries, with register 0 being mapped to the one with the smallest memory mapped address. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1074/1740 doc id 15177 rev 8 figure 600. eqadc cfifo0 extension regi sters (eqadc_cf0erw) (w=0, .., 3) eqadc rfifo registers (eqadc_rfxrw) (x=0, .., 5; w=0, .., 3) the eqadc rfifo registers (eqadc_rfxrw) (x=0, .., 5; w=0, .., 3) provide visibility of the contents of a rfifo for debugging purposes. each rfifo has four registers which are uniquely mapped to its four 16-bit entries. refer to section 25.6.5, eqadc result fifos , for more information on rfifos. these registers are read only. data written to these registers is ignored. register address: eqadc_base+0x110 register address: eqadc_base+0x114 register address: eqadc_base+0x118 register address: eqadc_base+0x11c 0123456789101112131415 r cfifo0_edataw w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cfifo0_edataw w reset: 0000000000000000 table 588. field description field description 0-31 cfifox_edataw [0:31] cfifox data w (w = 0, .., 3) reading cfifox_dataw returns the value stored on the wth entry of cfifox. each cfifo is composed of four 32-bit entries, with register 0 being mapped to the one with the smallest memory mapped address. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1075/1740 figure 601. eqadc rfifo0 registers (eqadc_rf0rw) (w=0, .., 3) figure 602. eqadc rfifo1 registers (eqadc_rf1rw) (w=0, .., 3) register address: eqadc_base+0x300 register address: eqadc_base+0x304 register address: eqadc_base+0x308 register address: eqadc_base+0x30c 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rfifo0_dataw w reset: 0000000000000000 register address: eqadc_base+0x340 register address: eqadc_base+0x344 register address: eqadc_base+0x348 register address: eqadc_base+0x34c 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rfifo1_dataw w reset: 0000000000000000 enhanced queued analog-to-dig ital converter (eqadc) RM0029 1076/1740 doc id 15177 rev 8 figure 603. eqadc rfifo2 registers (eqadc_rf2rw) (w=0, .., 3) figure 604. eqadc rfifo3 registers (eqadc_rf3rw) (w=0, .., 3) register address: eqadc_base+0x380 register address: eqadc_base+0x384 register address: eqadc_base+0x388 register address: eqadc_base+0x38c 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rfifo2_dataw w reset: 0000000000000000 register address: eqadc_base+0x3c0 register address: eqadc_base+0x3c4 register address: eqadc_base+0x3c8 register address: eqadc_base+0x3cc 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rfifo3_dataw w reset: 0000000000000000 RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1077/1740 figure 605. eqadc rfifo4 registers (eqadc_rf4rw) (w=0, .., 3) figure 606. eqadc rfifo5 registers (eqadc_rf5rw) (w=0, .., 3) register address: eqadc_base+0x400 register address: eqadc_base+0x404 register address: eqadc_base+0x408 register address: eqadc_base+0x40c 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rfifo4_dataw w reset: 0000000000000000 register address: eqadc_base+0x440 register address: eqadc_base+0x444 register address: eqadc_base+0x448 register address: eqadc_base+0x44c 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rfifo5_dataw w reset: 0000000000000000 enhanced queued analog-to-dig ital converter (eqadc) RM0029 1078/1740 doc id 15177 rev 8 25.5.3 on-chip adc registers this section describes a list of registers that control on-chip adc operation. the adc registers are not part of the cpu accessible memory map. these registers can only be accessed indirectly through configuration commands. there are 4 non memory mapped registers per adc, plus 12 registers shared by both adcs. the address, usage, and access privilege of each register is shown in table 590 . data written to or read from reserved areas of the memory map is undefined. their assigned addresses are the values used to set the adc_reg_address field of the read/write configurations commands bound for the on-chip adcs. these are half-word addresses. further, the following restrictions apply when accessing these registers: registers adc0_cr, adc0_gccr, adc0_occr, adc0_agr1/2 and adc0_aor1/2 can only be accessed by configuration commands sent to cbuffer0. registers adc1_cr, adc1_gccr, adc1_occr, adc1_agr1/2 and adc1_aor1/2 can only be accessed by configuration commands sent to cbuffer1. registers adc_tscr, adc_tbcr, adc_acr1-8 and adc_pudcr0-7 can be accessed by configuration commands sent to cbuffer0 or to cbuffer1. a data write to any of these registers through a configuration command sent to cbuffer0 will write the same memory location as when writing to it through a configuration command sent to cbuffer1. note: simultaneous write accesses from cbuffer0 and cbuffer1 to any of the shared registers are not allowed. table 589. eqadc rfifox registers (eqadc_rfxrw) (w=0, .., 3) field description field description 0-31 rfifox_dataw [0:15] rfifox data w (w = 0, .., 3) reading rfifox_dataw returns the value stored on the wth entry of rfifox. each rfifo is composed of four 16-bit entries, with register 0 being mapped to the one with the smallest memory mapped address. table 590. on-chip adc memory map adc address use access 0x00 adc0/adc1 (1) conversion command for standard configuration (see section , conversion command format for the standard configuration ) write 0x01 adc0/adc1 configuration control register (adc0_cr, adc1_cr) write/read 0x02 time stamp control register (adc_tscr) write/read 0x03 time base counter register (adc_tbcr) write/read 0x04 adc0/adc1 gain calibration constant register (adc0_gccr, adc1_gccr) write/read 0x05 adc0/adc1 offset calibration constant register (adc0_occr, adc1_occr) write/read 0x06- 0x07 reserved - 0x08 adc0/adc1 conversion command for alternate configuration 1 (see section , conversion command format for alternate configurations ) write 0x09 adc0/adc1 conversion command for alternate configuration 2 (see section , conversion command format for alternate configurations ) write 0x0a adc0/adc1 conversion command for alternate configuration 3 (see section , conversion command format for alternate configurations ) write RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1079/1740 0x0b adc0/adc1 conversion command for alternate configuration 4 (see section , conversion command format for alternate configurations ) write 0x0c adc0/adc1 conversion command for alternate configuration 5 (see section , conversion command format for alternate configurations ) write 0x0d adc0/adc1 conversion command for alternate configuration 6 (see section , conversion command format for alternate configurations ) write 0x0e adc0/adc1 conversion command for alternate configuration 7 (see section , conversion command format for alternate configurations ) write 0x0f adc0/adc1 conversion command for alternate configuration 8 (see section , conversion command format for alternate configurations ) write 0x10-0x2f reserved - 0x30 alternate configuration 1 control register (adc_acr1) write/read 0x31 adc0/adc1 alternate gain 1 register (adc0_agr1, adc1_agr1) write/read 0x32 adc0/adc1 alternate offset 1 register (adc0_aor1, adc1_aor1) write/read 0x33 reserved - 0x34 alternate configuration 2 control register (adc_acr2) write/read 0x35 adc0/adc1 alternate gain 2 register (adc0_agr2, adc1_agr2) write/read 0x36 adc0/adc1 alternate offset 2 register (adc0_aor2, adc1_aor2) write/read 0x37 reserved - 0x38 alternate configuration 3 control register (adc_acr3) write/read 0x39 reserved - 0x3a reserved - 0x3b reserved - 0x3c alternate configuration 4 control register (adc_acr4) write/read 0x3d reserved - 0x3e reserved - 0x3f reserved - 0x40 alternate configuration 5 control register (adc_acr5) write/read 0x41 reserved - 0x42 reserved - 0x43 reserved - 0x44 alternate configuration 6 control register (adc_acr6) write/read 0x45 reserved - 0x46 reserved - 0x47 reserved - 0x48 alternate configuration 7 control register (adc_acr7) write/read 0x49 reserved - 0x4a reserved - 0x4b reserved - 0x4c alternate configuration 8 control register (adc_acr8) write/read 0x4d-0x6f reserved - 0x70 pull up/down control register0 (adc_pudcr0) write/read table 590. on-chip adc memory map (continued) adc address use access enhanced queued analog-to-dig ital converter (eqadc) RM0029 1080/1740 doc id 15177 rev 8 adc0/1 control registers (adc0_cr and adc1_cr) the adc0/1 control registers (adc0/1_cr) is used to define the standard configuration of the adc. in the standard configuration, the parameters contained in the alternate configuration control registers (adc_acr1-8) are fixed at their reset value. a conversion uses the standard configuration when the conversion command (with the standard format) is written to address 0x00 of the on-chip adc memory map. refer to section , conversion command format for the standard configuration . 0x71 pull up/down control register0 (adc_pudcr1) write/read 0x72 pull up/down control register0 (adc_pudcr2) write/read 0x73 pull up/down control register0 (adc_pudcr3) write/read 0x74 pull up/down control register0 (adc_pudcr4) write/read 0x75 pull up/down control register0 (adc_pudcr5) write/read 0x76 pull up/down control register0 (adc_pudcr6) write/read 0x77 pull up/down control register0 (adc_pudcr7) write/read 0x78-0x97 reserved for adc_pudcr8 to adc_pudcr39 - 0x98-0xff reserved - 1. throughout the table, adc0/adc1 indicates that if the command is stored in cbuffer0 it will be applied to adc0 and if in cbuffer1 it applies to adc1. if this indication is omitt ed the register applies for both adc0 and adc1, independent of the cbuffer used. table 590. on-chip adc memory map (continued) adc address use access figure 607. adc0/1 control registers (adc0/1_cr) adc0 register address: 0x01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r adc0 _en 0 0 0 adc0 _emu x 0 adc0 _tbsel adc0 _odd _ps adc0 _clk_ dty adc0 _clk _ sel adc0_clk_ps w reset: 0 0 0 0 0 0 0 0 0 0 0 1 1111 adc1 register address: 0x01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r adc1 _en 0 0 0 adc1 _emu x 0 adc1 _tbsel adc1 _odd _ps adc1 _clk_ dty adc1 _clk _ sel adc1_clk_ps w reset: 0 0 0 0 0 0 0 0 0 0 0 1 1111 = unimplemented or reserved RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1081/1740 table 591. adc0/1 control registers (adc0/1_cr) field description field description 0 adc0/1_en enable bit for adc0/1 adc0/1_en enables adc0/1 to perform a/d conversions. refer to section , enabling and disabling the on-chip adcs , for details. 1 adc is enabled and ready to perform a/d conversions. 0 adc is disabled. clock supply to adc0/1 is stopped. conversion commands sent to the cbuffer of a disabled adc are ignored by the adc control hardware. when the adc0/1_en status is changed from asse rted to negated, the adc clock will not stop until it reaches its low phase. 4 adc0/1_emux external multiplexer enable for adc0/1 when adc0/1_emux is asserted, the ma pins will output digital values according to the number of the external channel being converted for selecting external multiplexer inputs. refer to section 25.6.7, internal/external multiplexing , for a detailed description about how adc0/1_emux affects channel number decoding. 1 external multiplexer enabled; external multiplexer channels can be selected. 0 external multiplexer disabled; no external multiplexer channels can be selected. both adc0 and adc1 of an eqadc module pair must be enabled before calibrating or using either adc0 or adc1 of the pair. failure to enable both adc0 and adc1 of the pair can result in inaccurate conversions. both adc0/1_emux bits must not be asserted at the same time. the adc0/1_emux bit must only be written when the adc0/1_en bit is negated. adc0/1_emux can be set during the same write cycle used to set adc0/1_en. 6-7 adc0/1_tbsel [0:1] timebase selection for adc0/1 the adc0/1_tbsel[0:1] field selects the time information to be used as timestamp according to table 592 . this selection is overriden by the corresponding fi eld atbsel in the adc_acr1-8 registers when the alternate conversion command is used. 8 adc0/1_odd_ps clock prescaler odd rates selector for adc0/1 the adc0/1_clk_dty field controls the duty rate of the adc0/1 clock when the adc0/1_clk_ps field is asserted. the generated clock has an odd number of system clock cycles, therefore this field is used to select a clock duty higher or lower than 50%. 1 odd divide factor is selected. the final divide factor is dependent of adc0/1_clk_ps field. 0 even divide factor is selected. the final divide factor is dependent of adc0/1_clk_ps field. 9 adc0/1_clk_dty clock duty rate selector for adc0/1 (for odd divide factors) the adc0/1_odd_ps field is used together with the adc0/1_clk_ps field to define even/odd divide factors in the generation of the adc0/1 clocks. refer to table 593 for available divide factors. 1 clock high pulse is longer 1 clock cycle than low portion. 0 clock low interval is longer 1 clock cycle than high pulse. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1082/1740 doc id 15177 rev 8 10 adc0/1_clk_sel clock selector for adc0/1 the adc0/1_clk_sel is used to select between the system clock signal or the prescaler output signal. the prescaler provides the system clock signal divided by a even factor from 2 to 64. this is required to permit the adc to run as fast as possible when the device is in low power active mode and system clock is around 1 mhz. 1 system clock is selected - maximum frequency. 0 prescaler output clock is selected. the adc0/1_clk_sel bits must only be wr itten when the adc0/1_en bit is negated. adc0/1_clk_sel can be set during the same write cycle used to set adc0/1_en. 11-15 adc0/1_clk_ps [0:4] clock prescaler field for adc0/1 the adc0/1_clk_ps field controls the system clock divide factor for the adc0/1 clock as in table 593 . see section , adc clock and conversion speed, for details about how to set adc0/1_clk_ps. the adc0/1_clk_ps field must only be written when the adc0/1_en bit is negated. this field can be configured during the same write cycle used to set adc0/1_en. table 591. adc0/1 control registers (adc0/1_cr) field description (continued) field description table 592. timebase selection adc0/1_tbsel[0:1] definition 00 selects internally generated time base as time stamp. 01 selects imported time base 1 indicated by srv1 bit field of eqadc_redlccr register. 10 selects imported time base 2 indicated by srv2 bit field of eqadc_redlccr register. 11 reserved table 593. system clock divide factor for adc clock adc0/1_clk_ps[0:4] system clock divide factor adc0/1_odd_ps = 0 adc0/1_odd_ps = 1 0b00000 2 3 0b00001 4 5 0b00010 6 7 0b00011 8 9 0b00100 10 11 0b00101 12 13 0b00110 14 15 0b00111 16 17 0b01000 18 19 RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1083/1740 adc time stamp control register (adc_tscr) the adc time stamp control register (adc_tscr) contains a system clock divide factor used in the making of the time base counter clock. it determines at what frequency the time base counter will run. adc_tscr can be accessed by configuration commands sent to cbuffer0 or to cbuffer1. a data write to adc_tscr through a configuration command sent to cbuffer0 will write the same memory location as when writing to it through a configuration command sent to cbuffer1. note: simultaneous write accesses from cbuffer0 and cbuffer1 to adc_tscr are not allowed. 0b01001 20 21 0b01010 22 23 0b01011 24 25 0b01100 26 27 0b01101 28 29 0b01110 30 31 0b01111 32 33 0b10000 34 35 0b10001 36 37 0b10010 38 39 0b10011 40 41 0b10100 42 43 0b10101 44 45 0b10110 46 47 0b10111 48 49 0b11000 50 51 0b11001 52 53 0b11010 54 55 0b11011 56 57 0b11100 58 59 0b11101 60 61 0b11110 62 63 0b11111 64 65 table 593. system clock divide factor for adc clock (continued) adc0/1_clk_ps[0:4] system clock divide factor adc0/1_odd_ps = 0 adc0/1_odd_ps = 1 enhanced queued analog-to-dig ital converter (eqadc) RM0029 1084/1740 doc id 15177 rev 8 note: if tbc_clk_ps is not set to disabled, it must not be changed to any other value besides disabled. if tbc_clk_ps is set to disabled it can be changed to any other value. figure 608. adc time stamp control register (adc_tscr) adc0/1 register address: 0x02 0123456789101112131415 r 000000000000 tbc_clk_ps w reset: 0000000000000000 = unimplemented or reserved table 594. adc time stamp control register (adc_tscr) field description field description 12-15 tbc_clk_ps [0:3] time base counter clock prescaler the tbc_clk_ps field contains the system clock divide factor for the time base counter. it controls the accuracy of the time stamp. the prescaler is disabled when tbc_clk_ps is set to 0b0000. table 595. clock divide factor for time stamp tbc_clk_ps[0:3] system clock divide factor clock to time stamp counter for a 120 mhz system clock (mhz) 0b0000 disabled disabled 0b0001 1 120 0b0010 2 60 0b0011 4 30 0b0100 6 20 0b0101 8 15 0b0110 10 12 0b0111 12 10 0b1000 16 7.5 0b1001 32 3.75 0b1010 64 1.88 0b1011 128 0.94 0b1100 256 0.47 0b1101 512 0.23 0b1110 - 0b1111 reserved - RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1085/1740 adc time base counter registers (adc_tbcr) the adc time base counter register (adc_tbcr) contains the current value of the time base counter. adc_tbcr can be accessed by configuration commands sent to cbuffer0 or to cbuffer1. a data write to adc_tbcr through a configuration command sent to cbuffer0 will write the same memory location as when writing to it through a configuration command sent to cbuffer1. note: simultaneous write accesses from cbuffer0 and cbuffer1 to adc_tbcr are not allowed. adc0/1 gain calibration constant registers (adc0_gccr and adc1_gccr) the adc0/1 gain calibration constant register (adc0/1_gccr) contains the gain calibration constant used to fine-tune the adc0/1 conversion results. refer to section , adc calibration feature , for details about the calibration scheme used in the eqadc. figure 609. adc time base counter register (adc_tbcr) adc0/1 register address: 0x03 0123456789101112131415 r tbc_value w reset: 0000000000000000 = unimplemented or reserved table 596. adc time base counter register (adc_tbcr) field description field description 0-15 tbc_value [0:15] time base counter value field the tbc_value field contains the current value of the time base counter. reading tbc_value returns the current value of time base counter. writes to tbc_value register load the written data to the counter. the time base counter counts from 0x0000 to 0xffff and wraps when reaching 0xffff. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1086/1740 doc id 15177 rev 8 adc0/1 offset calibration constant registers (adc0_occr and adc1_occr) the adc0/1 offset calibration constant re gister (adc0/1_occr) c ontains the offset calibration constant used to fine-tune of adc0/1 conversion results. the offset constant is a signed 14-bit integer value. refer to section , adc calibration feature , for details about the calibration scheme used in the eqadc. figure 610. adc0/1 gain calibration constant registers (adc0/1_gccr) adc0 register address: 0x04 0123456789101112131415 r0 gcc0 w reset: 0100000000000000 adc1 register address: 0x04 0123456789101112131415 r0 gcc1 w reset: 0100000000000000 = unimplemented or reserved table 597. adc0/1 gain calibration constant registers (adc0/1_gccr) field description field description 1-15 gcc0/1 [0:14] gain calibration constant for adc0/1 gcc0/1 contains the gain calibration constant used to fine-tune adc0/1 conversion results. it is a unsigned 15-bit fixed pointed value. the gain calibration constant is an unsigned fixed point number expressed in the gcc_int.gcc_frac binary format. the integer part of the gain constant (gcc_int) contains a single binary digit while its fractional part (gcc_frac) contains fourteen digits. for details about the gcc data format refer to section , mac unit and operand data format . RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1087/1740 alternate configuration 1-8 control registers (adc_acr1-8) the alternate configuration control registers (adc_acr1-8) are used to configure the alternate configurations of the adc. there are 8 possible alternate configurations, each one associated with one of the adc_acr1-8 registers. all alternate configurations share the same standard configuration parameters from the adc0/1_cr registers, plus additional configuration parameters contained in the adc_acr1-8. a conversion uses one of the alternate configurations when the conversion command (with the alternate configuration format) is written to an address in the range 0x08-0x0f of the on-chip adc memory map. refer to section , conversion command format for alternate configurations . figure 611. adc0/1 offset calibration constant registers (adc0/1_occr) adc0 register address: 0x05 0123456789101112131415 r00 occ0 w reset: 0000000000000000 adc1 register address: 0x05 0123456789101112131415 r00 occ1 w reset: 0000000000000000 = unimplemented or reserved table 598. adc0/1 offset calibration consta nt registers (adc0/1_o ccr) field description field description 2-15 occ0/1 [0:13] offset calibration constant of adc0/1 occ0/1 contains the offset calibration constant used to fine-tune adc0/1 conversion results. negative values should be expressed using the two?s complement representation. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1088/1740 doc id 15177 rev 8 figure 612. alternate configuration 1-8 control registers (adc_acr1-8) adc0/1 register address: 0x30 adc0/1 register address: 0x34 adc0/1 register address: 0x38 adc0/1 register address: 0x3c adc0/1 register address: 0x40 adc0/1 register address: 0x44 adc0/1 register address: 0x48 adc0/1 register address: 0x4c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ret_ inh 0 dest fmta 0 ressel 00 atbsel pre_gain w reset: 0 0 0 0 0 0 0 000000000 = unimplemented or reserved table 599. alternate configuration 1-8 cont rol registers (adc_acr1-8) field description field description 0 ret_inh result transfer inhibit / decimation filter pre-fill this bit is used to inhibit the transfer of the result data from the peripheral module to the result queue. when the module is a decimation filter, this bit sets the filter in a special mode (pre-fill) in which it does not generate decimated samples out from the conversion results received from the eqadc block, but the conversion samples are used by the filter algorithm. this feature allows a proper initialization of the decimation filter without generating any decimated result. or this bit is useful for sending the result of the adc to the stac bus master but not putting the result in the result queue. 1 no result transfer to result queue / decimation filter pre-fill mode 0 result transfer to result queue / decimation filter in filtering mode 2-5 dest [0:3] conversion result destination selection the dest[0:3] field selects the destination of the conversion result generated by the alternate conversion command as shown in table 600 . this field also affects the behavior of the fmta bit and the ffmt bit of the conversion command for alternate configurations (see section , conversion command format for alternate configurations ). 6 fmta conversion data format for alternate configuration if the dest field is not 0b000, the fmta bit specifies how the 12-bit conversion data returned by the adcs is formatted into the 16-bit data which is sent to the parallel side interface. 1 right justified signed 0 right justified unsigned 8-9 ressel [0:1] adc resolution selection the ressel[0:1] field selects the resolution of the adc according to table 601 . RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1089/1740 12-13 atbsel [0:1] alternate command timebase selector the atbsel[0:1] field selects the time information to be used as timestamp according to table 602 . this selection overrides the corresponding fiel ds adc0/1_tbsel in the adc0/1_cr registers when the alternate conversion command is used. 14-15 pre_gain [0:1] adc pre-gain control the pre_gain[0:1] controls the gain of the adc input stage by changing the internal adc iterations in the gain stage. the gain is selected according to table 603 . table 599. alternate configuration 1-8 contro l registers (adc_acr1-8) field description field description table 600. conversion destination selection dest[0:3] description 0000 the conversion result is sent to the rfifos. the data format is specified by the ffmt bit in the conversion command. 0001 the conversion result is sent to the parallel side interface of decimation filter a. the data format is specified by the fmta bit in the alternate configuration control register. 0010 the conversion result is sent to the parallel side interface of decimation filter b. the data format is specified by the fmta bit in the alternate configuration control register. 0011 - 1110 unused. 1111 the conversion result is sent to the parallel side interface of reaction module. the data format is specified by the fmta bit in the alternate configuration control register. table 601. resolution selection ressel[0:1] definition 00 adc set to 12-bits resolution 01 adc set to 10-bits resolution 10 adc set to 8-bits resolution 11 reserved table 602. timebase selection atbsel[0:1] definition 00 selects internally generated time base as time stamp. 01 selects imported time base 1 indicated by srv1 bit field of eqadc_redlccr register. 10 selects imported time base 2 indicated by srv2 bit field of eqadc_redlccr register. 11 reserved enhanced queued analog-to-dig ital converter (eqadc) RM0029 1090/1740 doc id 15177 rev 8 adc0/1 alternate gain registers (adc0_agr1-2 and adc1_agr1-2) the alternate gain registers (adc0_agrx and adc1_agrx, x=1-2) contain the gain calibration constants used to fine-tune the adcs conversion results for alternate configurations 1 or 2. a conversion from an adc uses the corresponding adc0_agrx or adc1_agrx register when the conversion command (with the alternate configuration format) is written to an address in the range 0x08-0x09 of the on-chip adc memory map. refer to section , adc calibration feature , for details about the calibration scheme used in the eqadc. table 603. adc pre-gain control bits pre_gain[0:1] description 00 x1 gain 01 x2 gain 10 x4 gain 11 reserved figure 613. adc0/1 alternate x gain register (adc0/1_agrx, x=1-2) adc0 register address: 0x31 adc0 register address: 0x35 0123456789101112131415 r0 altgcc0x w reset: 0100000000000000 adc1 register address: 0x31 adc1 register address: 0x35 0123456789101112131415 r0 altgcc1x w reset: 0100000000000000 = unimplemented or reserved figure 614. adc0/1 alternate x gain regist er (adc0/1_agrx, x=1-2) field description field description 1-15 altgcc0/1x [0:14] alternate gain calibration constant altgcc0/1x[0:14] contain the gain calibration constants used to fine-tune adc0/1 conversion results for alternate configurations 1 and 2. the gain calibration constants are 15-bit unsigned fixed point numbers expressed in the gcc_int.gcc_frac binary format. the integer part of the gain constants (gcc_int) contain a single binary digit while their fractional part (gcc_frac) contain fourteen digits. for details about the gcc data format refer to section , mac unit and operand data format . RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1091/1740 adc0/1 alternate offset register (adc0_aor1-2 and adc1_aor1-2) the alternate offset registers (adc0_aorx and adc1_aorx, x=1-2) contain the offset calibration constants used to fine-tune adcs conversion results for alternate configurations 1 and 2. the offset constants are signed 14-bit integer values. refer to section , adc calibration feature , for details about the calibration scheme used in the eqadc. adc pull up/down control register x (adc_pudcrx, x =0-7) the adc pull up/down control register x (adc_pudcr x ) contains configuration bits for pull up and pull down resistors present at adc input channels x , x =0 to 7. figure 615. adc0/1 alternate x offset registers (adc0/1_aorx, x=1-2) adc0 register address: 0x32 adc0 register address: 0x36 0123456789101112131415 r00 altocc0x w reset: 0000000000000000 adc1 register address: 0x32 adc1 register address: 0x36 0123456789101112131415 r00 altocc1x w reset: 0000000000000000 = unimplemented or reserved table 604. adc0/1 alternate x offset registers (adc0/1_aorx, x=1-2) field description field description 2-15 altocc0/1x [0:13] alternate offset calibration constant altocc0/1x[0:13] contain the offset calibration constants used to fine-tune adcs conversion results for alternate configurations 1 or 2. negative values should be expressed using the two?s complement representation. figure 616. adc pull up/down control register x (adc_pudcr x , x =0-7) adc0/1 register address: 0x70-0x77 0123456789101112131415 r00 ch_pull x 00 pull_str x 00000000 w reset: 0000000000000000 = unimplemented or reserved enhanced queued analog-to-dig ital converter (eqadc) RM0029 1092/1740 doc id 15177 rev 8 25.6 functional description 25.6.1 overview the eqadc provides a parallel interface to two on-chip adcs, a single master to single slave serial interface to an off-chip external device and a parallel side interface to an on-chip companion module, like a decimation filter. the two on-chip adcs are architected to allow access to all the analog channels. initially, command data is contained in system memory in a user defined data structure which is likely to be a queue as depicted in figure 570 (ax) . command data is moved between the cqueues and cfifos by the host cpu or by the dmac which respond to interrupt and dma requests generated by the eqadc. the eqadc supports software and table 605. adc pull up/down control register x (adc_pudcr x , x =0-7) field description field description 2-3 ch_pull x [0:1] channel x pull up/down control bits the ch_pull x [0:1] field controls the pull up/down configuration of the channel x according to table 606 . 6-7 pull_str x [0:1] pull up/down strength control bits of channel x the pull_str x [0:1] bit field defines the strength of the channel x pull up or down resistors, according to table 607 . table 606. channel x pull up/down field definition ch_pull x [0:1] definition 00 no pull resistors connected to the channel 01 pull up resistor connected to the channel 10 pull down resistor connected to the channel 11 pull up and pull down resistors connected to the channel table 607. pull up/down strength field definition pull_str x [0:1] definition 00 reserved 01 200 kohms pull resistor 10 100 kohms pull resistor 11 5 kohms (approx.) pull resistor (1) 1. this set is not av ailable for ch_pull_ x = 11. ax. command and result data can be stored in the system memo ry in any user defined data structure. however, in this document it will be assumed that the data structure of choice is a queue, since it is the most likely data structure to be used and because queues are the only ty pe of data structure supported by the dmac. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1093/1740 hardware triggers from other blocks or external pins to initiate transfers of commands from the multiple cfifos to the on-chip adcs or to the external device. cfifos can be configured in single-scan or continuous-scan mode. when a cfifo is configured in single-scan mode, the eqadc scans the cqueue one time. the eqadc stops transferring commands from the triggered cfifo after detecting the eoq bit set in the last transfer. after an eoq bit is detected, software involvement is required to rearm the cfifo so that it can detect new trigger events. when a cfifo is configured for continuous-scan mode, the whole cqueue is scanned multiple times. after the detection of an asserted eoq bit in the last command transfer, command transfers can continue or not depending on the mode of operation of the cfifo. cfifo0 has a special configuration option to allow a repetitive sequence of conversion commands (streaming mode) with high priority characteristics (abort operation) or not. this feature is useful with the immediate conversion command feature that allows the immediate execution of a conversion command or a sequence of commands with critical timing even with the possibility of abortion of some current adc conversion in progress. the aborted command is stored and executed again as soon as the critical timing commands have been finished. the multiple result fifos (rfifos) can receive data from the on-chip adcs, from an off- chip external device or from an on-chip companion module. data from the on-chip adcs can be routed to the side interface, processed by the on-chip companion module and then routed back through the side interface to the rfifos. 25.6.2 data flow in eqadc overview and basic terminology figure 617 shows how command data flows inside the eqadc system. a command message is the predefined format at which command data is stored on the cqueues. a command message has 32 bits and is composed of two parts: a cfifo header and an adc command. command messages are moved from the cqueues to the cfifos by the host cpu or by the dmac as they respond to interrupt and dma requests generated by the eqadc. the eqadc generates these requests whenever a cfifo is not full. the fifo control unit will only transfer to a cbuffer the adc command part of the command message. information in the cfifo header together with the upper bit of the adc command is used by the fifo control unit to arbitrate which triggered cfifo will be transferring the next command. since command transfer through the serial interface can take significantly more time than a parallel transfer to the on-chip adcs, command transfers for on-chip adcs occur concurrently with the ones through the serial interface. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1094/1740 doc id 15177 rev 8 figure 617. command flow during eqadc operation adc commands sent to the on-chip cbuffers are executed in a first-in-first-out basis with exception when the immediate conversion command function is enabled. three types of results can be expected: data read from an adc register, a conversion result, or a time stamp. the order at which adc commands sent to the external device are executed, and the type of results that can be expected depends on the architecture of that device with the exception of unsolicited data like null messages for example. note: while the eqadc pops commands out from a cfifo, it also is checking the number of entries in the cfifo and generating requests to fill it. the process of pushing and popping commands to and from a cfifo can occur simultaneously. however, this is not true for cfifo0 when configured to operate in streaming mode for popping. the fifo control unit expects all incoming results to be shaped in a predefined result message format. figure 618 shows how result data flows inside the eqadc system. results generated on the on-chip adcs are adjusted considering the selected resolution of the adc and are formatted into result messages inside the result format and calibration sub-block . this result message can be routed directly to one of the rfifos or to an on-chip companion module via the parallel side interface. after the data is processed by the companion module, it can be routed back to one of the rfifos via the side interface with the correct format. results returning from the external device are already formatted into result messages and therefore bypass the result format and calibration sub-block . a result message is composed of an rfifo header and an adc result. the fifo control unit decodes the information contained in the rfifo header to determine the rfifo to which the adc result should be sent. once in an rfifo, the adc result is moved to the priority cfifox note: x=0, 1, 2, 3, 4, 5 32 bits cqueuey cbuffer inside eqadc fifo control to adcs command message cfifo header adc command host cpu or dmac 32 bits dma or interrupt requests adc y=0, 1, 2, 3, ... system memory adc external device logic & buffers eqadc ssi eqadc ssi dma transaction done signals unit abort cont RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1095/1740 corresponding rqueue by the host cpu or by the dmac as they respond to interrupt and dma requests generated by the eqadc. the eqadc generates these requests whenever an rfifo has at least one entry. note: while conversion results are returned, the eqadc is checking the number of entries in the rfifo and generating requests to empty it. the process of pushing and popping adc results to and from an rfifo can occur simultaneously. figure 618. result flow during eqadc operation assumptions/requirements regarding the external device the external device exchanges command and result data with the eqadc through the eqadc ssi interface. this section explains the minimum requirements an external device has to meet to properly interface with the eqadc. some assumptions about the architecture of the external device are also described. note: x=0, 1, 2, 3, 4, 5 inside eqadc host cpu or dmac adc y=0, 1, 2, 3, ... system memory eqadc ssi external device decoder rqueue y rfifox 16 bits 16 bits adc result message rfifo header adc result logic & buffers eqadc ssi dma or interrupt requests dma transaction done signals fifo control unit result format and calibration sub-block on-chip companion eqadc psi module resolution adjust enhanced queued analog-to-dig ital converter (eqadc) RM0029 1096/1740 doc id 15177 rev 8 eqadc ssi protocol support the external device must fully support the eqadc ssi protocol as specified in section 25.6.9, eqadc synchronous serial interface (ssi) sub-block .. support for the abort feature is optional. when aborts are not supported, all command messages bound for an external cbuffer must have the abort_st bit negated - see section , command message format for external device operation . number of command buffers and result buffers the external device should have a minimum of one and a maximum of two command buffers (cbuffer) to store command data sent from the eqadc. even if more than two cbuffers are implemented in the external device, they are not recognized by the eqadc as valid destinations for commands. in this document, these two cbuffers will be referred as cbuffer2 and cbuffer3. the external device decides to which external cbuffer a command should go by decoding the upper bit (bn bit) of the adc command - see section , command message format for external device operation . an external device that only implements one cbuffer can ignore the bn bit. the limit of two cbuffers does not limit the number of rbuffers in the slave device. command execution and result return commands sent to an specific cbuffer should be executed in that order they were received. results generated by the execution of commands of a cbuffer should be returned in the order the cbuffer received these commands. null and result messages the external device must be capable of correctly processing null messages as specified in the section , eqadc null message send format register (eqadc_nmsfr) . in case no valid result data is available to be sent to the eqadc, the external device must send data in the format specified in section , null message format for external device operation . in case valid result data is available to sent to the eqadc, the external device must send data in the format specified in section , result message format for external device operation . the busy0/1 fields of all messages sent from the external device to the eqadc must be correctly encoded according to the latest information on the fullness state of the cbuffers. for example, if the cbuffer2 is empty before the end of the current serial transmission and if at the end of this transmission the external device receives a command to cbuffer2, then the busy0 field, that is to be sent to the eqadc on the next serial transmission, should be encoded assuming that cbuffer2 has one entry. message format in eqadc this section explains the command and result message formats used for on-chip adc operation and for external device operation. a command message is the predefined format at which command data is stored on the cqueues. a command message has 32 bits and is composed of two parts: a cfifo header and an adc command. the size of the cfifo header is fixed to 6 bits, and it works as inputs to the fifo control unit . it controls when a cqueue ends, when it pauses, if commands are sent to internal or external buffers, and if it can abort a serial data RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1097/1740 transmission. information contained in the cfifo header, together with the upper bit of the adc command is used by the fifo control unit to arbitrate which triggered cfifo will transfer the next command. adc commands are encoded inside the least significant 26 bits of the command message. a result message is composed of an rfifo header and an adc result. the fifo control unit decodes the information contained in the rfifo header to determine the rfifo to which the adc result should be sent. an adc result is always 16 bits long. message formats for on-chip adc operation this section describes the command/result message formats used for on-chip adc operation. note: although this subsection describes how the command and result messages are formatted to communicate with the on-chip adcs, nothing prevents the programmer from using a different format when communicating with an external device through the serial interface. refer to section , message formats for external device operation . apart from the bn bit, the adc command of a command message can be formatted to communicate to an arbitrary external device provided that the device returns an rfifo header in the format expected by the eqadc. when the fifo control unit receives return data message, it decodes the message tag field and stores the 16-bit data into the corresponding rfifo. conversion command format for the standard configuration figure 619 describes the format for conversion commands when interfacing with the on-chip adcs in the standard configuration. the standard configuration is selected when the lowest byte (bits 24-31) of the conversion command is set to zero. in the standard configuration, the conversion result is always routed to one of the rfifos. a time stamp information can be optionally requested. figure 619. conversion command format for the standard configuration 0123456789101112131415 eoq pau se rep reserve d eb (0b0) bn cal message_tag lst tsr fmt cfifo header adc command 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 channel_number 00000000 adc command enhanced queued analog-to-dig ital converter (eqadc) RM0029 1098/1740 doc id 15177 rev 8 table 608. conversion command format for the standard configuration field description field description 0 eoq end of queue bit the eoq bit is asserted in the last command of a cqueue to indicate to the eqadc that a scan of the cqueue is completed. eoq instructs the eqadc to reset its current cfifo transfer counter value (tc_cf) to zero. depending on the cfifo mode of operation, the cfifo status will also change upon the detection of an asserted eoq bit on the last transferred command - see section , cfifo scan trigger modes , for details. 1 last entry of the cqueue. 0 not the last entry of the cqueue. if both the pause and eoq bits are asserted in the same command message the respective flags are set, but the cfifo status changes as if only the eoq bit were asserted. 1 pause pause bit the pause bit allows software to create sub-queues within a cqueue. when the eqadc completes the transfer of a command with an asserted pause bit, the cfifo enters the waiting for trigger state. refer to section , cfifo operation status , for a description of the state transitions. the pause bit is only valid when cfifo operation mode is configured to single or continuous-scan edge trigger mode. 1 enter waiting for trigger state after transfer of the current command message. 0 do not enter waiting for trigger state after transfer of the current command message. if both the pause and eoq bits are asserted in the same command message the respective flags are set, but the cfifo status changes as if only the eoq bit were asserted. 2 rep repeat/loop start point indication bit the rep bit is asserted in the command to indicate where is the start point of the sub- queue to be repeated when the streaming mode is enabled. the pause bit indicates the end point of the sub-queue. therefore, both can occur in the same command or in separated ones. if two or more rep bits are read before a pause bit, this is an error case and the intermediary rep bits are ignored. 1 indicates the start point of the sub-queue to be repeated. 0 it is not the start point of a loop. 5 eb external buffer bit a negated eb bit indicates that the command is sent to an internal cbuffer. command is sent to an internal buffer. 6 bn buffer number bit bn indicates which buffer the message will be stored in. buffers 1 and 0 can either internal or external depending on the eb bit setting. message stored in buffer 1. message stored in buffer 0. 7 cal calibration bit cal indicates if the returning conversion result must be calibrated. calibrate conversion result. do not calibrate conversion result. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1099/1740 8-11 message_tag [0:3] message_tag field the message_tag allows the eqadc to separate returning results into different rfifos. table 609 describes the meaning of the message_tag. when the eqadc transfers a command, the message_tag is included as part of the command. eventually the external device/on-chip adc returns th e result with the same message_tag. the eqadc separates incoming messages into different rfifos by decoding the message_tag of the incoming data. 12-13 lst [0:1] long sampling time these two bits determine the duration of the sampling time in adc clock cycles. 14 tsr time stamp request tsr indicates the request for a time stamp. when tsr is asserted, the on-chip adc control logic returns a time stamp for the current conversion command after the conversion result is sent to the rfifos. see section , time stamp feature , for details. return conversion time stamp after the conversion result. return conversion result only. 15 fmt conversion data format fmt specifies to the eqadc how to format the 12-bit conversion data returned by the adcs into the 16-bit format which is sent to the rfifos. see section , adc result format for on-chip adc operation , for details. right justified signed. right justified unsigned. 16-23 channel_number [0:7] channel number field the channel_number field selects the analog input channel. the software programs this field with the channel number corresponding to the analog input pin to be sampled and converted. see section , channel assignment , for details. table 608. conversion command format for the standard configuration field description field description table 609. message_tag description message_tag[0:3] message_tag meaning 0b0000 result is sent to rfifo 0 0b0001 result is sent to rfifo 1 0b0010 result is sent to rfifo 2 0b0011 result is sent to rfifo 3 0b0100 result is sent to rfifo 4 0b0101 result is sent to rfifo 5 0b0110 - 0b0111 reserved 0b1000 null message received 0b1001 reserved for customer use (1) 0b1010 reserved for customer use (1) 0b1011 - 0b1111 reserved 1. these messages are treated as null messages. therefor e, they must obey the format for incoming null messages and return valid busy0/1 fields. refer to section , null message format for external device operation . enhanced queued analog-to-dig ital converter (eqadc) RM0029 1100/1740 doc id 15177 rev 8 conversion command format for alternate configurations figure 620 describes the format for conversion commands when interfacing with the on-chip adcs in one of the 8 alternate configurations. an alternate configuration is selected when the lowest byte (bits 24-31) of the conversion command is set to a value in the range 0x08- 0x0f. each value in this range selects one of the 8 alternate configuration (0x08 selects alternate configuration 1, 0x0f selects alternate configuration 8). in the alternate configurations, the conversion result can be routed to one of the rfifos or to the parallel side interface to communicate with an on-chip companion module. a bit field in the corresponding alternate configuration control register selects the internal rfifo or parallel side interface as the destination for the conversion result. a time stamp information can be optionally requested. all fields, except ffmt and alt_config_sel, are identical to the ones in the standard configuration format. only the fields which are different from the standard format will be described here. table 610. sampling time lst[0:1] sampling cycles (adc clock cycles) 0b00 2 0b01 8 0b10 64 0b11 128 figure 620. conversion command format for alternate configurations 0 1 23456789101112131415 eoq paus e rep reserved eb (0b0) bn cal message_tag lst tsr ffmt cfifo header adc command 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 channel_number alt_config_sel adc command RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1101/1740 write configuration command for mat for on-chip adc operation figure 620 describes the command message format for a write configuration command when interfacing with the on-chip adcs. a write configuration command is used to set the control registers of the on-chip adcs. no conversion data will be returned for a write configuration command. write configuration commands are differentiated from read configuration commands by a negated r/w bit. table 611. conversion command format for al ternate configurations field description field description 15 ffmt flush or format the function of this bit depends on the dest field of the alternate configuration control register. if dest is equal to 0b000, then ffmt defines the format in which the 12-bit conversion result are stored in the rfifos. if dest is not equal to 0b000, then the ffmt bit is used to send a flush (soft-reset) signal through the parallel side interface to the companion module addressed by the dest field. in case dest is not equal to 0b000, the fmta bit in the alternate configuration control register is used to define the conversion result format. 1 conversion result format set to right justified signed if dest is equal to 0b000. a flush signal is sent through the side interface if dest is not equal to 0b000. 0 conversion result format set to right justified unsigned if dest is equal to 0b000. no flush signal is sent through the side interface if dest is not equal to 0b000. the flush signal can be asserted along with a valid conversion result. in this case the companion module should execute the softwa re-reset first and then consider the conversion result as a valid data for the filtering algorithm. 24-31 alt_config_sel alternate configuration selection this field selects one of the alternate configurations according to table 612 . table 612. alternate configuration selection alt_config_sel[0:7] alternate configuration 0x08 1 0x09 2 0x0a 3 0x0b 4 0x0c 5 0x0d 6 0x0e 7 0x0f 8 enhanced queued analog-to-dig ital converter (eqadc) RM0029 1102/1740 doc id 15177 rev 8 read configuration command for mat for on-chip adc operation figure 622 describes the command message format for a read configuration command when interfacing with the on-chip adcs. a read configuration command is used to read the contents of the on-chip adc registers which are only accessible via command messages. read configuration commands are differentiated from write configuration commands by an asserted r/w bit. figure 621. write configuration command format for on-chip adc operation 0 1 23456789101112131415 eoq pause rep reserved eb (0b0) bn r/w (0b0) adc_register high byte cfifo header adc command 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc_register low byte adc_reg_address adc command table 613. write configuration command format for on-chip adc operation field description field description 0 eoq end of queue bit 1 pause pause bit 2 rep repeat/loop start point indication bit 5 eb external buffer bit 6 bn buffer number bit refer to section , conversion command format for the standard configuration. 7 r/w read/write bit a negated r/w indicates a write configuration command. write 8-11 adc_register_high_byte [0:7] adc register high byte field register_high_byte is the value to be written into the most significant 8 bits of control/configuration register when the r/w bit is negated. 16-23 adc_register_low_byte [0:7] register low byte field register_low_byte is the value to be written into the least significant 8 bits of a control/configuration register when the r/w bit is negated. 24-31 adc_reg_address [0:7] adc register address the adc_reg_address field selects a register on the adc register set to be written or read. only half-word addresses can be used. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1103/1740 adc result format for on-chip adc operation when the fifo control unit receives a return data message, it decodes the message_tag field and stores the 16-bit data into the appropriate rfifo. this section figure 622. read configuration command format for on-chip adc operation 0 1 23456789101112131415 eoq paus e rep reserved eb (0b0) bn r/w (0b1) message_tag reserved cfifo header adc command 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved adc_reg_address adc command table 614. read configuration command format for on-chip adc operation field description field description 0 eoq end of queue bit 1 pause pause bit 2 rep repeat/loop start point indication bit 5 eb external buffer bit 6 bn buffer number bit refer to section , conversion command format for the standard configuration .. 7 r/w r/w - read/write bit an asserted r/w bit indicates a read configuration command. 1read 8-11 message_tag [0:3] message_tag field refer to section , conversion command format for the standard configuration .. 24-31 adc_reg_address [0:7] adc register address the adc_reg_address field selects a register on the adc register set to be written or read. only half-word addresses can be used. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1104/1740 doc id 15177 rev 8 describes the adc result portion of the result message returned by the on-chip adcs. the 16-bit data stored in the rfifos can be: data read from an adc register with a read configuration command. in this case, the stored 16-bit data corresponds to the contents of the adc register that was read. a time stamp. in this case, the stored 16-bit data is the value of the time base counter latched when the eqadc detects the end of the analog input voltage sampling. for details see section , time stamp feature . a conversion result, coming directly from the adcs. in this case, the stored 16-bit data contains a right justified 14-bit result data. the conversion result can be calibrated or not depending on the status of cal bit in the command that requested the conversion (ay) . when the cal bit is negated, this 14-bit data is obtained by executing a 2-bit left-shift on the 12-bit data resultant from the resolution adjustment on the 8 or 10 or 12-bit data received from the adc. the resolution adjustment consists of changing the conversion result input from 8, 10 or 12 bits right aligned to a 12-bit word left aligned - refer to section , adc resolution selection feature , for details. when the cal bit is asserted, this 14-bit data is the result of the calculations performed in the eqadc mac unit using the 12-bit data result of the resolution adjustment and the calibration constants gcc and occ, or altgcc and altocc - refer to section , adc calibration feature , for details. then, this 14-bit data is further formatted into a 16-bit format according to the status of the fmt bit in conversion command of the standard configuration or ffmt bit in the conversion command of the alternate configurations (az) . when fmt/ffmt is asserted, the 14-bit result data is reformatted to look as if it was measured against an imaginary ground at vref/2 (the msb bit of the 14-bit result is inverted), and is sign-extended to a 16-bit format as in figure 623 . when fmt/ffmt is negated, the eqadc zero-extends the 14-bit result data to a 16-bit format as in figure 624 . correspondence between the analog voltage in a channel and the calculated digital values is shown in table 616 . ay. in case the conversion result is routed through an on-chip dsp via side interface, the calibration is applied before the data is sent to the dsp. az. for simplicity, the following text will refer to fmt only, but when using alternate configurations, refer to section , conversion command format for alternate configurations . figure 623. adc result format when fmt=1 (right justified signed) 0123456789101112131415 sign_ext resolution adjusted conversion_result (with inverted msb bit) adc result figure 624. adc result format when fmt=0 (right justified unsigned) 0123456789101112131415 0 0 resolution adjusted conversion_result adc result RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1105/1740 table 615. adc result format (right justified signed) field description field description 0-1 sign_ext [0:1] sign extension field sign_ext only has meaning when fmt is asserted. sign_ext is 0b00 when conversion_result is positive, an d 0b11 when conversion_result is negative. 2-15 conversion_result [0:13] conversion result field conversion_result is a digital value corresponding to the analog input voltage in a channel when the conversion command was initiated. the two?s complement representation is used to express negative values. table 616. correspondence between analog voltages and digital values (1), (2) voltage level on channel (v) corresponding 8-bit conversion result returned by the adc corresponding 10-bit conversion result returned by the adc corresponding 12-bit conversion result returned by the adc 16-bit result sent to rfifos (fmt=0) (3) 16-bit result sent to rfifos (fmt=1) (3) single- ended conversions 5.12 - - 0xfff 0x3ffc 0x1ffc - 0x3ff - 0x3ff0 0x1ff0 0xff - - 0x3fc0 0x1fc0 5.12 - lsb - - 0xfff 0x3ffc 0x1ffc - 0x3ff - 0x3ff0 0x1ff0 0xff - - 0x3fc0 0x1fc0 ... ... ... ... ... ... 2.56 - - 0x800 0x2000 0x0000 - 0x200 - 0x2000 0x0000 0x80 - - 0x2000 0x0000 ... ... ... ... ... ... 1 lsb - - 0x001 0x0004 0xe004 - 0x001 - 0x0010 0xe010 0x01 - - 0x0040 0xe040 0 0x00 0x000 0x000 0x0000 0xe000 enhanced queued analog-to-dig ital converter (eqadc) RM0029 1106/1740 doc id 15177 rev 8 message formats for external device operation this section describes the command messages, data messages, and null messages formats used for external device operation. command message format for external device operation figure 625 describes the command message format for external device operation. command message formats for on-chip operation and for external device operation share the same cfifo header format. however, there are no limitations regarding the format an adc command used to communicate to an arbitrary external device. only the upper bit of an adc command has a fixed format (bn field) to indicate to the fifo control unit /external device to which cbuffer the corresponding command should be sent. the remaining 25 bits can be anything decodable by the external device. only the adc command portion of a command message is transferred to the external device. differential conversions 2.56 - - 0xfff 0x3ffc 0x1ffc - 0x3ff - 0x3ff0 0x1ff0 0xff - - 0x3fc0 0x1fc0 2.56 - lsb - - 0xfff 0x3ffc 0x1ffc - 0x3ff - 0x3ff0 0x1ff0 0xff - - 0x3fc0 0x1fc0 ... ... ... ... ... ... 0 - - 0x800 0x2000 0x0000 - 0x200 - 0x2000 0x0000 0x80 - - 0x2000 0x0000 ... ... ... ... ... ... 2.56 - lsb - - 0x001 0x0004 0xe004 - 0x001 - 0x0010 0xe010 0x01 - - 0x0040 0xe040 -2.56 0x00 0x000 0x000 0x0000 0xe000 1. vref=vrh-vrl=5.12v. resulting in one 12-bit count (lsb) =1.25mv. 2. the two?s complement representation is used to express negative values. 3. assuming uncalibrated conversion results. table 616. correspondence between analog voltages and digital values (1), (2) voltage level on channel (v) corresponding 8-bit conversion result returned by the adc corresponding 10-bit conversion result returned by the adc corresponding 12-bit conversion result returned by the adc 16-bit result sent to rfifos (fmt=0) (3) 16-bit result sent to rfifos (fmt=1) (3) RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1107/1740 result message format for external device operation data is returned from the adcs in the form of result messages. a result message is composed of an rfifo header and an adc result. the fifo control unit decodes the information contained in the rfifo header and sends the contents of the adc result to the appropriate rfifo. only data stored on the adc_result field is stored in the rfifos/rqueues. the adc result of any received message with a null data message tag figure 625. command message format for external device operation 0123 4 56789101112131415 eoq paus e reserve d abort_st eb (0b1) bn off_chip_command cfifo header adc command 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 off_chip_command adc command table 617. command message format for external device operation field description field description 0 eoq end of queue bit 1 pause pause bit refer to section , conversion command format for the standard configuration . 4 abort_st abort serial transmission bit abort_st indicates whether an on-going serial transmission should be aborted or not. all cfifos can abort null message transmissions when triggered but only cfifo0 can abort command transmissions of lower priority cfifos. for more on serial transmission aborts see section , cfifo common prioritization and command transfer . abort current serial transmission. do not abort current serial transmission. 5 eb external buffer bit an asserted eb bit indicates that the command is sent to an external cbuffer. command is sent to an external cbuffer. 6 bn buffer number bit refer to section , conversion command format for the standard configuration . 7-31 off_chip_command [0:24] off-chip command field the off_chip_command field can be anything decodable by the external device. it is 25 bits long and it is transferred together with the bn bit to the external device when the cfifo is triggered. refer to section , conversion command format for the standard configuration , for a description of the command message used when interfacing with the on-chip adcs. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1108/1740 doc id 15177 rev 8 will be ignored. the format of a result message returned from the external device is shown in figure 626 . it is 26 bits long, and is composed of a message_tag field, information about the status of the cbuffers (busy fields), and result data. the busy fields are needed to inform the eqadc about when it is appropriate to transfer commands to the external cbuffers. figure 626. result message format for external device operation 0123456789101112131415 reserved message_tag busy1 busy0 rfifo header 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc_result adc result table 618. result message format for external device operation field description field description 8-11 message_tag [0:3] message_tag field refer to section , conversion command format for the standard configuration . 12-13 busy1[0:1] busy status field the busy fields indicate if the external device can receive more commands. table 619 shows how these two bits are encoded. when an external device cannot accept any more new commands, it must set busyx to a value indicating ?do not send commands? in the returning message. the busy fields of values 0b10 and 0b10 can be freely encoded by the external device to allow visibility of the status of the external cbuffers for debug, they could indicate the number of entries in a external cbuffer for example. after reset, the eqadc always assumes that the external cbuffers are full and cannot receive commands. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1109/1740 null message format for external device operation null messages are only transferred through the serial interface to allow results and unsolicited control data, like the status of the external cbuffers, to return when there are no more commands pending to transfer. null messages are only transmitted when serial transmissions from the eqadc ssi are enabled (see essie field in section , eqadc module configuration register (eqadc_mcr) ), and when one of the following conditions apply: 1. there are no triggered cfifos with commands bound for external cbuffers, or; 2. there are triggered cfifos with commands bound for external cbuffers but the external cbuffers are full. the eqadc detected returning busyx fields indicating ?do not send commands?. figure 627 illustrates the null message send format. when the eqadc transfers a null message, it directly shifts out the 26-bit data content inside the section , eqadc null message send format register (eqadc_nmsfr) . the register must be programmed with the null message send format of the external device. figure 628 illustrates the null message receive format. it has the same fields found in a result message with the exception that the adc result is not used. refer to section , result message format for external device operation , for more information. the message_tag 14-15 busy0[0:1] busy status field the busy fields indicate if the external device can receive more commands. table 619 shows how these two bits are encoded. when an external device cannot accept any more new commands, it must set busyx to a value indicating ?do not send commands? in the returning message. the busy fields of values 0b10 and 0b10 can be freely encoded by the external device to allow visibility of the status of the external cbuffers for debug, they could indicate the number of entries in a external cbuffer for example. after reset, the eqadc always assumes that the external cbuffers are full and cannot receive commands. 16-31 adc_result [0:15] adc result field adc_result is the result data received from the external device or on-chip adc. this can be the result of a conversion command, data requested via a read configuration command, or time stamp value. the adc_result of any incoming message with a null message tag will be ignored. when the message_tag is for an rfifo, the eqadc extracts the 16-bit adc_result from the raw message and stores it into the appropriate rfifo. table 618. result message format for external device operation field description (continued) field description table 619. command bufferx busy status busyx[0:1] meaning 0b00 send available commands - cbuffer is empty 0b01 send available commands 0b10 send available commands 0b11 do not send commands enhanced queued analog-to-dig ital converter (eqadc) RM0029 1110/1740 doc id 15177 rev 8 field must be set to the null message tag (0b1000). the eqadc does not store into an rfifo any incoming message with a null message tag. figure 627. null message send format for external device operation 0123456789101112131415 reserved contents of eqadc_nmsfr register 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 contents of eqadc_nmsfr register figure 628. null message receive format for external device operation 0123456789101112131415 reserved message_tag (0b1000) busy1 busy0 rfifo header 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 determined by the external device adc result table 620. field description field description 8-11 message_tag [0:3] message_tag field refer to section , conversion command format for the standard configuration . 21-13 busy1 [0:1] busy status field refer to section , result message format for external device operation . 14-15 busy0 [0:1] busy status field refer to section , result message format for external device operation . RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1111/1740 25.6.3 command/result queues the command and result queues (cqueues and rqueues) are actually part of the eqadc system although they are not hardware implemented inside the eqadc. each cqueue entry is a 32-bit command message.the last entry of a cqueue has the eoq bit asserted to indicate that it is the last entry of the cqueue. rqueue entry is a 16-bit data. see section , overview and basic terminology , for a description of the message formats and their flow in eqadc. refer to section 25.7.5, cqueue and rqueues usage , for examples of how cqueues and rqueues can be used. 25.6.4 eqadc command fifos cfifo basic functionality there are six prioritized cfifos located in th e eqadc. each cfifo is four entries deep, except cfifo0 that can be configured to eight entries deep in extended mode, and each cfifo entry is 32 bits long. a cfifo serves as a temporary storage location for the command messages stored on the cqueues in the system memory. when a cfifo is not full, the eqadc sets the corresponding cfff bit in section , eqadc fifo and interrupt status registers (eqadc_fisr) . if cffe is asserted in section , eqadc interrupt and dma control registers (eqadc_idcr) , the eqadc generates requests for more commands from a cqueue. an interrupt request, served by the host cpu, is generated when cffs is negated, and a dma request, served by the dmac, is generated when cffs is asserted. the host cpu or the dmac respond to these requests by writing to the section , eqadc cfifo push registers (eqadc_cfpr) , to fill the cfifo. note: the dmac should be configured to write a single command (32-bit data) to the cfifo push registers for every asserted dma request it acknowledges. refer to section 25.7.2, eqadc/dmac interface , for dmac configuration guidelines. note: cfifo0 can be configured to work in an alternative way called streaming mode. this mode is very different from the mode described here because it maintains some stored commands to execute them several times in sequence and in loop. note: only whole words must be written to eqadc_cfpr. writing half-words or bytes to eqadc_cfpr will still push the whole 32-bit cf_push field into the corresponding cfifo, but undefined data will fill the areas of cf_push that were not specifically designated as target locations for writing. figure 629 describes the important components in the cfifo. each cfifo is implemented as a circular set of registers to avoid the need to move all entries at each push/pop operation. the push next data pointer points to the next available cfifo location for storing data written into the eqadc command fifo push register. the transfer next data pointer points to the next entry to be removed from cfifox when it completes a transfer. the cfifo transfer counter control logic counts the number of entries in the cfifo and generates dma or interrupt requests to fill the cfifo. tnxtptr in section , eqadc fifo and interrupt status registers (eqadc_fisr) , indicates the index of the entry that is currently being addressed by the transfer next data pointer, and cfctr, in the same register, provides the number of entries stored in the cfifo. using tnxtptr and cfctr, the absolute addresses for the entries indicated by the transfer next data pointer and by the push next data pointer can be calculated using the following formulas: enhanced queued analog-to-dig ital converter (eqadc) RM0029 1112/1740 doc id 15177 rev 8 transfer next data pointer address = cfifox_base_address + tnxtptrx*4 push next data pointer address = cfifox_base_address + [(tnxtptrx+cfctrx) mod cfifo_depth] * 4 where a mod b returns the remainder of the division of a by b . cfifox_base_address is the smallest memory mapped address allocated to a cfifox entry. cfifo_depth is the number of entries contained in a cfifo - four in this implementation. when cfs x in section , eqadc cfifo status register (eqadc_cfsr) , is triggered, the eqadc generates the proper control signals for the transfer of the entry pointed by transfer next data pointer. cfufx in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is set when a cfifox underflow ev ent occurs. a cfifo underflow occurs when the cfifo is in triggered state and it becomes empty. no commands will be transferred from an underflowing cfifo, nor will command transfers from lower priority cfifos be blocked. cfifox is empty when the transfer next data pointer x equals the push next data pointer x and cfctrx is zero. cfifox is full when the transfer next data pointer x equals the push next data pointer x and cfctrx is not zero. when the eqadc completes the transfer of an entry from cfifox: the transferred entry is popped from cfifox, the cfifo counter cfctr in the section , eqadc fifo and interrupt status registers (eqadc_fisr) , is decremented by one, and transfer next data pointer x is incremented by one (or wrapped around) to point to the next entry in the cfifo. the transfer of entries bound for the on-chip adcs is considered completed when they are stored in the appropriate cbuffer. the transfer of entries bound for the external device is considered completed when the serial transmission of the entry is completed. when the eqadc_cfprx is written and cfifox is not full, the cfifo counter cfctrx is incremented by one, and the push next data pointer x then is incremented by one (or wrapped around) to point to the next entry in the cfifo. when the eqadc_cfprx is written but cfifox is full, the eqadc will not increment the counter value and will not overwrite any entry in cfifox. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1113/1740 figure 629. cfifo diagram the detailed behavior of the push next data pointer and transfer next data pointer is described in the example shown in figure 630 where a cfifo with 16 entries is shown for clarity of explanation, the actual hardware implementation has only four entries. in this example, cfifox with 16 entries is shown in sequence after pushing and transferring entries. 32-bit entry 1 32-bit entry 2 -------------------- -------------------- push next data pointer * transfer next data pointer * cfifo push register cfifo control logic dma done interrupt/dma request control signals data to external device or to on-chip adcs transfer counter * all cfifo entries are memory mapped and the entries addressed by thes e pointers can have their absolute addresses calculated using tnxtptr and cfctr. write to slave-bus interface by cpu or dma enhanced queued analog-to-dig ital converter (eqadc) RM0029 1114/1740 doc id 15177 rev 8 figure 630. cfifo entry pointer example cfifo0 streaming mode description cfifo0 can be configured to operate in streaming mode to allow repetition of a group of commands several times without the need of refilling the registers as in the normal mode of operation of cfifos. this mode makes use of the additional bit in the conversion command word (ccw) called ?repeat? (rep bit). the purpose of this bit is to mark in the push transfer cfifox first in after reset or invalidation next data pointer next data pointer last in valid entry empty entry push transfer cfifox some entries pushed but none executed next data pointer next data pointer transfer cfifox no entries pushed but some executed next data pointer first in last in push next data pointer push cfifox entries pushed until full and none executed next data pointer cfifox no entries pushed but some executed transfer cfifox some entries pushed and some executed next data pointer first in last in push next data pointer transfer next data pointer first in last in push next data pointer transfer next data pointer first in last in note: x=0, 1, 2, 3, 4, 5 RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1115/1740 command queue, where to start a repeating sequence. this location is stored in an additional pointer ?repeat pointer?. streaming mode requires 2 trigger inputs. the standard queue 0 trigger, in this mode referred to as repeat trigger and a new internal trigger input to the eqadc called advance trigger (no filter available). cfifo0 is configured to operate in streaming mode by setting the bit strme0 as described in section , eqadc cfifo control registers (eqadc_cfcr) . cfifo0 is eight entries deep in extended mode by setting the bit cfeee0 in the same eqadc_cfcr register, and each entry is 32 bits long. this cfifo0 serves as a local storage of a few commands that need to be executed sequentially as in a fifo but can contain sub-queues that need to be executed several times. the cfff0 bit in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is used to assure the cfifo0 is not full and command messages are stored from address 0x0 to 0x7. cfifo0 operation in streaming mode in streaming mode, the cfifo0 is filled with ccws using the dma exactly the same as existing modes. the cfifo executes commands as per the existing modes until it executes a conversion command word with the repeat bit set. when this ccw is executed, the repeat pointer is set to point to this fifo location and from this ccw onwards, cfifo0 entries is not invalidated, that is, the repeat pointer prevents this and subsequent entries from being overwritten. the queue continues to execute until a ccw with an asserted pause bit is completed; then the queue stops and enters the pause state, waiting for a trigger. this is the same as normal behavior. the pause state is exited in one of two ways: repeat trigger or repeat trigger with advance trigger. the repeat trigger with no advance trigger causes the transfer next data pointer to be loaded with the repeat pointer location and ccws are then executed from the repeat pointer back to the pause bit. this means that a section of the cfifo0 is repeatedly executed every time a repeat trigger occurs. the repeat trigger with the advance trigger pending causes all ccws from the repeat pointer to the pause bit to be invalidated and the ccw after the pause bit to be executed. this is achieved by invalidating the repeat pointer. the effect is that the queue advances beyond the repeating section of the cfifo0 to execute new ccws. note that the advance trigger can occur at any time between repeat triggers, but is only actioned when the next repeat trigger occurs. prior to that it is pending. in a typical application, the queue is made of some configuration commands to the adc (to flush the decimator or turn on pad pull-up/down) followed by a repeating section of adc conversions on one or more adc channels from one or more sensors; followed by a few more configuration commands; then more repeating adc conversions, until the entire engine cycle is complete; when the queue is restarted. the mechanism described permits any number of repeating sub-queues to be loaded and executed, interspersed by configuration commands. triggering description in streaming mode the additional trigger signal atrig0 is detected by a separate circuit that is configured by the bit field amode0 as described in section , eqadc cfifo control registers (eqadc_cfcr) . this trigger signal is used as an advance control of pop pointer of cfifo0. in addition, it is used as the enable trigger for the repeat trigger. this means it is enhanced queued analog-to-dig ital converter (eqadc) RM0029 1116/1740 doc id 15177 rev 8 necessary to have an advance trigger first to enable the detection of the repeat trigger. when the repeat trigger is enabled, the advance trigger is used to advance the pop pointer beyond some loop sub-queue. and it is to disable the repeat trigger by executing a pause without a previous rep bit. a typical sequence of events is presented below to describe the relationship between the triggers. in streaming mode, the cfifo0 is filled with ccws using the dma as usual. the two triggers are configured to positive edge and single scan mode. the sss bit is asserted and the trigger detector of the repeat trigger is disabled in the start of the queue. it is necessary to receive the first advance trigger to enable the detector of the other trigger. this enable is useful when the repeat trigger is received all the time and the trigger signal can be disabled when it is not desired. the advance trigger is received and detected and the repeat trigger detector is enabled. no commands are executed until now. the repeat trigger is detected and the commands start to be executed in sequence. if a rep bit is decoded with the pause bit, the loop is configured and the cfifo0 commands stop to be executed. the next repeat trigger is waited to start the execution of the loop again, or the advance trigger can be detected to break the loop and advance the queue in cfifo0. the repeat trigger detector remains enabled. if the advance trigger is received and the next command in the cfifo0 does not present the rep bit set, this means the cfifo0 is not starting a new loop. in this case (outside a loop) if a pause bit is decoded, this means to disable the repeat trigger detector. this can be useful if the repeat trigger is not required for some interval of time. the repeat trigger detector is enabled again when the next advance trigger event is detected. cfifo0 diagram description in streaming mode figure 631 represents the main components of cfifo0 in streaming mode. however, some signals behave in a different way from the common operation. the push next data pointer points to the next available cfifo0 location for storing data written into the eqadc command fifo push register. the transfer next data pointer points to the next entry to be transferred to cbuffer. the repeat pointer points to the first entry of the repeating sub- queue. tnxtptr in section , eqadc fifo and interrupt status registers (eqadc_fisr) , indicates the index of the entry that is currently being addressed by the transfer next data pointer, and cfctr, in the same register, provides the number of entries stored in the cfifo. when cfs0 in section , eqadc cfifo status register (eqadc_cfsr) , is triggered, the eqadc generates the proper control signals for the transfer of the entry pointed by transfer next data pointer. cfuf0 in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is set when cfifo0 underflow event occurs. a cfifo underflow occurs when the cfifo is in triggered state and it is empty. no commands will be transferred from an underflowing cfifo, nor will command transfers from lower priority cfifos be blocked. cfifo0 is empty when cfctr0 is zero. cfifo0 is full when (cfctr0 mod cfifo_depth) is zero but cfctr0 is not zero. when the eqadc completes the transfer of an entry from cfifo0 in loop condition: the transferred entry is not popped from cfifo0, the cfifo counter cfctr in the section , eqadc fifo and interrupt status registers (eqadc_fisr) , is not decremented by one, and transfer next data pointer 0 is incremented by one (or wrapped around) to point to the next entry in the cfifo0. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1117/1740 figure 631. cfifo0 in streaming mode diagram the detailed behavior of the push next data pointer and transfer next data pointer is described in the example shown in figure 632 where a cfifo with 16 entries is shown for clarity of explanation, the actual hardware implementation has only four/eight entries. in this example, cfifo0 with 16 entries is shown in sequence after pushing and transferring entries. 32-bit entry 1 32-bit entry 2 -------------------- -------------------- push next data pointer * transfer next data pointer * cfifo push register cfifo control logic dma done interrupt/dma request control signals data to external device or to on-chip adcs transfer counter * all cfifo entries are memory mapped and the entries addressed by these pointers can have their absolute addresses calculated using tnxtptr and cfctr. repeat pointer 32-bit entry n, rep write to slave-bus interface by cpu or dma enhanced queued analog-to-dig ital converter (eqadc) RM0029 1118/1740 doc id 15177 rev 8 figure 632. cfifo0 in streaming mode entry pointer example push transfer cfifo0 first in after reset or invalidation next data pointer next data pointer last in valid entry empty entry push transfer cfifo0 some entries pushed but none executed next data pointer next data pointer transfer cfifo0 no entries pushed but some executed next data pointer last in push next data pointer transitory state. repeat trigger with no entries pushed but not repeat pause repeat pointer repeat pause up to pause bit - waiting for trigger repeat pause repeat pointer transfer cfifo0 next data pointer last in push next data pointer repeat pause repeat pointer advance trigger causes loop execution. transfer cfifo0 next data pointer last in push next data pointer repeat pause repeat pointer transitory state. repeat trigger and with advance trigger causes execution of next entry after pause. repeat full and not executed. transfer cfifo0 next data pointer last in push next data pointer pause repeat pointer repeat first in non repeat command followed by 5 repeat commands pending. no trigger. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1119/1740 figure 633. cfifo0 in streaming mode entry pointer example (cont.) streaming mode error conditions in the repeat state, the existing error conditions still apply, but now there are new ways to trigger them. now, the ccws are not being invalidated so the dma is not able to load more ccws into those locations. so a queue overflow becomes more likely, and occurs if the repeat loop is longer than 8 entries. if all ccws in the cfifo0 are executed and no pause bit or eoq bit is detected, the eqadc will signal an underflow error. in practice this may limit a repeating queue to 7 entries since otherwise an underflow will occur at the point a repeat with advance trigger occurs, and there is no command in the cfifo0 to execute. the exception is a final command with both a pause and an eoq bit set. the end of queue bit eoq continues to operate as in normal mode, unless the repeat mode is enabled. in this case the pause bit takes precedence and a repeat trigger causes the jump back described. a repeat trigger with advance trigger causes the queue to end. another error condition occur when the repeat trigger is in the triggered state and a new repeat trigger is received. in this case, a trigger overflow occurs but the cfifo0 is defined to not restart the loop. the trigger in this case is not used in the cfifo0, but the overflow is indicated. cfifo common prioritization and command transfer the cfifo priority is fixed according to the cfifo number. a cfifo with a smaller number has a higher priority. when commands of distinct cfifos are bound for the same no entries pushed. last in push transfer cfifo0 entries pushed. fifo full. waiting next data pointer next data pointer repeat pointer repeat pause transfer cfifo0 next data pointer last in push next data pointer pause repeat pointer repeat entries executed to pause bit. pending trigger. at pause bit for repeat trigger or advance & repeat trigger. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1120/1740 doc id 15177 rev 8 destination (cbuffer), the higher priority cfifo is always served first. a triggered, not- underflowing cfifo will start the transfer of its commands when: its commands are bound for an internal cbuffer that is not full, and it is the highest priority triggered cfifo sending commands to that cbuffer. its commands are bound for an external cbuffer that is not full, and it is the highest priority triggered cfifo sending commands to an external cbuffer that is not full. a triggered cfifo with commands bound for a certain cbuffer consecutively transfers its commands to it until: an asserted end of queue bit is reached, or; an asserted pause bit is encountered and the cfifo is configured for edge trigger mode, or; cfifo is configured for level trigger mode and a closed gate is detected, or; in case its commands are bound for an internal cbuffer, a higher priority cfifo that uses the same internal cbuffer is triggered, or; in case its commands are bound for an external cbuffer, a higher priority cfifo that uses an external cbuffer is triggered. the prioritization logic of the eqadc, depicted in figure 634 , is composed of three independent sub-blocks: one prioritizing cfifos with commands bound for cbuffer0, another prioritizing cfifos with commands for cbuffer1, and a last one prioritizing cfifos with commands for cbuffer2 and cbuffer3 which reside inside the external device. as these three sub-blocks are independent, simultaneous writes to cbuffer0, to cbuffer1, and to eqadc ssi transmit buffer are allowed. the hardware identifies the destination of a command by decoding the eb and bn bits in the command message - see section , message format in eqadc , for details. note: triggered but empty cfifos, underflowing cfifos, are not considered for prioritization. no data from these cfifos will be sent to the cbuffers and nor will they stop lower priority cfifos from transferring commands. whenever cbuffer0 is able to receive new entries, the prioritization sub-block selects the highest-priority triggered cfifo with a command bound for cbuffer0, and writes its command into the buffer. in case cbuffer0 is able to receive new entries but there are no triggered cfifos with commands bound for it, nothing is written to the buffer. the sub-block prioritizing cbuffer1 usage behaves in the same way. when the eqadc ssi is enabled and ready to start serial transmissions, the sub-block prioritizing eqadc ssi usage writes command or null messages into the eqadc ssi transmit buffer, data written to the eqadc ssi transmit buffer is subsequently transmitted to the external device through the eqadc ssi link. the sub-block writes commands to the eqadc ssi transmit buffer when there are triggered cfifos with commands bound for not- full external cbuffers. the command written to the transmit buffer belongs to the highest priority cfifo sending commands to a external cbuffer that is not full. this implies that a lower priority cfifo can have its commands sent if a higher priority cfifo cannot send its commands due to a full cbuffer. the sub-block writes null messages to the eqadc ssi transmit buffer when there are no triggered cfifos with commands bound for external cbuffers, or when there are triggered cfifos with commands bound for external cbuffers but the external cbuffers are full. the eqadc monitors the status of the external cbuffers by decoding the busy fields of the incoming result messages from the external device - see section , result message format for external device operation , for details. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1121/1740 note: when a lower priority cfifo is served first because a higher priority cfifo cannot send its commands due to a full external cbuffer, there is a possibility that command transfers from the lower priority cfifo will be interrupted and the cfifo will become non-coherent, when the higher priority cfifo again becomes ready to send commands. if the lower priority cfifo becomes non-coherent or not depends on the rate at which commands on the external cbuffers are executed, on the rate at which commands are transmitted to the external cbuffers, and on the depth of those buffers. once a serial transmission is started, the sub-block monitors triggered cfifos and manages the abort of serial transmissions. in case a null message is being transmitted, the serial transmission is aborted when all following conditions are met: a not-underflowing cfifo in triggered state has commands bound for an external cbuffer that is not full, and it is the highest priority cfifo sending commands to an external cbuffer that is not full. the abort_st bit of the command to be transmitted is asserted. the 26th bit of currently transmitting null message has not being shifted out. the command from the cfifo is then written into eqadc ssi transmit buffer, allowing for a new serial transmission to initiate. in case a command is being transmitted, the serial transmission is aborted when all following conditions are met: cfifo0 is in triggered state, is not underflowing, and its current command is bound for an external cbuffer that is not full. the abort_st bit of the command to be transmitted is asserted. the 26th bit of currently transmitting command has not being shifted out. the command from cfifo0 is then written into eqadc ssi transmit buffer, allowing for a new serial transmission to initiate. note: the aborted command is not popped from the preempted cfifo and will be retransmitted as soon as its cfifo becomes the highest priority cfifo sending commands to an external cbuffer that is not full. after a serial transmission is completed, the eqadc prioritizes the cfifos and schedules a command or a null message to be sent in the next serial transmission. after the data for the next transmission has been defined and scheduled, the eqadc can, under certain conditions, stretch the sds negation time in order to allow the schedule of new data for that transmission. this occurs when the eqadc acknowledges that the status of a higher- priority cfifo changed to triggered and attempts to schedule that cfifo command before sds is asserted. only commands of cfifos that have the abort_st bit asserted can be scheduled in this manner. under such conditions: 1. a cfifo0 command is scheduled for the next transmission independently of the type of data that was previously scheduled. the time during which sds is negated is stretched in order to allow the eqadc to load the cfifo0 command and start its transmission. 2. cfifo1-5 commands are only scheduled for the next transmission if the previously scheduled data was a null message. the time during which sds is negated is stretched in order to allow the eqadc to load that command and start its transmission. however, if the previously scheduled data was a command, no rescheduling occurs and the next transmission starts without delays. if a cfifo becomes triggered while sds is negated, but the eqadc only attempts to reschedule that cfifo command after sds is asserted, then the current transmission is aborted depending on if the conditions for that are met or not. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1122/1740 doc id 15177 rev 8 figure 634. cfifo prioritization logic cfifo prioritization in abort mode the cfifo priority does not change when the eqadc is configured to allow abortion of conversion execution in on-chip adc analog blocks. however, cfifo0 is the only one that can be enabled to abort conversions. this feature is necessary when the timing of some conversion is very important. in normal priority scheme, when cfifo0 is triggered, its conversion command can be put behind 2 pending conversion commands in the cbuffer due to the queue structure. considering that these 2 pending commands are from lower priority cfifos and that the delay between the trigger and the sampling of the command from cfifo0 can be unacceptable, eqadc can be configured to permit immediate conversion commands from cfifo0 with abort function. when cfifo0 is triggered and abort is enabled, up to 2 commands in cbuffer0 or cbuffer1 are stored in a side register. the abort request signal is generated to adc0 or adc1 and the confirmation of adc reset/ready is waited to send the command from cfifo0 to the decoded cbuffer. after the transfer of all commands from cfifo0, the recovery phase restores the up to 2 commands that were in cbuffer when the abort occurred. after this recovery phase, it is established the normal process of prioritization of commands from cfifos. cfifo3 command cfifo4 command cfifo5 command cfifo0 command cfifo1 command cfifo2 command adc1 cbuffer1 adc0 for cbuffer0 prioritization 6 x command command (2 entries) command eqadc prioritization logic cbuffer0 (2 entries) usage for cbuffer1 prioritization usage abort cont0 abort cont1 RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1123/1740 external trigger event detection the digital filters for trigger signals can be individually bypassed by asserting the input control signals eqadc_intern_trig_sel5-0. when the filter is bypassed, the etrig input signal is not filtered and the logic after the filter receives a copy of this input trigger signal. the digital filter length field in section , eqadc external trigger digital filter register (eqadc_etdfr) , specifies the minimum number of system clocks that the etrig0-5 signals must be held at a logic level to be recognized as valid. all etrig signals are filtered. a counter for each queue trigger is implemented to detect a transition between logic levels. the counter counts at the system clock rate. the corresponding counter is cleared and restarted each time the signal transitions between logic levels. when the corresponding counter matches the value specified by the digital filter length field in section , eqadc external trigger digital filter register (eqadc_etdfr) , the eqadc considers the etrig logic level to be valid and passes that new logic level to the rest of the eqadc. the filter is only for filtering the etrig signal. logic after the filter checks for transitions between filtered values, such as for detecting the transition from a filtered logic level zero to a filter logic level one in rising edge external trigger mode. the eqadc can detect rising edge, falling edge, or level gated external triggers. the digital filter will always be active independently of the status of the mode x field in section , eqadc cfifo control registers (eqadc_cfcr) , but the edge, level detection logic is only active when modex is set to a value different from disabled, and in case modex is set to single scan mode, when the sss bit is asserted. note that the time necessary for a external trigger event to result into a cfifo status change is not solely determined by the dfl field in the section , eqadc external trigger digital filter register (eqadc_etdfr) . after being synchronized to the system clock and filtered, a trigger event is checked against the cfifo trigger mode. only then, after a valid trigger event is detected, the eqadc accordingly changes the cfifo status. refer to figure 635 for an example. figure 635. etrig event propagation example cfifo scan trigger modes the eqadc supports two different scan modes, single-scan and continuous-scan. refer to ta ble 62 1 for a summary of these two scan modes. when a cfifo is triggered, the eqadc scan mode determines whether the eqadc will stop command transfers from a cfifo, and wait for software intervention to rearm the cfifo to detect new trigger events, upon system clock external trigger signal filtered external cfifo status trigger signal signal state at input pin modex idle waiting for trigger triggered disabled continuous scan high level gated external trigger trigger detection delay trigger synchronization and filtering delay (obs. 1) obs. - 1: this delay is about 2 clocks when the filter bypass control is asserted. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1124/1740 doc id 15177 rev 8 detection of an asserted eoq bit in the last transfer. refer to section , message format in eqadc , for details about command formats. cfifos can be configured in single-scan or continuous-scan mode. when a cfifo is configured in single-scan mode, the eqadc scans the cqueue one time. the eqadc stops future command transfers from the triggered cfifo after detecting the eoq bit set in the last transfer. after a eoq bit is detected, software involvement is required to rearm the cfifo so that it can detect new trigger events. when a cfifo is configured for continuous-scan mode, no software involvement is necessary to rearm the cfifo to detect new trigger events after an asserted eoq is detected. in continuous-scan mode the whole cqueue is scanned multiple times. the eqadc also supports different triggering mechanisms for each scan mode. the eqadc will not transfer commands from a cfifo until the cfifo is triggered. the combination of scan modes and triggering mechanisms allows the support of different requirements for scanning input channels. the scan mode and trigger mechanism are configured by programming the modex field in section , eqadc cfifo control registers (eqadc_cfcr) . enabled cfifos can be triggered by software or external trigger events. the elapsed time from detecting a trigger to transferring a command is a function of clock frequency, trigger synchronization, trigger filtering or not, programmable trigger events, command transfer, cfifo prioritization, cbuffer availability, etc. fast and predictable transfers can be achieved by ensuring that the cfifo is not underflowing and that the target cbuffer is not full when the cfifo is triggered. disabled mode the mode x field in section , eqadc cfifo control registers (eqadc_cfcr) , for all of the cfifos can be changed from any other mode to disabled at any time. no trigger event can initiate command transfers from an cfifo which has its mode field programmed to disabled. note: if modex is not disabled, it must not be changed to any other mode besides disabled. if modex is disabled and the cfifo status is idle, modex can be changed to any other mode. if mode x is changed to disabled: the cfifo execution status will change to idle. the timing of this change depends on whether a command is being transferred or not: ? when no command transfer is in progress, the eqadc switches the cfifo to idle status immediately. ? when a command transfer to an on-chip cbuffer is in progress, the eqadc will complete the transfer, update tc_cf, and switch cfifo status to idle. command transfers to the internal cbuffers are considered completed when a command is written to the buffers. ? when a command transfer to an external cbuffer is in progress, the eqadc will abort the transfer and switch cfifo status to idle. if the eqadc cannot abort the transfer, that is when the 26th bit of the serial message has being already shifted out, the eqadc will complete the transfer, update tc_cf and then switch cfifo status to idle. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1125/1740 the cfifos are not invalidated automatically. the cfifo still can be invalidated by writing a ?1? to the cfinvx bit in section , eqadc cfifo control registers (eqadc_cfcr) . certify that cfs has changed to idle before setting cfinvx. the tc_cfx value also is not reset automatically, but it can be reset by writing ?0? to it. the sss bit in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is negated. the sss bit can be set even if a ?1? is written to the sse bit in section , eqadc cfifo control registers (eqadc_cfcr) , in the same write that the modex field is changed to a value other than disabled. the trigger detection hardware is reset. if modex is changed from disabled to an edge trigger mode, a new edge, matching that edge trigger mode, is needed to trigger the command transfers from the cfifo. note: cfifo fill requests, which generated when cfff is asserted, are not automatically halted when modex is changed to disabled. cfifo fill requests will still be generated until cffe is cleared in section , eqadc interrupt and dma control registers (eqadc_idcr) . single-scan mode in single-scan mode, a single pass through a sequence of command messages in a cqueue is performed. in single-scan software trigger mode, the cfifo is triggered by an asserted single-scan status bit (sss) in section , eqadc fifo and interrupt status registers (eqadc_fisr) . the sss bit is set by writing ?1? to the single-scan enable bit (sse) in section , eqadc cfifo control registers (eqadc_cfcr) . in single-scan edge- or level-trigger mode, the respective triggers are only detected when the sss bit is asserted. when the sss bit is negated, all trigger events for that cfifo are ignored. writing a ?1? to the sse bit can be done during the same write cycle that the cfifo operation mode is configured. only the eqadc can clear the sss bit. once sss is asserted, it remains asserted until the eqadc completes the cqueue scan, or the cfifo operation mode (modex) in section , eqadc cfifo control registers (eqadc_cfcr) , is changed to disabled. the sssx bit will be negated while mode x is disabled. single-scan software trigger when single-scan software trigger mode is selected, the cfifo is triggered by an asserted sss bit. the sss bit is asserted by writing ?1? to the sse bit. writing to sse while sss is already asserted will not have any effect on the state of the sss bit, nor will it cause a trigger overrun event. the cfifo commands start to be transferred when the cfifo becomes the highest priority cfifo using a not-full on-chip cbuffer or an not-full external cbuffer. when an asserted eoq bit is encountered, the eqadc will clear the sss bit. setting the sss bit is required for the eqadc to start the next scan of the queue. the pause bit has no effect in single-scan software trigger mode. single-scan edge trigger when sss is asserted and an edge triggered mode is selected for a cfifo, an appropriate edge on the associated trigger signal causes the cfifo to become triggered. for example, if rising-edge trigger mode is selected, the cfifo becomes triggered when a rising edge is sensed on the trigger signal. the cfifo commands start to be transferred enhanced queued analog-to-dig ital converter (eqadc) RM0029 1126/1740 doc id 15177 rev 8 when the cfifo becomes the highest priority cfifo using a not-full on-chip cbuffer or an not-full external cbuffer. when an asserted eoq bit is encountered, the eqadc clears sss and stops command transfers from the cfifo. an asserted sss bit and a subsequent edge trigger event are required to start the next scan for the cfifo. when an asserted pause bit is encountered, the eqadc stops command transfers from the cfifo, but sss remains set. another edge trigger event is required for command transfers to continue. a trigger overrun happens when the cfifo is in triggered state and an edge trigger event is detected. single-scan level trigger when sss is asserted and a level gated trigger mode is selected, the input level on the associated trigger signal puts the cfifo in triggered state. when the cfifo is asserted to high-level gated trigger, a high level signal opens the gate, and a low level closes the gate. when the cfifo is set to low-level gated trigger mode, a low level signal opens the gate, and a high level closes the gate. if the corresponding level is already present, setting the sss bit triggers the cfifo. the cfifo commands start to be transferred when the cfifo becomes the highest priority cfifo using a not-full on-chip cbuffer or a not -full external cbuffer. the eqadc clears the sss bit and stops transferring commands from a triggered cfifo when an asserted eoq bit is encountered or when cfifo status changes from triggered due to the detection of a closed gate. if a closed gate is detected while no command transfers are taking place and the cfifo status is triggered, the cfifo status is immediately changed to idle, the sss bit is negated, and the pf flag is asserted. if a closed gate is detected during the serial transmission of a command to the external device, it will have no effect on the cfifo status until the transmission completes. once the transmission is completed, the tc_cf counter is updated, the sss bit is negated, the pf flag is asserted, and the cfifo status is changed to idle. an asserted sss bit and a level trigger are required to restart the cfifo. command transfers will restart from the point they have stopped. if the gate closes and opens during the same serial transmission of a command to the external device, it will have no effect on the cfifo status or on the pf flag, but the torf flag will become asserted as was exemplified in figure 637 . therefore, closing the gate for a period less than a serial transmission time interval does not guarantee that the closure will affect command transfers from a cfifo. the pause bit has no effect in single-scan level-trigger mode. continuous-scan mode in continuous-scan mode, multiple passes looping through a sequence of command messages in a cqueue are executed. when a cfifo is programmed for a continuous-scan mode, the sse bit in the section , eqadc cfifo control registers (eqadc_cfcr) , does not have any effect. continuous-scan software trigger when a cfifo is programmed to continuous-scan software trigger mode, the cfifo is triggered immediately. the cfifo commands start to be transferred when the cfifo becomes the highest priority cfifo using a not-full on-chip cbuffer or an not-full external cbuffer. when a cfifo is programmed to run in continuous-scan software trigger mode, the eqadc will not halt transfers from the cfifo until the cfifo operation mode is modified to disabled or a higher priority cfifo preempts it. although command transfers will RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1127/1740 not stop upon detection of an asserted eoq bit, the eoqf is set and, if enabled, an eoq interrupt request is generated. the pause bit has no effect in continuous-scan software trigger mode. continuous-scan edge trigger when rising, falling, or either edge trigger mode is selected for a cfifo, a corresponding edge on the associated etrig signal places the cfifo in triggered state. the cfifo commands start to be transferred when th e cfifo becomes the highest priority cfifo using a not-full on-chip cbuffer or an not-full external cbuffer when an eoq or a pause is encountered, the eqadc halts command transfers from the cfifo and, if enabled, the appropriate interrupt requests are generated. another edge trigger event is required to resume command transfers but no software involvement is required to rearm the cfifo in order to detect such event. a trigger overrun happens when the cfifo is already in triggered state and a new edge trigger event is detected. continuous-scan level trigger when high or low level gated trigger mode is selected, the input level on the associated trigger signal places the cfifo in triggered state. when high-level gated trigger is selected, a high-level signal opens the gate, and a low level closes the gate. the cfifo commands start to be transferred when th e cfifo becomes the highest priority cfifo using a not-full on-chip cbuffer or an not-full external cbuffer. although command transfers will not stop upon detection of an asserted eoq bit at the end of a command transfer, the eoqf is asserted and, if enabled, an eoq interrupt request is generated. the eqadc stops transferring commands from a triggered cfifo when cfifo status changes from triggered due to the detection of a closed gate. if a closed gate is detected while no command transfers are taking place and the cfifo status is triggered, the cfifo status is immediately changed to waiting for trigger and the pf flag is asserted. if a closed gate is detected during the serial transmission of a command to the external device, it will have no effect on the cfifo status until the transmission completes. once the transmission is completed, the tc_cf counter is updated, the pf flag is asserted, and the cfifo status is changed to waiting for trigger. command transfers will restart as the gate opens. if the gate closes and opens during the same serial transmission of a command to the external device, it will have no effect on the cfifo status or on the pf flag, but the torf flag will become asserted as was exemplified in figure 637 . therefore, closing the gate for a period less than a serial transmission time interval does not guarantee that the closure will affect command transfers from a cfifo. the pause bit has no effect in continuous-scan level-trigger mode. cfifo scan trigger mode start/stop summary ta ble 62 1 summarizes the start and stop conditions of command transfers from cfifos for all of the single-scan and continuous-scan trigger modes. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1128/1740 doc id 15177 rev 8 cfifo and trigger status cfifo operation status each cfifos has its own cfifo status field. cfifo status (cfs) can be read from section , eqadc cfifo status register (eqadc_cfsr) . figure 636 and table 622 indicate the cfifo status switching condition. refer to table 579 for the meaning of each cfifo operation status. the last cfifo to transfer a command to an on-chip cbuffer can be read from the lcftcb n (n=0,1) fields in the section , eqadc cfifo status snapshot registers (eqadc_cfssr) . the last cfifo to transfer a command to a specific external cbuffer can be identified by reading the lcftssi and ecbni fields in the section , eqadc cfifo status snapshot registers (eqadc_cfssr) . table 621. cfifo scan trigger mode - command transfer start/stop summary trigger mode requires asserted sss to recognize trigger events? command transfer start/restart condition stop on asserted eoq bit (1) ? stop on asserted pause bit (2) ? other command transfer stop condition (3) (4) single scan software don?t care asserted sss bit. yes no none. single scan edge yes a corresponding edge occurs when the sss bit is asserted. yes yes none. single scan level yes gate is opened when the sss bit is asserted. yes n o eqadc also stops transfers from the cfifo when cfifo status changes from triggered due to the detection of a closed gate. (5) continuous scan software no cfifo starts automatically after being configured into this mode. no no none. continuous scan edge no a corresponding edge occurs. yes yes none. continuous scan level no gate is opened. no no eqadc also stops transfers from the cfifo when cfifo status changes from triggered due to the detection of a closed gate. (5) 1. refer to section , cqueue completion status , for more information on eoq. 2. refer to section , pause status , for more information on pause. 3. eqadc always stops command transfers from a cfifo when the cfifo operation mode is disabled. 4. eqadc always stops command transfers from a cfifo when a higher priority cfifo is triggered. refer to section , cfifo common prioritization and command transfer , for information on cfifo priority. 5. if a closed gate is detected while no command transfers are ta king place, it will have immediat e effect on the cfifo status. if a closed gate is detected during the seri al transmission of a command to the external device, it will have no effect on the cfifo status until the transmission completes. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1129/1740 figure 636. state machine of cfifo status idle waiting for trigger triggered 2 1 3 4 5 6 7 8 9 table 622. command fifo status switching condition no. from current cfifo status (cfs) to new cfifo status (cfs) status switching condition 1 idle (00) idle (0b00) ? cfifo mode is programmed to disabled, or ? cfifo mode is programmed to single-scan edge or level trigger mode and sss is negated. 2 waiting for trigger (0b10) ? cfifo mode is programmed to continuous-scan edge or level trigger mode, or ? cfifo mode is programmed to single-scan edge or level trigger mode and sss is asserted, or ? cfifo mode is programmed to single-scan software trigger mode. 3 triggered (0b11) ? cfifo mode is programmed to continuous-scan software trigger mode 4 waiting for trigger (10) idle (0b00) ? cfifo mode is modified to disabled mode. 5 waiting for trigger (0b10) ? no trigger occurred. 6 triggered (0b11) ? appropriate edge or level trigger occurred, or ? cfifo mode is programmed to single-scan software trigger mode and sss bit is asserted. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1130/1740 doc id 15177 rev 8 cqueue completion status the end of queue flag (eoqf) in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is asserted when the eqadc completes the transfer of a cfifo entry with an asserted eoq bit. software sets the eoq bit in the last command message of a cqueue to indicate that this entry is the end of the cqueue - see section , message format in eqadc , for information on command message formats. the transfer of entries bound for the on-chip adcs is considered completed when they are stored in the appropriate cbuffer. the transfer of entries bound for the external device is considered completed when the serial transmission of the entry is completed. the command with a eoq bit asserted is valid and will be transferred. when eoqie in section , eqadc cfifo control registers (eqadc_cfcr) , and eoqf are asserted, the eqadc will generate an end of queue interrupt request. in single-scan modes, command transfers from the corresponding cfifo will cease when eqadc completes the transfer of a entry with an asserted eoq. software involvement is required to rearm the cfifo so that it can detect new trigger events. 7 triggered (11) idle (0b00) ? cfifo in single-scan mode, eqadc detects the eoq bit asserted at end of command transfer, and cfifo mode is not modified to disabled.or ? cfifo, in single-scan level trigger mode, and the gate closes while no commands are being transferred from the cfifo, and cfifo mode is not modified to disabled. or ? cfifo, in single-scan level trigger mode, and eqadc detects a closed gated at end of command transfer, and cfifo mode is not modified to disabled. or ? cfifo mode is modified to disabled mode and cfifo was not transferring commands. ?cfifo mode is modified to disabled mode while cfifo was transferring commands, and cfifo completes or aborts the transfer. 8 waiting for trigger (0b10) ? cfifo in single or continuous-scan edge trigger mode, eqadc detects the pause bit asserted at the end of command transfer, the eoq bit in the same command is negated, and cfifo mode is not modified to disabled, or ? cfifo in continuous-scan edge trigger mode, eqadc detects the eoq bit asserted at the end of command transfer, and cfifo mode is not modified to disabled, or ? cfifo, in continuous-scan level trigger mode, and the gate closes while no commands are being transferred from the cfifo, and cfifo mode is not modified to disabled, or ? cfifo, in continuous-scan level trigger mode, and eqadc detects a closed gated at end of command transfer, and cfifo mode is not modified to disabled. 9 triggered (0b11) ? no event to switch to idle or waiting for trigger status has happened. table 622. command fifo status switching condition (continued) no. from current cfifo status (cfs) to new cfifo status (cfs) status switching condition RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1131/1740 note: an asserted eoqfx only implies that eqadc has finished transferring a command with an asserted eoq bit from cfifox. it does not imply that result data for the current command and for all previously transferred commands has been returned to the appropriate rfifo. pause status in edge trigger mode, when the eqadc completes the transfer of a cfifo entry with an asserted pause bit, the eqadc will stop future command transfers from the cfifo and set the corresponding pause flag (pf) in section , eqadc fifo and interrupt status registers (eqadc_fisr) . refer to section , message format in eqadc , for information on command message formats. the eqadc ignores the pause bit in command messages in any software and external level trigger mode. the eqadc sets the pf flag upon detection of an asserted pause bit only in single or continuous-scan edge trigger mode. when the pf flag is set for a cfifo in single-scan edge trigger mode, the sss bit will not be cleared in section , eqadc fifo and interrupt status registers (eqadc_fisr) . in level trigger mode, the definition of the pf flag has been redefined. in level trigger mode, when cfifox is in triggered status, pfx is set when cfifo status changes from triggered due to detection of a closed gate. the pause flag interrupt routine can be used to verify if the a complete scan of the cqueue was performed. if a closed gate is detected while no command transfers are taking place, it will have immediate effect on the cfifo status. if a closed gate is detected during the serial transmission of a command to the external device, it will have no effect on the cfifo status until the transmission completes. when pie in section , eqadc cfifo control registers (eqadc_cfcr) , and pf are asserted, the eqadc will generate a pause interrupt request. note: in edge trigger mode, an asserted pfx only implies that the eqadc finished transferring a command with an asserted pause bit from cfifox. it does not imply that result data for the current command and for all previously transferred commands has been returned to the appropriate rfifo. note: in software or level trigger mode, when the eqadc completes the transfer of an entry from cfifox with an asserted pause bit, pfx will not be set and command transfers will continues without pausing. trigger overrun status when a cfifo is configured for edge- or level-trigger mode and is in triggered state, an additional trigger occurring for the same cfifo results in a trigger overrun. the trigger overrun bit for the corresponding cfifo will be set (torf x = 1) in section , eqadc fifo and interrupt status registers (eqadc_fisr) . when torie in section , eqadc cfifo control registers (eqadc_cfcr) , and torf are asserted, the eqadc generates a trigger overrun interrupt request. for cfifos configured for level-trigger mode, a trigger overrun event is only detected when the gate closes and opens during a single serial command transmission as shown in figure 637 . enhanced queued analog-to-dig ital converter (eqadc) RM0029 1132/1740 doc id 15177 rev 8 figure 637. trigger overrun on level-trigger mode cfifos note: the trigger overrun flag will not set for cfifos configured for software trigger mode. command sequence non-coherency detection the eqadc provides a mechanism to indicate if a command sequence has been completely executed without interruptions. a command sequence is defined as a group of consecutive commands bound for the same cbuffer and it is expected to be executed without interruptions. a command sequence is coherent if its commands are executed in order without interruptions. since commands are stored in the cbuffers before being executed in the eqadc, a command sequence is coherent if, while it is transferring commands to a cbuffer, the buffer is only fed with commands from that sequence without ever becoming empty. a command sequence starts when: a cfifo in triggered state transfers its first command to cbuffer. the cfifo is constantly transferring commands and the previous command sequence ended. the cfifo resumes command transfers after being interrupted. and a command sequence ends when: an asserted eoq bit is detected on the last transferred command. cfifo is in edge-trigger mode and asserted pause bit is detected on the last transferred command. the cbuffer to which the next command is bound is different from the one to which the last command was transferred. figure 638 shows examples of how the eqadc would detect command sequences when transferring commands from a cfifo to a cbuffer. the smallest possible command sequence can have a single command as shown in example 3 of figure 638 . command transmission through eqadc ssi assumptions: low active level trigger cfifo status torf command 1 null message command 2 triggered wft triggered wft triggered if gate closes during a command transmission it is only recognized when the transmission ends. 1) cfifo programmed to ?continuous-scan low level gated external trigger mode? 2) command 2 has its abort_st bit negated. wft= waiting for trigger 3) there are no other cfifos using the serial interface. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1133/1740 figure 638. command sequence examples the ncf flag is used to indicate command sequence non-coherency. when the ncfx flag is asserted, it indicates that the command sequence being transferred through cfifox became non-coherent. the ncf flag only becomes asserted for cfifos in triggered state. cf5_cb1_cm0 cf5_cb1_cm1 cf5_cb1_cm2 cf5_cb1_cm3 (pause =1) cf5_cb1_cm4 cf5_cb1_cm5 cf5_cb1_cm6 (eoq =1) cf5_cb1_cm0 cqueue with a three cf5_cb1_cm1 cf5_cb1_cm2 cf5_cb0_cm3 cf5_cb0_cm4 cf5_cb1_cm5 cf5_cb1_cm6 (eoq =1) command sequences cf5_cb1_cm0 cqueue with a seven cf5_cb2_cm1 cf5_cb3_cm2 cf5_cb1_cm3 cf5_cb0_cm4 cf5_cb2_cm5 cf5_cb1_cm6 (eoq =1) command sequences example 3 example 1 example 2 cqueue with a two command sequences assuming that these commands are tr ansferred by a cfifo configured for edge trigger mode and the command transfers are never interrupted, the eqadc would check for non-coherency of two command sequences: one formed by commands 0, 1, 2, 3, and the other by commands 4, 5, 6. assuming that command transfers from the cfifo are never interrupted, the eqadc would check for non-coherency of three command sequences. the first being formed by commands 0, 1, 2, the second by commands 3, 4 and the third by commands 5, 6. note that even when the commands of this cqueue are transferred through a cfifo in continuous-scan mode, the first three commands and the last two commands of this cqueue would still constitute two distinct command sequences, although they are all bound for the same cbuffer, since an asserted eoq ends a command sequence. the eqadc would check for non-coherency of seven command sequences, all containing a single command, but ncf would never get set. cf x _cb a _cm n - command n in cfifo x bound for cbuffer a enhanced queued analog-to-dig ital converter (eqadc) RM0029 1134/1740 doc id 15177 rev 8 a command sequence is non-coherent when, after transferring the first command of a sequence from a cfifo to a cbuffer, it cannot successively send all the other commands of the sequence before any of the following conditions are true: the cfifo through which commands are being transferred is preempted by a higher priority cfifo which sends commands to the same cbuffer. the ncf flag becomes asserted immediately after the first command transfer from the preempting cfifo, that is the higher priority cfifo, to the cbuffer in use is completed. see figure 640 . the external cbuffer in use becomes empty (ba) . this case happens when different cfifos attempt to use different external cbuffers and the higher priority cfifo bars the lower priority one from sending new commands to its cbuffer - see figure 641 . an external cbuffer is considered empty when the corresponding busy field in the last result message received from external device is encoded as ?send available commands - cbuffer is empty?. refer to section , result message format for external device operation . the ncf flag becomes asserted immediately after the eqadc detects that the external cbuffer in use becomes empty. note: after the transfer of a command sequence to an external cbuffer starts, the eqadc ignores, for non-coherency detection purposes, the busy fields captured at the end of the first serial transmission. thereafter, all busy fields captured at the end of consecutive serial transmissions are used to check the fullness of that external cbuffer. this is done because the eqadc only updates its external cbuffers status record when it receives a serial message, resulting that the record kept by the eqadc is always outdated by, at least, the length of one serial transmission. this prevents a cfifo from immediately becoming non- coherent when it starts transferring commands to an empty external cbuffer. refer to figure 639 for an example. ba. only the fullness of external cbuffers is monitored bec ause the fill rate for internal cbuffers is many times faster than the drain rate, and each has a dedicated priority engine. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1135/1740 figure 639. external cbuffer status detection at command sequence transfer start once a command sequence starts to be transferred, the eqadc will check for the command sequence coherency until the command sequence ends or until one of the conditions below becomes true. the command sequence became non-coherent. the cfifo status changed from triggered. the cfifo underflowed. note: the ncf flag still becomes asserted if an external cbuffer empty event is detected at the same time the eqadc stops checking for the coherency of a command sequence. once command transfers restart/continue, the non-coherency hardware will behave as if the command sequence started from that point. figure 642 depicts how the non-coherency hardware will behave when a non-coherency event is detected. note: if modex is changed to disabled while a cfifo is transferring commands, the ncf flag for that cfifo will not become asserted. note: when the eqadc enters debug or stop mode while a command sequence is being executed, the ncf will become asserted if an empty external cbuffer is detected after debug/stop mode is exited. null message 1st command 2nd command 3rd command sds serial data (a) (b) (c) external cbuffer status capture point at eqadc cbuffer status at external device cbuffer status as captured by the eqadc used for ncf detection on the eqadc? (a) empty empty don?t care (b) 1 entry empty no (c) 2 entry 1 entry yes transmitted assumptions: 1. the cfifo starts sending commands to an empty external cbuffer when triggered. 2. execution of a command on the external device takes longer than the time to complete three serial transmissions. external cbuffer status starts to be monitored here. transfer of command sequence starts enhanced queued analog-to-dig ital converter (eqadc) RM0029 1136/1740 doc id 15177 rev 8 figure 640. non-coherency event when different cfifos use the same cbuffer * tnxtptr - transfer next data pointer tnxtptr * cf5_cb1_cm0 0 cf5_cb1_cm1 1 cf5_cb1_cm2 2 cf5_cb1_cm3 3 cf0_cb1_cm0 0 cf0_cb1_cm1 1 cf0_cb1_cm2 2 cf0_cb1_cm3 3 tnxtptr * empty 0 empty 1 cbuffer1 cfifo5 cfifo0 tnxtptr * sent 0 sent 1 cf5_cb1_cm2 2 cf5_cb1_cm3 3 cf0_cb1_cm0 0 cf0_cb1_cm1 1 cf0_cb1_cm2 2 cf0_cb1_cm3 3 tnxtptr * cf5_cb1_cm0 0 cf5_cb1_cm1 1 cbuffer1 cfifo5 cfifo0 tnxtptr * sent 0 sent 1 cf5_cb1_cm2 2 cf5_cb1_cm3 3 sent 0 cf0_cb1_cm1 1 cf0_cb1_cm2 2 cf0_cb1_cm3 3 tnxtptr * cf5_cb1_cm1 0 cf0_cb1_cm0 1 cbuffer1 cfifo5 cfifo0 (a) cfifo0 and cfifo5 both have commands to be sent to cbuffer1, and both are not triggered (b) cfifo5 becomes triggered and transfers two commands to cbuffer1 (c) cfifo0 becomes triggered and transfers a command to cbuffer1. the sequence sent through cf x _cb a _cm n - command n in cfifo x bound for cbuf cfifo5 becomes non-coherent. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1137/1740 figure 641. non-coherency event when different cfifos are using different external cbuffers * tnxtptr - transfer next data pointer tnxtptr * sent 0 sent 1 cf5_cb3_cm2 2 cf5_cb3_cm3 3 cf0_cb2_cm0 0 cf0_cb2_cm1 1 cf0_cb2_cm2 2 cf0_cb2_cm3 3 tnxtptr * cfifo5 cfifo0 empty 0 empty 1 cbuffer2 cf5_cb3_cm0 0 cf5_cb3_cm1 1 cbuffer3 eqadc ssi (a) cfifo0 and cfifo5 both have commands to be s ent to external cbuffers. cfifo0 is not triggered. cfifo5 is triggered and sent two commands to cbuffer3 tnxtptr * sent 0 sent 1 cf5_cb3_cm2 2 cf5_cb3_cm3 3 sent 0 sent 1 cf0_cb2_cm2 2 cf0_cb2_cm3 3 tnxtptr * cfifo5 cfifo0 cf0_cb2_cm0 0 cf0_cb2_cm1 1 cbuffer2 empty 0 cf5_cb3_cm1 1 cbuffer3 eqadc ssi (b) cfifo0 is triggered and sent two commands to cbuffer2. cfifo5 cannot send commands to cbuffer3 because the eqadc ssi is busy transferring commands from cfifo0. execution of first command of cfifo5 is completed. tnxtptr * sent 0 sent 1 cf5_cb3_cm2 2 cf5_cb3_cm3 3 sent 0 sent 1 sent 2 cf0_cb2_cm3 3 tnxtptr * cfifo5 cfifo0 cf0_cb2_cm1 0 cf0_cb2_cm2 1 cbuffer2 empty 0 cf5_cb3_cm1 1 cbuffer3 eqadc ssi (c) execution of first command of cfifo0 is completed and cfifo0 sends new command to cbuffer2. tnxtptr * sent 0 sent 1 cf5_cb3_cm2 2 cf5_cb3_cm3 3 sent 0 sent 1 sent 2 sent 3 tnxtptr * cfifo5 cfifo0 cf0_cb2_cm2 0 cf0_cb2_cm3 1 cbuffer2 empty 0 empty 1 cbuffer3 eqadc ssi (d) second command in cbuffer3 completes. cbuffer3 became empty before the complete command sequence in cfifo5 is sent to it. ncf5 becomes asserted when the eqadc receives an indication that cbuffer3 is empty, by the busy fields in the returning serial message. cf x _cb a _cm n - command n in cfifo x bound for cbuffer a enhanced queued analog-to-dig ital converter (eqadc) RM0029 1138/1740 doc id 15177 rev 8 figure 642. non-coherency detection when transfers from a command sequence are interrupted 25.6.5 eqadc result fifos rfifo basic functionality there are six rfifos located in the eqadc. each rfifo is four entries deep, and each rfifo entry is 16 bits long. each rfifo serves as a temporary storage location for the one of the rqueues allocated in system memory. result data is saved in the rfifos before being moved into the system rqueues. when an rfifo is not empty, the eqadc sets the corresponding rfdf bit in section , eqadc fifo and interrupt status registers (eqadc_fisr) . if rfde is asserted in section , eqadc interrupt and dma control registers (eqadc_idcr) , the eqadc generates a request so that an rfifo entry is moved to the rqueue. an interrupt request, served by the host cpu, is generated when rfds is negated, and a dma request, served by the dmac, is generated when rfds is asserted. the host cpu or the dmac responds to these requests by reading section , eqadc result fifo pop registers (eqadc_rfpr) , to retrieve data from the rfifo. note: the dmac should be configured to read a single result (16-bit data) from the rfifo pop registers for every asserted dma request it acknowledges. refer to section 25.7.2, eqadc/dmac interface , for dmac configuration guidelines. note: reading a word, a half-word, or any bytes from eqadc_rfprx will pop an entry from rfifox, and the rfctrx field will be decremented by one. figure 643 describes the important components in the rfifo. each rfifo is implemented as a circular set of registers to avoid the need to move all entries at each push/pop operation. the pop next data pointer always points to the next rfifo message to be retrieved from the rfifo when reading eqadc_rfpr. the receive next data pointer points to the next available rfifo location for storing the next incoming message from the on-chip adcs or from the external device. the rfifo counter logic counts the number of entries in rfifo and generates interrupt or dma requests to drain the rfifo. cf5_cb1_cm0 cf5_cb1_cm1 cf5_cb1_cm2 cf5_cb1_cm3 cf5_cb1_cm4 cf5_cb1_cm5 cf5_cb1_cm6 cf5_cb1_cm7 cf5_cb1_cm8 cf5_cb1_cm9 cf5_cb1_cm10 cf5_cb1_cm11 cf5_cb1_cm12 cf5_cb1_cm13 command sequence became non-coherent before command 4 was transferred. once command transfers are resumed, eqadc will only check for coherency after command 4. command sequence became non-coherent before command 11 was transferred. once command transfers are resumed, eqadc will only check for coherency after command 11. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1139/1740 popnxtptr in section , eqadc fifo and interrupt status registers (eqadc_fisr) , indicates which entry is currently being addressed by the pop next data pointer, and rfctr, in the same register, provides the number of entries stored in the rfifo. using popnxtptr and rfctr, the absolute addresses for pop next data pointer and receive next data pointer can be calculated using the following formulas: pop next data pointer address= rfifox_base_address + popnxtptrx*4 receive next data pointer address = rfifox_base_address + [(popnxtptrx+rfctrx) mod rfifo_depth] * 4 where a mod b returns the remainder of the division of a by b . rfifox_base_address is the smallest memory mapped address allocated to an rfifox entry. rfifo_depth is the number of entries contained in a rfifo - four in this implementation. when a new message arrives and rfifox is not full, the eqadc copies its contents into the entry pointed by the receive next data pointer. the rfifo counter rfctrx in section , eqadc fifo and interrupt status registers (eqadc_fisr) , is incremented by one, and the receive next data pointer x is also incremented by one (or wrapped around) to point to the next empty entry in rfifox. ho wever, if the rfifox is full, the eqadc sets the rfof in section , eqadc fifo and interrupt status registers (eqadc_fisr) . the rfifox will not overwrite the older data in the rfifo, the new data will be ignored, and the receive next data pointer x is not incremented or wrapped around. rfifox is full when the receive next data pointer x equals the pop next data pointer x and rfctrx is not zero. rfifox is empty when the receive next data pointer x equals the pop next data pointer x and rfctrx is zero. when the eqadc rfifo pop register x is read and the rfifox is not empty, the rfifo counter rfctrx is decremented by one, and the pop next data pointer is incremented by one (or wrapped around) to point to the next rfifo entry. when the eqadc rfifo pop register x is read and rfifox is empty, eqadc will not decrement the counter value and the pop next data pointer x will not be updated. the read value will be undefined. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1140/1740 doc id 15177 rev 8 figure 643. rfifo diagram the detailed behavior of the pop next data pointer and receive next data pointer is described in the example shown in figure 644 where an rfifo with 16 entries is shown for clarity of explanation, the actual hardware implementation has only four entries. in this example, rfifox with 16 entries is shown in sequence after popping or receiving entries. data entry 2 data entry 1 -------------------- -------------------- pop next data pointer * receive next data pointer * rfifo pop register data from rfifo counter control logic dma done interrupt/dma request external device or from on-chip adcs or from control signals * all rfifo entries are memory mapped and the entries addressed by these pointers can have their absolute addresses calculated using popnxtptr and rfctr. parallel side interface read from slave- bus interface by cpu or dma RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1141/1740 figure 644. rfifo entry pointer example receive pop rfifox first in after reset or invalidation next data pointer next data pointer last in valid entry empty entry receive pop rfifox some entries received but none popped next data pointer next data pointer pop rfifox no entries received but some popped next data pointer first in last in receive next data pointer receive rfifox entries received until full and none popped next data pointer rfifox no entries received but some popped pop rfifox some entries received and some popped next data pointer first in last in receive next data pointer pop next data pointer first in last in receive next data pointer pop next data pointer first in last in note: x=0, 1, 2, 3, 4, 5 enhanced queued analog-to-dig ital converter (eqadc) RM0029 1142/1740 doc id 15177 rev 8 distributing result data into rfifos data to be moved into the rfifos can come from four sources: from adc0, from adc1, from the external device or from the decimation filter a or b, or reaction module through the psi. all result data comes with a message_tag field and a dest field defining what should be done with the received data. the eqadc hardware decodes the message_tag and dest fields and: stores the 16-bit data into the appropriate rfifo if the message_tag indicates a valid rfifo number, or; sends the 16-bit data, the message_tag and the dest data through the psi to decimation filter a or b or reaction module, or; ignores the data in case of a null or ?reserved for customer use? message_tag. in general received data is moved into rfifos as they become available, while an exception happens when multiple results from different sources become available at the same time. in that case, result data from adc0 is processed first, result data from adc1 is only process after all adc0 data is processed, result data from the external device is only processed after all data from adc0/1 is processed, and finally returned data from companion module is only processed after all data from adc0/1 and external device is processed. when time-stamped results return from the on-chip adcs, the conversion result and the time stamp are always moved to the rfifos in consecutive clock cycles in order to guarantee they are always stored in consecutive rfifo entries. 25.6.6 on-chip adc configuration and control enabling and disabling the on-chip adcs the on-chip adcs have an enable bit (adc0/1_en) in the section , , which allows the enabling of the adcs only when necessary. when the enable bit for an adc is negated, the clock input to that adc is stopped. the adcs are disabled out of reset - adc0/1_en bits are negated - to allow for their safe configuration. the adc must only be configured when its enable bit is negated. once the enable bit of an adc is asserted, clock input to is started. note: conversion commands sent to the cbuffer of a disabled adc are ignored by the adc control hardware. note: a 8ms wait time from vdda power up to enabling adc is required to pre-charge the external 100nf capacitor on refbypc pin. this time must be guaranteed by crystal startup time plus reset duration or user. note: due to legacy reasons, the eqadc will always wait 120 adc clocks before issuing the first conversion command following the enabling of one of on-chip adcs, or the exiting of stop mode. there are two independent counters checking for this delay: one clocked by adc0_clk and another by adc1_clk. conversion commands can start to be executed whenever one of these counters completes counting 120 adc clocks. adc clock and conversion speed the clock input to the adcs is defined by setting the adc0/1_odd_ps, the adc0/1_clk_sel and the adc0/1_clk_ps fields in the section , adc0/1 control registers (adc0_cr and adc1_cr) . when the adc0/1_clk_sel is set, the adc clock frequency is the same as the system clock, but it has the inverted phase. when it is clear, the adc0/1_odd_ps and the adc0/1_clk_ps fields select the clock divide factor by RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1143/1740 which the system clock will be divided as showed in table 593 . the adc clock frequency is calculated as below and it must not exceed 15 mhz. this is also the maximum frequency of system clock when the adc0/1_clk_sel is asserted. figure 645 depicts how the adc clocks for adc0 and adc1 are generated. figure 645. adc0/1 clock generation the adc conversion speed (in k samples per second - ksps) is calculated by the following formula. t he number of sampling cycles is determined by the lst bits in the command message - see section , conversion command format for the standard configuration - and it can take one of the following values: 2, 8, 64, or 128 adc clock cycles. the number of ad conversion cycles is 13 for differential conversions and 14 for single-ended 12-bit resolution and unitary input gain. the maximum conversion speed is achieved when the adc clock frequency is set to its maximum (15 mhz) and the number of sampling cycles set to its minimum (2 cycles). the maximum conversion speed for differential and single-ended conversions are 1msps and 937.5ksps, respectively. adcclockfrequency systemclockfrequency mhz () systemclockdividefactor ------------------------------------------------------------------------------------------ adcclockfrequency 15mhz () ; = divide by: 2, 3, 4, .. , 63, 64, 65 adc0 control register adc0_clk_ps to adc0 system clock divider system clock adc0clock sel adc0_clk_sel divide by: 2, 3, 4, .. , 63, 64, 65 adc1 control register adc1_clk_ps to adc1 system clock divider system clock adc1clock sel adc1_clk_sel adc0_odd_ps adc1_odd_ps adcconversionspeed adcclockfrequency mhz () numberofsamplingcycles numberofadconversioncycles + () ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------ = enhanced queued analog-to-dig ital converter (eqadc) RM0029 1144/1740 doc id 15177 rev 8 ta ble 62 3 shows an example of how the adc0/1_clk_ps can be set when using a 120 mhz system clock and the corresponding conversion speeds for all possible adc clock frequencies. the table also shows that according to the system clock frequency, certain clock divide factors are invalid (2, 4, 6, 8 clock divide factors in the example) since their use would result in a adc clock frequency higher than the maximum one supported by the adc. adc clock frequency must not exceed 15 mhz. table 623. adc clock configuration example (system clock frequency=120 mhz) adc0/1_clk_ps [0:4] adc0/1_ odd_ps system clock divide factor adc clock (system clock = 120 mhz) differential conversion speed with default sampling time (2 cycles) single-ended conversion speed with default sampling time (2 cycles) 0b00000 0 2 n/a n/a n/a 1 3 n/a n/a n/a 0b00001 0 4 n/a n/a n/a 1 5 n/a n/a n/a 0b00010 0 6 n/a n/a n/a 1 7 n/a n/a n/a 0b00011 0 8 15.0 mhz 1.0 msps 938 ksps 1 9 13.3 mhz 889 ksps 833 ksps 0b00100 0 10 12.0 mhz 800 ksps 750 ksps 1 11 10.9 mhz 727 ksps 682 ksps 0b00101 0 12 10.0 mhz 667 ksps 625 ksps 1 13 9.23 mhz 615 ksps 577 ksps 0b00110 0 14 8.57 mhz 571 ksps 536 ksps 1 15 8.0 mhz 533 ksps 500 ksps 0b00111 0 16 7.5 mhz 500 ksps 469 ksps 1 17 7.06 mhz 471 ksps 441 ksps 0b01000 0 18 6.67 mhz 444 ksps 417 ksps 1 19 6.32 mhz 421 ksps 395 ksps 0b01001 0 20 6.0 mhz 400 ksps 375 ksps 1 21 5.71 mhz 381 ksps 357 ksps 0b01010 0 22 5.45 mhz 364 ksps 341 ksps 1 23 5.22 mhz 348 ksps 326 ksps 0b01011 0 24 5.0 mhz 333 ksps 313 ksps 1 25 4.80 mhz 320 ksps 300 ksps 0b01100 0 26 4.62 mhz 308 ksps 288 ksps 1 27 4.44 mhz 296 ksps 278 ksps RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1145/1740 0b01101 0 28 4.29 mhz 286 ksps 268 ksps 1 29 4.14 mhz 276 ksps 259 ksps 0b01110 0 30 4.0 mhz 267 ksps 250 ksps 1 31 3.87 mhz 258 ksps 242 ksps 0b01111 0 32 3.75 mhz 250 ksps 234 ksps 1 33 3.64 mhz 242 ksps 227 ksps 0b10000 0 34 3.53 mhz 235 ksps 221 ksps 1 35 3.43 mhz 229 ksps 214 ksps 0b10001 0 36 3.33 mhz 222 ksps 208 ksps 1 37 3.24 mhz 216 ksps 203 ksps 0b10010 0 38 3.16 mhz 211 ksps 198 ksps 1 39 3.08 mhz 205 ksps 192 ksps 0b10011 0 40 3.0 mhz 200 ksps 188 ksps 1 41 2.93 mhz 195 ksps 183 ksps 0b10100 0 42 2.86 mhz 190 ksps 179 ksps 1 43 2.79 mhz 186 ksps 174 ksps 0b10101 0 44 2.73 mhz 182 ksps 170 ksps 1 45 2.67 mhz 178 ksps 167 ksps 0b10110 0 46 2.61 mhz 174 ksps 163 ksps 1 47 2.55 mhz 170 ksps 160 ksps 0b10111 0 48 2.5 mhz 167 ksps 156 ksps 1 49 2.45 mhz 163 ksps 153 ksps 0b11000 0 50 2.4 mhz 160 ksps 150 ksps 1 51 2.35 mhz 157 ksps 147 ksps 0b11001 0 52 2.31 mhz 154 ksps 144 ksps 1 53 2.26 mhz 151 ksps 142 ksps 0b11010 0 54 2.22 mhz 148 ksps 139 ksps 1 55 2.18 mhz 145 ksps 136 ksps 0b11011 0 56 2.14 mhz 143 ksps 134 ksps 1 57 2.11 mhz 140 ksps 132 ksps 0b11100 0 58 2.07 mhz 138 ksps 129 ksps 1 59 2.03 mhz 136 ksps 127 ksps table 623. adc clock configuration example (s ystem clock frequency=120 mhz) (continued) adc0/1_clk_ps [0:4] adc0/1_ odd_ps system clock divide factor adc clock (system clock = 120 mhz) differential conversion speed with default sampling time (2 cycles) single-ended conversion speed with default sampling time (2 cycles) enhanced queued analog-to-dig ital converter (eqadc) RM0029 1146/1740 doc id 15177 rev 8 adc sampling delay after power-up to guarantee accuracy specifications, a delay of at least 8 ms must be present between the power-up of the vdda supply and the start of the first adc conversion. this delay allows internal adc references to settle. the accuracy of a conversion during the first 8 ms is not guaranteed by the specifications, however conversion within the first 8 ms will be possible on the eqadc if this delay is not implemented in software. time stamp feature the on-chip adcs can provide a time stamp for the conversions they execute. a time stamp is the value of the time base counter latched when the eqadc detects the end of the analog input voltage sampling. a time stamp for a conversion command is requested by setting the tsr bit in the corresponding command. when tsr is negated, that is a time stamp is not requested, the adc returns a single result message containing the conversion result. when tsr is asserted, that is a time stamp is requested, the adc returns two result messages; one containing the conversion result, and afterwards another containing the time stamp for that conversion. the result messages are sent in this order to the rfifos and both messages are sent to the same rfifo was specified in the message_tag field of the executed conversion command. the time stamp can be provided by an external source using the stac bus interface (more details in section , stac client submodule (redlc) ) or by the internal time base counter. the selection between the two sources is done by field adc0/1_tbsel in the adc0/1_cr register or by field atbsel in registers adc_acr1-8. refer to ta ble 59 2 and table 602 for selection details. the time base counter is a 16-bit up counter that wraps after reaching 0xffff. it is disabled after reset and it is enabled according to the setting of tbc_clk_ps field in section , adc time stamp control register (adc_tscr) . tbc_clk_ps defines if the counter is enabled or disabled, and, if enabled, at what frequency it is incremented. the time stamps are returned regardless of whether the time base counter is enabled or disabled. the time base counter can be reset by writing 0x0000 to the section , adc time base counter registers (adc_tbcr) , with a write configuration command. 0b11101 0 60 2.0 mhz 133 ksps 125 ksps 1 61 1.97 mhz 131 ksps 123 ksps 0b11110 0 62 1.94 mhz 129 ksps 121 ksps 1 63 1.90 mhz 127 ksps 119 ksps 0b11111 0 64 1.88 mhz 125 ksps 117 ksps 1 65 1.85 mhz 123 ksps 115 ksps table 623. adc clock configuration example (s ystem clock frequency=120 mhz) (continued) adc0/1_clk_ps [0:4] adc0/1_ odd_ps system clock divide factor adc clock (system clock = 120 mhz) differential conversion speed with default sampling time (2 cycles) single-ended conversion speed with default sampling time (2 cycles) RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1147/1740 stac client submodule (redlc) the shared time and angle count (stac) bus provides access to one external time base, imported from the stac bus to the eqadc. the etpu2 module's time bases and angle count can be exported through the stac client submodule interface. time base and/or angle information of the etpu2 engine can be exported to the emios module and the eqadc, which are stac clients. the device?s stac server identification assignment is shown in table 624 . the time slot assignment is fixed, so only time bases running at system clock divided by four or slower can be integrally exported. the stac client submodule runs with the system clock, and its time slot timing is synchronized with the etpu2 timing on reset. the time slot sequence is 0- 1-2-3, such that they alternate between etpu time bases. figure 646. redlc block diagram the eqadc_redlccr[srv1] bit selects the time slot of the stac timebase 1 output and the eqadc_redlccr[srv2] bit selects the time slot of the stac timebase 2 output. figure 647 shows a timing diagram for the stac client submodule. table 624. stac client submodule server slot assignment etpu2 engine time base server id tcr1 0 tcr2 2 srv3 srv2 srv1 srv0 stac bus time base stac client submodule 1 (24-bit wide) output time slot selector bits srv3 srv2 srv1 srv0 time base stac client submodule 2 output time slot selector bits enhanced queued analog-to-dig ital converter (eqadc) RM0029 1148/1740 doc id 15177 rev 8 figure 647. timing diagram for the stac bus and stac client submodule output every time the selected time slot changes, the stac client submodule output is updated. after the slot selection is done and the timebase data is extracted, the stac client submodule selects 16 bits from the original 24-bit timebase data. these selected bits are the timebase to be used internal to the eqadc. adc pre-gain feature each adc can be configured to have a selectable input gain as defined in section , alternate configuration 1-8 control registers (adc_acr1-8) . this means the input signal is sampled and the result is amplified by factor 2, or 4 before the conversion phase. in present implementation of this feature, the conversion is 1 or 2 adc clock cycles longer for gain 2 or gain 4, respectively. adc resolution selection feature the adcs conversion resolutions can be 8 bits, 10 bits or 12 bits as described in section , alternate configuration 1-8 control registers (adc_acr1-8) . for conversions at a resolution less than 12, the adc is executing less operations and the conversion time is smaller. in this adc, it is verified that there is 1 adc clock cycle for each bit of resolution. therefore, for the same adc clock frequency, the adc sample frequency is higher for lower resolutions. when a conversion is undertaken at a resolution less than 12, the result is presented by the adc in right justified format in the 12-bit input bus e.g.: 0000xxxxxxxx for 8 bits and 00xxxxxxxxxx for 10 bits. the eqadc inverts the result to left justified format i.e.: xxxxxxxx0000 for 8 bits and xxxxxxxxxx00 for 10 bits. this is because the same calibration coefficients in the mac can then be used. the left shift operation is done just after the conversion result enters the eqadc, in the resolution adjustment block prior to the mac, as illustrated in figure 650 . ts[02] stac bus (submodule input) ts[00] ts[01] ts[02] time base (submodule output) ts[01] xx the srv bits are set to capture ts[01]. ts[03] ts[00] ts[03] ts[00] ts[01] system clock ts[01] stac bus (redc input) ts[00] ts[01] ts[02] 1. maximum of 16 time slots (tsn) notes: ts[01] ts[00] tsn1 ts[02] time base (redc output) ts[01] ts[01] xx 2. the srv bits capture ts[01] RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1149/1740 adc calibration feature overview there are three sets of calibration coefficients for each adc. each set is composed by a gain factor and an offset factor: gccn/occn, altgccn1/altgccn1, and altgccn2/altgccn2, where n is the adc number 0 or 1. the pair gccn/occn is selected when it is used the normal configuration or the alternate configurations 3 to 8. the pair altgccn1/altgccn1 is used only when the alternate configuration 1 is selected. and the pair altgccn2/altgccn2 is for the alternate configuration 2. the description below is for a generic pair of gain/offset gcc/occ. the eqadc provides a calibration scheme to remove the effects of gain and offset errors from the results generated by the on-chip adcs. only results generated by the on-chip adcs are calibrated. the results generated by adcs on the external device are directly sent to rfifos unchanged. the main component of calibration hardware is a multiply-and- accumulate (mac) unit, one per on-chip adc, that is used to calculate the following transfer function which relates a calibrated result to a raw, uncalibrated one. cal_res = gcc * raw_res + occ+2; where: cal_res is the calibrated result corresponding the input voltage v i . gcc is the gain calibration constant. raw_res is the raw, uncalibrated result with resolution adjustment corresponding to an specific input voltage v i . occ is the offset calibration constant. the addition of two reduces the maximum quantization error of the adc. see section , quantization error reduction during calibration . calibration constants gcc and occ are determined by taking two samples of known reference voltages and using these samples to calculate the values for the constants. for details and an example about how to calculate the calibration constants and use them in result calibration refer to section 25.7.6, adc result calibration . once calculated, gcc is stored in the section , adc0/1 gain calibration constant registers (adc0_gccr and adc1_gccr) , and occ in section , adc0/1 offset calibration constant registers (adc0_occr and adc1_occr) , from where their values are fed to the mac unit. the alternate gain values are stored in section , adc0/1 alternate gain registers (adc0_agr1-2 and adc1_agr1-2) , and the alternate offset values in section , adc0/1 alternate offset register (adc0_aor1-2 and adc1_aor1-2) . since the analog characteristics of each on-chip adcs differs, each adc has an independent pair of calibration constants. a conversion result is calibrated according to the status of cal bit in the command that initiated the conversion. if the cal bit is asserted, the eqadc will automatically calculate the calibrated result before sending the result to the appropriate rfifo or companion module. if the cal bit is negated, the result is not calibrated, it bypasses the calibration hardware, and is directly sent to the appropriate rfifo or companion module. mac unit and operand data format the mac unit diagram is shown in figure 648 . each on-chip adc has a separate mac unit to fine-tune its conversion results. the description below considers the general calibration constant registers but it is the same for the alternate calibration constants. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1150/1740 doc id 15177 rev 8 the occ0/1 operand is a 14-bit signed value stored in the section , adc0/1 offset calibration constant regi sters (adc0_occr and adc1_occr) . the raw_res operand is the raw uncalibrated result, and it is the direct output from the on-chip adcs but passing through the resolution adjustment block. the gcc0/1 operand is a 15-bit fixed point unsigned value stored in the section , adc0/1 gain calibration constant registers (adc0_gccr and adc1_gccr) . the gcc is expressed in the gcc_int.gcc_frac binary format. the integer part of the gcc (gcc_int=gcc[1]) contains a single binary digit while its fractional part (gcc_frac=gcc[2:15]) contains 14 bits - see figure 649 . the gain constant equivalent decimal value ranges from 0 to 1.999938..., as shown in ta ble 62 5 . two is always added to the mac output - see section , quantization error reduction during calibration . cal_res output is the calibrated result, and it is a 14-bit unsigned value. cal_res is truncated to 0x3fff, in case of a overflow, and to 0x0000, in case of an underflow. figure 648. mac unit diagram gcc_int - integer part of the gain calibration constant for adc0/1 gcc_int is the integer part of the gain calibration constant for adc0/1. gcc_frac[1:14] - fractional part of th e gain calibration constant for adc0/1 gcc_frac is the fractional part of the gain calibration constant for adc0/1. gcc_frac expresses decimal values ranging from 0 to 0.999938... mac unit calibrated result (cal_res) (14-bit unsigned value) raw uncalibrated result (raw_res) (12-bit unsigned value) gain calibration constant (gcc0/1) (15-bit fixed point unsigned value from adc0/1_gccr register) offset calibration constant (occ0/1) (14-bit signed value from adc0/1_occr register) + 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 gcc_int gcc_frac gcc[1] gcc[2:15] figure 649. gain calibration constant format RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1151/1740 adc control logic overview and command execution figure 650 shows the basic logic blocks involved in the adc control and how they interact. cfifos/rfifos interact with cbuffers/ abort cont / result message return logic through the fifo control unit . the eb and bn bits in the command message uniquely identify the cbuffer to which a command should be sent. the fifo control unit decodes these bits and sends the adc command to the proper cbuffer. other blocks of logic are the resolution adjustment , result format and calibration sub-block , the time stamp logic, and the mux control logic . the resolution adjustment sub-block receives the 12-bit data bus directly from the adc and changes the received conversion results from right aligned format of adc to the left aligned format depending on the selected resolution of the conversion. this operation helps the calibration processing to use the calibration coefficients always with the same format. the result format and calibration sub-block formats the returning data into result messages and sends them to the rfifos (bb) . the returning data can be data read from an adc register, a conversion result, or a time stamp. the formatting and calibration of conversion results also take place inside this sub-block. the time stamp logic latches the value of the time base counter or the stac bus time base when detecting the end of the analog input voltage sampling, and sends it to the result format and calibration sub-block as time stamp information. the mux control logic generates the proper mux control signals and, when the adc0/1_emux bits are asserted, the ma signals based on the channel numbers extracted from the adc command. when the on-chip adc abort feature is not enabled, adc commands are stored in the cbuffers as they come and they are executed in the first-in-first-out basis. after the execution of a command in entry1 finishes all commands are shifted one entry. after the table 625. binary and decimal representations of the gain constant gain constant (gcc_int.gcc_frac binary format) corresponding decimal value 0.0000_0000_0000_00 0 ... ... 0.1000_0000_0000_00 0.5 ... ... 0.1111_1111_1111_11 0.999938... 1.0000_0000_0000_00 1 ... ... 1.1100_0000_0000_00 1.75 ... ... 1.1111_1111_1111_11 1.999938... bb. the result messages may also be routed to an on-chip companion module via the side interface, and then fed back to the rfifos. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1152/1740 doc id 15177 rev 8 shift, entry0 is always empty and ready to receive a new command. execution of configuration commands only start when they reach entry1. consecutive conversion commands are pipelined and their execution can start while in entry0. this is explained below. ad conversion accuracy can be affected by the settling time of the input channel multiplexers. some time is required for the channel multiplexers internal capacitances to settle after the channel number is changed. if the time prior to sampling is not long enough to absorb this settling, then the settling time will take from adc sampling time which may result in inaccurate sampling and ultimately compromise conversion result accuracy - see figure 651 (a). this could be avoided by switching the multiplexers in preparation for the next command?s sampling during the ad conversion phase of the current command as showed in figure 651 (b). in eqadc, this is done in the following way; when a conversion command is in buffer entry1 and another conversion command is identified in entry0, then the channel number of entry0 is sent to the mux control logic some cycles before the sampling phase of the command in entry0 starts. in this way, sampling for the next command can promptly start after the current conversion finishes because the internal capacitance of the multiplexers will be settled by that time, allowing for more accurate sampling. this is specially important for applications that require high conversion speeds, that is with the adc running at maximum clock frequency and with the analog input voltage sampling time set to a minimum (2 adc clock cycles), when the short sampling time does not allow the multiplexers to completely settle. the second advantage of pipelining conversion commands is to provide precise conversion intervals, which means the time intervals between two consecutive conversions are the same. this is important for any digital signal process application. when the on-chip adc abort feature is enabled, adc commands from cfifo0 should be considered immediately, even stopping the execution of some command that is already in entry1. when the abort request is sent to the adc, the already stored commands in the cbuffers are copied in a temporary set of registers. the first adc command from cfifo0 is sent after the abort acknowledge indication from adc. the process is the same as usual until the transfer of the last command from cfifo0. then the temporarily stored commands that were postponed by the abortion are recovered and they are pipelined for execution. after the last command from this temporary memory is transferred, the next commands are pipelined from the cfifos. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1153/1740 figure 650. on-chip adc control scheme channel_number1 mux 40:1 adc0 adc1 cfifox rfifox mux 40:1 bias gen mux an0-an39 refbypc control 16 bits time stamp result1 time stamp 0 result0 tsr0 message_tag1; fmt1, cal1 emux1 tbc_clk_ps 32 bits ma0, ma1, ma2 entry1 entry0 configuration entry1 entry0 tsr1 addr or/and data addr or/and data register data 0/1 channel_number0 time stamp1 registers cbuffer1 cbuffer0 logic logic fifo control unit emux0 register field words in shaded boxes represent configuration register fields adc1_result1 adc0_result0 lst1 lst0 note: x=0, 1, 2, 3, 4, 5 message_tag0; fmt0, cal0 pre-charge ref gen psi abort cont abort cont resolution adjust resolution adjust result format and calibration sub-block enhanced queued analog-to-dig ital converter (eqadc) RM0029 1154/1740 doc id 15177 rev 8 figure 651. overlapping consecutive conversion commands 25.6.7 internal/external multiplexing channel assignment the internal analog multiplexers select one of the 40 analog input pins for conversion, based on the channel_number field of a command message. the analog input pin channel number assignments and the pin definitions vary depending on how the adc0/1_emux are configured. allowed combinations of adc0/1_emux bits are shown in ta ble 62 6 together with references to tables indicating how channel_number field of each conversion command must be set to avoid channel selection conflicts. during differential conversions the analog multiplexer passes differential signals to both the positive and negative terminals of the adc. the differential conversions can only be initiated on four channels: dan0, dan1, dan2, and dan3. refer to table 627 and ta ble 62 8 for the channel numbers used to select differential conversions. channel # change and sample start (a) command execution sequence for two non-overlapped commands (b) command execution sequence for two overlapped commands minimum time necessary to perform a single conversion after c hannel number is changed channel # change and sample start ad conversion mux settle time and sampling ad conversion mux settle time and sampling conversion starts immediately after channel # change.adc sample time should compensate for mux internal capacitance settling and for the sampling on the sampling capacitor. if sample time is not long enough, this can lead to inaccurate conversion results. ad conversion change channel # mux settle time and sampling channel # change and sample start ad conversion sampling sample start channel # changes before sampling starts leading to more time for mux internal capacitance to settle. mux settle time RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1155/1740 table 627 shows the channel number assignments for the non-multiplexed mode. the 43 single-ended channels and 4 differential pairs are shared between the two adcs. table 626. adc0/1_emux bits combinations adc0_emux adc1_emux channel_number should be set as in adc0 adc1 0 0 refer to table 627 refer to table 627 0 1 refer to table 627 refer to table 628 1 0 refer to table 628 refer to table 627 11 reserved (1) 1. adc0_emux and adc1_emux must not be asserted at the same time. table 627. non-multiplexed channel assignments (1) input pins adc channel number in channel_number field analog pin name other functions conversion type adc number binary decimal an0 to an39 single-ended adc0/adc1 0000_0000 to 0010_0111 0 to 39 vrh single-ended adc0/adc1 0010_1000 40 vrl single-ended adc0/adc1 0010_1001 41 50% x vref (2),(3) (do not use for calibration) single-ended adc0/adc1 0010_1010 42 75% x vref (2) single-ended adc0/adc1 0010_1011 43 25% x vref (2) single-ended adc0/adc1 0010_1100 44 ina_adc0/1_0 buffered bandgap single-ended adc0/adc1 0010_1101 45 reserved 0010_1110 to 0101_1111 46 to 95 dan0+ and dan0- differential adc0/adc1 0110_0000 96 dan1+ and dan1- differential adc0/adc1 0110_0001 97 dan2+ and dan2- differential adc0/adc1 0110_0010 98 dan3+ and dan3- differential adc0/adc1 0110_0011 99 reserved 0110_0100 to 0111_1111 100 to 127 ina_adc0/1_1 temp sensor single-ended adc0/adc1 1000_0000 128 ina_adc0/1_2 spare single-ended adc0/adc1 1000_0001 129 reserved 1000_0010 to 1000_1111 130 to 143 enhanced queued analog-to-dig ital converter (eqadc) RM0029 1156/1740 doc id 15177 rev 8 ta ble 62 8 shows the channel number assignments for multiplexed mode. the adc with the adc0/1_emux bit asserted can access 4 differential pairs, 39 single-ended, and, at most, 64 externally multiplexed channels. refer to section , external multiplexing , for a detailed explanation about how external multiplexing can be achieved. device specific use adc0 1001_0000 to 1001_0011 144 to 147 reserved adc1 1001_0000 to 1001_0011 144 to 147 reserved 1001_0100 to 1010_0001 148 to 161 reserved adc1 1010_0010 to 1010_0111 162 to 167 ina_adc0_3 device specific single-ended adc0 1010_0010 162 ina_adc0_4 device specific single-ended adc0 1010_0011 163 ina_adc0_5 device specific single-ended adc0 1010_0100 164 ina_adc0_6 device specific single-ended adc0 1010_0101 165 ina_adc0_7 device specific single-ended adc0 1010_0110 166 ina_adc0_8 device specific single-ended adc0 1010_0111 167 reserved 1010_1000 to 1100_0001 168 to 193 reserved adc0 1100_0010 to 1100_0111 194 to 199 ina_adc1_3 device specific single-ended adc1 1100_0010 194 ina_adc1_4 device specific single-ended adc1 1100_0011 195 ina_adc1_5 device specific single-ended adc1 1100_0100 196 ina_adc1_6 device specific single-ended adc1 1100_0101 197 ina_adc1_7 device specific single-ended adc1 1100_0110 198 ina_adc1_8 device specific single-ended adc1 1100_0111 199 reserved 1100_1000 to 1111_1111 200 to 255 1. the two on-chip adcs can access the same analog input pi ns but simultaneous conversions are not allowed. also, when one adc is performing a differential conversion on a pair of pi ns, the other adc must not acce ss either of these two pins as single-ended channels. 2. vref=vrh-vrl. 3. 50% x vref = 50% ref = (vrh / vrl)/2, but this only applies before calibration. after calibration, the 50% reference point will actually return approximately 20 mv lower than the expected 50% of the difference between the high reference voltage (vrh) and the low reference voltage (vrl).the 50% re ference point should not be used to calibrate adc. for calibration of the adc only the 25% and 75% points should be used as described in section 25.7.6, adc result calibration . table 627. non-multiplexed channel assignments (1) (continued) input pins adc channel number in channel_number field analog pin name other functions conversion type adc number binary decimal RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1157/1740 table 628. multiplexed channel assignments (1) input pins adc channel number in channel_number field analog pin name other functions conversion type adc number binary decimal an0 to an39 (2) single-ended adc0/adc1 0000_0000 to 0010_0111 0 to 39 vrh single-ended adc0/adc1 0010_1000 40 vrl single-ended adc0/adc1 0010_1001 41 50% x vref (3),(4) single-ended adc0/adc1 0010_1010 42 75% x vref (3) single-ended adc0/adc1 0010_1011 43 25% x vref (3) single-ended adc0/adc1 0010_1100 44 ina_adc0/1_0 buffered bandgap single-ended adc0/adc1 0010_1101 45 reserved 0010_1110 to 0011_1111 46 to 63 anw ? single-ended adc0/adc1 0100_0xxx 64 to 71 anx ? single-ended adc0/adc1 0100_1xxx 72 to 79 any ? single-ended adc0/adc1 0101_0xxx 80 to 87 anz ? single-ended adc0/adc1 0101_1xxx 88 to 95 dan0+ and dan0- differential adc0/adc1 0110_0000 96 dan1+ and dan1- differential adc0/adc1 0110_0001 97 dan2+ and dan2- differential adc0/adc1 0110_0010 98 dan3+ and dan3- differential adc0/adc1 0110_0011 99 reserved 0110_0100 to 0111_1111 100 to 127 ina_adc0/1_1 temp sensor single-ended adc0/adc1 1000_0000 128 ina_adc0/1_2 spare single-ended adc0/adc1 1000_0001 129 reserved 1000_0010 to 1000_1111 130 to 143 device specific use adc0 1001_0000 to 1001_0011 144 to 147 reserved adc1 1001_0000 to 1001_0011 144 to 147 reserved 1001_0100 to 1010_0001 148 to 161 enhanced queued analog-to-dig ital converter (eqadc) RM0029 1158/1740 doc id 15177 rev 8 external multiplexing the eqadc can use from one to eight external multiplexer chips to expand the number of analog signals that may be converted. up to 64 analog channels can be converted through external multiplexer selection. the externally multiplexed channels are automatically selected by the channel_number field of a command message, in the same way done with internally multiplexed channels. the software selects the external multiplexed mode by setting the adc0/1_emux bit in either adc0_cr or adc1_cr depending on which adc reserved adc1 1010_0010 to 1010_0111 162 to 167 ina_adc0_3 device specific single-ended adc0 1010_0010 162 ina_adc0_4 device specific single-ended adc0 1010_0011 163 ina_adc0_5 device specific single-ended adc0 1010_0100 164 ina_adc0_6 device specific single-ended adc0 1010_0101 165 ina_adc0_7 device specific single-ended adc0 1010_0110 166 ina_adc0_8 device specific single-ended adc0 1010_0111 167 reserved 1010_1000 to 1100_0001 168 to 193 reserved adc0 1100_0010 to 1100_0111 194 to 199 ina_adc1_3 device specific single-ended adc1 1100_0010 194 ina_adc1_4 device specific single-ended adc1 1100_0011 195 ina_adc1_5 device specific single-ended adc1 1100_0100 196 ina_adc1_6 device specific single-ended adc1 1100_0101 197 ina_adc1_7 device specific single-ended adc1 1100_0110 198 ina_adc1_8 device specific single-ended adc1 1100_0111 199 reserved 1100_1000 to 1101_1111 200 to 223 reserved 1110_0xxx to 1111_1xxx 224 to 255 1. the two on-chip adcs can access the same analog input pins but simultaneous conversions are not allowed. also, when one adc is performing a differential conversion on a pair of pins, the other adc must not access ei ther of these two pins as single-ended channels. 2. old version has reserved values for channel numbers 8 to 11 when emux =1. therefore, now the behavior is different because it is converted the signal at an8 to an11, respectively. 3. vref=vrh-vrl. 4. 50% x vref = 50% ref = (vrh / vrl)/2, but this only applies before calibration. after calibration, the 50% reference point will actually return approximately 20 mv lower than the expected 50% of the difference between the high reference voltage (vrh) and the low reference voltage (vrl). for calibration of the adc only the 25% and 75% points should be used as described in section 25.7.6, adc result calibration . table 628. multiplexed channel assignments (1) (continued) input pins adc channel number in channel_number field analog pin name other functions conversion type adc number binary decimal RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1159/1740 will perform the conversion. table 628 shows the channel number assignments for the multiplexed mode. there are 4 differential pairs, 39 single-ended, and, at most, 64 externally multiplexed channels which can be selected. only one adc can have its adc0/1_emux bit asserted at a time. figure 652 shows the maximum configuration of eight external multiplexer chips connected to the eqadc. the external multiplexer chip selects one of eight analog inputs and connects it to a single analog output, which is fed to a specific input of the eqadc. the eqadc provides three multiplexed address signals, ma0, ma1, and ma2, to select one of eight inputs. these three multiplexed address signals are connected to all eight external multiplexer chips. the analog output of the eight multiplex chips are each connected to eight separate eqadc inputs, anr, ans, ant, anu, anw, anx, any, and anz. the ma pins correspond to the three least significant bits of the channel number that selects anr, ans, ant, anu, anw, anx, any, and anz with ma0 being the most significant bit - see ta ble 62 9 . when the external multiplexed mode is selected for either adc, the eqadc automatically creates the ma output signals from channel_number field of a command message. the eqadc also converts the proper input channel (anw, anx, any, and anz) by interpreting the channel_number field. as a result, up to 64 externally multiplexed channels appear to the conversion queues as directly connected signals. table 629. encoding of ma pins (1) channel number selecting anw, anx, any, anz (decimal) ma0 ma1 ma2 anw anx any anz 64 72 80 88 0 0 0 65 73 81 89 0 0 1 66 74 82 90 0 1 0 67 75 83 91 0 1 1 68 76 84 92 1 0 0 69 77 85 93 1 0 1 70 78 86 94 1 1 0 71 79 87 95 1 1 1 1. ?0? means pin is driven low and ?1? that pin is driven high. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1160/1740 doc id 15177 rev 8 figure 652. example of external multiplexing ma0 ma1 ma2 mux an64 an65 an66 an67 an68 an69 an70 an71 mux an72 an73 an74 an75 an76 an77 an78 an79 mux an80 an81 an82 an83 an84 an85 an86 an87 mux an88 an89 an90 an91 an92 an93 an94 an95 anw anx any anz 4 an0-an7 32 40 mux 40:1 mux 40:1 adc0 adc1 mux control channel number0/1 eqadc an12-an15 note: limited availability of pins may result in the sharing of adc inputs and mux outputs. mux an224 an225 an226 an227 an228 an229 an230 an231 mux an232 an233 an234 an235 an236 an237 an238 an239 mux an240 an241 an242 an243 an244 an245 an246 an247 mux an248 an249 an250 an251 an252 an253 an254 an255 anr ans ant anu 4 an20-an39 RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1161/1740 25.6.8 eqadc dma/interrupt request ta ble 63 0 lists methods to generate interrupt requests in the eqadc queuing control and triggering control. the dma/interrupt request select bits and the dma/interrupt enable bits are described in section , eqadc interrupt and dma control registers (eqadc_idcr) , and the interrupt flag bits are described in section , eqadc fifo and interrupt status registers (eqadc_fisr) . ta ble 65 3 depicts all interrupts and dma requests generated by the eqadc. ta ble 63 1 describes a list of methods to generate dma requests in the eqadc. table 630. eqadc fifo interrupt summary (1) interrupt condition clearing mechanism non coherency interrupt nciex = 1 ncfx = 1 clear ncfx bit by writing a ?1? to the bit. result fifo overflow interrupt (2) rfoiex = 1 rfofx = 1 clear rfofx bit by writing a ?1? to the bit. command fifo underflow interrupt (2) cfuiex = 1 cfufx = 1 clear cfufx bit by writing a ?1? to the bit. result fifo drain interrupt rfdex = 1 rfdsx = 0 rfdfx = 1 clear rfdfx bit by writing a ?1? to the bit. command fifo fill interrupt cffex = 1 cffsx = 0 cfffx = 1 clear cfffx bit by writing a ?1? to the bit. end of queue interrupt eoqiex = 1 eoqfx = 1 clear eoqfx bit by writing a ?1? to the bit. pause interrupt piex = 1 pfx =1 clear pfx bit by writing a ?1? to the bit. trigger overrun interrupt (2) toriex = 1 torfx =1 clear torfx bit by writing a ?1? to the bit. 1. for details refer to section , eqadc fifo and interrupt status registers (eqadc_fisr) , and section , eqadc interrupt and dma control registers (eqadc_idcr) . 2. apart from generating an independent interrupt request for when a rfifo overflow interrupt, a cfifo underflow interrupt, and a cfifo trigger overrun interrupt occurs, the eqadc al so provides a combined interrupt request at which these requests from all cfifos are ored. refer to figure 653 for details. table 631. eqadc fifo dma summary (1) dma request condition clearing mechanism result fifo drain dma request rfdex = 1 rfdsx = 1 rfdfx = 1 the eqadc automatically clears the rfdfx when rfifox becomes empty. writing ?1? to the rfdfx bit is not allowed. command fifo fill dma request cffex = 1 cffsx = 1 cfffx = 1 the eqadc automatically clears the cfffx when cfifox becomes full. writing ?1? to the cfffx bit is not allowed. 1. for details refer to section , eqadc fifo and interrupt status registers (eqadc_fisr) , and section , eqadc interrupt and dma control registers (eqadc_idcr) . enhanced queued analog-to-dig ital converter (eqadc) RM0029 1162/1740 doc id 15177 rev 8 figure 653. eqadc dma and interrupt requests nciex ncfx toriex torfx piex pfx cffex cfffx cfifo fill interrupt request eoqiex eoqfx cfuiex cfufx rfoiex rfofx non coherency interrupt request pause interrupt request end of queue interrupt request trigger overrun interrupt request cfifo underflow interrupt request rfifo overflow interrupt request combined interrupt request cffsx rfdex rfdfx rfifo drain interrupt request rfdsx rfdex rfdfx rfifo drain dma request rfdsx dma request generation logic cffex cfffx cfifo fill dma request cffsx dma request generation logic RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1163/1740 25.6.9 eqadc synchronous serial interface (ssi) sub-block figure 654. eqadc synchronous serial interface block diagram the eqadc ssi protocol allows for a full duplex, synchronous, serial communication between the eqadc and a single external device. figure 654 shows the different components inside the eqadc ssi block. the eqadc ssi sub-block on the eqadc is always configured as a master. the eqadc ssi has four associated port pins: free running clock (fck) serial data select (sds ) serial data in (sdi) serial data out (sdo) the fck clock signal times the shifting and sampling of the two serial data signals and it is free running between transmissions, allowing it to be used as the clock for the external device. the sds signal will be asserted to indicate the start of a transmission, and negated to indicate the end or the abort of a transmission. sdi is the master serial data input and sdo the master serial data output. the eqadc ssi sub-block is enabled by setting the essie field in the section , eqadc module configuration register (eqadc_mcr) . when enabled, the eqadc ssi can be optionally capable of starting serial transmissions. when serial transmissions are disabled (essie set to 0b10), no data will be transmitted to the external device but fck will be free- running. this operation mode permits the control of the timing of the first serial transmission, and can be used to avoid the transmission of data to an unstable external device, for example, a device that is not fully reset. this mode of operation is specially important for the reset procedure of an external device that uses the fck as its main clock. master slave in out pad interface sds fck sdo sdi eqadc ssi control register fck clock system transmit shift register eqadc ssi control logic receive shift register br cfifo data rfifo data eqadc fifo control unit control mdt clock divide by: 2, 3, 4, .. , 15, 16, 17 baud clock generator slave bus interface enhanced queued analog-to-dig ital converter (eqadc) RM0029 1164/1740 doc id 15177 rev 8 the main elements of the eqadc ssi block are the shift registers. the 26-bit transmit shift register in the master and 26-bit receive shift register in the slave are linked by the sdo pin. in a similar way, the 26-bit transmit shift register in the slave and 26-bit receive shift register in the master are linked by the sdi pin. see figure 655 . when a data transmission operation is performed, data in the transmit registers is serially shifted twenty-six bit positions into the receive registers by the fck clock from the master; data is exchanged between the master and the slave. data in the master transmit shift register in the beginning of a transmission operation becomes the output data for the slave, and data in the master receive shift register after a transmission operation is the input data from the slave. figure 655. full duplex pin connection eqadc ssi data transmission protocol figure 656 shows the timing of an eqadc ssi transmission operation. the main characteristics of this protocol are: fck is free running, it does not stop between data transmissions. fck will be driven low: ? when the serial interface is disabled. ? in stop/debug mode. ? immediately after reset. frame size is fixed to 26 bits. msb bit is always transmitted first. master drives data on the positive edge of fck and latches incoming data on the next positive edge of fck. slave drives data on the positive edge of fck and latches incoming data on the negative edge of fck. master initiates a data transmission by driving sds low, and its msb bit on sdo on the positive edge of fck. once an asserted sds is detected, the slave shifts its data out, one bit at a time, on every fck positive edge. both the master and the slave drive new data on the serial lines on every fck positive edge. this process continues until all the initial 26-bits in the master shift register are moved into the slave shift register. t dt is the delay between master slave sdo sdi fck sds baud rate generator transmit shift register receive shift register receive shift register transmit shift register data registers cfifos and rfifos RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1165/1740 two consecutive serial transmissions, time during which sds is negated. when ready to start of the next transmission, the slave must drive the msb bit of the message on every positive edge of fck regardless of the state of the sds signal. on the next positive edge, the second bit of the message is conditionally driven according to if an asserted sds was detected by the slave on the preceding fck negative edge. this is an important requisite since the sds and the fck are not synchronous. the sds signal is not generated by fck, rather both are generated by the system clock, so that it is not guaranteed that fck edges will precede sds ones. while sds is negated, the slave continuously drives its msb bit on every positive edge of fck until it detects an asserted sds on the immediately next fck negative edge. see figure 657 for three situations showing how the slave should behave according to when sds is asserted. note: on the master, the fck is not used as a clock. although, the eqadc ssi behavior is described in terms of the fck positive and negative edges, all eqadc ssi related signals (sdi, sds, sdo, and fck) are synchronized by the system clock on the master side. there are no restrictions regarding the use of the fck as a clock on the slave device. abort feature the master indicates it is aborting the current transfer by negating sds before the whole data frame has being shifted out, that is the 26th bit of data being transferred has not being shifted out. the eqadc ignores the incompletely received message. the eqadc resends the aborted message whenever the corresponding cfifo becomes again the highest priority cfifo with commands bound for not-full external cbuffer. refer to section , cfifo common prioritization and command transfer , for more information on aborts and cfifo priority. baud clock generation as shown in figure 654 , the baud clock generator divides the system clock to produce the baud clock. the br field in section , eqadc ssi control register (eqadc_ssicr) , selects the system clock divide factor as in table 582 . (bc) bc. maximum fck frequency is highly dependable on track delays, master pad delays, and slave pad delays. baudclockfrequency systemclockfrequency mhz () systemclockdividefactor ------------------------------------------------------------------------------------------ = enhanced queued analog-to-dig ital converter (eqadc) RM0029 1166/1740 doc id 15177 rev 8 figure 656. synchronous serial interface protocol timing 2 3 ... 23 24 25 26 2 3 ... 23 24 25 2 3 ... 23 24 25 2 3 ... 23 24 25 fck sds sdo master sample sdi slave sample input input t dt begin transmission begin transmission end transmission end transmission 1 26 26 26 11 msb 1 1 msb msb msb msb t mdt = minimum t dt is programmable and defined in the section , eqadc ssi control register (eqadc_ssicr) ? RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1167/1740 figure 657. slave driving the msb and consecutive bits in a data transmission sds is asserted after positive edge of fck. slave drives second bit due to detection of an asserted sds on the negative edge of fck. master?s sdi 25 26 1 2 3 ... 25 26 1 2 3 ... 25 26 1 1 2 3 ... sds fck slave sample input t dt t dt t dt begin transmission begin transmission begin transmission end transmission end transmission sds is asserted before positive edge of fck. slave drives second bit due to detection of an asserted sds on the negative edge of fck. slave drives msb bit again due to detection of a negated sds on the negative edge of fck. (1) (2) (3) master?s sdi sds fck slave sample input master?s sdi sds fck slave sample input end transmission enhanced queued analog-to-dig ital converter (eqadc) RM0029 1168/1740 doc id 15177 rev 8 25.6.10 eqadc parallel side interface (psi) sub-block figure 658. eqadc parallel side interface block diagram the eqadc psi sub-block allows communication between the eqadc and the companion modules through a local slave bus that has the eqadc block as the master and the companion modules as the slaves. however, due to the poor processing capability of eqadc, it is defined a very limited number of addresses and a maximum of 15 different slave blocks to be enabled. the conversion result goes through the result formatting and calibration sub-block and the corresponding message_tag and dest fields are decoded to decide the destination of the conversion result data. when the dest field is not zero as described in section , alternate configuration 1-8 control registers (adc_acr1-8) , the message_tag bits, and some control bits, and the conversion result data are sent to the transmission section of the psi sub-block. this set of data is processed and sent to the corresponding on-chip companion module. the companion module can also send back to eqadc the result of some processing in the received data. in this case, the receiver section of he psi sub-block treats this request and receives the result data with the corresponding message_tag or tag field. this tag is used by the decoder to select which rfifo will be written with the received companion module data. adc conv data, rdata read / write sel tx section result data rx section addr, rwb, module_en wdata dest message_tag, write request read request tag psi ready flush, ctrl from: fifo control unit to: fifo control unit psi slave bus interface dma interface signals RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1169/1740 input / output signals description the information content of the input and the output data buses from/to the companion modules are described in figure 659 . the input data format is used in the read cycle and corresponds to the data supplied by some companion module. the output data format is used in the write cycle of this interface block and contains information / controls to some companion module. figure 659. psi input and output data buses content flush ? master block flush request/control bit the flush signal is used to request a flush flow in the slave block. more details is presented in item section , conversion command format for alternate configurations . 1 = flush request 0 = no flush request. ctrl[0:1] ? control bits table 632 describes the ctrl[0:1] field functions. this field is used for the control of the companion module. read (input) / write (output) data buses content 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 tag [0:3] w flu sh ctrl [0:1] message_tag [0:3] reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r result_data [0:15] w adc_conv_result [0:15] reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 632. ctrl[0:1] field description ctrl[0:1] description 00 inh_ret or prefill - this mode indicates that the companion module should not send back some result_data corresponding to the accompanying adc_conv_result data. when the slave module is the decimation filter, this control enables the prefill filter mode. 01 conversion result - it indicates that the adc_conv_result field should be treated as a valid sample data. this control mode is useful to decimation filter to put the filter em normal mode instead of prefill mode. 10 time stamp o register read - a time stamp indicates that the adc_conv_result field should follow a bypass flow in the companion module, returning back to the eqadc without any modification. 11 reserved enhanced queued analog-to-dig ital converter (eqadc) RM0029 1170/1740 doc id 15177 rev 8 message_tag[0:3] ? message tag bits field this field indicates the rfifo destination associated with the adc_conv_result sample. this value is stored by the companion module and is used to address the destination rfifo register when a result_data is generated due to that adc_conv_result sample. tag[0:3] ? companion module tag bits this bit field is used to address the appropriate destination rfifo in the eqadc for the accompanying result_data bits. in eqadc application, this is used to address the appropriate rfifo in the eqadc block. in this case, the possible values are only from 0000 to 0101. adc_conv_result[0:15] ? adc conversion result data this bit field is the adc conversion result data after passing through the calibration and formatting block. result_data[0:15] ? companion module result data this bit field corresponds to the companion module data processing result to eqadc. psi transmitter / write section the transmission sub-block formats the data bus from rfifo control sub-block to send to the psi slave wdata bus. the transmission data is registered and its content is described in section , input / output signals description. the transmission has higher priority than reception. this is done to avoid the use of memory to store transmission data and it is not used waiting time for transmission. the destination companion module for the transmission data is obtained by decoding the dest[0:3] bits. the not null decimal value of dest[0:3] is used to uniquely set the corresponding module enable signal. for example, dest[0:3] value equal to 0xf that corresponds to the decimal value 15 is going to set only the module enable 15. all other module enable from 1 to 14 are not set. psi receiver / read section the receiver sub-block receives data from some companion module using the psi slave bus interface. the companion module sends a read request to eqadc using the dma read request line. the psi logic sends a read command if there is no transmission request. the received data has the structure described in item section , input / output signals description . RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1171/1740 25.6.11 analog sub-block analog to digital converter (adc) adc architecture figure 660. rsd adc block diagram the rsd cyclic adc consists of two main portions, the analog rsd stage, and the digital control and calculation block, as shown in figure 660 . to begin an analog to digital conversion, a differential input is passed into the analog rsd stage. the signal is passed through the rsd stage, and then from the rsd stage output, back to its input to be passed again. to complete a 12-bit conversion, the signal must pass through the rsd stage 12 times. for 10-bit and 8-bit resolution, the signal must pass 10 or 8 times through the rsd. each time an input signal is read into the rsd stage, a digital sample is taken by the digital control/calculation block. the digital control/calculation block uses this sample to tell the analog block how to condition the signal. the digital block also saves each successive sample and adds them according to the rsd algorithm at the end of the entire conversion cycle. rsd single-stage digital control and calculation pipeline_control sample 12 bit output diff input clock pipeline enhanced queued analog-to-dig ital converter (eqadc) RM0029 1172/1740 doc id 15177 rev 8 rsd overview figure 661. rsd stage block diagram on each pass through the rsd stage, the input signal will be multiplied by exactly two, and summed with either -vref, 0, or vref, depending on the logic control. the logic control will determine -vref, 0, or vref depending on the two comparator inputs. as the logic control sets the summing operation, it also sends a digital value to the rsd adder. each time an analog signal passes through the rsd single-stage, a digital value is collected by the rsd adder. at the end of an entire ad conversion cycle, the rsd adder uses these collected values to calculate the 12-bit/10-bit/8-bit digital output. figure 662 shows the transfer function for the rsd stage. note how the digital value (a, b) is dependent on the two comparator inputs. x2 sum vrl vrh input voltage logic control residue voltage + - + - -vref,0,vref digital signal rsd adder RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1173/1740 figure 662. rsd stage transfer function in each pass through the rsd stage, the residue will be sent back to be the new input, and the digital signals, a and b, will be stored. for the 12-bit adc, input signal is sampled during the input phase, and after each of the 12 passes through the rsd stage. thus, 13 total a and b values are collected. upon collecting all these values, they will be added according to the rsd algorithm to create the 12-bit digital representation of the original analog input. the bits are added in the following manner: rsd adder the array, s1 to s12,will be the digital output of the rsd adc with s1 being the msb and s12 being the lsb. vref vref -vref -vref vl vh input voltage residue voltage vres=2vin+vref vres=2vin vres=2vin-vref a=0, b=0 a=0, b=1 a=1, b=0 enhanced queued analog-to-dig ital converter (eqadc) RM0029 1174/1740 doc id 15177 rev 8 figure 663. rsd adder variable gain amplification (vga) for pre-gain the vga starts after sampling completes. it is enabled by a 2-bit signal pre_gain described in section , alternate configuration 1-8 control registers (adc_acr1-8) . the adc takes 2, 8, 64 or 128 clock cycles to do sampling which is selected by the lst[0:1] field in the conversion command message. after the sampling, if 2x vga is enabled, there is a 2x gain stage without comparison before the regular conversion cycles. when 4x vga is enabled, there are the 2x gain stage without comparison by 2 times before the normal conversion processing. 25.7 initialization/application information 25.7.1 multiple queues control setup example this section provides an example of how to configure multiple cqueues. table 633 describes how each cqueue can be used for a different application. also documented in this section are general guidelines on how to initialize the on-chip adcs and the external device, and how to configure the cqueues and the eqadc. a13 b12 a12 b11 a11 b10 .. .. ... ... a3 b2 a2 b1 ------------------------------------------ s12 s11 s10 ... ... s2 s1 carry + table 633. application of each cqueue cqueue number cqueue type running speed number of contiguous conversions example 0 very fast burst time- based cqueue every 2 s for 200 s; pause for 300 s and then repeat 2 injector current profiling 1 fast hardware- triggered cqueue every 900 s3 current sensing of pwm controlled actuators 2 fast repetitive time- based cqueue every 2 ms 8 throttle position RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1175/1740 eqadc initialization the following steps provide an example about how to configure the eqadc controls and how to initialize the on-chip adcs and the external device. in this example, all conversion commands will be transferred through cfifo0. 1. load all required configuration commands in the ram in such way that they form a queue; this data structure will be referred below as cqueue0. figure 664 shows an example of a cqueue able to configure the on-chip adcs and external device at the same time. although, this example uses the dmac to store commands in cfifo0, configuration commands could have also been directly written to the cfifo0 push register. 2. select source driving eqadc hardware trigger ports (etrig). before proceeding to next step, allow some time (minimum of two system clocks - filter period is set to minimum after reset) so that the logic level at the source is filtered and reaches the eqadc control logic. note: etrig ports could be driven by an external pin or by the output port of other blocks in the device, such as timers. in order to avoid unexpected triggering of cfifos in hardware trigger modes, the source driving the etrig port must be selected and set to a known logic level before putting the cfifos into the waiting for trigger state. 3 software-triggered cqueue every 3.9 ms 3 command triggered by software strategy 4 repetitive angle- based cqueue every 625 s7 airflow read every 30 degrees at 8000 rpm 5 slow repetitive time-based cqueue every 100 ms 10 temperature sensors table 633. application of each cqueue cqueue number cqueue type running speed number of contiguous conversions example enhanced queued analog-to-dig ital converter (eqadc) RM0029 1176/1740 doc id 15177 rev 8 the trigger filter bypass control inputs must be set considering the characteristics of the trigger signal. a particular case to assert the bypass control is when a device?s internal signal with one clock width pulse is used. 3. configure section , eqadc external trigger digital filter register (eqadc_etdfr) . 4. configure section , eqadc null message send format register (eqadc_nmsfr) . 5. configure section , eqadc ssi control register (eqadc_ssicr) , to communicate with the external device. 6. enable the eqadc ssi by programming the essie field in the section , eqadc module configuration register (eqadc_mcr) . a) write 0b10 to essie field to enable the eqadc ssi. fck is free running but serial transmissions are not started. b) wait until the external device becomes stable after reset. c) write 0b11 to essie field to enable the eqadc ssi to start serial transmissions. 7. configure the dmac to transfer data from cqueue0 to cfifo0 in the eqadc. 8. configure section , eqadc interrupt and dma control registers (eqadc_idcr) . a) set cffs0 to configure the eqadc to generate a dma request to load commands from cqueue 0 to the cfifo0. b) set cffe0 to enable the eqadc to generate a dma request to transfer commands from cqueue0 to cfifo0; command transfers from the ram to the cfifo0 will start immediately. c) set eoqie0 to enable the eqadc to generate an interrupt after transferring all of the commands of cqueue0 through cfifo0. 9. configure section , eqadc cfifo control registers (eqadc_cfcr) . a) write 0b0001 to the mode0 field in eqadc_cfcr0 to program cfifo0 for software single-scan mode. b) write ?1? to sse0 to assert sss0 and trigger cfifo0. 10. since cfifo0 is in single-scan software mode and it is also the highest priority cfifo, the eqadc starts to transfer configuration commands to the on-chip adcs and to the external device. 11. when all of the configuration commands have been transferred, cf0 in section , eqadc fifo and interrupt status registers (eqadc_fisr) , will be set. the eqadc generates a end of queue interrupt. the initialization procedure is complete. figure 664. example of a cqueue confi guring the on-chip adcs/external device the initialization procedure described above does not generate adc clocks that are in phase because the timing at which the adc0/1_en bits, in the section , adc0/1 control registers (adc0_cr and adc1_cr) , are set is different. below follows an example on how configuration command to cbuffer0 - ex: write adc0_cr cqueue in 0x0 0x1 0x2 0x3 system memory configuration command to cbuffer2 - ex: write to external device configuration register configuration command to cbuffer0 - ex: write adc_tscr configuration command to cbuffer1 - ex: write adc1_cr command address RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1177/1740 to simultaneously set these bits so that in-phase adc clocks are generated. in this example, adc0/1_clk are configured to the same frequency. 1. push an adc0_cr write configuration command in cfifo0 that enables adc0 (adc0_en=1) and that sets the adc0_clk_ps to an appropriate value. for example, 0x80800801. 2. push an adc1_cr write configuration command in cfifo1 that enables adc1 (adc1_en=1) and that sets the adc1_clk_ps to an appropriate value. for example, 0x82800801. 3. configure cfifo0 and cfifo1 to single scan software trigger mode and simultaneously trigger them by writing 0x04100410 to the eqadc_cfcr0 register - see section , eqadc cfifo control registers (eqadc_cfcr) . configuring eqadc for applications this section provides an example based on the applications in table 633 . the example describes how to configure multiple cqueues to be used for those applications and provides a step-by-step procedure to configure the eqadc and the associated cqueue structures. in the example, the ?fast hardware-triggered cqueue?, described on the second row of ta ble 63 3 , will have its commands transferred to cbuffer1; the conversion commands will be executed by adc1. the generated results will be returned to rfifo3 before being transferred to the rqueues in the ram by the dmac. note: there is no fixed relationship between cfifos and rfifos with the same number. the results of commands being transferred through cfifo1 can be returned to any rfifo, regardless of its number. the destination of a result is determined by the message_tag field of the command that requested the result. see section , message format in eqadc , for details. step one: setup the cqueues and rqueues. 1. load the ram with configuration and conversion commands. table 634 is an example of how cqueue1 commands should be set. a) each trigger event will cause four commands to be executed. when the eqadc detects the pause bit asserted, it will wait for another trigger to restart transferring commands from the cfifo. b) at the end of the cqueue, the ?eoq? bit is asserted as shown in ta ble 63 4 . c) results will be returned to rfifo3 as specified in the message_tag field of commands. 2. reserve memory space for storing results. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1178/1740 doc id 15177 rev 8 step two: configure the dmac to handle data transfers between the cqueues/rqueues in ram and the cfifos/rfifos in the eqadc. 1. for transferring, set the source address of the dmac to point to the start address of cqueue1. set the destination address of the dmac to point to eqadc_cfpr1. refer to section , eqadc cfifo push registers (eqadc_cfpr) . 2. for receiving, set the source address of the dmac to point to eqadc_rfpr3. refer to section , eqadc result fifo pop registers (eqadc_rfpr) . set the destination address of the dmac to point to the starting address of rqueue1. step three: configure the eqadc control registers. table 634. example of cqueue commands (1) bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bit name eoq pause rep reserved eb bn reserved message tag adc command cmd 1 0 0 0 0 0 1 0 0b0011 conversion command cmd 2 0 0 0 0 0 1 0 0b0011 conversion command cmd 3 0 0 0 0 0 1 0 0b0011 conversion command cmd 4 0 1 0 0 0 1 0 0b0011 (2) configure peripheral device for next conversion sequence cmd 5 0 0 0 0 0 1 0 0b0011 conversion command cmd 6 0 0 0 0 0 1 0 0b0011 conversion command cmd 7 0 0 0 0 0 1 0 0b0011 conversion command cmd 8 0 1 0 0 0 1 0 0b0011 (2) configure peripheral device for next conversion sequence 0 etc. ... cmd eoq 1 0 0 0 0 1 0 0b0011 eoq message cfifo header adc command 1. fields lst, tsr, fmt, and channel_number are not showed for clarity. see section , conversion command format for the standard configuration , for details. 2. message_tag field is only defined for read configuration commands. RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1179/1740 1. configure section , eqadc interrupt and dma control registers (eqadc_idcr) . a) set eoqie1 to enable the end of queue interrupt request. b) set cffs1 and rfds3 to configure the eqadc to generate dma requests to push commands into cfifo1 and to pop result data from rfif03. c) set cfinv1 to invalidate the contents of cfifo1. d) set rfde3 and cffe1 to enable the eqadc to generate dma requests. command transfers from the ram to the cfifo1 will start immediately. e) set rfoie3 to indicate if rfifo3 overflows. f) set cfuie1 to indicate if cfifo1 underflows. 2. configure mode1 to continuous-scan rising edge external trigger mode in section , eqadc cfifo control registers (eqadc_cfcr) . step four: command transfer to adcs and result data reception. when an external rising edge event occurs for cfifo1, the eqadc automatically will begin transferring commands from cfifo1 when it becomes the highest priority cfifo trying to send commands to cbuffer1. the received results will be placed in rfifo3 and then moved to rqueue1 by the dmac. 25.7.2 eqadc/dmac interface this section provides an overview about the eqadc/dmac interface and general guidelines about how the dmac should be configured in order for it to correctly transfer data between the queues in system memory and the eqadc fifos. note: advanced dmacs provide more functionality then the ones discussed in this section. cqueue/cfifo transfers in transfers involving cqueues and cfifos, the dmac moves data from a queued source to a single destination as showed in figure 665 . the location of the data to be moved is indicated by the source address, and the final destination for that data, by the destination address. the dmac contains a data structure containing these addresses and other parameters used in the control of data transfers. for every dma request issued by the eqadc, the dmac has to be configured to transfer a single command (32-bit data) from the cqueue, pointed to by the source address, to the cfifo push register, pointed to by the destination address. after the service of a dma request is completed, the source address has to be updated to point to the next valid command. the destination address remains unchanged. when the last command of a queue is transferred one of the following actions is recommended. the corresponding dma channel should be disabled. this might be desirable for cfifos in single scan mode. the source address should be updated to pointed to a valid command which can be the first command in the queue that has just been transferred (cyclic queue), or the first command of any other cqueue. this is desirable for cfifos in continuous scan mode, and at some cases, for cfifos in single scan mode. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1180/1740 doc id 15177 rev 8 figure 665. cqueue/cfifo interface rqueue/rfifo transfers in transfers involving rqueues and rfifos, the dmac moves data from a single source to a queue destination as showed in figure 666 . the location of the data to be moved is indicated by the source address, and the final destination for that data, by the destination address. for every dma request issued by the eqadc, the dmac has to be configured to transfer a single result (16-bit data), pointed to by the source address, from the rfifo pop register to the rqueue, pointed to by the destination address. after the service of a dma request is completed, the destination address has to be updated to point to the location where the next 16-bit result will be stored. the source address remains unchanged. when the last expected result is written to the rqueue, one of the following actions is recommended. the corresponding dma channel should be disabled. the destination address should be updated pointed to the next location where new coming results are stored, which can be the first entry of the current rqueue (cyclic queue), or the beginning of a new rqueue. source address command 1 command 2 command 3 ..... command n-1 command n cfprx cqueue in system memory cfifo push register one command transfer per dma request destination address RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1181/1740 figure 666. rqueue/rfifo interface 25.7.3 sending immediate command setup example in the eqadc, there is no immediate command register for sending a command immediately after writing to that register. however, a cfifo can be configured to perform the same function as an immediate command register. the following steps illustrate how to configure cfifo5 as an immediate command cfifo. the results will be returned to rfifo5. 1. configure the section , eqadc interrupt and dma control registers (eqadc_idcr) . a) clear cfifo fill enable5 (cffe5 = 0) in eqadc_idcr2. b) clear cfifo underflow interrupt enable5 (cfuie5 = 0) in eqadc_idcr2. c) clear rfds5 to configure the eqadc to generate interrupt requests to pop result data from rfif05. d) set rfifo drain enable5 (rfde5 = 1) in eqadc_idcr2. 2. configure the section , eqadc cfifo control registers (eqadc_cfcr) . a) write ?1? to cfinv5 in eqadc_fcr2. this will invalidate the contents of cfifo5. b) set mode5 to continuous-scan software trigger mode in eqadc_cfcr2. 3. to transfer a command, write it to eqadc cfifo push register 5 (eqadc_cfpr5) with message tag = 0b0101. refer to section , eqadc cfifo push registers (eqadc_cfpr) . 4. up to four commands can be queued in cfifo5. check the cfctr5 status in eqadc_fisr5 before pushing another command to avoid overflowing the cfifo. refer to section , eqadc fifo and interrupt status registers (eqadc_fisr) . 5. when the eqadc receives a conversion result for rfifo5, it generates an interrupt request. rfifo pop register 5 (eqadc_rfpr5) can be popped to read the result. refer to section , eqadc result fifo pop registers (eqadc_rfpr) . result 1 result 2 result 3 ..... result n-1 result n rfprx rqueue in system memory rfifo pop register one result transfer per dma request source address destination address enhanced queued analog-to-dig ital converter (eqadc) RM0029 1182/1740 doc id 15177 rev 8 25.7.4 modifying queues more cqueues may be needed than the six supported by the eqadc. these additional cqueues can be supported by interrupting command transfers from a configured cfifo, even if it is triggered and transferring, modifying the corresponding cqueue in the ram or associating another cqueue to it, and restarting the cfifo. more details on disabling a cfifo are described in section , disabled mode . 1. determine the resumption conditions when later resuming the scan of the cqueue at the point before it was modified. a) change modex in section , eqadc cfifo control registers (eqadc_cfcr) , to disabled. refer to section , disabled mode , for a description of what happens when modex is changed to disabled. b) poll cfsx until it becomes idle in section , eqadc cfifo status register (eqadc_cfsr) . c) read and save tc_cfx in section , eqadc cfifo transfer counter registers (eqadc_cftcr) , for later resuming the scan of the queue. the tc_cfx provides the point of resumption. d) since all result data may not have being stored in the appropriate rfifo at the time modex is changed to disable, wait for all expected results to be stored in the rfifo/rqueue before reconfiguring the dmac to work with the modified rqueue. the number of results that must return can be estimated from the tc_cfx value obtained above. 2. disable the dmac from responding to the dma request generated by cfffx and rfdfx in section , eqadc fifo and interrupt status registers (eqadc_fisr) . 3. write ?0x0000? to the tc_cfx field. 4. load the new configuration and conversion commands into ram. configure the dmac to support the new cqueue/rqueue, but do not configure it yet to respond to dma requests from cfifox/rfifox. 5. if necessary, modify section , eqadc interrupt and dma control registers (eqadc_idcr) , to suit the modified cqueue. 6. write ?1? to cfinvx in section , eqadc cfifo control registers (eqadc_cfcr) , to invalidate the entries of cfifox. perform any other modifications to eqadc_cfcr except changing modex from disabled. 7. configure the dmac to respond to dma requests generated by cfffx and rfdfx. 8. change modex to the modified cfifo operation mode. write ?1? to ssex to trigger cfifox if modex is software trigger. 25.7.5 cqueue and rqueues usage figure 667 is an example of cqueue and rqueue usage. it shows the cqueue0 commands requesting results that will be stored in rqueue0 and rqueue1, and cqueue1 commands requesting results that will be stored only in rqueue1. some command messages request data to be returned from the on-chip adc/external device, but some only configure them and do not request returning data. when a cqueue contains both write and read commands like cqueue0, the cqueue and rqueue entries will not be aligned; as shown in figure 667 , the result for the second command of cqueue0 is the first entry of rqueue0. the figure also shows that cqueue and rqueue entries can also become unaligned even if all commands in a cqueue request data as cqueue1. cqueue1 entries became unaligned to rqueue1 entries because a result requested by the forth cqueue0 RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1183/1740 command was sent to rqueue1. this happens because the system can be configured so that several cqueues can have its results sent to a single rqueue. figure 667. eqadc command and result queues no result cqueue0 write command 0 0x0000 result to rqueue0 cqueue0 read command 1 0x0004 result to rqueue0 cqueue0 conversion command 2 0x0008 result to rqueue1 cqueue0 conversion command 3 0x000c ... ... result to rqueue0 cqueue0 conversion command n 0x001c command queue 0 (cqueue0) result cqueue0 read command 1 0x0000 result cqueue0 conversion command 2 0x0002 ... ... result queue 0 (rqueue0) result to rqueue1 cqueue1 read command 0 0x0000 result to rqueue1 cqueue1 read command 1 0x0004 result to rqueue1 cqueue1 conversion command 2 0x0008 ... ... result to rqueue1 cqueue1 conversion command m 0x001c command queue 1 (cqueue1) result cqueue1 read command 0 0x0000 ... ... result queue 1 (rqueue1) result cqueue1 read command 1 0x0002 result cqueue1 conversion command 2 0x0006 result cqueue0 conversion command 3 0x0004 rqueue0 is not aligned with cqueue0 because the first command of cqueue0 does not request results. rqueue1 is not aligned with cqueue1 because it contains results for cqueue0 and cqueue1 commands. the timing at which the cqueue0 command result is stored in rqueue1 depends on the relative speed at which commands from both cqueues are executed. this is influenced by factors like resource sharing, adc clock frequency, sampling time, and triggering time. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1184/1740 doc id 15177 rev 8 25.7.6 adc result calibration the adc result calibration process consists of two steps: determining the gain and offset calibration constants, and calibrating the raw results generated by the on-chip adcs by solving the following equation discussed in section , adc calibration feature . equation 13 cal_res = gcc * raw_res + occ+2; the calibration constants gcc and occ can be calculated from equation equation 13 provided that two pairs of expected (cal_res) and measured (raw_res) result values are available for two different input voltages. most likely calibration points to be used are 25% vref (bd) and 75% vref since they are far apart but not too close to the end points of the full input voltage range. this allows for calculations of more representative calibration constants. the eqadc provides these voltages via channel numbers 43 and 44. the raw, uncalibrated results for these input voltages are obtained by converting these channels with conversion commands that have the cal bit negated. the transfer equations for when sampling these reference voltages are: cal_res 75%vref = gcc * raw_res 75%vref + occ+2; cal_res 25%vref = gcc * raw_res 25%vref + occ+2; thus; equation 14 gcc = (cal_res 75%vref ? cal_res 25%vref ) / (raw_res 75%vref ? raw_res 25%vref ); equation 15 occ = cal_res 75%vref ? gcc*raw_res 75%vref ? 2; or equation 16 occ = cal_res 25%vref ? gcc*raw_res 25%vref ? 2; after being calculated, the gcc and occ values must be written to adc registers: section , adc0/1 gain calibration constant registers (adc0_gccr and adc1_gccr) , and section , adc0/1 offset calibration constant registers (adc0_occr and adc1_occr) , using write configuration commands. the eqadc will automatically calibrate the results, according to equation equation 13 , of every conversion command that has its cal bit asserted using the gcc and occ values stored in the adc calibration registers. note: for accurate calibration, the 25% vref channel must be converted using the long sample time (lst) setting for either 64 or 128 adc sample cycles in the adc conversion command message (lst = 0b10 or 0b11). mac configuration procedure the following steps illustrate how to configure the calibration hardware, namely, determining the values of the gain and offset calibration constants, and the writing of these constants to the calibration registers. the procedure below should be performed for adc0 and for adc1. bd. vref=vrh-vrl RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1185/1740 1. convert channel 44 with a command that has its cal bit negated and obtain the raw, uncalibrated result for 25%vref (raw_res 25%vref ). 2. convert channel 43 with a command that has its cal bit negated and obtain the raw, uncalibrated result for 75%vref (raw_res 75%vref ). 3. since the expected values for the conversion of these voltages are known (cal_res 25%vref and cal_res 75%vref ), gcc and occ values can be calculated from equations equation 14 and equation 15 using these values, and the ones determined in steps 1 and 2. 4. reformat gcc and occ to the proper data formats as specified in section , mac unit and operand data format . gcc is an unsigned 15-bit fixed point value and occ is a signed 14-bit value. 5. write gcc value to section , adc0/1 gain calibration constant registers (adc0_gccr and adc1_gccr) , and occ value to section , adc0/1 offset calibration constant regi sters (adc0_occr and adc1_occr) , using write configuration commands. example the raw results obtained when sampling reference voltages 25%vref and 75%vref were, respectively, 3798 and 11592. the results that should have been obtained from the conversion of these reference voltages are, respectively, 4096 and 12288. therefore, using equations equation 14 and equation 15 , the gain and offset calibration constants are: gcc=(12288-4096)/(11592-3798) = 1.05106492-> 1.05102539 = 0x4388 occ=12288 - 1.05106492*11592 - 2 = 102.06-> 102 = 0x0066 ta ble 63 5 shows, for this particular case, examples of how the result values change according to gcc and occ when result calibration is executed (cal=1) and when it is not (cal=0). quantization error reduction during calibration figure 668 shows how the adc transfer curve changes due to the addition of two to the mac output during the calibration - see mac output equation at section , overview . the maximum absolute quantization error is reduced by half leading to an increase in accuracy. table 635. calibration example input voltage raw result (cal=0) calibrated result (cal=1) hexadecimal decimal hexadecimal decimal 25% vref (1) 1. for accurate calibration, the 25% vref channel must be converted using the long sample time (lst) setting for either 64 or 128 adc sample cycles in the adc conversion command message (lst = 0b10 or 0b11). 0x0ed6 3798 0x1000 4095.794 75% vref 0x2d48 11592 0x3000 12287.486 enhanced queued analog-to-dig ital converter (eqadc) RM0029 1186/1740 doc id 15177 rev 8 figure 668. quantization error reduction during calibration 25.7.7 eqadc versus qadc this section describes how the eqadc upgrades the qadc functionality. the section also provides a comparison between the eqadc and qadc in terms of their functionality. this section targets the users familiar with terminology in qadc. figure 669 is an overview of a qadc. figure 670 is an overview of the eqadc system. 0 1/2 lsb lsb input voltage digital value 4 error for adc transfer curve shifted ideal transfer curve transfer curve 0 input voltage - 4 2 quantization error - 2 (12-bit ad resolution) (12-bit ad resolution) 1/2 lsb lsb (14-bit result) error for shifted transfer curve adc transfer curve RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1187/1740 figure 669. qadc overview external triggers result queues command queues analog to digital converter interrupt request digital control logic for analog device trigger and queue control logic enhanced queued analog-to-dig ital converter (eqadc) RM0029 1188/1740 doc id 15177 rev 8 figure 670. eqadc system overview the eqadc system consists of four parts: queues in ram, the eqadc, on-chip adcs, and an external device. as compared with the qadc, the eqadc system requires two pieces of extra hardware. 1. a dma or an mcu is required to move data between the eqadc?s fifos and queues in the system memory. 2. a serial interface (eqadc synchronous serial interface - eqadc ssi) is implemented to transmit and receive data between the eqadc and the external device. since there are only fifos inside the eqadc, much of the terminology or use of the register names, register contents, and signals of the eqadc involve ?fifo? instead of ?queue?. these register names, register contents, and signals are functionally equivalent to external triggers cqueues rqueues dmac/cpu dma/interrupt requests eqadc trigger and fifo control logic system bus analog to digital converter cfifos rfifos analog to digital converter eqadc ssi external device serial connection RM0029 enhanced queued analog-to-digital converter (eqadc) doc id 15177 rev 8 1189/1740 the ?queue? counterparts in the qadc. table 636 lists how the eqadc register, register contents, and signals are related to qadc. . the eqadc and qadc also have similar procedures for the configuration or execution of applications. table 637 shows the steps required for the qadc versus the steps required for the eqadc system. table 636. terminology comparison between qadc and eqadc qadc terminology eqadc terminology function ccw command message in the qadc, the hardware only executes conversion command words. in the eqadc, not all commands are conversion commands; some are configuration commands. queue trigger cfifo trigger in the qadc, a trigger event is required to start the execution of a queue. in the eqadc, a trigger event is required to start command transfers from a cfifo. when a cfifo is triggered and transferring, commands are continuously moved from cqueues to cfifos. thus, the trigger event initiates the ?execution of a queue? indirectly. current word pointer queue x (cwpqx) counter value of commands transferred from command fifox (tc_cfx) in the qadc, cwpqx allows the last executed command on queue x to be determined. in the eqadc, the tc_cfx value allows the last transferred command on cqueue x to be determined. queue pause bit (p) cfifo pause bit in the qadc, detecting a pause bit in the ccw will pause the queue execution. in the eqadc, detecting a pause bit in the command will pause command transfers from a cfifo. queue operation mode (mqx) cfifo operation mode (modex) the eqadc supports all queue operation modes in the qadc except operation modes related to a periodic timer. a timer elsewhere in the system can provide the same functionality if it is connected to etrigx. queue status (qs) cfifo status (cfsx) in the qadc, the queue status is read to check whether a queue is idle, active, paused, suspended, or trigger pending. in the eqadc, the cfifo status is read to check whether a queue is idle, waiting for trigger (idle or paused in qadc), or triggered (suspended or trigger pending in qadc). what cfifo is currently ?active? can be determined by reading the lcftcbz field on the eqadc_cfssr registers. table 637. usage comparison between qadc and eqadc system procedure qadc eqadc system analog control configuration configure analog device by writing to the qadc registers. program configuration commands into command queues. prepare scan sequence program scan commands into command queues. program scan commands into command queues. queue control configuration write to the qadc control registers. write to the eqadc control registers. enhanced queued analog-to-dig ital converter (eqadc) RM0029 1190/1740 doc id 15177 rev 8 data transferred between queues and buffers not required. program the dmac or the cpu to handle the data transfer. serial interface configuration not required. write to the eqadc ssi registers. queue execution require software or external trigger events to start queue execution. require software or external trigger events to start command transfers from a cfifo. table 637. usage comparison between qadc and eqadc system (continued) procedure qadc eqadc system RM0029 decimation filter doc id 15177 rev 8 1191/1740 26 decimation filter 26.1 information specific to this device this section presents device-specific parameterization and customization information not specifically referenced in the remainder of this chapter. 26.1.1 device-specific features two decimation filter modules are implemented in spc564a74xx, spc564a80xx. the decimation filter is used to decimate conversion results from the eqadc block. a dedicated slave-bus interface provides bidirectional communication between the eqadc and decimation filters. another slave-bus interface is also provided for setting up the filter parameters and configuration registers. the decimation filter receives conversion results generated by the eqadc block. these results can be generated from eight different adc setup configurations which are identified by an specific eqadc control address within a conversion command. conversion commands with register address set to zero use the standard configuration setup. the samples generated by the standard configuration setup are sent to one of the local eqadc rfifo buffers. the samples generated by the alternate configurations, with address from 1 to 6, can be sent to the internal rfifo or to the eqadc dedicated slave-bus interface to communicate with the external decimation filter ip block or any other block that can communicate with this interface. a bit field in the alternate configuration control register selects the internal rfifo or this slave-bus interface as the destination for the conversion result. 26.1.2 device-specific parameters mdis_default resets mdis bit in decimation filter module configuration register to 0. 26.2 introduction 26.2.1 overview the decimation filter is a dedicated hardware block, designed to decimate fixed point sample conversion results, generated by master block, usually an eqadc. a dedicated parallel side interface (psi) provides bi-directional communication between the master block and the filter. a second interface is provided for use by the cpu, allowing setup of the filter parameters and read/write of the configuration registers. the decimation filter receives data samples from the master block (eqadc) in the psi rx sub-block. each sample arrives at the decimation filter with an identifier tag and associated commands. the input information is decoded by the psi rx and control logic sub-blocks. when receiving a filtering command, the data is transferred to the filter tap register?s sub- block and is processed by the filter using the mac, the coefficient register, and the control logic sub-blocks. then the result is returned to the master block by the psi tx sub-block. table 638. decimation filter parameters for spc564a74xx, spc564a80xx parameter name description value mdis_default decfilter_mcr[31], mdis reset state 0 decimation filter RM0029 1192/1740 doc id 15177 rev 8 this result is accompanied by the corresponding tag information that provides an address for the data. to summarize normal mode, the decimation filter works as a slave block on this second slave-bus line, and there is a psi master block such as the eqadc to send and read data. this is illustrated in the application example in section 26.7, application information . the decimation filter can also work in a standalone mode. in this mode, the input data is supplied and the output results are read by the chip core processor (cpu) using status and interrupt signals or dma requests. mixed modes are also provided, allowing input data fed from the psi interface, and output results read by the cpu or dma, or input fed from cpu or dma and output directed to the psi interface. an integrator unit independently accumulates the values of filter outputs. the integration can be restricted to time windows defined by hardware signals or software. two or more decimation filter blocks can also be configured to work in the cascade mode of operation to obtain a more complex filtering function. the output result of a filter block is connected to the input of the next filter by means of a dedicated interface. all signals in the interface are generated in the system clock domain. figure 671 is the block diagram for the decimation filter. figure 671. decimation filter block diagram control coefficient register file logic enable/clear counter tx en mac done bypass select en data-in 1 data-in 2 decimated result intermediary result mac done coefficient select clear/load rx data psi rx decimated sample tap data filter tap result bypass data path data new sample/ control field psi tx psi slave-bus line device slave-bus line en data decoder counter filter tap registers cascade input cascade output integrator integration control signals external trigger signal RM0029 decimation filter doc id 15177 rev 8 1193/1740 26.2.2 features the decimation filter block includes these distinctive features: selectable 4th order iir filter, or an 8th order fir filter ? input/output with 16-bit (fixed point) two?s complement signed values ? internal taps with 16-bit (feed-forward portion of first iir) and 24-bit (feedback portion) resolutions (fixed point) for two?s complement signed value ? 24-bit programmable filter coefficients (fixed point) for two?s complement signed value ? mac unit with 51-bit fixed point accumulator ? convergent rounding methodology ? two?s complement overflow or saturation selection ? 58 clock cycles to process the input implements a local slave-bus interface to a master block (e.g. the eqadc block) input and output buffers with dma capability slave-bus interface to device filter taps access for debug filter initialization (flush) and stabilization (prefill) commands timestamp support decimation controlled by an internal counter or from an on-chip independent trigger signal (triggered output result) integrator unit accumulates filter output values, signaled or absolute, with 32-bit resolution. the integrator can be controlled by software or hardware signals. cascade of 2 or more individual blocks to compose a more complex filter 26.2.3 modes of operation this section describes the operation modes of the decimation filter. the modes are selected using the decfilter_mcr fields mdis, fren, frz, isel, mixm, and cascd (see section , decimation filter module configuration register (decfilter_mcr) ). the mode selection is summarized in table 639 . table 639. operation mode selection mode mdis fren, frz isel mixm cascd normal 0 (0, 0) or (0, 1) or (1, 0) 00 00 standalone 1 0 psi input mixed 0 1 psi output mixed 1 1 cascade 0 or 1 0 01 or 10 or 11 freeze (1) 1. freeze mode can also be activated from outside the decimation filter, depending on the mcu, if fren = 1. 1, 1 x x x low power 1 x x x x decimation filter RM0029 1194/1740 doc id 15177 rev 8 normal mode this is the default operational mode of the decimation filter block. it corresponds to the prefill/filter operation with input data supplied through the psi slave-bus interface (i.e. its input data is the adc conversion result), with output going to the same psi interface. standalone mode standalone mode differs from normal mode because the input data is not supplied by the master block through the psi slave-bus interface. in this case, the data is provided by the central processor using the device slave-bus interface or dma interface signals. once the data is filtered the decimated result is available in the output buffer register. the filter output is also consumed by a cpu or dma mastering the same device slave-bus interface. this operation mode can be used to debug the filter stability or to decimate data in system ram. psi input mixed mode in this mode the input is selected from the psi slave-bus interface, but the output is directed to the device slave-bus interface, where it can be read by the cpu or dma. psi output mixed mode this mode works inverted from the psi input mixed mode: the input is selected from the device slave-bus interface, fed either by the cpu or dma, and the output is directed to the psi slave-bus interface. if an eqadc is connected to the psi interface, the output is directed to an rfifo selected by the tag field in the decfilter_ib register (see section , decimation filter interface input buffer register (decfilter_ib) ). cascade mode cascade mode is a filter structure mode with two or more individual filter blocks connected in a chain to form a more complex filter function. the output result of the first block (head block) is connected to the input of the next block (middle or tail block) to be filtered again. more details in section 26.5.16, cascade mode description . low power mode low power mode corresponds to the module disable mode or stop mode. in the module disable mode the psi slave-bus line is disabled and it is not possible to enter freeze mode. the system clock is stopped. and in stop mode, the system clock is also stopped. freeze mode this mode is also known as debug mode. all filter action is frozen, either through software or by the hardware soc debug request signal. if a freeze request comes when the filter is processing an input, it enters freeze mode only after the processing finishes. 26.3 external signal description note: the decimation filter does not provide metastability protection nor filtering for these signals. 26.3.1 decimation trigger signal this signal is used to control the output of the decimation filter, allowing decimation to be driven externally. for more details, see section , triggered output result description . RM0029 decimation filter doc id 15177 rev 8 1195/1740 26.3.2 integrator enable signal this signal is used to enable the hardware integrator. for more details, see section , integrator enabling and halting . 26.3.3 integrator halt signal this signal is used to halt the hardware integrator. for more details, see section , integrator enabling and halting . 26.3.4 integrator reset signal this signal is used to reset the hardware integrator. for more details, see section , integrator reset . 26.3.5 integrator output request signal this signal is used to update the integrator output result. for more details, see section , integrator outputs . 26.4 memory map and register definition this section provides the memory maps and detailed descriptions of all registers. accesses to reserved areas of the memory map can return a bus error, depending on the device integration. this module communicates with two distinct slave-bus lines. one is related to the device integration and the second is related to a psi master block for data transfers. below both memory maps are described. 26.4.1 decimation filter device memory map the addresses of the decimation filter registers are specified as offsets from the module?s base address, described in table 640 . the registers allocated in this memory map are sufficient for a 4th order iir filter implementation. table 640. decimation filter device memory map offset from decfilter_ base 0xfff8_8000 (filter a) 0xfff8_c000 (filter b) register location 0x000 decimation filter module configuration register (decfilter_mcr) on page 26- 1197 0x004 decimation filter module status register (decfilter_msr) on page 26- 1203 0x008 decimation filter module extended configuration register (decfilter_mxcr) on page 26- 1206 0x00c decimation filter module extended status register (decfilter_mxsr) on page 26- 1210 decimation filter RM0029 1196/1740 doc id 15177 rev 8 0x010 decimation filter interface input buffer register (decfilter_ib) on page 26- 1212 0x014 decimation filter interface output buffer register (decfilter_ob) on page 26- 1213 0x018?0x01f reserved 0x020 decimation filter coefficient 0 register (decfilter_coef0) on page 26- 1214 0x024 decimation filter coefficient 1 register (decfilter_coef1) 0x028 decimation filter coefficient 2 register (decfilter_coef2) 0x02c decimation filter coefficient 3 register (decfilter_coef3) 0x030 decimation filter coefficient 4 register (decfilter_coef4) 0x034 decimation filter coefficient 5 register (decfilter_coef5) 0x038 decimation filter coefficient 6 register (decfilter_coef6) 0x03c decimation filter coefficient 7 register (decfilter_coef7) 0x040 decimation filter coefficient 8 register (decfilter_coef8) 0x044?0x077 reserved 0x078 decimation filter tap0 register (decfilter_tap0) (1) on page 26- 1214 0x07c decimation filter tap1 register (decfilter_tap1) 0x080 decimation filter tap2 register (decfilter_tap2) 0x084 decimation filter tap3 register (decfilter_tap3) 0x088 decimation filter tap4 register (decfilter_tap4) 0x08c decimation filter tap5 register (decfilter_tap5) 0x090 decimation filter tap6 register (decfilter_tap6) 0x094 decimation filter tap7 register (decfilter_tap7) 0x098?0x0cf reserved 0x0d0 decimation filter interface enhanced debug input data register (decfilter_edid) on page 26- 1215 0x0d4?0x0df reserved table 640. decimation filter device memory map (continued) offset from decfilter_ base 0xfff8_8000 (filter a) 0xfff8_c000 (filter b) register location RM0029 decimation filter doc id 15177 rev 8 1197/1740 26.4.2 decimation filter register descriptions all registers are 32-bit wide. decimation filter module configuration register (decfilter_mcr) the decimation filter module configuration register provides configuration control bits for the decimation filter internal logic. note: one must not modify this register contents when the status bit bsy is set, except for fields fren, frz and idis. to guarantee that bsy does not set during the read-modify-write operation, it is advisable to set idis = 1 and wait for bsy = 0 beforehand. 0x0e0 decimation filter final integration value register (decfilter_fintval) on page 26- 1215 0x0e4 decimation filter final integration count value register (decfilter_fintcnt) on page 26- 1216 0x0e8 decimation filter current integration value register (decfilter_cintval) on page 26- 1217 0x0ec decimation filter current integration count value register (decfilter_cintcnt) on page 26- 1217 0x0f0?0x1ff reserved 1. the tap register stores, on each filter node, the i nput sample data and, for the iir type, the filter intermediary results. table 640. decimation filter device memory map (continued) offset from decfilter_ base 0xfff8_8000 (filter a) 0xfff8_c000 (filter b) register location figure 672. decimation filter module c onfiguration register (decfilter_mcr) address: decfilter_base + 0x000 access: user read/write 0123456789101112131415 r mdis fren 0 frz 0 cascd[1:0] iden oden erren 0 ftype[1:0] 0 scal[1:0] w sres reset ? (1) 000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r idis sat isel mixm dec_rate[3:0] sdie dsel ibie obie edme tore tmode[1:0] w reset1000000000000000 1. reset value is defined by the mdis_default parameter value. decimation filter RM0029 1198/1740 doc id 15177 rev 8 table 641. decfilter_mcr register field descriptions field description 0 mdis module disable. the mdis bit puts the decimation filter in low power mode. communication through the psi slave-bus interface is ignored in this mode. writes to the configuration register are allowed with the exception of writes to the fren and sres bits, which are ignored. writes to the coefficient registers are also allowed. the decimation filter cannot enter freeze mode once in disable mode. once the module is disabled it no longer receives the system clock. 1 low power mode 0 normal mode 1 fren freeze enable. the fren bit enables the decimation filter to enter freeze mode if the soc debug request signal or the frz bit is asserted. see section 26.5.13, freeze mode description , for more details. 1 decimation filter freeze mode enabled 0 decimation filter freeze mode disabled 2 reserved, should be cleared. 3 frz freeze mode the frz bit controls the freeze mode of the decimation filter. for this bit to take effect the fren freeze enable bit also needs to be asserted. while in freeze mode the mac operations are halted. see section 26.5.13, freeze mode description , for more details. 1 decimation filter in freeze mode 0 decimation filter in normal mode 4 sres software-reset bit the sres is a self-negated bit which provides the cpu with the capability to initialize the decimation filter through the slave-bus interface. this bit always reads as zero. see section 26.5.10, soft-reset command description , for more details. 1 software-reset 0 no action 5?6 cascd[1:0] cascade mode configuration. the cascd[1:0] bit field configures the block to work in cascade mode of operation according to table 642 . for more details about the cascade mode, see section 26.5.16, cascade mode description . any change to this field must follow the procedure described in the section , cascade freeze, stop, and configuration change procedures . iden 7 input data interrupt enable. the iden bit enables the decimation filter to generate interrupt requests on all new input data written to the interface input buffer register or input/output buffers register. 1 input data interrupt enabled 0 input data interrupt disabled table 642. cascd[1:0] ? filter cascade mode configuration selection cascd[1:0] description 00 no cascade mode (single block) 01 cascade mode, head block configuration 10 cascade mode, tail block configuration 11 cascade mode, middle block configuration RM0029 decimation filter doc id 15177 rev 8 1199/1740 oden 8 output data interrupt enable. the oden bit enables the decimation filter to generate interrupt requests on all new data written to the filter output buffer. it is independent of how isel and mixm are set. 1 output data interrupt enabled 0 output data interrupt disabled erren 9 error interrupt enable. the erren bit enables the decimation filter to generate interrupt requests based on the assertion of the decfilter_msr error flags ovf, divr, svr, ovr or ivr. 1 error interrupts enabled 0 error interrupts disabled 10 reserved, should be cleared. ftype[1:0] 11?12 filter type selection bits. the ftype[1:0] bits select the filter type according to table 643 . bypass must not be configured in cascade mode (see field cascd). 13 reserved, should be cleared. 14?15 scal[1:0] filter scaling factor. the scal[1:0] bit field selects the scaling factor used by the filter algorithm according to table 644 . table 641. decfilter_mcr register field descriptions (continued) field description table 643. ftype[1:0] ? filter type selection ftype[1:0] description 00 filter bypass (1) 1. in bypass configuration the filter is disabled. 01 iir filter - 1 x 4th order 10 fir filter - 1 x 8th order 11 reserved table 644. scal[1:0] ? filter scaling factor definition scal[1:0] description 00 scaling factor = 1 01 scaling factor = 4 10 scaling factor = 8 11 scaling factor = 16 decimation filter RM0029 1200/1740 doc id 15177 rev 8 16 idis input disable. the idis bit disables the block input, so that writes to the input buffer have no effect (either from the device slave-bus or from the psi interface), and input dma or interrupt requests are not issued. input disabling is neede d to change the block configuration to or from cascade mode. see section 26.5.16, cascade mode description for more details. 1 input disabled 0 input enabled idis resets in 1 (hardware reset only), and the modul e configuration procedures for previous versions (without idis bit) are upward compatible provided that the decfilter_mcr is written with 0 into the idis position (previously reserved). 17 sat saturation enable. the sat bit enables the saturation of the filter output. see section , saturation , for more details. 1 enable saturation 0 disables saturation isel 18 input selection. the isel bit selects the source of input data to the filter. possible data sources are the master block of the psi slave-bus interface, or the cpu/dma on the device slave-bus interface. each device slave-bus write to the interface input buffer register or dma transfer to the input buffer is interpreted as a new sample to be processed by the filter. the output interface used is the same as the one selected by isel if the output selection bit mixm = 0. when mixm = 1, the output selection (slave-bus or device slave-bus) is contrary to the input selection (see table 645 and the mixm bit definition), configuring a mixed mode operation. the slave-bus interface can always read the input/output buffers, however the psi slave-bus interface can only read the output buffer by request of the decimation filter, in normal or input mixed modes. this behavior is outlined in detail in table 645 . 1 filter input from the device slave-bus interface 0 filter input from psi slave-bus interface isel completely selects the output when the filter is configured as cascade tail, and is ignored when it is configured as cascade middle. isel must no t be modified during the filter operation (when the status bit bsy is set). in addition, the interface not selected by isel must not be used to write into the input buffer. table 641. decfilter_mcr register field descriptions (continued) field description RM0029 decimation filter doc id 15177 rev 8 1201/1740 isel 18 (cont) 19 mixm mixed mode. the mixm field selects the interface used for filter output, either device slave-bus or the psi slave-bus, in relation to the interface selected by isel (see isel bit definition and table 645 for more details): 1 interface not selected by isel is used for output, configuring mixed mode. 0 interface selected by isel is used for output, configuring normal or standalone mode mixm must be set to 0 (zero) when the filter is configured as cascade mode. table 641. decfilter_mcr register field descriptions (continued) field description table 645. isel/mixm definition ? read/write from/to input/output buffers isel mixm mode operation device slave-bus interface psi slave-bus interface input buffer output buffer input buffer output buffer 0 0normal read always, by dma or interrupt (1) request if edme = 1 1. bit dsel selects between interrupt or dma request always, no dma or interrupt forbidden, write only by decfil request (2) 2. decimation filter issues a read request to the master block 1 psi input mixed always, issues dma or interrupt (1) disabled 0normal write forbidden no effect, read only enabled (read only) 1 psi input mixed 1 0 standalone read always, no dma or interrupt always, issues dma or interrupt (1) forbidden, write only disabled 1 psi output mixed always, no dma or interrupt by decfil request (2) 0 standalone write enabled, by dma or interrupt request (1) no effect, read only forbidden read only 1 psi output mixed decimation filter RM0029 1202/1740 doc id 15177 rev 8 20?23 dec_rate[3:0] decimation rate selection. the dec_rate[3:0] fi eld selects the decimation rate used by the decimation filter. the decimation rate defines the number of data samples from the master block that is required to generate one decimated result in the decimation filter output. 24 sdie integrator data interrupt enable. the sdie field enables output buffer interrupts due to integrator data result being ready (at registers decfilter_fintval and decfilter_fintcnt): 1 integration ready causes an output interrupt 0 integration ready does not cause an output interrupt. 25 dsel dma selection. the dsel bit determines whether the data transfers ? to the input buffer (write to) and from the output buffer (read from) ? are performed by dma requests or by interrupt requests. this bit can also be active when psi input is selected with enhanced debug (isel = 0, edme = 1), in which case the input buffer generates read requests only (see section 26.5.14, enhanced debug monitor description ). 1 dma requests are generated 0 interrupt requests are generated 26 ibie input buffer interrupt request enable. the ibie bit enables the decimation filter to generate interrupt requests when: ? device slave-bus input is selected (isel = 1) and dsel = 0 when the input buffer is available to receive new data; ? psi input is selected with enhanced debug (isel = 0, edme = 1) and dsel = 0 when the input buffer has data to be read by the device cpu. 1 input buffer interrupt request enabled 0 input buffer interrupt request disabled 27 obie output buffer interrupt request enable the obie bit enables the decimation filter interrupt requests when outputs are directed to the device slave-bus (isel!= mixm) and dma is not selected (dsel = 0). 1 output buffer interrupt request enabled 0 output buffer interrupt request disabled 28 edme enhanced debug monitor enable the edme bit defines the enhanced debug monitor when input selection is from psi (isel = 0). in this case, the raw data fed from the psi master block is also, in parallel, made available in the register decfilter_edid (see section 26.5.14, enhanced debug monitor description ), generating and input interrupt or dma request. 1 enhanced debug monitor enabled (read requests of input data from master block enabled) 0 enhanced debug monitor disabled table 641. decfilter_mcr register field descriptions (continued) field description table 646. dec_rate[3:0] definition dec_rate[3:0] description 0000 no decimation: one filter output for each sample input 0001 ? 1111 one filter output for each (dec_rate+1) sample inputs RM0029 decimation filter doc id 15177 rev 8 1203/1740 decimation filter module status register (decfilter_msr) 29 tore triggered output result enable. the tore bit enables an input trigger signal to force the decimation filter to send the next result of the filter back to the master block. for more details, see section , triggered output result description . 1 output buffer update using an external signal is enabled 0 output buffer update using an external signal is disabled tore must only be asserted when psi is selected as output (normal or psi output mixed modes).tore must not be asserted with the filter bypassed (ftype = 00). 30?31 tmode[1:0] trigger mode. the tmode field selects the way the trigger signal controls the output result sampling function enabled by the tore bit, as shown in table 647 . the tmode definition replaces, and is upward com patible with, the trfe bit definition found in previous versions of the decimation filter. table 641. decfilter_mcr register field descriptions (continued) field description table 647. tmode[1:0] definition tmode[1:0] description 00 output is posted at the rising edge of the trigger signal 01 output is posted whenever the trigger signal is a logical 0 10 output is posted at the falling edge of the trigger signal 11 output is posted whenever the trigger signal is a logical 1 figure 673. decimation filter status register (decfilter_msr) address: decfilter_base + 0x004 access: user read/write 0123456789101112131415 r bsy 0 dec_counter[3:0] 0 0 0 0 0 0 0 0 0 0 w idfc odfc ibic obic divrc ovfc ovrc ivrc reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 idf odf 0 ibif obif 0 divr ovf ovr ivr w reset0000000000000000 decimation filter RM0029 1204/1740 doc id 15177 rev 8 table 648. decfilter_msr register field descriptions field description 0 bsy decimation filter busy indication. the bsy bit indicates that the decimation filter is processing new input data from the master block in normal mode or from the device core in standalone mode. bsy is not asserted when the filter is disabled (ftype = 00). however, the bsy bit is asserted when the soft reset is executed. 1 decimation filter busy 0 decimation filter idle 1 reserved, should be cleared. 2?5 dec_counter [3:0] decimation counter. the dec_counter[3:0] field indicates the current value of the dec_counter decimation counter (see figure 671 ), which counts the number of input data samples received by the decimation filter. when the value of this counter matches the dec_rate[3:0] configuration register field, one decimated result is generated and the dec_counter counter is reinitialized at zero. this register is cleared by a soft reset or a flush command. 6 idfc input data flag clear bit. the idfc bit clears the idf flag bit in the status register. this bit is self negated, therefore it is always read as zero. 1clears idf 0 no action 7 odfc output data flag clear bit. the odfc bit clears the odf flag bit in the status register. this bit is self negated, therefore it is always read as zero. 1clears odf 0 no action 8 reserved, should be cleared. 9 ibic input buffer interrupt request clear bit. the ibic bit clears the ibif flag bit in the status register. this bit is self negated, therefore it is always read as zero. 1 clears ibif 0 no action 10 obic output buffer interrupt request clear bit. the obic bit clears the obif flag bit in the status register. this bit is self negated, therefore it is always read as zero. 1clears obif 0 no action 11 reserved, should be cleared. 12 divrc divr clear bit. the divrc bit clears the divr debug filter input data read overrun indication bit in the status register. this bit is self negated, therefore it is always read as zero. 1clears divr 0 no action 13 ovfc ovf clear bit. the ovfc bit clears the ovf output overflow bit in the status register. this bit is self negated, therefore it is always read as zero. 1clears ovf 0 no action 14 ovrc ovr clear bit. the ovrc bit clears the ovr output overrun bit in the status register. this bit is self negated, therefore it is always read as zero. 1clears ovr 0 no action RM0029 decimation filter doc id 15177 rev 8 1205/1740 15 ivrc ivr clear bit. the ivrc bit clears the ivr filter input overrun indication bit in the status register. this bit is self negated, therefore it is always read as zero. 1clears ivr 0 no action 16?21 reserved, should be cleared. 22 idf input data flag. the idf bit flag indicates when new data is available at the decfilter_ib register or at the decfilter_iob register. this flag generates an interrupt request if enabled by the iden bit in the configuration register. this flag is cleared by the idfc status bit or by a soft reset of the decimation filter. 1 new sample received 0 sample not received obs: this flag is not used for read / write requests. it is used only to announce the input data event. for read / write request flag, refer to ibif. 23 odf output data flag. the odf bit flag indicates when a new decimated sample is available at the decfilter_ob register or at the decfilter_iob register. this flag generates an interrupt request if enabled by the oden bit in the configuration register. this flag is cleared by the odfc status bit or by a soft reset of the decimation filter. 1 new decimated output sample available 0 no new decimated output sample available obs: this flag is not used for read requests. it is used only to announce the output data event. for read request flag, refer to obif. 24 reserved, should be cleared. 25 ibif input buffer interrupt request flag. the ibif bit flag indicates that the input buffer decfilter_ib is available to be filled with new data, when enhanced debug monitor is off. in enhanced debug monitor, it indicates the input buffer decfilter_ib was filled with a new sample and is ready to be read. ibif assertion also asserts the interrupt signal when enabled by the ibie bit in the configuration register when dma is not selected (dsel = 0) and the input buffer requires access from the device slave-bus (isel!= edme). this flag is cleared by the ibic status bit or by a soft reset of the decimation filter. 1 new sample is requested (isel = 1, edme = 0) or new sample is available in enhanced debug monitor (isel = 0, edme = 1). 0 no action 26 obif output buffer interrupt request flag. the obif bit flag indicates that either a new decimated sample is available at the decfilter_ob register. this flag generates an interrupt request if enabled by the obie bit in the configuration register and with isel!=mixm and dsel = 0. this flag is cleared by the obic status bit or by a soft reset of the decimation filter. 1 new decimated output available 0 no new decimated output available 27 reserved, should be cleared. 28 divr enhanced debug monitor input data read overrun. the divr bit indicates that a received sample in the filter interface input register was overwritten by a new sample and was not read by the core. this flag generates an interrupt request if enabled by the erren bit in the configuration register. this flag is cleared by the divrc status bit or by a soft reset of the decimation filter. 1 enhanced debug monitor input data read overrun occurred 0 input data read overrun did not occur in enhanced debug monitor table 648. decfilter_msr register field descriptions (continued) field description decimation filter RM0029 1206/1740 doc id 15177 rev 8 decimation filter module extended configuration register (decfilter_mxcr) 29 ovf filter overflow flag. the ovf bit indicates that an overflow occurred in the filtered sample result. this flag generates an interrupt request if enabled by the erren bit in the configuration register. this flag is cleared by the ovfc status bit or by a soft reset of the decimation filter. 1 overflow occurred 0 no overflow 30 ovr output interface buffer overrun. the ovr bit indicates that a decimated sample was overwritten by a new sample in the interface output buffer register. this flag generates an interrupt request if enabled by the erren bit in the configuration register. this flag is cleared by the ovrc status bit or by a soft reset of the decimation filter. 1 filter output overrun occurred 0 no output overrun 31 ivr input interface buffer overrun. the ivr bit indicates that a received sample in the filter interface input register was overwritten by a new sample. this was probably caused by a violation of the decimation filter maximum throughput. this flag generates an interrupt request if enabled by the erren bit in the configuration register. this flag is cleared by the ivrc status bit or by a soft reset of the decimation filter. 1 input buffer overrun occurred 0 input buffer overrun did not occur ivr does not set due to input register writes wh en input is disabled (decfilter_mcr bit idis = 1). table 648. decfilter_msr register field descriptions (continued) field description figure 674. decimation filter extended c onfiguration register (decfilter_mxcr) address: decfilter_base + 0x008 access: user read/write 0123456789101112131415 r sdmae ssig ssat scsat 000000000000 w srq szro reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sisel 0 szrosel 00 shltsel 0 srqsel 00 sensel w reset0000000000000000 RM0029 decimation filter doc id 15177 rev 8 1207/1740 table 649. decfilter_mxcr register field descriptions field description 0 sdmae integrator dma enable. the sdmae bit enables the dma request when an integrator output is requested (see section , integrator outputs ). 1 integrator dma request enabled 0 integrator dma request disabled the dma channel used is the same one used for filt er outputs, and any configuration that generates dma requests from both of those sources is not allowed. 1 ssig integrator signal operation selection. the ssig bit defines how the filtered data signal is treated for integration: 1 integrator input takes signaled filter output 0 integrator input takes the abs olute value of filter output 2 ssat integrator saturated operation selection. the ssat bit defines how the integrator accumulator behaves in case of an overflow. 1 integrator accumulator saturates on an overflow 0 integrator accumulator holds a modulo 2 17 value (considering the 15-bit fractional part) on an overflow. in saturated operation the overflown integration sum holds the value 0xffffffff for absolute integration (ssig = 0), or values 0x7ffffff f (positive saturation) and 0x80000000 (negative saturation) for signaled integration (ssig = 1). non-saturated mode is not supported with signaled integration, therefore one must not configure ssig = 1 and ssat = 0. 3 scsat integrator counter saturated operation selection. the scsat bit defines how the integrator sample counter behaves in case of an overflow. 1 integrator sample counter saturates on an overflow, holding a value of 0xffffffff. 0 integrator sample counter holds a modulo 2 32 value on an overflow. 4?13 reserved, should be cleared. 14 srq integrator output request. the srq bit is used to command the update of the integrator output, reflected in the registers decfilter_fintval and decfilter_fintcnt. it may also cause a dma or interrupt request, depending on the decfilter_mcr bit sdie and decfilter_mxcr bit sdmae. this is a write-only bit, so reads always return 0. for more details see section , integrator outputs . 1 requests integrator output update 0 no integrator output update request 15 szro integrator zero. the szro bit is used to zero the integrator sum. this is a write-only bit, reads always return 0. for more details see section , integrator reset . 1 zeroes integrator sum 0 does not zero integrator sum if bits srq and szro are both written 1 at the same time, the integrator is reset only after the registers decfilter_fintval and decfilter_fintcnt are updated. 16 sisel integrator input selection. the sisel bit selects the input of the integrator. for more details see section , integrator inputs . 1 filter outputs before the decimation feed the integrator 0 decimated filter outputs feed the integrator 17 reserved, should be cleared. decimation filter RM0029 1208/1740 doc id 15177 rev 8 18?19 szrosel[1:0] (1) integrator zero control mode selection the szrosel field defines the use of the integrator zero hardware input signal, according to table 650 . for more details see section , integrator reset . 20?21 reserved, should be cleared. 22?23 shltsel[1:0] (2) integrator halt control selection. the shltsel field defines the integrator halting mechanism, according to table 651 . when the integrator is halted, the integration accumulator remains unaltered on filter outputs independently of the enabling selected by sensel. for more details see section , integrator enabling and halting 24 reserved, should be cleared. table 649. decfilter_mxcr register field descriptions (continued) field description table 650. szrosel ? integrator zero mode szrosel[1: 0] description 00 hardware integrator zero request disabled 01 integrator zero on toggle of hardware signal 10 integrator zero on rising edge of hardware signal 11 integrator zero on falling edge of hardware signal table 651. shltsel ? integrator halt control selection shltsel[1:0] description 00 hardware halt control signal disabled 01 integrator halted, independently of the hardware signal 10 integrator halted when signal is at logical 0 11 integrator halted when signal is at logical 1 RM0029 decimation filter doc id 15177 rev 8 1209/1740 25?27 srqsel[2:0] (1) integrator output read request mode selection. the srqsel field defines the use of the integrator output request hardware input signal, according to table 652 . an integrator output request updates the registers decfilter_fintval and decfilter_fintcnt, also causing a dma or interrupt request. note that dma or interrupt requests due to integrator output updates depend on the decfilter_mxcr bit sdmae and decfilter_mcr bit sdie. when continuous output is on, an integrator output request is issued whenever a new filter output is accumulated. for more details see section , integrator outputs . 28?29 reserved, should be cleared. 30?31 sensel[1:0] (1) integrator enable control selection. the sensel field defines the integrator enabling mechanism, according to table 653 . when the integrator is enabled, filter outputs selected by the sisel bit are added to the integration accumulator. when the integrator is disabled, the integration accumulator remains unaltered on filter outputs. for more details see section , integrator enabling and halting . 1. the hardware input signals are zsela for decimation filter a and zselb for decimation filter b, defined in section 16.6.24, imux select register 10 (siu_isel10) . 2. the hardware input signals are hsela for decimation filter a and hselb for decimation filter b, defined in section 16.6.24, imux select register 10 (siu_isel10) . table 649. decfilter_mxcr register field descriptions (continued) field description table 652. srqsel ? integrator output request mode srqsel[2:0] description 000 hardware output request disabled 001 integrator output request on toggle of hardware signal 010 integrator output request on rising edge of hardware signal 011 integrator output request on falling edge of hardware signal 100 reserved 101 continuous output request on, independently of hardware signal 110 continuous output request on when signal is at logical 0 111 continuous output request on when signal is at logical 1 table 653. sensel ? integrator enable control selection sensel[1:0] description 00 integrator disabled, independently of the hardware enable control signal 01 integrator enabled, independently of the hardware signal 10 integrator enabled when signal is at logical 0 11 integrator enabled when signal is at logical 1 decimation filter RM0029 1210/1740 doc id 15177 rev 8 decimation filter module extended status register (decfilter_mxsr) figure 675. decimation filter extended status register (decfilter_mxsr) address: decfilter_base + 0x00c access: user read/write 0123456789101112131415 r0000000000000000 w sdfc ssec scec ssovfc scovfc svrc reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000sdf00ssesce0 ssovf scovf svr w reset0000000000000000 table 654. decfilter_mxsr register field descriptions field description 0?6 reserved, should be cleared. 7 sdfc integrator output data flag clear bit. the sdfc bit clears the sdf flag bit in the status register. this bit is self negated, therefore it is always read as zero. 1clears sdf 0 no action 8?9 reserved, should be cleared. 10 ssec integrator sum exception clear bit. the ssec bit clears the sse flag bit in the status register. this bit is self negated, therefore it is always read as zero. 1 clears sse 0 no action 11 scec integrator count exception clear bit. the scec bit clears the sce flag bit in the status register. this bit is self negated, therefore it is always read as zero. 1clears sce 0 no action 12 reserved, should be cleared. 13 ssovfc integrator sum overflow clear bit. the ssovfc bit clears the ssovf flag bit in the status register. this bit is self negated, therefore it is always read as zero. 1 clears ssovf 0 no action 14 scovfc integrator count overflow clear bit. the scovfc bit clears the scovf flag bit in the status register. this bit is self negated, therefore it is always read as zero. 1clears scovf 0 no action RM0029 decimation filter doc id 15177 rev 8 1211/1740 15 svrc svr clear bit. the svrc bit clears the svr integrator data overrun indication bit in the status register. this bit is self negated, therefore it is always read as zero. 1 clears svr 0 no action 16?22 reserved, should be cleared. 23 sdf integrator data flag. the sdf bit flag indicates when a new integrator result is available at the decfilter_fintval register. this flag generates an interrupt request if enabled by the sdie bit in the configuration register. this flag is cleared by the sdfc status bit or by a soft reset of the decimation filter. 1 new integrator result available 0 no new integrator result available 24?25 reserved, should be cleared. 26 sse integrator sum exception flag. the sse bit indicates an exceptional condition of the integrator accumulator. this flag generates an interrupt request if enabled by the decfilter_mcr bit erren, and it is cleared by the ssec bit or by a soft reset. integrator exceptions are defined in section , integrator exceptions . 1 integrator accumulator exception. 0 no exception in the integrator accumulator. 27 sce integrator count exception flag. the sce bit indicates an exceptional condition of the integrator counter. this flag generates an interrupt request if enabled by the decfilter_mcr bit erren, and it is cleared by the scec bit or by a soft reset. integrator exceptions are defined in section , integrator exceptions . 1 integrator counter exception. 0 no exception in the integrator counter. 28 reserved, should be cleared. 29 ssovf integrator sum overflow flag. the ssovf bit indicates an overflow of the integrator accumulator. this flag is cleared by the ssovfc bit or by a soft reset. 1 integrator accumulator overflown. 0 no overflow in the integrator accumulator. the ssovf bit samples the integrator accumulator overflow condition when and only when either registers decfilter_fintval or decfilter_cintcnt are updated. therefore, only one of the register pairs (decfilter_fintval/decfilter_fintcnt and decfilter_cintval/decfilter_cintcnt) must be used by the application, in order to avoid races. table 654. decfilter_mxsr register field descriptions (continued) field description decimation filter RM0029 1212/1740 doc id 15177 rev 8 decimation filter interface input buffer register (decfilter_ib) the input buffer register provides access to the input buffer of the decimation filter when the filter is in the standalone or psi output mixed modes of operation. writes to this register are interpreted as requests to the decimation filter to process new sample data. writes to this register when isel = 0 are not allowed. 30 scovf integrator count overflow flag. the scovf bit flag indicates an overflow of the internal integrated sample counter. this flag is cleared by the scovfc bit or by a soft reset. 1 integrator sample counter overflown. 0 no overflow in the integrator sample counter. the scovf bit samples the integrator accumula tor overflow condition when and only when either registers decfilter_fintval or decfilter_cintcnt are updated. therefore, only one of the register pairs (decfilter_fintval/decfilter_fintcnt and decfilter_cintval/decfilter_cintcnt) must be used by the application, in order to avoid races. 31 svr integrator data overrun. the svr bit indicates that an integration value and count in the registers decfilter_fintval and decfilter_fintcnt was overwritten by a new integrator output request and was not read by th e cpu or dma. this flag generates an interrupt request if enabled by the erren bit in the configuration register. this flag is cleared by the svrc bit or by a soft reset. 1 integrator data overrun occurred. 0 integrator data overrun did not occur. table 654. decfilter_mxsr register field descriptions (continued) field description figure 676. decimation filter interface input buffer register (decfilter_ib) address: decfilter_base + 0x010 access: user read/write 0123456789101112131415 r0000 intag[3:0] 000000 prefill flush w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r inpbuf[15:0] w reset0000000000000000 table 655. decfilter_ib register field descriptions field description 0?3 reserved, should be cleared. 4?7 intag[3:0] decimation filter input tag bits the intag[3:0] bit field is defined as a selector signal and it is used to identify different destinations for the inbuf[15:0] data. when the psi master block is an eqadc, it is used in psi output mixed mode to address the appropriate rfifo in the eqadc block. RM0029 decimation filter doc id 15177 rev 8 1213/1740 decimation filter interface output buffer register (decfilter_ob) 8?13 reserved, should be cleared. 14 prefill decimation filter prefill/filter control bit the prefill bit selects the decimation filter operation mode. for more details, see section 26.5.7, filter prefill control description . 1 decimation filter prefill sample 0 decimation filter normal sample 15 flush decimation filter flush control bit assertion of the flush bit initializes the decimation filter to a initial state, as defined in section 26.5.9, flush command description . this bit is self negated and it is cleared only when the data is read and the flush is executed. 1 flush request 0 no flush request 16?31 inpbuf[15:0] input buffer data the inpbuf[15:0] bit field carries the sample data to be filtered. this data buffer can be written from the psi slave-bus interface or by the device slave-bus interface. see section 26.5.3, input buffer description , for more details. table 655. decfilter_ib register field descriptions (continued) field description figure 677. decimation filter interface output buffer register (decfilter_ob) address: decfilter_base + 0x014 access: user read only 0123456789101112131415 r000000000000 outtag[3:0] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 routbuf[15:0] w reset0000000000000000 table 656. decfilter_ob register field descriptions field description 0?11 reserved, should be cleared. 12?15 outtag[3:0] decimation filter output tag bits. the outtag[3:0] bit field is defined as a selector signal and it is used to identify different destinations for the outbuf[15:0] data. when an eqadc is the psi block master, it holds the same number used to address the destination rfifo. 15?31 outbuf[15:0] output buffer data. the outpbuf[15:0] bit field is the result data in the decimation filter output buffer. it represents a fixed point signed number in two?s complement format and is updated only when a decimated result is ready to be transmitted, meaning it contains the last decimated result from the filter. decimation filter RM0029 1214/1740 doc id 15177 rev 8 decimation filter coefficient n register (decfilter_coefn) decimation filter tapn register (decfilter_tapn) figure 678. decimation filter coeffi cient n register (decfilter_coefn) address: decfilter_base + 0x020?0x040 access: user read/write 0123456789101112131415 r8{coefn[23]} coefn[23:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r coefn[15:0] w reset0000000000000000 table 657. decfilter_coefn register field descriptions field description 0?7 8?31 coefn[23:0] coefficient n field the coefn[23:0] bit fields are the digital filter coefficients registers. the coefficients are fractional signed values in two?s complement format, in the range (-1 coef < 1). reads to this register are sign-extended, meaning the coefficient?s sign bit is copied to all eight most significant register bits.writing to th ese fields when bsy = 1 is not allowed. figure 679. decimation filter tapn register (decfilter_tapn) address: decfilter_base + 0x078?0x094 access: user read only 0123 4 5 6 7 8 9 10 11 12 13 14 15 r 8{tapn[23]} tapn[23:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tapn[15:0] w reset0000000000000000 table 658. decfilter_tapn register field descriptions field description 8?31 tapn[23:0] tapn register the read-only tapn[23:0] bit fields shows the contents of the digital filter tap registers, as fractional signed values in two?s complement format, in the range (-1 coef < 1). RM0029 decimation filter doc id 15177 rev 8 1215/1740 note: reads to this register are sign-extended, meaning the coefficient?s sign bit is copied to all eight most significant register bits. the content of these registers is meaningless when bsy = 1. decimation filter interface enhanced debug input data register (decfilter_edid) the enhanced debug input data register provides read-only access to the sample data received by the decimation filter when the input is selected from the device slave-bus (isel = 0), allowing the monitoring of filter operation. see section 26.5.14, enhanced debug monitor description for more details. writes to this register are not allowed. decimation filter final integration value register (decfilter_fintval) figure 680. decimation filter interface input buffer register (decfilter_edid) address: decfilter_base + 0x0d0 access: user read only 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r samp_data[15:0] w reset0000000000000000 table 659. decfilter_edid register field descriptions field description 0?31 samp_data [15:0] conversion sample data. the samp_data[15:0] bit field carries the data that was loaded in the decimation filter to be processed by the fir/iir sub-block. this conversion data is supplied by the psi slave-bus interface only. see section 26.5.11, interrupts requests description , and section 26.5.12, dma requests description , for more details. figure 681. decimation filter final integration value register (decfilter_fintval) address: decfilter_base + 0x0e0 access: user read only 0123456789101112131415 r sum_value[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sum_value[15:0] w reset0000000000000000 decimation filter RM0029 1216/1740 doc id 15177 rev 8 note: if the defilter_mxcr bit ssat = 1, the integration sum is saturated, so that if the accumulation overflows decfilter_fintval holds the value 0xffffffff for absolute integration (ssig = 0), or values 0x7fffffff (positive saturation) and 0x80000000 (negative saturation) for signaled integration (ssig = 1). if ssat = 0, decfilter_fintval holds the integration sum modulo 2 17 (considering the 15-bit fractional part). decimation filter final integration count value register (decfilter_fintcnt) table 660. decfilter_fintval register field descriptions field description 0?31 sum_value [31:0] integration sum value. the sum_value[31:0] field holds the sum of filtered output values. the 17 most significant bits hold the integer part, and the 15 least significant ones the fractional part of the integration value. the control of the integration sum and update of this register is determined by the register decfilter_mxcr (see section , decimation filter module extended configuration register (decfilter_mxcr) ). the register is updated only upon an integration output request. sum_value should be taken as an unsigned number when the integrator is configured for absolute operation (decfilter_mxcr bit ssig = 0), and a two?s complement signed number otherwise. figure 682. decimation filter final integrati on count value register (decfilter_fintcnt) address: decfilter_base + 0x0e4 access: user read only 0123456789101112131415 r count[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r count[15:0] w reset0000000000000000 table 661. decfilter_fintcnt register field descriptions field description 0?31 count[31:0] integration count value the count field holds the count of filtered outputs integrated. the control of the integration sum and update of this register is determined by the register decfilter_mxcr (see section , decimation filter module extended configuration register (decfilter_mxcr) ). the register is updated together with decfilter_fintval, only upon an integration output request. RM0029 decimation filter doc id 15177 rev 8 1217/1740 decimation filter current integration value register (decfilter_cintval) note: if the defilter_mxcr bit ssat = 1, the integration sum is saturated, so that if the accumulation overflows decfilter_cintval holds the value 0xffffffff for absolute integration (ssig = 0), or values 0x7fffffff (positive saturation) and 0x80000000 (negative saturation) for signaled integration (ssig = 1). if ssat = 0, decfilter_fintval holds the integration sum modulo 2 17 (considering the 15-bit fractional part). note: a read on this register automatically commands an update of the register decfilter_cintcnt. decimation filter current integration count value register (decfilter_cintcnt) figure 683. decimation filter current integration value register (decfilter_cintval) address: decfilter_base + 0x0e8 access: user read only 0123456789101112131415 r sum_value[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sum_value[15:0] w reset0000000000000000 table 662. decfilter_cintval register field descriptions field description 0?31 sum_value [31:0] integration sum value. the sum_value[31:0] field holds an unsigned number representing the sum of filtered output values, continuously updated as the integration proceeds. the control of the integration sum is determined by the register decfilter_mxcr (see section , decimation filter module extended configuration register (decfilter_mxcr) ). figure 684. decimation filter current integration count value register (decfilter_cintcnt) address: decfilter_base + 0x0ec access: user read only 0123456789101112131415 r count[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r count[15:0] w reset0000000000000000 decimation filter RM0029 1218/1740 doc id 15177 rev 8 26.4.3 decimation filter memory map for parallel side interface the decimation filter exchanges data with the master block through the psi. the master block sends data to the input buffers and reads data from the output buffers of the filter. to implement this exchange, only a single register is required as described in table 664 , therefore the psi address is ignored. 26.4.4 psi register description this register is defined as 24-bit. decimation filter input/output buffers register (decfilter_iob) the input/output buffers register is used by the psi master block to access the input and output buffers of the decimation filter. writes to this register are interpreted as requests to the decimation filter to process new sample data or to bypass timestamp data. reads from this register frees the decimation filter output buffer from filtered data or from bypass timestamp data. table 663. decfilter_cintcnt register field descriptions field description 0?31 count[31:0] integration count value. the count field holds the count of filtered outputs integrated. the value is updated only when register decfilter_cintval is read, to keep the coherency between the integration and count values. table 664. parallel side interface memory map for decfilter data exchange decimation filter address description access 0x0 decfilter_iob - decimation filter (1) input/output registers 1. the input registers are addressed for write only and output registers are addressed for read only. r/w figure 685. decimation filter interface input/ output buffers register (decfilter_iob) address: psi_base + 0x0 access: user read/write 0123456789101112131415 r 0000 out_tag[3:0] w m_flush m_ctrl [1:0] inp_tag[3:0] reset???????? 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r out_buff[15:0] w inp_buff[15:0] reset0000000000000000 RM0029 decimation filter doc id 15177 rev 8 1219/1740 table 665. decfilter_iob register field descriptions field description 0?7 reserved, should be cleared. 8 m_flush master block flush request/control bit. assertion of the m_flush bit initializes the decimation filter to a initial state, as defined in section 26.5.9, flush command description . the sample or timestamp data written with a flush request in the same iob register write is processed normally after the flush. 1 flush request 0 no flush request 9?10 m_ctrl[1:0] decimation filter mode control bits. table 666 describes the m_ctrl[1:0] field functions. this field is used for control of the decimation filter. 11 reserved, should be cleared. 12?15 inp_tag[3:0] decimation filter input tag bits. the inp_tag[3:0] field indicates the destination associated with the inpbuff[15:0] sample. this value is stored by the decimation filter and used to address the destination register when a decimated sample is available to be read by the master block. since several input data samples can be received before a decimated result is generated, the inp_tag[3:0] used for the decimated sample corresponds to the latest inp_tag[3:0] received. therefore it is expected that the tag fi eld be constant during the decimation process. 12?15 out_tag[3:0] decimation filter output tag bits. the out_tag[3:0] bit field is used to address the appropriate destination register in the master block for the accompanying outbuf[15:0] data. when this value is updated, it is a copy of the inp_tag[3:0] value that was received with the last processed input data. when an eqadc is the psi master block, this is used to address the appropriate rfifo in the eqadc block. table 666. m_ctrl[1:0] ? decimation filter control functions m_ctrl[1:0] description 00 prefill ? a prefill indicates to the decimation filter to accept inp_buff[15:0] as valid data but no decimated samples are generated out of these master samples. the prefill function is used to initialize and stabilize the decimation filter without generating decimated samples. 01 conversion result ? a conversion result indicates that the inp_buff[15:0] field is data to be treated as valid sample data and it is considered for decimation counting and output buffer update. 10 timestamp ? a timestamp indicates that the inp_buff[15:0] field has data that bypasses the flow in the decimation filter logic, returning back to the master block without any modification when: ? the previous accompanying data is not for prefill, and ? when the previous accompanying input data is generating decimated filter output. also, bit m_flush is always 0 for timestamp data type. 11 reserved decimation filter RM0029 1220/1740 doc id 15177 rev 8 26.5 functional description 26.5.1 overview figure 671 shows the block diagram of the decimation filter. the control logic provides the control signals for all other sub-modules. the psi data interface is subdivided into two sub- modules, transmitter and receiver, that are accessed by the psi slave-bus interface. the bypass path is used when the filter is disabled and the incoming data can be transmitted back to the master block without being processed by the filter algorithm. the filter hardware is implemented in such a way that an iir (1 x 4 poles) or fir filter type can be implemented. the selection between the two types of filter algorithms is implemented by the control logic sub-block. the coefficient register file provides the digital filter coefficients. this block is a register bank with read/write access by the device slave-bus interface. the filter tap registers are also accessed through the device slave-bus line interface, providing additional debug capabilities to the decimation filter block. the mac (multiply accumulate) sub-block executes the filter arithmetic operations controlled by the control logic. the mac results are routed to the filter tap registers and to the output buffer when the result is a decimated filter sample. 26.5.2 parallel side inte rface (psi) description this section describes the operation of the parallel side interface (psi) sub-block which is responsible for communication and data exchange between the master block (for instance, the eqadc block) and the decimation filter block. the decimation filter receives sample data from the master block. the input data bus format is presented in figure 685 . the sample data arrives along with the control bits. these control bits are decoded and the proper action is decided in the control logic sub-block. when the decimation filter finishes its processing and a result is available, the read request signal is issued to the master block. this data transfer request remains set until the result is read by the master block. when using two or more decimation filter blocks in the device, the output of the second block is connected to the input data of the next block, and the output of the first block is connected to the read data input of the psi master block. 16?31 inp_buff[15:0] input buffer data. the inp_buff[15:0] bit field is the data input from the master block. the input register can be written with this data when isel = 0. this data can be timestamp information that is not processed by the filter, or sample data that is processed by the digital filter. in this case, the information is a signed signal in two?s complement format. 16?31 out_buff[15:0] output buffer data. the out_buff[15:0] bit field corresponds to the data result of the decimation filter that has been processed to the master block. this data can be timestamp information or a digital filter result. in this case, the information is a signed signal in two?s complement format. table 665. decfilter_iob register field descriptions (continued) field description RM0029 decimation filter doc id 15177 rev 8 1221/1740 26.5.3 input buffer description the decimation filter receives data samples for filtering from a master block (e.g., eqadc) using the psi interface, or from the cpu using the device slave-bus interface. the data source is selected by the isel bit of the module configuration register decfilter_mcr. when the device slave-bus interface is selected and dma operation is chosen (decfilter_mcr bit dsel = 1), the input data request signal is asserted when the input buffer is empty. when dma operation is not chosen (dsel = 0) in standalone or psi output mixed modes, the logic asserts an input interrupt request and the input buffer waits for data from the device slave-bus. input buffer filling is flagged by the decfilter_msr bit idf. the idf flag remains set, even after the input data has been consumed and the buffer is free, until it is cleared by software. input buffer overrun is detected and flagged by the decfilter_msr bit ivr. the idle (bsy = 0) decimation filter is able to receive two consecutive input writes without input overrun. for more details, see section , input buffer overrun . when the selected input source is the psi master block, the psi master may send timestamp data after related sample data for filtering. the timestamp is sent back to the psi following the respective filter output, using the same request mechanism. as the decimation filter takes several clock cycles to process a sample, the timestamp is copied into an internal timestamp register until the filtered output is sent out, therefore freeing the input buffer for yet another sample data. when the input buffer is loaded with a sample data coming from the psi interface and enhanced debug monitor enabled is enabled (decfilter_mcr bits isel = 0, edme = 1), input dma or interrupt requests are asserted, so that the psi input samples can be monitored from the device slave-bus interface. these interrupt or dma requests result in input read accesses from the decfilter_ib register, unlike write accesses needed when the same requests are made and the device slave-bus interface is selected for input (isel = 1). only the sample data input (not timestamps), can be monitored in this way. see also section 26.5.14, enhanced debug monitor description . soft reset clears the input buffer indication flags and any data write/read request that was generated in any mode. input buffer overrun an input overrun occurs when the input buffer is holding input data and new data is received by the filter. see section 26.5.3, input buffer description , for details of the input buffer. the input buffer overrun can occur only when the input is enabled (decfilter_mcr bit idis = 0), and in the following cases: when the input buffer has sample data to be processed but the filter is busy and another input (data or timestamp) is received. when the input buffer has a timestamp, the internal timestamp register is loaded and the next input data is received. as an example of the input data sequence, assume that the filter is enabled and not busy, and all registers are empty. then a word of sample data is received followed by a timestamp and another word of sample data. no input overrun occurs in this case, because the first sample is immediately transferred to the tap input register, the timestamp is immediately transferred to the internal timestamp storage register, and the second sample can be held in decimation filter RM0029 1222/1740 doc id 15177 rev 8 the input buffer until the end of the processing of the sample data by the filter. the input overrun may occur if more input is received before the end of the processing, or if the filter is busy at the beginning of the received sequence. when the filter is in bypass/disable mode (decfilter_mcr field ftype = 00), the data from the input buffer is transferred to the output buffer, if it is not already full. if the output buffer is full, the input buffer is loaded, and another word of input data is sent, then an input overrun occurs. note: configuring isel = 1, mixm = 1 and ftype = 00 (bypass), writes to the decfilter_ib are routed directly to the psi output. 26.5.4 output buffer description the decimation filter has an output buffer to send filtering results to a master block using the psi, or to the cpu using the device slave-bus, as selected through the decfilter_mcr bits isel and mixm bits. filtering of prefill inputs do not update the output buffer, so the flag odf is not set. when filter types iir and fir are selected and the input source is the psi master block (normal or psi input mixed modes), the output buffer receives data from the mac sub-block or from the timestamp storage register. the result from the mac is written immediately after the processing if the decimation is enabled. however, the timestamp data is enabled to be written in the output buffer only when the output buffer is empty, the decimation count is reached, and the corresponding data was also ready to be transmitted. when a new word of data is available in the output buffer, a read request signal is sent to the master block. the master block has to send the corresponding read commands to clear the read request signal. in this configuration, the core can always read the output buffer. the flag odf is set when the buffer is updated. when in filter operation mode with input from the device slave-bus (isel = 1), only sample data is processed by the filter, as there is no way to input timestamps. when the filter result from the mac is ready, this is immediately written to the output buffer when the decimation count is reached. the flag odf is set when the buffer is updated. it also generates a dma read request if dsel = 1 in standalone or psi input mixed modes. when the filter is bypassed (ftype = 00), and psi is selected as output (normal mode or psi output mixed mode), the data written into the input buffer waits until the output buffer is empty before passing the data. this is needed because the master block takes some clock cycles to send the read commands to the decimation filter after the read request signal is asserted. when the filter is bypassed and the device slave-bus is selected as output (standalone mode or psi input mixed mode), the data written into the input buffer is immediately written into the output buffer. the flag odf is set when the buffer is updated and a dma read request is asserted if dsel = 1. soft reset clears the output buffer, as well as any data read request generated in any mode. output buffer overrun an output overrun occurs when the output buffer is holding output data (sample or timestamp) that has not been read is overwritten with another word of data (sample or timestamp). RM0029 decimation filter doc id 15177 rev 8 1223/1740 output overruns are flagged by the decfilter_msr bit ovr, if the output buffer is updated when not empty. the output buffer empty condition depends on the mode and output selection as follows: if psi is selected as output (normal mode or psi output mixed mode), the output buffer is considered empty when the last output has been read. if cascade mode is selected, the output buffer is considered empty if the last output request was acknowledged. if the device slave-bus is selected (standalone or psi input mixed mode) for output and dma is selected (dsel = 1), the output buffer is considered empty if the last output has been read. if the device slave-bus is selected (standalone or psi input mixed mode) for output and dma is not selected (dsel = 0), the output buffer is considered empty when the odf flag is negated. note: when the device slave-bus is selected (standalone or psi input mixed mode) for output and dma is not selected (dsel = 0), the odf flag must be cleared to avoid overrun, even if its corresponding interrupt is not used (oden = 0). prefill inputs do not cause iir or fir output overrun in standalone, normal, and cascade tail modes, but can cause overruns in cascade head or middle configurations (see section , cascade mode ). when bypass is selected, the output overrun does not occur because the data written into the input buffer is written into the output buffer only when this buffer is empty, but an input overrun may still occur (see section , input buffer overrun ). triggered output result description the posting of a filter output, either to the psi interface or to the device slave-bus can be controlled by an additional input trigger signal (see section 26.3.1, decimation trigger signal ). it allows the decimation to be controlled by another circuit, instead of the internal decimation counter. triggered output operation is enabled by the bit tore in the configuration register decfilter_mcr. when triggered output is enabled, the decimation count configured by decfilter_mcr field dec_counter is ignored. the decimation filter detects the rising edge or the falling edge of the trigger signal as selected by the configuration field tmode in the decfilter_mcr. when the corresponding edge is detected, the output buffer is enabled to receive the next filter result. the input trigger signal can also be used as a simple filtered output enable: in this trigger mode, when the input trigger signal is asserted, every filtered output is posted to the output buffer; no output is posted when the signal is negated. this trigger mode and the assertion polarity (active 0 or 1) of the input trigger signal is also defined in the decfilter_mcr field tmode. 26.5.5 bypass configuration description bypass operation is configured by setting the field ftype[1:0] of module configuration register decfilter_mcr to 00. in this case, the input sample and tag are sent to the decimation filter RM0029 1224/1740 doc id 15177 rev 8 output with no change. this behavior is independent of the isel/mixm setting. the following applies to the bypass configuration: flush is ignored prefill is ignored trigger or counted decimation is ignored bsy bit is not set the input and output flags are set note: bypass must not be configured in cascade mode (see section 26.5.16, cascade mode description ). 26.5.6 iir and fir filter this section describes the iir filters implemented in the decimation filter block. figure 686 shows the filters functional diagrams. the figure shows a iir filter of fourth order (4 poles). the filter topology, not the hardware, is represented. the hardware implementation is based on a mac unit controlled by an fsm which implements the filter algorithm. figure 686. 1 x 4 poles iir filter functional diagram the difference equation for the iir filter of figure 686 can be written as: equation 17 y(n) z -1 z -1 z -1 z -1 + + + + b 0 z -1 z -1 z -1 z -1 + + + + x(n) a 4 a 3 a 2 a 1 b 4 b 3 b 2 b 1 x(n-1) y(n-1) x(n-2) x(n-3) x(n-4) y(n-2) y(n-3) y(n-4) yn () b i xn i ? () a j yn j ? () j1 = m ? + i0 = n ? = RM0029 decimation filter doc id 15177 rev 8 1225/1740 where x(n) is the filter input at time n, y(n) is the filter output at time n , n is the number of feed-forward filter coefficients minus one, b i are the feed-forward filter coefficients, m is the number of feed-back filter coefficients, and a j are the feedback filter coefficients. equation 17 can be written as: equation 18 equation 19 where all the coefficients are scaled down by s. the block diagram for equation 18 and equation 19 is shown in figure 687 in a fourth-order iir filter implementation where the coefficients a j and b i are called coefficient n , where n = 0-8. figure 687. fourth order iir filter implementation block diagram the fourth order iir filter is implemented with a fir section followed by an iir section. if the fir type filter mode is selected, the iir section is converted into an fir section. in this case the order of the fir filter is twice the iir filter order, since all the tap and coefficient wn () b i s ---- - xn i ? () i0 = n ? = yn () swn () a j s ---- - yn j ? () j1 = m ? + ?? ?? ?? ?? ?? = z -1 z -1 z -1 z -1 + coefficient 2 tap 1 coefficient 4 coefficient 3 tap 2 tap 3 tap 0 coefficient 0 coefficient 1 n) + coefficient 6 tap 5 coefficient 8 coefficient 7 tap6 tap 7 tap 4 scale factor s coefficient 5 y fir section iir section z -1 z -1 z -1 z -1 decimation filter RM0029 1226/1740 doc id 15177 rev 8 registers are allocated for the fir section. the filter configuration paths are shown in figure 688 . multiplexer a controls the bypass filter path and multiplexer b controls/selects the filter mode of operation, to either iir mode or fir mode. the selection is controlled by the ftype[1:0] bits in the filter module configuration register. the order of the filter can be controlled by setting the appropriate filter coefficients to zero. figure 688. filter configuration paths (fir or 1x4 poles iir) rounding the decimation filter performs rounding operations in two different locations, as shown in figure 688 : to obtain the filter output result with 16 bits to obtain the iir feedback result to be stored in tap4 registers with 24 bits the rounding mechanism implements the convergent rounding methodology (also known as round-to-nearest even number), which makes the decision on rounding up or down based on the value of the lower portion of data to be rounded (ls_word). the rounding up/down condition is equal to the traditional rounding except when the ls_word has the format {1000...00}. in this particular case, the rounding procedure is like the example of figure 689 . if the ms_word is odd, the value is rounded up. otherwise the value is rounded down. by- fi z -1 z -1 z -1 z -1 + coefficient 2 ta p1 coefficient 4 coefficient 3 ta p2 ta p3 ta p0 coefficient 1 x(n) + coefficient 6 tap 5 coefficient 8 coefficient 7 tap6 tap 7 tap 4 coefficient 5 y(n) 01 10 b z -1 z -1 z -1 z -1 round/sat ftype[1:0] round/sat iir 00 a scale factor s register coefficient 0 fir section iir section RM0029 decimation filter doc id 15177 rev 8 1227/1740 figure 689. convergent rounding methodology saturation filter output saturation occurs when an overflow or underflow condition of the filter is detected by dedicated logic, and if it is enabled by the sat control bit of the configuration register decfilter_mcr. in this condition, the filter output is set to a saturated value equal to the maximum or minimum value that can be represented by the 16-bit output port. also, for the iir filter an equivalent logic is used to assert the saturation for the 24-bit feedback result. 26.5.7 filter prefill control description a prefill indicates that the input data should be accepted by the decimation filter, but no decimated output should be generated while the control field indicates prefill. therefore the prefill function is used in the beginning of the filter operation to initialize and stabilize the decimation filter without generating decimated samples. in addition, the prefill does not operate when the filter is in bypass (ftype = 0b00). the prefill is controlled by the value in the m_ctrl[1:0] field in the decfilter_iob register. when isel = 0, the m_ctrl[1:0] field in the decfilter_iob register controls the prefill. when isel = 1, it is controlled by the prefill field in the decfilter_ib register. the prefill control is usually activated only in a certain number of words of sample data in the beginning of the input data sequence. when the prefill control is set, the decimation filter block operates as follows: input data is processed normally by the digital filter and tap values are updated. the decimation counter is maintained in reset value. the output buffer is not updated and no output interrupt or read request is generated. the accompanying timestamp for the identified prefill conversion data is not bypassed. the overflow detector/flag operates normally and the error interrupt request is set if enabled. in cascade mode, prefill control is ignored in all cascaded filters except the tail one: the prefill samples are filtered, decimated and forwarded to the next block with the prefill xx.......xx.......0010 1 xx.......xx.......00100 xx...xx 1000.....00......00 before rounding xx.......xx.......00100 xx...xx rounded down ms_word ls_word +0 xx...xx 1000.....00......00 before rounding xx.......xx.......00110 xx...xx rounded up +1 decimation filter RM0029 1228/1740 doc id 15177 rev 8 indication. the tail block takes the samples with prefill indication, filter them and discard the result. note: the combined decimation count of the cascade combo may not be reset after the last prefill sample. unlike in a single (non-cascaded) filter, the number of non-prefill inputs until an output comes out depends on the number of past prefill inputs. 26.5.8 timestamp data transmission the timestamp information is identified by the master block using the m_ctrl[1:0] bit field of the register decfilter_iob. for timestamp data, the input data and tag values that come with m_ctrl[1:0] bits set to 0b10 are sent back to the master block without changing. however, some additional conditions are considered: the timestamp is additional information that accompanies a sample conversion data. the psi master block sends the decimation filter the conversion data with control bits for either prefill or filter operation. this data may optionally be followed by the corresponding timestamp data. when the corresponding conversion data is marked for prefill, the timestamp data is not sent to the output buffer. this occurs because the filter result is not sent to the output buffer. similarly, when the filter is decimating the results, the timestamp is only sent to the output buffer if the corresponding received conversion data has generated a filter output that is selected by the decimation counter to be sent to the output buffer. other received timestamps that come with data not selected by the decimator are discarded. sending two consecutive words of timestamp data is not allowed: there must be at least one conversion data between two timestamp inputs. in normal operation, the filter should receive only one timestamp for each word of conversion data to be filtered. timestamps are not allowed in psi input mixed mode. 26.5.9 flush command description the flush signal is used by the decimation filter to execute a partial reset of the filter. this is useful when the same filter is used on a new set of data samples after finishing the filtering of another set of data. when the flush control is detected, all filter taps are cleared and the dec_counter[3:0] field in the status register decfilter_msr is reset. the flush function does not clear the coefficient registers file in the decimation filter, thus it is not required to re-write these registers after a flush. the integrator accumulator and sample count are not cleared either. the output buffer also keeps the last result and may be retrieved until the next output is posted. the flush control precedes the input data to be filtered. therefore, the corresponding sample data is processed by the block after the flush. when isel = 0, the field m_flush in the decfilter_iob register is processed. when isel = 1, the field flush in the decfilter_ib register is processed. note that a word of valid sample data can be available at the same time the flush signal is asserted. in this case the flush is executed and the sample is processed after the flush. when isel = 0, flush bit m_flush must not be asserted when the input data is a timestamp (m_ctrl = 10). when the filter is disabled by the ftype[1:0] control bit field, the flush command is not executed. RM0029 decimation filter doc id 15177 rev 8 1229/1740 note: in cascade mode, the flush command is forwarded to the next cascaded block together with the output, after the decimation count. therefore it is possible that, in a given moment, the taps of a cascaded block are zeroed after a flush input, while the following ones still retain the old values. 26.5.10 soft-reset command description the soft-reset command is requested through the self-negated bit sres of the decfilter_mcr register and provides the cpu with the capability to initialize the decimation filter through the slave-bus interface. the procedure below must be performed for a software reset when the filter is active: 1. disable filter inputs, writing decfil_mcr bit idis = 1. 2. poll the register decfil_msr until the bit bsy is 0. 3. repeat the step 2 polling; this is necessary to cover the case when a sample is left in the input buffer. 4. write decfilter_mcr bit sres = 1. after the software reset is issued, all internal filter tap registers, the decimation counter, the integrator outputs (except decfilter_cintcnt) and the state machine are put in the initial state. the status register decfilter_msr is also cleared. the coefficient registers are not affected by the sres. in case there is some filter processing, the filter process is aborted and the last sample is discarded. in addition, data in the input buffer waiting to be processed, and data in the output buffer waiting to be read, are discarded (the requests of service are cleared). the software reset command has high priority and the bsy bit is set during its operation. the configuration registers decfilter_mxcr and decfilter_mcr are also not affected by a soft reset, except the bit sres that is self-negated and is always read as zero. when in debug or freeze mode, the soft reset is executed but the filter remains in debug or freeze mode. note: it is recommended to clear the ibie bit before a software reset, especially if isel changes, in order to avoid unwanted interrupt requests. note: dma transfers must not be active during soft reset. data loss can occur. 26.5.11 interrupts requests description block interrupt request there are several interrupt request events that can be enabled using the module configuration register decfilter_mcr. basically, the interrupt request can be issued under any of the following conditions: when a word of input data is received when a word of output data is available when an error has occurred. the input data flag idf is set when a word of data is received from the cpu when in standalone mode, or when a word of data is received in the psi when it is not in standalone mode (normal mode). it is not used to generate the read or write requests (as defined in section , input buffer interrupt request ) when dsel = 0. decimation filter RM0029 1230/1740 doc id 15177 rev 8 output data is available and its flag (odf) is set when the input data sample is processed by the filter and the decimation counter matches the decimation rate value. it is not used to generate the read requests (as defined in section , output buffer interrupt request ) when dsel = 0. an error event in the decimation filter block is defined as one of these events: overflow in the filter, flagged by ovf overrun in the decimation filter input, flagged by ivr overrun in the decimation filter output, flagged by ovr overrun in enhanced debug monitor, flagged by divr integrator overrun, flagged by svr integrator value exception, flagged by sse integrator count exception, flagged by sce an overflow occurs when the two?s-complement result value from the mac accumulator is out of the range of values that can be stored in tap register 4 (iir) or in the output register. an input overrun occurs when the input buffer is holding a word of input data and one more word of data is received by the filter. see section , input buffer overrun , for more details. an output overrun occurs when a new word of data is sent to the output buffer but the previous word of data has not been handled yet. see section , output buffer overrun , for more details. these flags can be set by the psi events, however they are only cleared by the cpu, or by the soft reset command in the decfilter_mcr, or by the clear flag fields in the decfilter_msr. input buffer interrupt request this interrupt is enabled by the register ibie in the decfilter_mcr and is asserted only when dsel = 0. this request is flagged in the decfilter_msr by field ibif. in standalone and psi output mixed modes, the input buffer interrupt request is asserted when the input buffer is available to receive a conversion sample and dma operation is not selected (dsel = 0), meaning the block is requesting data to be written into the input buffer. the interrupt request is cleared when the cpu writes a one in field ibic of the decfilter_msr, or by the soft reset command. when in normal, cascade or psi input mixed modes with enhanced debug enabled (isel = 0 and edme = 1, dsel = 0), the input sample data can be read by the cpu when this interrupt request is asserted. the interrupt is asserted just when a new word of sample data is supplied to the filter sub-block to be processed. as this filter register is overwritten by the next word of sample data, an input read overrun event can occur (the divr bit in decfilter_msr is asserted) if the interrupt request is not cleared before, or at the same time as, the new sample arrives to set the interrupt. this divr bit is cleared by the divrc bit in the status register decfilter_msr. however, in enhanced debug monitoring, the set condition has higher priority than the clear. this means that if the set condition and the clear bit ibic occur at the same time, the interrupt remains asserted. RM0029 decimation filter doc id 15177 rev 8 1231/1740 output buffer interrupt request this interrupt is enabled by the register obie in the decfilter_mcr and is asserted only when dsel = 0. this request is also indicated in the field obif of the decfilter_msr. when in standalone mode, the output buffer can be read by the cpu with the dma disabled. the output buffer interrupt request is asserted when the output buffer receives a new result from the filter sub-block. this means the block is requesting data to be read by the cpu. the output buffer interrupt request can also be asserted due to an integrator result being ready, as flagged by the decfilter_mxsr bit sdf, when the decfilter_mcr bit sdie = 1. note that both the filter output and integrator share the same interrupt source. this interrupt request is cleared when a one is written in the bit obic and/or bit sdfc of the decfilter_mxsr, or by the soft reset command. 26.5.12 dma requests description the dma function for integrator result, input and output buffers is enabled using dsel = 1 in the decfilter_mcr. input buffer dma request this dma request is enabled by the isel and dsel bits in the decfilter_mcr. when in standalone mode, the input buffer can be written by the dma. the input buffer dma request is asserted when the input buffer is available to receive a conversion sample (it is not holding a word of data). this dma request is cleared when an input data word is written in the input buffer. therefore, the dma request is always cleared before it is asserted again. when in normal mode with enhanced debug enabled (isel = 0 and edme = 1, dsel = 1), the input sample data can be read by the dma when this dma request is asserted. the request is asserted when a new word of sample data is written into the input buffer to be processed. as this filter register is overwritten by the next word of sample data, a dma read overrun event can occur (the divr bit in decfilter_msr is asserted) if the dma request is not cleared before, or at the same time as, a new sample arrives to set the dma request. this divr bit is cleared by the divrc bit in the status register decfilter_msr or by soft reset. this dma request is cleared when the dma transfer is complete or by soft reset. output buffer dma request this dma request is enabled by the isel, mixm and dsel bits in the decfilter_mcr. when in standalone mode, the output buffer can be read using the dma. the output buffer dma request is asserted when the output buffer receives a new result from the internal filter sub-block. this dma request is cleared when the output buffer is read by the processor. the output buffer dma request is also asserted when an integrator output is ready, if decfilter_mxcr bit sdmae = 1 and the filter output is directed to the psi interface (isel = mixm). the dma request is also cleared by soft reset. decimation filter RM0029 1232/1740 doc id 15177 rev 8 26.5.13 freeze mode description the freeze mode operation is asserted using the fren enable bit and frz bit in the decfilter_mcr or by the modules debug input. it is not possible to enter freeze mode when the module is disabled by the configuration bit mdis. in case of a freeze mode request during the processing of an input sample, the current processing is finished and then the module enters freeze mode. access to input and output buffers remain operational in freeze, as well as their related flags. note: for cascaded blocks (see section 26.5.16, cascade mode description ), it is recommended to freeze only the head block. if it is really necessary to freeze all the blocks, it is recommended that they are frozen sequentially starting from the head block towards the tail one. unfreezing is recommended to be done sequentially from the tail block towards the head one. 26.5.14 enhanced debug monitor description this feature is enabled by the edme bit in the configuration register decfilter_mcr. the monitoring operation works either in normal or cascade modes, when the sample data is supplied by a master block through the psi slave-bus interface (isel = 0) or another cascaded block (see section 26.5.16, cascade mode description ). the enhanced debug monitor feature makes the input sample data also available in the decfilter_edid register. a dma or interrupt request (selected by dsel) indicates a new input was fed and decfilter_edid was updated. the input is processed normally by the filter. an enhanced debug input data register (decfilter_edid) overrun can occur if a sample is not read by the cpu or dma before overwritten by a new sample. the overrun is indicated in a separate flag divr in the status register decfilter_msr. if the erren bit is set in the decfilter_mcr configuration register, this overrun asserts the module interrupt request. 26.5.15 integrator the hardware sample integrator accumulates the filter output values for determined periods. integrator inputs the integrator can be fed either by raw or decimated filter outputs, selected by the decfilter_mxcr bit sisel (see section , decimation filter module extended configuration register (decfilter_mxcr) ). the accumulated input value taken can be the filtered sample ?as is? (signaled), or its absolute value, depending on the decfilter_mxcr bit ssig. note: t he integrator accumulates input samples when bypass is selected. integrator outputs the integrator output is either: the 32-bit, fixed point unsigned accumulation of the absolute values from the filter output, when the integrator is configured for absolute operation (decfilter_mxcr RM0029 decimation filter doc id 15177 rev 8 1233/1740 bit ssig = 0). this resolution allows a minimum of 131071 samples to be integrated before an overflow occurs in absolute operation, or 65536 samples in signed operation. the 32-bit, fixed point signed two?s complement accumulation of the signed values from the filter output, when the integrator is configured for signed operation (ssig = 1). the fractional part of the accumulation is 15 bits wide in both cases. an accumulation overflow is flagged by the decfilter_mxsr bit ssovf. the accumulator can overflow in either of the ways below, selected through the decfilter_mxcr bit ssat: saturated accumulation (ssat = 1), so that an overflow results in the value of 0xffffffff for absolute value accumulation (ssig = 0), or 0x7fffffff (positive) and 0x80000000 (negative) for signaled accumulation (ssig = 1). non-saturated accumulation (ssat = 0), so that an overflow results in the modulo 2 17 accumulation value. this operation is only allowed in absolute accumulation (ssig = 0). the integrator output value becomes available in register decfilter_fintval (see section , decimation filter final integration value register (decfilter_fintval) ) when an integrator output request is issued. the integrator output request can be issued in the following ways: by hardware, controlled by an external signal; the enabling and the selection of the signal request modes is done through the decfilter_mxcr field srqsel (see section , decimation filter module extended configuration register (decfilter_mxcr) ); by software, writing 1 to the decfilter_mxcr bit srq; the ssovf flag is asserted upon an integrator output request, based on the overflow state of the internal accumulator. this internal overflow state is cleared upon an output request, just after ssovf is asserted, or upon an integrator reset (see section , integrator reset ). the internal overflow state is also cleared by writing ssovfc to 1, but only in saturated accumulation. therefore, a non-saturated overflow that occurs before an ssovf clear is still flagged in the next output request. the integrator output request also updates the register decfilter_fintcnt, which holds the number of samples accumulated into the register decfilter_fintval. this internal accumulated sample counter can operate either in a saturated or ?wrapped? count mode, as selected by the decfilter_mxcr bit scsat. in both cases, the counter overflow is flagged by the decfilter_mxsr bit scovf. the scovf flag is asserted upon an integrator output request, based on the overflow state of the internal counter. this internal overflow state is negated upon an output request, just after scovf is asserted, or upon an integrator reset (see section , integrator reset ). the internal overflow state is also negated by writing scovfc to 1, but only in saturated count. therefore, a non-saturated overflow that occurs before an scovf clear is still flagged in the next output request. an integrator output update can also issue a dma or interrupt request. the interrupt and dma requests are the same ones used for the filter output buffer (see section , output buffer interrupt request and section , output buffer dma request ). the decfilter_mcr bit sdie is used to enable integrator interrupts, and the decfilter_mxcr bit sdmae enables the dma integrator requests. the integrator dma request uses the same signal as the filter output dma request, so one must never use any configuration that allows both the integrator and filter output to make dma requests. decimation filter RM0029 1234/1740 doc id 15177 rev 8 integrator output updates are flagged by the decfilter_mxsr bit sdf. the integrator overrun is detected in the same way as a filter output buffer overrun, and is flagged by decfilter_mxsr bit svr. an integrator overrun also generates an error interrupt if the decfilter_mcr bit erren = 1 (see section , output buffer overrun ). registers decfilter_cintval and decfilter_cintcnt provide a way to poll intermediate integration values and sample counts, respectively (see section , decimation filter current integration value register (decfilter_cintval) and section , decimation filter current integration count value register (decfilter_cintcnt) ). decfilter_cintval is updated whenever the integrator is reset or a new sample is accumulated. decfilter_cintcnt is updated only when decfilter_cintval is read, so that coherency between the value and count values is guaranteed. therefore, the read access order of that pair of registers must be decfilter_cintval first, followed by decfilter_cintcnt. note: the flags ssovf and scovf can also asserted when decfilter_cintval is read. the ssovf and scovf set and clearing rules apply for the decfilter_cintval read the same way as for an integrator output request. integrator reset the integration value is reset to the value of zero, in the following ways: by hardware: on hardware reset, or controlled by an external signal; the enabling and the selection of the zero signal modes is done through the decfilter_mxcr field szrosel (see section , decimation filter module extended configuration register (decfilter_mxcr) ); by software: on software reset, or writing 1 to the decfilter_mxcr bit szro; the integrator reset also zeroes the internal counter of accumulated samples and the internal overflow state (but not ssovf and scovf). software and hardware reset resets all integrator registers immediately. integrator zero command from external signal or by software (szro) affects the integrator registers and flags as follows: decfilter_cintval resets immediately; decfilter_cintcnt does not reset immediately; it is updated only upon a decfilter_cintval read, loaded with the number of integrated samples occurred after the reset; decfilter_fintval and decfilter_fintcnt do not reset immediately; being updated only upon a new output request (see section , integrator outputs ); if a integrator software zero command (through szro bit) and an integrator output request (through srq bit) are made at the same time, the registers decfilter_fintval and decfilter_fintcnt are updated with the last internal values before reset; the same applies to simultaneous integrator zero command and output request by hardware signal; the ssovf and scovf flags do not negate; however, the internal overflow states which assert ssovf and scovf do reset immediately, so that the next output update (either by hardware request, software request or decfilter_cintval read) before an overflow does not assert ssovf/scovf. note: the integrator reset does not depend on the integrator enabling (see section , integrator enabling and halting ). RM0029 decimation filter doc id 15177 rev 8 1235/1740 integrator enabling and halting two mechanisms, enabling and halting, drive the integrator accumulation, allowing it to be controlled by a combination of two distinct sources, both software, both hardware, or one hardware and other software. values are accumulated when the integrator is enabled and not halted. the integrator halt and enable states can be controlled in the following ways: by hardware, through external signals; the enabling and the selection of the signal request modes is done through the decfilter_mxcr fields sensel and shltsel, respectively (see section , decimation filter module extended configuration register (decfilter_mxcr) ); by software, through the same decfilter_mxcr fields sensel and shltsel. note that these fields are in different bytes, so that two distinct, concurrent software tasks can avoid coherency problems by changing the fields using byte read-modify- write accesses. note: enabling and halting does not affect output requests or integrator reset. integrator exceptions integrator may run into exception states due to overflow, either of the accumulated value or the sample counter. exceptions are flagged by the decfilter_mxsr bits sse, for sum value exception, and sce, for counter exception. these flags generate an error interrupt, if it is enabled (see section , block interrupt request ). the accumulator exception condition depends on whether it operates in saturated mode or not, as follows: in saturated operation (decfilter_mxcr bit ssat = 1): a sum exception occurs (sse = 1) whenever an overflow is flagged; sse asserts together with ssovf. in non-saturated operation (decfilter_mxcr bit ssat = 0): a sum exception occurs (sse = 1) when an overflow is flagged and the decfilter_mxsr bit ssovf is already set to 1. in non-saturated operation, an accumulator exception also occurs if the accumulator overflows twice without any update of the final integrator value decfilter_fintval or the current integrator counter decfilter_cintcnt (by a read to the decfilter_cintval register), neither an integrator reset occurs. the ssovf flag does not assert in this situation. note: the ssovf flag can only be asserted upon a hardware request, a software request, or when decfilter_cintval is read, based on the internal accumulator overflow state. similarly, the sample counter exception condition depends on whether it operates in saturated mode or not, as follows: in saturated operation (decfilter_mxcr bit scsat = 1): a counter exception occurs (sce = 1) whenever an overflow is flagged; sce asserts together with scovf. in non-saturated operation (decfilter_mxcr bit scsat = 0): a counter exception occurs (sce = 1) when an overflow is flagged and the decfilter_mxsr bit scovf is already set to 1. in non-saturated operation, a counter exception also occurs if the counter overflows twice without any update of the final count decfilter_fintcnt or the current integrator counter decfilter_cintcnt (by a read to the decfilter_cintval register), neither an integration reset occurs. the scovf flag does not assert in this situation. decimation filter RM0029 1236/1740 doc id 15177 rev 8 note: the scovf flag can only be asserted upon a hardware request, a software request, or when decfilter_cintval is read (also updating decfilter_cintcnt), based on the internal counter overflow state. 26.5.16 cascade mode description the cascade mode is defined as a configuration mode of the decimation filter to work together with other ones in a chain arrangement. all blocks in the arrangement, hereafter called a cascade combo , are configured to operate in cascade mode by the cascd[1:0] field in the decfilter_mcr. figure 690 shows an example of cascade combo: the figure shows psi being used for both data input and output, but cascade can also work in standalone or mixed modes. the leftmost block, named head. receives the raw data to be filtered from the psi master block (or from the device slave-bus interface in standalone/psi output modes). the head type is configured using cascd[1:0] = 01 in the configuration register decfilter_mcr. the rightmost block, named tail, is the last filter block in the chain. it sends the output result back to the psi master block (or to the device slave-bus interface in standalone/psi input modes). this type of cascaded block is configured using cascd[1:0] = 10. the blocks in between, named middle, do not exchange data (receive / transmit) with the psi master, only with other decimation filter blocks. this type of block is configured by setting cascd[1:0] = 11. middle blocks are optional in a cascaded combo: two blocks, one head block feeding a tail one, can be used in cascade. note: the values passed between cascaded blocks can be monitored using enhanced debug monitor (see section 26.5.14, enhanced debug monitor description ). each decimation filter block has one cascade-in and one cascade-out ports, besides the psi connections used in normal mode. the format of the cascade bus is described in section , cascade mode data/control bus description . the arrows show how they are physically connected. the bold arrows show the connections used in cascade mode. the block configurations as head, tail or middle must respect their physical connections such that all the following apply: ? a head block feeds a middle or tail one ? a middle block feeds another middle block or a tail one ? tail feeds no other block, and head is fed by no other block. as a consequence of the conditions above, there must be one and only one head block and one and only one tail block in a cascade combo. a group of physically chained blocks can form more than one cascade combo. for instance, figure 691 shows the same physical chain, but now with blocks 1 and 2 configured as head and tail, respectively, forming one combo. the remaining blocks form another combo starting with block 3 (head), and ending with block n (tail). note RM0029 decimation filter doc id 15177 rev 8 1237/1740 that the chain-in inputs of blocks from block 3 on are used to carry output data from the first cascaded combo (tail block 2) to the psi master block. blocks not used in a cascaded chain can be used normally, isolated (defilter_mcr field cascd[1:0] = 00), as exemplified in figure 692 . the optional connection show from block n to block 1 in figure 690 allows block n to be configured as head or middle, feeding block 1 configured as middle or tail, yielding more flexibility, as in the last example of figure 692 . figure 690. cascade mode chain structure the input to a cascaded configuration is selected by the decfilter_mcr bit isel of the head block. the output target of the cascaded blocks is selected by the decfilter_mcr bit isel of the tail block, with the same values used for input selection (isel = 0 for psi, isel = 1 for device slave-bus). decfilter_mcr bit mixm must be written 0 for all cascaded blocks. head psi master block cascade cascade (optional connections) psi bus ta i l psi bus middle psi bus middle psi bus in out in out in out in out data in data out out in cascade cascade out in cascade cascade out in cascade cascade out in chain in chain in chain in physical connection unused in cascade mode physical connection active in cascade mode (psi) 1 2 3n cascade ack in cascade ack in cascade ack in cascade ack out cascade ack out cascade ack out cascade ack in cascade ack out decimation filter RM0029 1238/1740 doc id 15177 rev 8 figure 691. multiple cascade mode chain structure head psi master block cascade cascade (optional connections) psi bus tail psi bus tail psi bus head psi bus in out in out in out in out data in data out out in cascade cascade out in cascade cascade out in cascade cascade out in chain in chain in chain in physical connection unused in cascade mode physical connection active in cascade mode (psi) 1 2 3n first cascade combo second cascade combo cascade ack in cascade ack in cascade ack in cascade ack out cascade ack out cascade ack out cascade ack in cascade ack out RM0029 decimation filter doc id 15177 rev 8 1239/1740 figure 692. examples of mixed cascaded and single blocks cascade freeze, stop, and configuration change procedures to change a block configuration mode to or from cascade mode, the following safe procedures must be observed: to modify a cascade combo, either to single or any other cascade combo combination, all the cascade combo blocks must have their inputs disabled (using decfilter_mcr bit idis), in order, from the head to the tail block. after a block idis bit has been set to 1 (one), one must wait for its decfilter_msr bit bsy to be 0 (zero) before disabling the input of the next block in the sequence. each block in a new cascade combo must be configured with its input disabled. when the mode configuration is done, the combo blocks must have their inputs enabled in order, from the tail towards the head block. a single block must also be reconfigured the same way, to or from a cascade combo configuration: first disabling its input, and then waiting for a non-busy state before writing decfilter_mcr field cascd. to take cascade combo blocks to or from freeze or low power modes, a similar procedure must be used: take the head to freeze or low-power first, wait for decfilter_msr bit bsy = 0, and repeat the procedure for the other blocks in the chain in sequence, towards the tail block. take the blocks out of freeze or low-power modes in the inverse sequence, from tail to head. single head middle ta i l single head ta i l single (arrows show just the physical cascading order) head ta i l head ta i l single single head tai l single head middle middle middle tai l single single tai l single head middle ta i l single head middle decimation filter RM0029 1240/1740 doc id 15177 rev 8 cascade mode data/control bus description a separate data bus is used to cascade the filters. the bus content is presented in figure 693 and the signals descriptions are present below. cascade middle and tail blocks do not make input feed requests, either on psi or slave-bus interfaces. similarly, cascade head and middle block do not make filtered (not integrator) output data requests, either on psi or slave-bus interfaces. figure 693. decimation filter cascade mode data bus 0123456789101112131415 dfcin/out_stop dfcin/out_req reserved dfcin/out_flush dfcin/out _ctrl[1:0] res. dfcin/out_tag[3:0] 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dfcin/out_data[15:0] table 667. decimation filter cascade mode data bus field description field description 0 dfcin/out_stop decimation filter cascade input/output stop flag the dfcin/out_stop bit indicates that a cascade bus driver block in a cascade configuration is stopped. when the block is configured as cascade middle or tail, it only stops when this bit is asserted. 1 dfcin/out_req decimation filter cascade request the dfcin/out_req bit indicates that a cascade bus driver block in a cascade configuration has data ready to be sent. the driven block responds to the request asserting its decfil_cascade_ack signal at the same time it copies the relevant cascade data bus fields. 8 dfcin/out_flush decimation filter cascade input/output flush control bit the dfcin/out_flush bit indicates to the receiver decimation filter block that it should execute a flush command ? thus some internal registers are placed in the initial state. 9-10 dfcin/out_ctrl [1:0] decimation filter cascade input/output control bits the dfcin/out_ctrl[1:0] field has the same function as the m_ctrl[1:0] control bits described in table 666 . this field defines the operation to be executed with the dfcin/out_data[15:0] data. 12-15 dfcin/out_tag [3:0] decimation filter cascade input/output tag bits the dfcin/out_tag[3:0] field indicates the destination associated with the dfcin/out_data[15:0] data. this value is stored by the decimation filter and used to address the destination register when a decimated sample is available to be read by the master block. dfcin/out_data [15:0] decimation filter cascade input/output data the dfcin/out_data[15:0] bit field carries the data to be transmitted in the chain of cascaded decimation filter blocks. RM0029 decimation filter doc id 15177 rev 8 1241/1740 cascaded blocks can be configured with different filter types (decfilter_mcr field ftype), including bypass. the ta ble 66 8 shows how decimation filter features work in each of the cascade mode configurations. 26.6 initialization information following are some simple initialization steps to be done before using the decimation filter block. these steps assume that the user has already calculated the filter coefficients using a filter design tool. 26.6.1 initialization procedure the sequence of steps for the block initialization is as follows: 1. program the configuration registers decfilter_mcr and decfilter_mxcr as desired for your application. 2. write all filter coefficient registers decfilter_coefn with the previously calculated values. 3. enable the filter input, writing decfilter_mcr bit idis = 0. 4. run a soft-reset cycle if necessary. 5. the module is ready to receive data from psi or from the device slave-bus interface. 26.7 application information 26.7.1 eqadc ip as the psi master block the system block diagram for the eqadc application is shown in figure 694 . in this case, the decimation filter receives conversion results generated by the eqadc block. these results can be generated from eight different adc setup configurations which are identified by a specific eqadc control address within a conversion command. conversion commands with register address set to zero use the standard configuration setup. the samples generated by the standard configuration setup are sent to one of the local eqadc rfifo buffers. the samples generated by the alternate configurations, with an address from 1?8, can be sent to the internal rfifo or to the eqadc dedicated slave-bus interface (parallel side interface psi) to communicate with the external decimation filter ip block or any other block that can communicate with this interface. a bit field in the alternate configuration control register selects the internal rfifo or this slave-bus interface as the table 668. features in cascade mode feature head middle tail prefill output and prefill command are forwarded to the next cascaded block effective flush effective, and forwarded to the next cascaded block effective decimation effective in each block timestamp forwarded to the next cascaded block effective enhanced debug effective in each block integrator effective in each block decimation filter RM0029 1242/1740 doc id 15177 rev 8 destination for the conversion result. the eqadc can send either conversion data or timestamp data. the conversion data is filtered by the decimation filter and the timestamp is bypassed and sent back to the eqadc. in the eqadc application, the tag field is used to address the appropriate rfifo in the eqadc block. in this case, only addresses 0?5 are used since there are only six rfifos available in the eqadc block. figure 694. decimation filter/eqadc interface 26.8 filter example simulation the decimation filter block operation was checked in a verilog simulation using calculated filter coefficient values and noisy input data. the expected output values and the rms error were then calculated. 26.8.1 coefficients calculation the coefficients were calculated using a digital filter design tool. we have supplied some hypothetical filter parameters to the tool and obtained the filter coefficients. the input parameters are: filter characteristics: elliptic/low pass filter type: 4th order iir input sample rate: 800k sample/s passband edge: 100 khz stopband edge: 150 khz passband attenuation: 1 db the software tool gives the iir filter coefficients in the z-transform format expressed by equation 20 : adc eqadc (analog) buffer cal fifo control psi (master) psi (slave) cfifo rfifo control coefficients filter decimation filter serial slave-bus RM0029 decimation filter doc id 15177 rev 8 1243/1740 equation 20 the coefficient results in fixed point decimal representation are shown in table 669 . comparing equation 19 with equation 20 , we obtain the relationship between the calculated values of coefficients and the values to be loaded in the decfilter_coefn registers. see ta ble 67 0 below to obtain the coefficients. a scale factor of eight is used, being the smallest divider factor to have all coefficient values in the range (?1 coef < +1). also note that the signal of the an coefficients has signals inverted. 26.8.2 input data calculation the 24-bit words of input data are samples of a sum of two tones: one tone of 30 khz and another tone of 250 khz. the samples were calculated at the rate of 800k samples per second. the tones have the same amplitude and it is assured that the resultant amplitude is smaller than 1 so as to obtain samples in the range (?1 sample < +1). it is supposed the ys () xs () ----------- - b 0 b 1 sb 2 s 2 b 3 s 3 b 4 s 4 ++ + + a 0 a 1 s ? a 2 s 2 ? a 3 s 3 ? a 4 s 4 ? ---------------------------------------------------------------------------------- - = table 669. coefficient values given by spw digital filter design tool coefficient decimal value coefficient decimal value b0 0.0221455 a0 1.0 b1 0.00445582948893748 a1 -2.69772868375858 b2 0.0318517846509088 a2 3.234056294853 b3 0.00445582948893748 a3 -1.92028561712454 b4 0.0221455 a4 0.47939080709495 table 670. coefficient values for decimation filter scale s = 1 s = 8 coefn decimal value decimal value hexadecimal values (24 bits) coef0 = b0/s 0.0221455 0.00276815891266 0x005ab5 coef1 = b1/s 0.00445582948893748 0.00055694580078 0x001240 coef2 = b2/s 0.0318517846509088 0.00398147106171 0x008277 coef3 = b3/s 0.00445582948893748 0.00055694580078 0x001240 coef4 = b4/s 0.0221455 0.00276815891266 0x005ab5 coef5 = ?a1/s 2.69772868375858 0.33721613883972 0x2b29e6 coef6 = ?a2/s ?3.234056294853 ?0.40425717830658 0xcc414e coef7 = ?a3/s 1.92028561712454 0.24003565311432 0x1eb97d coef8 = ?a4/s ?0.47939080709495 ?0.05992400646210 0xf8546a decimation filter RM0029 1244/1740 doc id 15177 rev 8 input data are signed values in the two?s complement format in the range (?1 sample < +1). 26.8.3 filter results the decimation filter block was used in a verilog simulator using the calculated coefficients and the input data samples. a scaling factor of eight in the configuration register decfilter_mcr, and no decimation factor, were used to obtain the maximum of output results from the filter.the theoretical expected values from this filter were also calculated, and these results were compared with those from the decimation filter. the resultant rms error when considering about 500 samples was about ?97 db. RM0029 temperature sensor doc id 15177 rev 8 1245/1740 27 temperature sensor 27.1 overview spc564a74xx, spc564a80xx mcus include an onboard temperature sensor that monitors device temperature and produces a voltage directly proportional to the internal junction temperature. internal junction temperature must be calculated by software based on the sampled temperature sensor voltage, sampled bandgap voltage and calibration parameter values stored in internal flash memory. 27.2 detailed description the temperature sensor generates a voltage that increases linearly with temperature. since the voltage is an amplified version of a v be voltage it is proportional to absolute temperature. this voltage, v tsens (t), is read by software using the onboard eqadc module and used with the bandgap voltage and constants stored in flash memory during factory test to calculate device junction temperature. five calibration parameters are stored in flash memory during factory test: t low is the low temperature factory calibration temperature value. t high is the hot factory calibration temperature value. v bg_code (t low ) is the bandgap voltage at low calibration temperature (t low ) sampled by the eqadc and converted to a 14-bit value. t tsens_code (t low ) is the temperature sensor voltage at low calibration temperature (t low ) sampled by the eqadc and converted to a 14-bit value. t tsens_code (t high ) is the temperature sensor voltage at high calibration temperature (t high ) sampled by the eqadc and converted to a 14-bit value. the calibration points are illustrated in figure 695 . temperature sensor RM0029 1246/1740 doc id 15177 rev 8 figure 695. calibration points 27.3 temperature formula the temperature formula is shown in figure 696 . t junction v bg t low t high t junction v tsens v bg (t low ) t low t high v tsens (t low ) v tsens (t high ) RM0029 temperature sensor doc id 15177 rev 8 1247/1740 figure 696. temperature formula the following sections detail the values required and where to obtain them. 27.3.1 t low and t high t low is the factory low calibration temperature; t high is the hot factory calibration temperature. these values are stored in shadow flash memory during factory calibration. see section , temperature calculation constants register 0 (tsens_tccr0) for details. 27.3.2 t tsens_code (t low ) and t tsens_code (t high ) t tsens_code (t low ) is the sampled output voltage of the temperature sensor during low temperature factory calibration. t tsens_code (t high ) is the sampled output voltage of the temperature sensor during hot temperature factory calibration. these values are stored in shadow flash memory during factory calibration. see section , temperature calculation constants register 0 (tsens_tccr0) for details. = v bg_code (t low ) t tsens_code (t) x ? t tsens_code (t low ) t tsens_code (t high ) ? t tsens_code (t low ) t = t low + x (t high ? t low ) t tsens_code (t) = v tsens (t) v ref x 2 14 t tsens_code (t low ) = v tsens (t low ) v ref0 x 2 14 t tsens_code (t high ) = v tsens (t high ) v ref0 x 2 14 v bg_code (t) = v bg (t) v ref x 2 14 v bg_code (t low ) = v bg (t low ) v ref0 x 2 14 v bg_code (t) where: notes: 1. v tsens (t) is the temperature sensor output sampled by the adc. 2. v bg (t) is the bandgap voltage sampled by the adc. 3. v ref is the adc reference voltage. 4. v ref0 is the adc reference voltage during factory calibration. 5. t low is the low temperature factory calibration temperature (stored in device flash). 6. t high is the hot factory calibration temperature (stored in device flash). (stored in device flash during factory calibration) (stored in device flash during factory calibration) (stored in device flash during factory calibration) temperature sensor RM0029 1248/1740 doc id 15177 rev 8 27.3.3 v bg_code (t low ) v bg_code (t low ) is the value of the bandgap voltage sampled during low temperature factory calibration. this value is stored in shadow flash memory during factory calibration. see section , temperature calculation constants register 1 (tsens_tccr1) for details. 27.3.4 temperature sensor voltage (v tens (t)) v tens (t) is the output voltage of the device temperature sensor. software must sample the voltage from eqadc_a channel 128 (adc0 and adc1). 27.3.5 bandgap reference voltage (v bg_code (t)) v bg is the bandgap reference voltage. software must sample the voltage from eqadc_a channel 144 (adc0). 27.3.6 registers the calibration constants described previously, that is, t low , t high , t sens_code (t low ), t sens_code (t high ), and v bg_code (t low ), are stored in device shadow flash memory during factory test. this section details the registers where the values reside. temperature calculation constants register 0 (tsens_tccr0) this register contains the calibration temperatures and temperature sensor outputs measured during factory calibration: t high t sens_code (t high ) t low t sens_code (t low ) figure 697. temperature calculation constants register 0 (tsens_tccr0) address: 0xfffe_c000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r tscv2 w reset: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tscv1 w reset: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = unimplemented or reserved RM0029 temperature sensor doc id 15177 rev 8 1249/1740 temperature calculation constants register 1 (tsens_tccr1) this register contains the v bg_code (t low ) parameter value used in the temperature calculation. table 671. temperature calculation constants register 0 (tsens_tccr0) field descriptions field bits description tscv2 0?15 combination of encoded hot factory calibration temperature (t high ) and the temperature sensor output at that temperature (tsens_code(t high )). bits 0?1 contain a value representing the hot factory calibration temperature (t high ). the values are as follows: ?00: t high = reserved ?01: t high = reserved ?10: t high = 145 c ?11: t high = 150 c bits 2?15 are the temperature sensor voltage sampled and converted by the eqadc during factory test with device at hot temperature (t high ). this is the t sens_code (t high ) parameter value referenced in the temperature calculation formula (see figure 696 ). the reset value of this register is device-dependent. the value is set during factory test. tscv1 16?31 combination of encoded low factory calibration temperature (t low ) and the temperature sensor output at that temperature (tsens_code(t low )). bits 16?17 contain a code indicating the value of t low . the values are as follows: ?00: t low =25c ?01: t low =-40c ?10: t low = reserved ?11: t low = reserved bits 18?31 are the temperature sensor voltage sampled and converted by the eqadc during factory test with device at the low calibration temperature. this is the t sens_code (t low ) parameter value referenced in the temperature calculation formula (see figure 696 ). the reset value of this register is device-dependent. the value is set during factory test. temperature sensor RM0029 1250/1740 doc id 15177 rev 8 figure 698. temperature calculation constants register 1 (tsens_tccr1) address: 0xfffe_c004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r reserved tscv3 w reset: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r reserved w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 672. temperature calculation constants register 1 (tsens_tccr1) field descriptions field bits description reserved 0?1 reserved tscv3 2?15 bandgap voltage sampled and converted by adc during factory test. this is the v bg_code (t low ) parameter value referenced in the temperature calculation formula (see figure 696 ). the reset value of this register is device-dependent. the value is set during factory test. reserved 16?31 reserved RM0029 system information module and trim (sim) doc id 15177 rev 8 1251/1740 28 system information module and trim (sim) 28.1 overview the system information module loads configuration data for the device, and trims data used by various analog ip blocks to calibrate current/voltage references or other tunable circuits from flash module test rows. configuration data is maintained by the system information module. some, but not all, of the data is readable by the user. 28.2 user trim values ta ble 67 3 specifies the spc564a74xx, spc564a80xx microcontroller temperature sensor calibration values from address offset 0x00 ? 0x3c. note: the sim base address is 0xfffe_c000 (same as the temperature sensor base) . the temperature sensor calibration values are available as for read-only access. table 673. user trim values offset from tsens_base bits 0:15 bits 16:31 0x00 temperature sensor calibration (1) 16 bits 1. the temperature sensor calibration values, are ava ilable as a read-only slave-bus access in user mode. see the temperature sensor chapter for further details. temperature sensor calibration (1) 16 bits 0x04 temperature sensor calibration (1) 16 bits reserved 0x08 reserved 0x0c 0x10 unique device id (2) 2. the unique device id is a serial number that is different for every device manufactured. 0x14 0x18 0x1c 0x20 ? 0x3c reserved cyclic redundancy checker (crc) unit RM0029 1252/1740 doc id 15177 rev 8 29 cyclic redundancy checker (crc) unit 29.1 overview the crc module provides a fast on-chip capability for verifying code and data integrity. this capability is particularly important in safety applications. examples include: verifying memory integrity by setting it to a known value, calculating a checksum and comparing the calculated checksum against a stored checksum value verifying code integrity by comparing its calculated checksum to its stored checksum value verifying the integrity of data received from a network by comparing its received checksum to its calculated checksum crc functionality can be implemented in software but there are significant speed advantages to be gained by offloading crc computation tasks from the processor core to the crc module. further gains are made when data is written to the crc module via dma. note: this chapter does not discuss the details of computing crc checksums but there are many articles to be found via internet searches. one that might be of particular interest is ?a painless guide to crc error detection algorithms? by ross williams. 29.2 features the crc module on the spc564a74xx, spc564a80xx includes the following features: 3 ?contexts??a context is a crc engine with its own independent set of configuration and data registers. the spc564a74xx, spc564a80xx crc module can process up to three separate data streams concurrently. each context supports crc-16-ccitt and crc-32 ethernet polynomials bit-swap and bit-inversion operations can be applied on the final crc signature support for byte/half-word/word width of the input data stream computation is performed with zero wait states 29.2.1 access and performance all crc registers are accessible (read/write) in each access mode: user, supervisor or test. the following bus operations (contiguous byte enables) are supported: 32-bit data read/write operations to any register low and high half-word read/write operations to any register (be) byte data write/read operations to any register (bf) be. 16-bit operations must be aligned to 16-bit boundaries, i.e., bits 0?15 or bits 16?31. any unaligned operation results in a bus error. bf. byte operations must be aligned to 8-bit boundaries, i. e., bits 0?7, bits 8?15, bits 16?23, or bits 24?31. any unaligned operation results in a bus error. RM0029 cyclic redundancy checker (crc) unit doc id 15177 rev 8 1253/1740 bus performance of the operations is as follows: zero wait state (single bus cycle) for each read/write to the crc_cfg and crc_inp registers zero wait state (single bus cycle) for each write operation to the crc_ cstat register double wait state (3 bus cycles) for each read operation to the crc_ cstat or crc_outp registers immediately following (next clock cycle) a write operation to the crc_cstat, crc_inp or crc_cfg registers belonging to the same context. in all the other cases no wait states are inserted. the following will result in transfer errors: unaligned reads or writes any attempt to read or write an address that is assigned to the crc module but not actually mapped to a register. 29.3 calculating a crc checksum the spc564a74xx, spc564a80xx crc module has three independent sets of crc engines and registers, each set called a context. each context supports a single data stream, structured as a sequence of bytes, half-words or words, written to its input register. since the context operate independently, the crc module can process up to three data streams concurrently. figure 699 illustrates the steps to calculating a crc checksum (also called a signature) for a data stream: 1. configure the context to be used. 2. write a seed value into the crc cu rrent status register (crc_cstat). 3. write the data to the crc input register (crc_inp), until the end of the data to be checked. 4. retrieve the calculated checksum from the crc output register (crc_outp) and verify the checksum against a stored value. cyclic redundancy checker (crc) unit RM0029 1254/1740 doc id 15177 rev 8 figure 699. crc checksum processing flow the following sections describe each step in the process. 29.3.1 configuring the context a context consists of a crc engine and a dedic ated set of registers. the spc564a74xx, spc564a80xx crc module includes three contexts. the configuration step consists of: selecting the polynomial specifying whether a swap operation is to be performed on the output specifying whether a bit inversion is to be performed on the output selections are made by writing the appropriat e values to fields in the crc_cfg register. two standard polynomials are provided by the crc module: crc-16-ccitt (x25 protocol) and crc-32 (ethernet protocol). they are illustrated in equation 21 and equation 22 . configure context select polynomial, swap, inversion via the crc_cfg register start initialize seed value write seed value to crc_cstat register write data to crc input write 32-bit word, half word or byte to crc_inp register end of data stream reached read crc checksum read signature from crc_outp register RM0029 cyclic redundancy checker (crc) unit doc id 15177 rev 8 1255/1740 equation 21 crc-ccitt (x25 protocol) equation 22 crc-32 (eth ernet protocol) the polynomial to be used is based on system requirements. in case of usage of the crc signature for encapsulation in the data frame of a communication protocol (e.g., spi) a bit swap (msb lsb, lsb msb) and/or bit inversion of the final crc signature can be applied (crc_outp register). 29.3.2 initializing the context seed value a crc checksum can be thought of as the remainder of a division of a long, arbitrary number (the data stream) by a known fixed value. the known fixed value is known as the seed value. the same seed value must be used to generate the checksums that are to be compared to each other. the seed value is specified in the crc current status register (crc_cstat), which as a dual purpose. before crc checksum calculation is performed, i.e., during the configuration phase, the crc_cstat register is used to program the seed value. during crc checksum calculation, the register contains the current checksum value. the seed value can be any arbitrary 32-bit value. note: as with the crc configuration register ( crc_cfg) the crc_cstat register can only be written during the configuration phase. a write protection error generated by a write operation to this register indicates it is currently in use. 29.3.3 writing the data stream to the context input after the context is configured and a seed is written, the data stream is written to the context?s input register (crc_inp). the crc_inp register can be written at byte, half-word (high and low) or word in any sequence. in case of half-word write operation, the bytes must be contiguous. note: the crc_inp register only supports aligned writes. half-word (16-bit) writes must be either to bits 0?15 or 16?31. byte writes must be to bits 0?7, bits 8?15, bits 16?23, or bits 24?31. the writes can be by the processor core or by dma transfer. the writes continue until the end of the data stream is reached. 29.3.4 reading the checksum after writing of the data stream to the input register has been completed, the checksum is read from the output register (crc_outp). the crc_outp register includes the final checksum (signature) corresponding to the crc_cstat register value with swap and inversion operations applied, if selected via the crc_cfg register. x 16 x 12 x 5 1 +++ x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x1 +++++++ +++++++ cyclic redundancy checker (crc) unit RM0029 1256/1740 doc id 15177 rev 8 in case of crc-16-ccitt polynomial only the 16 least significant bits have meaning. the 16 most significant bits are set to 0 during the computation. 29.4 register descriptions table 674. crc register map context address (1) 1. crc_base for the spc564a74xx, spc564a80xx is 0xffe6_8000 register location 1 crc_base + 0x0000 crc configuration register (crc_cfg) on page 29- 1257 crc_base + 0x0004 crc input register (crc_inp) on page 29- 1258 crc_base + 0x0008 crc current status register (crc_cstat) on page 29- 1259 crc_base + 0x000c crc output register (crc_outp) on page 29- 1260 2 crc_base + 0x0010 crc configuration register (crc_cfg) on page 29- 1257 crc_base + 0x0014 crc input register (crc_inp) on page 29- 1258 crc_base + 0x0018 crc current status register (crc_cstat) on page 29- 1259 crc_base + 0x001c crc output register (crc_outp) on page 29- 1260 3 crc_base + 0x0020 crc configuration register (crc_cfg) on page 29- 1257 crc_base + 0x0024 crc input register (crc_inp) on page 29- 1258 crc_base + 0x0028 crc current status register (crc_cstat) on page 29- 1259 crc_base + 0x002c crc output register (crc_outp) on page 29- 1260 RM0029 cyclic redundancy checker (crc) unit doc id 15177 rev 8 1257/1740 29.4.1 crc configuration register (crc_cfg) figure 700. crc configuration register (crc_cfg) offset: pmc_base + 0x0000 pmc_base + 0x0010 pmc_base + 0x0020 access: user read/write 0 1 2345678 9101112131415 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0000000 0000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 000000 0 0 000 polyg swap inv w reset 0 0 0000000 00000/1 (1) 00 1. reset value is 1 for context 2 and 0 for context 1 and context 3. table 675. crc_cfg field descriptions field description 0?28 reserved 29 polyg polyg: polynomial selection 0: crc-ccitt polynomial. 1: crc-32 polynomial. this bit can be read and written by software. this bit can be written only during the configuration phase. 30 swap swap: swap selection 0: no swap selection applied on the crc_outp content 1: swap selection (msb lsb, lsb msb) applied on the crc_outp content. in case of crc- ccitt polynomial the swap operation is applied on the 16 lsb bits. this bit can be read and written by software. this bit can be written only during the configuration phase. 31 inv inv: inv selection 0: no inversion selection applied on the crc_outp content 1: inversion selection (bit x bit) applied on the crc_outp content. in case of crc-ccitt polynomial the inversion operation is applied on the 16 lsb bits. this bit can be read and written by software. this bit can be written only during the configuration phase. cyclic redundancy checker (crc) unit RM0029 1258/1740 doc id 15177 rev 8 29.4.2 crc input register (crc_inp) figure 701. crc input register (crc_inp) offset: pmc_base + 0x0004 pmc_base + 0x0014 pmc_base + 0x0024 access: user read/write 0 1 2345678 9101112131415 r inp w reset 0 0 0000000 0000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r inp w reset 0 0 0000000 0000000 table 676. crc_inp field descriptions field description 0?31 inp: input data for the crc computation the inp register can be written at byte, half-word (high and low) or word in any sequence. in case of half- word write operation, the bytes must be contiguous. this register can be read and written by software. RM0029 cyclic redundancy checker (crc) unit doc id 15177 rev 8 1259/1740 29.4.3 crc current status register (crc_cstat) figure 702. crc current status register (crc_cstat) offset: pmc_base + 0x0008 pmc_base + 0x0018 pmc_base + 0x0028 access: user read/write 0 1 2345678 9101112131415 r cstat w reset 1 1 1111111 1111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cstat w reset 1 1 1111111 1111111 table 677. crc_cstat field descriptions field description 0?31 cstat: status of the crc signature the cstat register includes the current status of the crc signature. no bit swap and inversion are applied to this register. in case of crc-ccitt polynomial only the16 least significant bits have meaning. the 16 most significant bits are tied to 0 during the computation. the cstat register can be written at byte, half-word or word. this register can be read and written by software. this register can be written only during the configuration phase. cyclic redundancy checker (crc) unit RM0029 1260/1740 doc id 15177 rev 8 29.4.4 crc output register (crc_outp) a figure 703. crc output register (crc_outp) offset: pmc_base + 0x000c pmc_base + 0x001c pmc_base + 0x002c access: user read/write 0 1 2345678 9101112131415 r outp w reset 1 1 1111111 1111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r outp w reset 1 1 1111111 1111111 table 678. crc_outp field descriptions field description 0?31 outp: final crc signature the outp register includes the final signature corresponding to the crc_cstat register value after swap/inversion operations, if specified. in case of crc-ccitt polynomial only the16least significant bits have meaning. the 16 most significant bits are tied to 0 during the computation. this register can be read by software. RM0029 cyclic redundancy checker (crc) unit doc id 15177 rev 8 1261/1740 29.5 use cases and limitations two main use cases are considered: calculation of the crc of the configuration registers during the process safety time calculation of the crc on the incoming and outgoing frames for the communication protocols (not protected with crc by definition of the protocol itse lf) used as a safety- relevant peripheral. 29.5.1 checksums for configuration registers the checksum (signature) of configuration registers is computed in a correct way only if these registers do not contain any status bits, i.e., configuration register contents must not dynamically change during, or as a result of, a crc checksum calculation. 29.5.2 calculations on inco ming/outgoing protocol frames the following sections show the sequence for managing crc checksums as part of a communication external to the device. calculating checksums on data to be transmitted figure 704 illustrates the sequence used to calculate a crc checksum on a data stream, append the checksum and transfer it to the peripheral to be used for transmission. the sequence is as follows: 1. software configures the dma channel and crc context to be used. 2. dma copies the data to be transmitted to the crc context?s input register (crc_inp) to calculate the crc signature (phase 1) 3. software copies the crc checksum (sig nature) from the crc module (crc_outp register) to the memory location immediately following the transmission data. (phase 2) 4. dma transfers the data bl ock (payload + crc checksum from memory to the peripheral module (e.g., spi tx fifo) (phase 3) cyclic redundancy checker (crc) unit RM0029 1262/1740 doc id 15177 rev 8 figure 704. transmission sequence calculating checksums on received data figure 705 illustrates the sequence used to calculate a crc checksum on a received data stream. the sequence is as follows: data to be transmitted crc_outp crc_inp memory crc context cpu transmission phase 2 data to be transmitted crc_outp crc_inp memory crc context dma transmission phase 1 crc checksum data to be transmitted tx fifo memory spi cpu transmission phase 3 crc checksum RM0029 cyclic redundancy checker (crc) unit doc id 15177 rev 8 1263/1740 1. software configures the dma channel and /crc context to be used 2. dma copies the received data block (paylo ad + crc) from the peripheral (e.g., spi rx fifo) module to memory (phase 1) 3. dma copies the received data block transfer (payload + crc) from memory to the crc context (crc_inp register) to calculate the crc signature (phase 2) 4. the crc signature is read from the crc context (crc_outp register) by software (phase 3) cyclic redundancy checker (crc) unit RM0029 1264/1740 doc id 15177 rev 8 figure 705. reception sequence crc_outp crc_inp memory crc context dma received data crc checksum received data rx fifo memory spi dma reception phase 1 crc checksum received data reception phase 2 crc_outp crc_inp crc context reception phase 3 software check RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1265/1740 30 deserial serial peripheral interface (dspi) 30.1 introduction figure 706 is a block diagram of the deserial serial peripheral interface (dspi) module. the revision history for this chapter is located at the end of this file. figure 706. dspi block diagram 30.2 overview the deserial serial peripheral interface (dspi) module provides a synchronous serial interface for communication between the spc564a74xx, spc564a80xx and external baud rate, delay & transfer control sout sin ht pcs[x]/ss /pcss/mtrig shift register spi sck spi and dsi internal internal parallel inputs parallel outputs priority logic csi 32 32 8 cmd data dma and interrupt control data tx fifo rx fifo dsi 32 32 32 32 edma intc slave bus interface clock/reset dspi_pushr dspi_popr sdr asdr ddr frame data selection logic deserial serial peripheral interface (dspi) RM0029 1266/1740 doc id 15177 rev 8 devices. the dspi supports pin count reduction through serialization and deserialization of etpu channels, emios channels and memory-mapped registers. incoming deserialized data can also be used to trigger external interrupt requests. the channels and register content are transmitted using a spi-like protocol. there are three identical dspi modules (dspi_b, dspi_c and dspi_d) on the spc564a74xx, spc564a80xx. the dspis have three configurations: serial peripheral interface (spi)?dspi operates as a spi with support for queues deserial serial interface (dsi)?dspi serializes etpu and emios output channels and deserializes the received data by placing it on the etpu and emios input channels and as inputs to the external interrupt request sub-block of the siu combined serial interface (csi)?dspi operates in both spi and dsi configurations interleaving dsi frames with spi frames, giving priority to spi frames for queued operations, the spi queues reside in system memory external to the dspi. data transfers between the memory and the dspi fifos are accomplished through the use of the edma controller or through host software. RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1267/1740 30.3 features the dspi supports these spi features: full-duplex, synchronous transfers selectable lvds pads working at 40 mhz for sout and sck pins (only in dspi_b and dspi_c) master and slave mode buffered transmit operation using the tx fifo with depth of 4 entries buffered receive operation using the rx fifo with depth of 4 entries tx and rx fifos can be disabled individually for low-latency updates to spi queues visibility into the tx and rx fifos for ease of debugging fifo bypass mode for low-latency updates to spi queues programmable transfer attributes on a per-frame basis: ? parameterized number of transfer attribute registers (from 2 to 8) ? serial clock with programmable polarity and phase ? various programmable delays: pcs to sck delay sck to pcs delay delay between frames ? programmable serial frame size of 4 to 32 bits, expandable with software control ? continuously held chip select capability 8 peripheral chip selects, expandable to 256 with external demultiplexer deglitching support for up to 128 peripheral chip selects with external demultiplexer dma support for adding entries to tx fifo and removing entries from rx fifo: ? tx fifo is not full (tfff) ? rx fifo is not empty (rfdf) 6 interrupt conditions: ? end of queue reached (eoqf) ? tx fifo is not full (tfff) ? transfer of current frame complete (tcf) ? attempt to transmit with an empty transmit fifo (tfuf) ?or? serial frame received while rx fifo is full (rfof). these two interrupts are ored and given out as fifo overrun interrupt. ? rx fifo is not empty (rfdf) ? fifo underrun (slave only and spi mode, the slave is asked to transfer data when the tx fifo is empty) modified transfer formats for communication with slower peripheral devices continuous serial communications clock (sck) power-saving architectural features ? support for ipi green-line stop mode enhanced dsi logic to implement a 32-bit timed serial bus (tsb) configuration, supporting the micro second channel (msc) bus downstream frame format deserial serial peripheral interface (dspi) RM0029 1268/1740 doc id 15177 rev 8 the dspis also support these features unique to the dsi and csi configurations: 2 sources of the serialized data: ? etpu_a and emios output channels ? memory-mapped register in the dspi destinations for the deserialized data: ? etpu_a and emios input channels ? siu external interrupt request inputs ? memory-mapped register in the dspi deserialized data is provided as parallel output signals and as bits in a memory- mapped register transfer initiation conditions: ? continuous ? edge sensitive hardware triggered ? change in data pin serialization/deserialization with interleaved spi frames for control and diagnostics continuous serial communications clock support for parallel and serial chaining of up to 3 dspi modules parity generation and checking 30.4 dspi configurations the dspi module can operate in three configurations: spi, dsi and csi. 30.4.1 spi configuration the spi configuration allows the dspi to send and receive serial data. this configuration allows the dspi to operate as a basic spi block with internal fifos supporting external queues operation. transmit data and received data reside in separate fifos. the host cpu or a dma controller read the received data from the receive fifo and write transmit data to the transmit fifo. for queued operations the spi queues can reside in system ram, external to the dspi. data transfers between the queues and the dspi fifos are accomplished by a dma controller or host cpu. figure 707 shows a system example with dma, dspi and external queues in system ram. RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1269/1740 figure 707. dspi with queues and dma 30.4.2 dsi configuration the dsi configuration supports pin count reduction by serializing etpu and emios output channels or bits from a memory-mapped register and shifting them out with a spi-like protocol. the dspi deserializes the received data, and provides the received data to the etpu?s and emios? input channels, the siu irq inputs, or to a memory-mapped register in the dspi. see section 30.9.17, dspi connections to etpu_a, emios and siu for the source of the serialization data for each dspi module. figure 708 shows an example of how a master dspi block connects to a dsi slave in dsi configuration. figure 708. dspi connections for spi and dsi transfers specifically in the tsb configuration, detailed in section 30.9.8, timed serial bus (tsb) , the dspi serializes from 4 to 32 parallel input signals or register bits. the tsb downstream frame used to communicate with a single slave is shown in figure 743 . system ram dspi dma controller tx queue rx fifo tx fifo shift register data data addr/ctrl rx queue data data addr/ctrl done req shift register sin sin sout sout sck sck ss pcsx dspi master spi/dsi slave shift register baud rate generator deserial serial peripheral interface (dspi) RM0029 1270/1740 doc id 15177 rev 8 30.4.3 csi configuration the csi configuration allows serialized data to be interleaved with configuration or diagnostic data and be transferred to a slave device using only one serial link. the csi configuration supports spi and dsi functionality on a frame by frame basis. csi configuration allows interleaving of dsi data frames from the etpu?s and emios? output channels with spi commands and data from the tx fifo. in the csi configuration, transmission of spi data has higher priority than dsi data. the data returned from the bus slave is either used to drive the etpus or emios input channels, or the data is stored in the rx fifo. the dspi only supports csi configuration in master mode. figure 709 shows an example of how a dspi can be used with a deserializing peripheral that supports spi control for control and diagnostic frames. figure 709. dspi connections for csi transfer 30.5 dspi frequency support the dspi supports frequencies up to 40 mhz when used with lvds outputs (dspi_b and dspi_c only), and frequencies up to 20 mhz in non-lvds mode. ta ble 67 9 shows possible divider settings to achieve maximum frequency for different system clock frequencies. shift register shift register sin sin sout sout sck sck ss0 pcsx dspi master external slave deserializer ss1 pcsy spi dsi tx priority control spi frame select logic frame dsi frame tx fifo table 679. dspi channel frequency support system clock (mhz) dspi use mode max. usable frequency (mhz) notes 150 lvds 37.5 use sysclock /4 divide ratio non-lvds 18.75 use sysclock /8 divide ratio 120 lvds 40 use sysclock /3 divide ratio. gives 33/66 duty cycle. use dspi configuration dbr = 0b1 (double baud rate), br = 0b0000 (scaler value 2) and pbr = 0b01 (prescaler value 3). non-lvds 20 use sysclock /6 divide ratio 80 lvds 40 use sysclock /2 divide ratio non-lvds 20 use sysclock /4 divide ratio RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1271/1740 30.6 modes of operation the dspi has four modes of operation that can be divided into two categories: module- specific modes and an mcu-specific mode. master mode, slave mode and module disable mode are the module-specific modes, and debug mode is the mcu-specific mode. the module-specific modes are entered by host software writing to a register bit. the mcu- specific mode is selected by a signal external to the dspi. the mcu-specific mode is a mode that spc564a74xx, spc564a80xx may enter in parallel to the dspi being in one of its module-specific modes. 30.6.1 master mode master mode allows the dspi to initiate and control serial communication. in this mode the sck, dspi_x_pcs and sout signals are controlled by the dspi and configured as outputs. 30.6.2 slave mode slave mode allows the dspi to communicate with spi/dsi bus masters. in this mode the dspi responds to externally controlled serial transfers. the dspi cannot initiate serial transfers in slave mode. 30.6.3 module disable mode the module disable mode is used for mcu power management. the clock to the non- memory mapped logic in the dspi is stopped while in module disable mode. the dspi enters the module disable mode when bit dspi_mcr[mdis] is set. 30.6.4 debug mode debug mode is used for system development and debugging. if the spc564a74xx, spc564a80xx mcu enters debug mode while bit dspi_mcr[frz] is set, the dspi halts operation on the next frame boundary. if the spc564a74xx, spc564a80xx enters debug mode while the frz bit is negated, the dspi behavior is unaffected and remains dictated by the module-specific mode and configuration of the dspi. 30.7 external signal description 30.7.1 overview ta ble 68 0 lists the signals that may connect off-chip depending on the device implementation. table 680. signal properties name i/o type function master mode slave mode dspi_x_pcs[0]/ss output / input peripheral chip select 0 slave select dspi_x_pcs[1] ? pcs[3] output peripheral chip select 1 ? 3 unused deserial serial peripheral interface (dspi) RM0029 1272/1740 doc id 15177 rev 8 30.7.2 detailed signal description remove brackets for single signals (pcs[0] becomes pcs0) and use brackets to denote range (pcs[1] - pcs[3] becomes pcs[3:1])?--rcs dspi_x_pcs[0]/ss ? peripheral chip select/slave select in master mode, the dspi_x_pcs[0] signal is a peripheral chip select output that selects which slave device the current transmission is intended for. in slave mode, the active low ss signal is a slave select input signal that allows a spi master to select the dspi as the target for transmission. dspi_x_pcs[1] ? pcs[3] ? peripheral chip selects 1 ? 3 dspi_x_pcs[1] ? pcs[3] are peripheral chip select output signals in master mode. in slave mode these signals are unused. dspi_x_pcs[4]/mtrig ? peripheral chip select 4/master trigger in master mode, dspi_x_pcs[4] is a peripheral chip select output signal. in slave mode, the active low mtrig is an output trigger signal that indicates that a change in data to be serialized has occurred. the mtrig provides a pulse in dsi configuration when a change in data to be serialized occurs. the mtrig pulse is four system clock cycles in duration. if the dspi is in slave mode and the mto is disabled, the dspi_x_pcs[4]/mtrig signal is unused. dspi_x_pcs[5]/pcss ? peripheral chip select 5/peripheral chip select strobe dspi_x_pcs[5] is a peripheral chip select output signal. when the dspi is in master mode and the dspi_mcr[pcsse] bit is cleared, this signal selects which slave device the current transfer is intended for. when the dspi is in master mode and the dspi_mcr[pcsse] bit is set, the pcss signal acts as a strobe to external peripheral chip select demultiplexer, which decodes the dspi_x_pcs[0] ? pcs[4] signals, preventing glitches on the demultiplexer outputs. this signal is not used in slave mode. dspi_x_pcs[4]/mtrig output peripheral chip select 4 master trigger dspi_x_pcs[5]/pcss output peripheral chip select 5 / peripheral chip select strobe unused dspi_x_sin input serial data in serial data in dspi_x_sout output serial data out serial data out dspi_x_sck output / input serial clock (output) serial clock (input) ht input hardware trigger hardware trigger table 680. signal properties (continued) name i/o type function master mode slave mode RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1273/1740 dspi_x_sin ? serial input dspi_x_sin is a serial data input signal. dspi_x_sout ? serial output dspi_x_sout is a serial data output signal. dspi_x_sck ? serial clock dspi_x_sck is a serial communication clock signal. in master mode, the dspi generates the sck. in slave mode, sck is an input from an external bus master. ht ? hardware trigger ht is a trigger input signal that is used with multiple transfer operations in dsi configuration. in master mode while in dsi or csi configurations, the ht signal initiates a data transfer when the trre bit in the dspi_dsicr is set and a rising or falling edge is detected on ht. which edge to trigger on is determined by the tpol bit in the dspi_dsicr. in slave mode, the dspi generates a trigger pulse on the mtrig pin, when a rising or falling edge is detected on ht. which edge that generates an output pulse is selected by the tpol bit in the dspi_dsicr. 30.8 memory map and register definition 30.8.1 memory map register accesses to memory addresses that are reserved or undefined result in a transfer error. write access to the dspi_popr also result in a transfer error. ta ble 68 1 shows the dspi memory map. table 681. memory map address register name location dspi_base dspi module configuration register (dspi_mcr) on page 30- 1275 dspi_base+0x4 dspi hardware configuration register (dspi_hcr) on page 30- 1277 dspi_base+0x8 dspi transfer count register (dspi_tcr) on page 30- 1278 dspi_base+0xc ? dspi_base+0x28 dspi clock and transfer attributes register 0 (dspi_ctar0) ? dspi clock and transfer attributes register 7 (dspi_ctar7) on page 30- 1279 dspi_base+0x2c dspi status register (dspi_sr) on page 30- 1285 dspi_base+0x30 dspi dma/interrupt request select and enable register (dspi_rser) on page 30- 1288 fifo registers deserial serial peripheral interface (dspi) RM0029 1274/1740 doc id 15177 rev 8 dspi_base+0x34 dspi push tx fifo register (dspi_pushr) on page 30- 1290 dspi_base+0x38 dspi pop rx fifo register (dspi_popr) on page 30- 1292 dspi_base+0x3c ? dspi_base+0x48 dspi transmit fifo register 0 (dspi_txfr0) ? dspi transmit fifo register 3 (dspi_txfr3) on page 30- 1293 dspi_base+0x4c ? dspi_base+0x78 reserved dspi_base+0x7c ? dspi_base+0x88 dspi receive fifo register 0 (dspi_rxfr0) ? dspi receive fifo register 3 (dspi_rxfr3) on page 30- 1293 dspi_base+0x8c ? dspi_base+0xb8 reserved dsi registers dspi_base+0xbc dspi dsi configuration register (dspi_dsicr) on page 30- 1294 dspi_base+0xc0 dspi dsi serialization data register (dspi_sdr) on page 30- 1296 dspi_base+0xc4 dspi dsi alternate serialization data register (dspi_asdr) on page 30- 1297 dspi_base+0xc8 dspi dsi transmit comparison register (dspi_compr) on page 30- 1298 dspi_base+0xcc dspi dsi deserialization data register (dspi_ddr) on page 30- 1298 dspi_base+0xd0 dspi dsi configuration register 1 (dspi_dsicr1) on page 30- 1299 dspi_base+0xd4 dspi dsi serialization source select register (dspi_ssr) on page 30- 1300 dspi_base+0xd8 dspi dsi parallel input select register 0 (dpsi_pisr0) (1) on page 30- 1301 dspi_base+0xdc dspi dsi parallel input select register 1 (dpsi_pisr1) (1) on page 30- 1301 dspi_base+0xe0 dspi dsi parallel input select register 2 (dpsi_pisr2) (1) on page 30- 1301 dspi_base+0xe4 dspi dsi parallel input select register 3 (dpsi_pisr3) (1) on page 30- 1301 dspi_base+0xe8 dspi dsi deserialized data interrupt mask register (dspi_dimr) on page 30- 1305 dspi_base+0xec dspi dsi deserialized data polarity interrupt register (dspi_dpir) on page 30- 1306 1. dspi_pisr0-3 registers and assosiated with them functional ity may be not implemented in particular dspi instances of the soc. table 681. memory map (continued) address register name location RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1275/1740 30.8.2 register descriptions register diagrams below need access information. also, it seems that many registers--such as the 16 transmit fifo registers--would benefit from the use of an n variable to indicate the range.--rcs dspi module configuration register (dspi_mcr) the dspi_mcr contains bits which configure various attributes associated with dspi operation. the halt and mdis bits can be changed at any time, but only take effect on the next frame boundary. only the halt and mdis bits in the dspi_mcr are allowed to be changed, while the dspi is in the running state. figure 710. dspi module configuration register (dspi_mcr) address: dspi_base 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mstr cont_scke dconf frz mtfe pcsse rooe pcsis7 pcsis6 pcsis5 pcsis4 pcsis3 pcsis2 pcsis1 pcsis0 w reset0 00000 0 000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 mdis dis_txf dis_rxf 00 smpl_pt 000000 pes halt w clr_txf clr_rxf reset0 00000 0 000000001 table 682. dspi_mcr field description field description 0 mstr master/slave mode select the mstr bit configures the dspi for either master mode or slave mode. 0 dspi is in slave mode 1 dspi is in master mode 1 cont_scke continuous sck enable the cont_scke bit enables the serial communication clock (sck) to run continuously. see section 30.9.7, continuous serial communications clock for details. 0 continuous sck disabled 1 continuous sck enabled 2?3 dconf[0:1] dspi configuration the dconf field selects between the three different configurations of the dspi: 00 spi 01 dsi 10 csi 11 reserved deserial serial peripheral interface (dspi) RM0029 1276/1740 doc id 15177 rev 8 4 frz freeze the frz bit enables the dspi transfers to be stopped on the next frame boundary when the device enters debug mode. 0 do not stop serial transfers 1 stop serial transfers 5 mtfe modified timing format enable the mtfe bit enables a modified transfer format to be used. see section , modified spi/dsi transfer format (mtfe = 1, cpha = 1) for more information. 0 modified spi transfer format disabled 1 modified spi transfer format enabled 6 pcsse peripheral chip select strobe enable the pcsse bit enables the dspi_x_pcs[5]/pcss to operate as a pcs strobe output signal. see section , peripheral chip select strobe enable (pcss) for more information. 0 dspi_x_pcs[5]/pcss is used as the peripheral chip select[5] signal 1 dspi_x_pcs[5]/pcss is used as an active-low pcs strobe signal 7 rooe receive fifo overflow overwrite enable the rooe bit enables in rx fifo overflow condition to ignore the incoming serial data or to overwrite existing data. if the rx fifo is full and new data is received, the data from the transfer, generated the overflow, is ignored or shifted in to the shift register. see section , receive fifo overflow interrupt request for more information. 0 incoming data is ignored 1 incoming data is shifted in to the shift register 8?15 pcsis x peripheral chip select inactive state the pcsis bit determines the inactive state of the pcs x signal. 0 the inactive state of pcs x is low 1 the inactive state of pcs x is high 17 mdis module disable the mdis bit allows the clock to be stopped to the non-memory mapped logic in the dspi effectively putting the dspi in a software controlled power-saving state. see section 30.9.18, power saving features for more information. the reset value of the mdis bit is parameterized, with a default reset value of ?0?. 0 enable dspi clocks. 1 allow external logic to disable dspi clocks. 18 dis_txf disable transmit fifo when the tx fifo is disabled, the transmit part of the dspi operates as a simplified double- buffered spi. see section , fifo disable operation for details. 0 tx fifo is enabled 1 tx fifo is disabled 19 dis_rxf disable receive fifo when the rx fifo is disabled, the receive part of the dspi operates as a simplified double- buffered spi. see section , fifo disable operation for details. 0 rx fifo is enabled 1 rx fifo is disabled table 682. dspi_mcr fiel d description (continued) field description RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1277/1740 dspi hardware configuration register (dspi_hcr) dspi hardware configuration register provides particular implementation details about the dspimodule, i.e. number of receive and transmit fifo entries, number of ctar registers and if dsi featuresare implemented in the module or not. it is read only register. 20 clr_txf clear tx fifo clr_txf is used to flush the tx fifo. writing a ?1? to clr_txf clears the tx fifo counter. the clr_txf bit is always read as zero. 0 do not clear the tx fifo counter 1 clear the tx fifo counter 21 clr_rxf clear rx fifo clr_rxf is used to flush the rx fifo. writing a ?1? to clr_rxf clears the rx counter. the clr_rxf bit is always read as zero. 0 do not clear the rx fifo counter 1 clear the rx fifo counter 22?23 smpl_pt sample point smpl_pt field controls when the dspi master samples sin in modified transfer format. figure 745 shows where the master can sample the sin pin. 00 dspi samples sin at driving sck edge. 01 dspi samples sin one system clock after driving sck edge 10 dspi samples sin two system clocks after driving sck edge 11 reserved 24?29 reserved, should be cleared. 30 pes parity error stop pes bit controls spi operation when a parity error detected in received spi frame. 0 spi frames transmission continue. 1 spi frames transmission stop. 31 halt halt the halt bit starts and stops dspi transfers. see section 30.9.1, start and stop of dspi transfers for details on the operation of this bit. 0 start transfers 1 stop transfers table 682. dspi_mcr fiel d description (continued) field description deserial serial peripheral interface (dspi) RM0029 1278/1740 doc id 15177 rev 8 dspi transfer count register (dspi_tcr) the dspi_tcr contains a counter that indicates the number of spi transfers made. the transfer counter is intended to assist in queue management. do not write the dspi_tcr, when the dspi is in the running state. figure 711. dspi hardware configuration register (dspi_hcr) address: dspi_base + 0x4 access: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r dsi pisr 0 0 0 ctar txfr rxfr w reset - (1) -000----------- 1514131211109876543210 r0000000000000000 w reset0000000000000000 1. the reset bits in the dspi_hcr are set by configuration parameters in the soc. table 683. dspi_hcr field description field description 31 dsi dsi features are implemented for the module. 0 - dsi features are not implemented, dsi registers don?t exist. 1 - dsi features are implemented 30 pisr pisr, pisr0-3 and parallel inputs frame positions selection logic are implemented for the module. 0 - dspi_pisr0-3 registers are not implemented. 1 - dspi_pisr0-3 registers are implemented 29?27 reserved, should be cleared. 26?24 ctar[2:0] ctar, maximum implemented dspi_ctar register number. 23?20 txfr3:0] txfr, maximum implemented dspi_txfr register number. 19?16 rxfr3:0] rxfr, maximum implemented dspi_rxfr register number. 15?0 reserved, should be cleared. RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1279/1740 dspi clock and transfer attributes registers 0?7 (dspi_ctar0? dspi_ctar7) the dspi_ctar registers are used to define different transfer attributes. the number of ctar registersis parameterized in the rtl and can be from two to eight registers. do not write to the dspi_ctarregisters, while the dspi is in the running state. in master mode, the dspi_ctar0 - dspi_ctar7 registers define combinations of transfer attributessuch as frame size, clock phase and polarity, data bit ordering, baud rate, and various delays. in slave mode,a subset of the bitfields in the dspi_ctar0 and dspi_ctar1 registers are used to set the slave transfer attributes. when the dspi is configured as a spi master, the ctas field in the command portion of the tx fifoentry selects which of the dspi_ctar register is used. when the dspi is configured as a spi bus slave,the dspi_ctar0 register is used. when the dspi is configured as a dsi master, the dsictas field in the dspi dsi configuration register (dspi_dsicr), selects which of the dspi_ctar register is used. when the dspi is configured as a dsi bus slave, the dspi_ctar1 register is used. in csi configuration, the transfer attributes are selected based on whether the current frame is spi data or dsi data. spi transfers in csi configuration follow the protocol described for spi configuration, and dsi transfers in csi configuration follow the protocol figure 712. dspi transfer count register (dspi_tcr) address: dspi_base + 0x8 0123456789101112131415 r tcnt w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 table 684. dspi_tcr field description field description 0?15 tcnt[0:15] spi transfer counter the spi_tcnt field counts the number of spi transfers the dspi makes. the spi_tcnt field increments every time the last bit of a spi frame is transmitted. a value written to spi_tcnt presets the counter to that value. spi_tcnt is reset to zero at the beginning of the frame when the ctcnt field is set in the executing spi command. the transfer counter ?wraps around? i.e. incrementing the counter past 65535 resets the counter to zero. 16?31 reserved, should be cleared. deserial serial peripheral interface (dspi) RM0029 1280/1740 doc id 15177 rev 8 described for dsi configuration. csi configuration is only valid in conjunction with master mode. see section 1.5.4, ?combined serial interface (csi) configuration,? for more details.. tsb mode sets some limitations on transfer attributes: clock phase is forced to be cpha = 1 and the cpha bit setting has no effect. pcs lines are driven at the driving edge of the sck clock together with sout, so pcs assertion and negation delays control is unavailable and pcssck, pasc, cssck and asc fields have no effect. delay after transfer can be set from 1 to 64 serial clocks with help of pdt and dt fields. figure 713. dspi clock and transfer attributes register 0?7 (dspi_ctar0?dspi_ctar7) in the master mode address: dspi_base + 0xc?dspi_base + 0x28 0 1234 5 6 7 8 9101112131415 r dbr fmsz cpol cpha lsbfe pcssck pasc pdt pbr w reset01111 0 0 0 0 0 0 00000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cssck asc dt br w reset00000 0 0 0 0 0 0 00000 figure 714. dspi clock and transfer attributes register 0 (dspi_ctar0) in the slave mode address: dspi_base + 0xc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r fmsz cpol cpha pe pp not used w reset01111 0 0 000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r not used w reset00000 0 0 000000000 RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1281/1740 table 685. dspi_ctar n field description in master mode field descriptions 0 dbr double baud rate the dbr bit doubles the effective baud rate of the serial communications clock (sck). this field is only used in master mode. it effectively halves the baud rate division ratio supporting faster frequencies and odd division ratios for the serial communications clock (sck). when the dbr bit is set, the duty cycle of the serial communications clock (sck) depends on the value in the baud rate prescaler and the clock phase bit as listed in table 686 . see the br field description for details on how to compute the baud rate. 0 the baud rate is computed normally with a 50/50 duty cycle 1 the baud rate is doubled with the duty cycle depending on the baud rate prescaler 1?4 fmsz[0:3] frame size the number of bits transferred per frame is equal to fmsz field value plus 1. minimum valid fmsz field value is 3. when operating in tsb mode, detailed in section 30.9.8, timed serial bus (tsb) the fmsz field value plus 1 is equal the data frame bit number, where control of the pcs assertion switches from the dspi_dsicr to the dspi_dsicr1 register. 5 cpol clock polarity the cpol bit selects the inactive state of the serial communications clock (sck). this bit is used in both master and slave mode. for successful communication between serial devices, the devices must have identical clock polarities. when the continuous selection format is selected, switching between clock polarities without stopping the dspi can cause errors in the transfer due to the peripheral device interpreting the switch of clock polarity as a valid clock edge. 0 the inactive state value of sck is low 1 the inactive state value of sck is high 6 cpha clock phase the cpha bit selects which edge of sck causes data to change and which edge causes data to be captured. this bit is used in both master and slave mode. for successful communication between serial devices, the devices must have identical clock phase settings. in continuous sck mode or tsb mode the bit value is ignored and the transfers are done as cpha bit is set to 1. 0 data is captured on the leading edge of sck and changed on the following edge 1 data is changed on the leading edge of sck and captured on the following edge 7 lsbfe lsb first the lsbfe bit selects if the lsb or msb of the frame is transferred first. when operating in tsb configuration, this bit should be set to be compliant to msc specification. 0 data is transferred msb first 1 data is transferred lsb first 8?9 pcssck[0:1] pcs to sck delay prescaler the pcssck field selects the prescaler value for the delay between assertion of pcs and the first edge of the sck. see the cssck field description how to compute the pcs to sck delay. in the tsb mode the pcssck field has no effect. 00 pcs to sck prescaler value is 1 01 pcs to sck prescaler value is 3 10 pcs to sck prescaler value is 5 11 pcs to sck prescaler value is 7 deserial serial peripheral interface (dspi) RM0029 1282/1740 doc id 15177 rev 8 10?11 pasc[0:1] after sck delay prescaler the pasc field selects the prescaler value for the delay between the last edge of sck and the negation of pcs. see the asc field description how to compute the after sck delay. in the tsb mode the pasc field has no effect. 00 after sck delay prescaler value is 1 01 after sck delay prescaler value is 3 10 after sck delay prescaler value is 5 11 after sck delay prescaler value is 7 12?13 pdt[0:1] delay after transfer prescaler the pdt field selects the prescaler value for the delay between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginning of the next frame. the pdt field is only used in master mode. in the tsb mode the pdt field defines two msb bits of the delay after transfer. see the dt field description for details on how to compute the delay after transfer. 00 delay after transfer prescaler value is 1 01 delay after transfer prescaler value is 3 10 delay after transfer prescaler value is 5 11 delay after transfer prescaler value is 7 14?15 pbr[0:1] baud rate prescaler the pbr field selects the prescaler value for the baud rate. this field is only used in master mode. the baud rate is the frequency of the serial communications clock (sck). the system clock is divided by the prescaler value before the baud rate selection takes place. see the br field description for details on how to compute the baud rate. 00 baud rate prescaler value is 2 01 baud rate prescaler value is 3 10 baud rate prescaler value is 5 11 baud rate prescaler value is 7 16?19 cssck[0:3] pcs to sck delay scaler the cssck field selects the scaler value for the pcs to sck delay. this field is only used in master mode. the pcs to sck delay is the delay between the assertion of pcs and the first edge of the sck. table 687 list the scaler values.the pcs to sck delay is a multiple of the system clock period and it is computed according to the following equation: equation 23 see section , pcs to sck delay (t csc ) for more details.in the tsb mode the field has no effect. table 685. dspi_ctar n field description in master mode (continued) field descriptions t csc 1 f sys ------------ - pcssck cssck = RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1283/1740 20?23 asc[0:3] after sck delay scaler the asc field selects the scaler value for the after sck delay. this field is only used in master mode. the after sck delay is the delay between the last edge of sck and the negation of pcs. table 687 list the scaler values.the after sck delay is a multiple of the system clock period, and it is computed according to the following equation: equation 24 see section , after sck delay (t asc ) for more details. in the tsb mode the field has no effect. 24?27 dt[0:3] delay after transfer scaler the dt field selects the delay after transfer scaler. this field is only used in master mode. the delay after transfer is the time between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginning of the next frame. table 687 lists the scaler values. in the continuous serial communications clock operation the dt value is fixed to one sck clock period, the delay after transfer is a multiple of the system clock period and it is computed according to the following equation: equation 25 in the tsb mode the delay after transfer is equal to a number formed by concatenation of pdt and dt fields plus 1 of the sck clock periods. see section , delay after transfer (tdt) for more details. 28?31 br[0:3] baud rate scaler the br field selects the scaler value for the baud rate. this field is only used in master mode. the prescaled system clock is divided by the baud rate scaler to generate the frequency of the sck. table 688 lists the baud rate scaler values.the baud rate is computed according to the following equation: equation 26 see section , baud rate generator for more details. table 685. dspi_ctar n field description in master mode (continued) field descriptions t asc 1 f sys ------------ - pasc asc = t dt 1 f sys ------------ - pdt dt = sck baud rate f sys pbr ------------ - 1dbr + br ---------------------- - = table 686. dspi sck duty cycle dbr cpha pbr sck duty cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10 40/60 deserial serial peripheral interface (dspi) RM0029 1284/1740 doc id 15177 rev 8 1011 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1111 57/43 table 687. delay scaler encoding field value scaler value field value scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 688. dspi baud rate scaler br baud rate scaler value br baud rate scaler value 0000 2 1000 256 0001 4 1001 512 0010 6 1010 1024 0011 8 1011 2048 0100 16 1100 4096 0101 32 1101 8192 0110 64 1110 16384 0111 128 1111 32768 table 686. dspi sck duty cycle (continued) dbr cpha pbr sck duty cycle RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1285/1740 dspi status register (dspi_sr) the dspi_sr contains status and flag bits. the bits reflect the status of the dspi and indicate the occurrence of events that can generate interrupt or dma requests. software can clear flag bits in the dspi_sr by writing a ?1? to it. writing a ?0? to a flag bit has no effect. this register may not be writable in module disable mode due to the use of power saving mechanisms. table 689. dspi_ctar0 field description in slave mode field descriptions 0?4 fmsz[0:4] frame size the number of bits transferred per frame is equal fmsz field value plus 1. minimum valid fmsz field value is 3. 5 cpol clock polarity the cpol bit selects the inactive state of the serial communications clock (sck). 0 the inactive state value of sck is low 1 the inactive state value of sck is high 6 cpha clock phase the cpha bit selects which edge of sck causes data to change and which edge causes data to be captured. 0 data is captured on the leading edge of sck and changed on the following edge 1 data is changed on the leading edge of sck and captured on the following edge 7 pe parity enable pe bit enables parity bit transmission and reception for the frame 0 no parity bit included/checked. 1 parity bit is transmitted instead of last data bit in frame, parity checked for received frame. 8 pp parity polarity pp bit controls polarity of the parity bit transmitted and checked 0 even parity: number of ?1? bits in the transmitted frame is even. the dspi_sr[spef] bit is set if in the received frame number of ?1? bits is odd. 1 odd parity: number of ?1? bits in the transmitted frame is odd. the dspi_sr[spef] bit is set if in the received frame number of ?1? bits is even. 29?31 ? not used, write always zero to keep software compatible with future updates. deserial serial peripheral interface (dspi) RM0029 1286/1740 doc id 15177 rev 8 figure 715. dspi status register (dspi_sr) address: dspi_base + 0x2c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r tcf txrxs 0 eoqf tfuf 0 tfff 0 0 dpef spef ddif rfof 0 rfdf 0 ww1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00 00000000 000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txctr txnxtptr rxctr popnxtptr w reset00 00000000 000000 table 690. dspi_sr field description field description 0 tcf transfer complete flag the tcf bit indicates that all bits in a frame have been shifted out. the tcf bit remains set until cleared by writing 1 to it. 0 transfer not complete 1 transfer complete 1 txrxs tx & rx status the txrxs bit reflects the run status of the dspi. section 30.9.1, start and stop of dspi transfers explains what causes this bit to be set or cleared. 0 tx and rx operations are disabled (dspi is in stopped state) 1 tx and rx operations are enabled (dspi is in running state) 2 reserved, should be cleared. 3 eoqf end of queue flag the eoqf bit indicates that the last entry in a queue has been transmitted when the dspi in the master mode. the eoqf bit is set when tx fifo entry has the eoq bit set in the command halfword and the end of the transfer is reached. the eoqf bit remains set until cleared by writing 1 to it. when the eoqf bit is set, the txrxs bit is automatically cleared. 0 eoq is not set in the executed command 1 eoq bit is set in the executed spi command 4 tfuf transmit fifo underflow flag the tfuf bit indicates that an underflow condition in the tx fifo has occurred. the transmit underflow condition is detected only for dspi modules operating in slave mode and spi configuration. the tfuf bit is set when the tx fifo of a dspi operating in spi slave mode is empty, and a transfer is initiated by an external spi master. the tfuf bit remains set until cleared by writing 1 to it. 0 tx fifo underflow has not occurred 1 tx fifo underflow has occurred 5 reserved, should be cleared. RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1287/1740 6 tfff transmit fifo fill flag the tfff bit provides a method for the dspi to request more entries to be added to the tx fifo. the tfff bit is set while the tx fifo is not full. the tfff bit can be cleared by writing 1 to it or by acknowledgement from the dma controller to the tx fifo full request. 0 tx fifo is full 1 tx fifo is not full 7?8 reserved, should be cleared. 9 dpef dsi parity error flag the dpef flag indicates that a dsi frame with parity error had been received. the bit remains set until cleared by writing 1 to it. 0 parity error has not occurred 1 parity error has occurred 10 spef spi parity error flag the spef flag indicates that a spi frame with parity error had been received. the bit remains set until cleared by writing 1 to it. 0 parity error has not occurred 1 parity error has occurred 11 ddif dsi data received with active bits the ddif flag indicates that dsi frame had been received with bits, selected by dspi_dimr with active polarity, defined by dspi_dpir. the bit remains set until cleared by writing 1 to it. 0 no dsi data with active bits was received 1 dsi data with active bits was received 12 rfof receive fifo overflow flag the rfof bit indicates that an overflow condition in the rx fifo has occurred. the bit is set when the rx fifo and shift register are full and a transfer is initiated. the bit remains set until cleared by writing 1 to it. 0 rx fifo overflow has not occurred 1 rx fifo overflow has occurred 13 reserved, should be cleared. 14 rfdf receive fifo drain flag the rfdf bit provides a method for the dspi to request that entries be removed from the rx fifo. the bit is set while the rx fifo is not empty. the rfdf bit can be cleared by writing 1 to it or by acknowledgement from the dma controller when the rx fifo is empty. 0rx fifo is empty 1 rx fifo is not empty 15 reserved. 16?20 txctr tx fifo counter the txctr field indicates the number of valid entries in the tx fifo. the txctr is incremented every time the dspi _pushr is written. the txctr is decremented every time a spi command is executed and the spi data is transferred to the shift register. 20?23 txnxtptr transmit next pointer the txnxtptr field indicates which tx fifo entry is transmitted during the next transfer. the txnxtptr field is updated every time spi data is transferred from the tx fifo to the shift register. see section , transmit fifo underflow interrupt request for more details. table 690. dspi_sr field description (continued) field description deserial serial peripheral interface (dspi) RM0029 1288/1740 doc id 15177 rev 8 dspi dma/interrupt request select and enable register (dspi_rser) the dspi_rser controls dma and interrupt requests. do not write to the dspi_rser while the dspi is in the running state. 24?27 rxctr rx fifo counter the rxctr field indicates the number of entries in the rx fifo. the rxctr is decremented every time the dspi _popr is read. the rxctr is incremented every time data is transferred from the shift register to the rx fifo. 28?31 popnxtptr pop next pointer the popnxtptr field contains a pointer to the rx fifo entry that will be returned when the dspi_popr is read. the popnxtptr is u pdated when the dspi_popr is read. see section , receive first-in first-out (rx fifo) buffering mechanism for more details. table 690. dspi_sr field description (continued) field description figure 716. dspi dma/interrupt request select and enable register (dspi_rser) address: dspi_base + 0x30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r tcf_re 00 eoqfre tfufre 0 tfffre tfffdirs 0 dpefre spefre ddifre rfofre 0 rfdfre rfdfdirs w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 691. dspi_rser field description field description 0 tcf_re transmission complete request enable the tcf_re bit enables tcf flag in the dspi_sr to generate an interrupt request. 0 tcf interrupt requests are disabled 1 tcf interrupt requests are enabled 1?2 reserved, should be cleared. 3 eoqfre dspi finished request enable the eoqfre bit enables the eoqf flag in the dspi_sr to generate an interrupt request. 0 eoqf interrupt requests are disabled 1 eoqf interrupt requests are enabled RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1289/1740 4 tfufre transmit fifo underflow request enable the tfufre bit enables the tfuf flag in the dspi_sr to generate an interrupt request. 0 tfuf interrupt requests are disabled 1 tfuf interrupt requests are enabled 5 reserved, should be cleared. 6 tfffre transmit fifo fill request enable the tfffre bit enables the tfff flag in the dspi_sr to generate a request. the tfffdirs bit selects between generating an interrupt request or a dma requests. 0 tfff interrupt requests or dma requests are disabled 1 tfff interrupt requests or dma requests are enabled 7 tfffdirs transmit fifo fill dma or interrupt request select the tfffdirs bit selects between generating a dma request or an interrupt request. when the tfff flag bit in the dspi_sr is set, and the tfffre bit in the dspi_rser is set, this bit selects between generating an interrupt request or a dma request. 0 interrupt request will be generated 1 dma request will be generated 8 reserved, should be cleared. 9 dpefre dsi parity error request enable the dpefre bits enables dpef flag in the dspi_sr to generate an interrupt requests. 0 pef interrupt requests are disabled 1 pef interrupt requests are enabled 10 spefre spi parity error request enable the spefre bits enables spef flag in the dspi_sr to generate an interrupt requests. 0 pef interrupt requests are disabled 1 pef interrupt requests are enabled 11 ddifre dsi data received with active bits request enable the ddifre bit enables the ddif flag in the dspi_sr to generate an interrupt requests. 0 ddif interrupt requests are disabled 1 ddif interrupt requests are enabled 12 rfofre receive fifo overflow request enable the rfofre bit enables the rfof flag in the dspi_sr to generate an interrupt requests. 0 rfof interrupt requests are disabled 1 rfof interrupt requests are enabled 13 reserved, should be cleared. table 691. dspi_rser field description (continued) field description deserial serial peripheral interface (dspi) RM0029 1290/1740 doc id 15177 rev 8 dspi push tx fifo register (dspi_pushr) the dspi_pushr provides means to write to the tx fifo. data written to this register is transferred to the tx fifo. see section , transmit first-in first-out (tx fifo) buffering mechanism for more information. eight or 16-bit write accesses to the dspi_pushr transfers all 32 register bits to the tx fifo. the register structure is different in master and slave modes. in master mode the register provides 16-bit commands and 16-bit data to the tx fifo. in slave mode all 32 register bits can be used as data, supporting up to 32-bit spi frame operation. 14 rfdfre receive fifo drain request enable the rfdfre bit enables the rfdf flag in the dspi_sr to generate a request. the rfdfdirs bit selects between generating an interrupt request or a dma request. 0 rfdf interrupt requests or dma requests are disabled 1 rfdf interrupt requests or dma requests are enabled 15 rfdfdirs receive fifo drain dma or interrupt request select the rfdfdirs bit selects between generating a dma request or an interrupt request. when the rfdf flag bit in the dspi_sr is set, and the rfdfre bit in the dspi_rser is set, the rfdfdirs bit selects between generating an interrupt request or a dma request. 0 interrupt request will be generated 1 dma request will be generated table 691. dspi_rser field description (continued) field description figure 717. dspi push tx fifo register (dspi_pushr) in master mode address: dspi_base + 0x34 01234 5 6789101112131415 r cont ctas eoq ctcnt pe pp pcs7 pcs6 pcs5 pcs4 pcs3 pcs2 pcs1 pcs0 w reset00000 0 0000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txdata w reset00000 0 0000000000 RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1291/1740 table 692. dspi_pushr field description in master mode field descriptions 0 cont continuous peripheral chip select enable the cont bit selects a continuous selection format. the bit is used in spi master mode. the bit enables the selected pcs signals to remain asserted between transfers. see section , continuous selection format for more information. 0 return peripheral chip select signals to their inactive state between transfers 1 keep peripheral chip select signals asserted between transfers 1?3 ctas[0:2] clock and transfer attributes select the ctas field selects the number of the dspi_ctar to be used to set the transfer attributes for the associated spi frame. the field is only used in spi master mode. in spi slave mode dspi_ctar0 is used. the number of dspi_ctar registers is implementation specific and the ctas should be set to select only implemented one. 4 eoq end of queue the eoq bit provides a means for host software to signal to the dspi that the current spi transfer is the last in a queue. at the end of the transfer the eoqf bit in the dspi_sr is set. 0 the spi data is not the last data to transfer 1 the spi data is the last data to transfer 5 ctcnt clear transfer counter the ctcnt bit clears field dspi_tcr[tcnt]. the tcnt field is cleared before transmission of the current spi frame begins. 0 do not clear field dspi_tcr[tcnt] 1 clear field dspi_tcr[tcnt] 6 pe parity enable pe bit enables parity bit transmission and parity reception check for the spi frame 0 no parity bit included/checked. 1 parity bit is transmitted instead of last data bit in frame, parity checked for received frame. 7 pp parity polarity pp bit controls polarity of the parity bit transmitted and checked 0 even parity: number of ?1? bits in the transmitted frame is even. the dspi_sr[spef] bit is set if in the received frame number of ?1? bits is odd. 1 odd parity: number of ?1? bits in the transmitted frame is odd. the dspi_sr[spef] bit is set if in the received frame number of ?1? bits is even. 8?15 pcs x peripheral chip select 0?7 the pcs bits select which pcs signals will be asserted for the transfer. 0 negate the pcs[x] signal 1 assert the pcs[x] signal 16?31 txdata[0:15] transmit data the txdata field holds spi data to be transferred according to the associated spi command. deserial serial peripheral interface (dspi) RM0029 1292/1740 doc id 15177 rev 8 dspi pop rx fifo register (dspi_popr) the dspi_popr provides the means to read the rx fifo. see section , receive first-in first-out (rx fifo) buffering mechanism for a description of the rx fifo operations. eight or 16-bit read accesses to the dspi_popr have the same effect on the rx fifo as 32-bit read access. figure 718. dspi push tx fifo register (dspi_pushr) in slave mode address: dspi_base + 0x34 0123456789101112131415 r txdata w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txdata w reset0000000000000000 table 693. dspi_pushr field description in slave mode field descriptions 0?31 txdata[0:31] transmit data the txdata field holds spi data to be transferred. figure 719. dspi pop rx fifo register (dspi_popr) address: dspi_base + 0x38 01 2 3456789101112131415 rrxdata w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrxdata w reset00 00000000000000 RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1293/1740 dspi transmit fifo registers 0?15 (dspi_txfr0?dspi_txfr15) the dspi_txfr0 ? dspi_txfr15 registers provide visibility into the tx fifo for debugging purposes. each register is an entry in the tx fifo. the registers are read-only and cannot be modified. reading the dspi_txfrx registers does not alter the state of the tx fifo. the number of registers used to implement the tx fifo is device specific. if a four-entry tx fifo is implemented, dspi_txfr0 ? dspi_txfr3 are accessible. dspi receive fifo registers 0?15 (dspi_rxfr0?dspi_rxfr15) the dspi_rxfr0 ? dspi_rxfr15 registers provide visibility into the rx fifo for debugging purposes. each register is an entry in the rx fifo. the dspi_rxfr registers are read-only. reading the dspi_rxfrx registers does not alter the state of the rx fifo. the number of registers used to implement the rx fifo is device specific. if a four-entry rx fifo is implemented, dspi_rxfr0 ? dspi_rxfr3 exist, for example. table 694. dspi_popr field description field description 0?31 rxdata[0:31] received data the rxdata field contains the spi data from the rx fifo entry pointed to by the pop next data pointer. figure 720. dspi transmit fifo register 0?15 (dspi_txfr0?dspi_txfr15) address: dspi_base+0x3c?dspi_base+0x78 01 2 3456789101112131415 r txcmd/txdata w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rtxdata w reset00 00000000000000 table 695. dspi_txfr n field description field description 0?15 txcmd[0:15]/ txdata[0:15] transmit command or transmit data in master mode the txcmd field contains the command that sets the transfer attributes for the spi data. see section , dspi push tx fifo register (dspi_pushr) for details on the command field. in slave mode the txdata contains 16 msb bits of the spi data to be shifted out 16?31 txdata[16:31 ] transmit data the txdata field contains the spi data to be shifted out. deserial serial peripheral interface (dspi) RM0029 1294/1740 doc id 15177 rev 8 dspi dsi configuration register (dspi_dsicr) the dsi configuration register selects various attributes associated with dsi and csi configurations. do not write to the dspi_dsicr, while the dspi is in the running state. figure 721. dspi receive fifo registers 0?15 (dspi_rxfr0?dspi_rxfr15) address: dspi_base + 0x7c?dspi_base + 0xb8 0123456789101112131415 r rxdata w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rxdata w reset0000000000000000 table 696. dspi_rxfr n field description field description 0?31 rxdata[0:31] receive data the rxdata field contains the received spi data. figure 722. dspi dsi configuration register (dspi_dsicr) address: dspi_base + 0xbc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mtoe fmsz[4] mtocnt 000 tsbc txss tpo l trre cid w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dcont dsictas dms pe s pe pp dpcs7 dpcs6 dpcs5 dpcs4 dpcs3 dpcs2 dpcs1 dpcs0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1295/1740 table 697. dspi_dsicr field description field description 0 mtoe multiple transfer operation enable the mtoe bit enables multiple dspis to be connected in a parallel or serial configuration. see section , multiple transfer operation (mto) for more information. 0 multiple transfer operation disabled 1 multiple transfer operation enabled the mtoe and tsb bits should not be set simultaneously. 1 msb of the frame size if the bit is set, 16 is added to the frame size, defined by field dspi_ctarn[fmsz]. dspi_ctarn register is selected by field dspi_dsicr[dsictas]. 2?7 mtocnt[0:5] multiple transfer operation count the mtocnt field selects number of bits to be shifted out during a transfer in multiple transfer operation. the field sets the number of sck cycles that the bus master will generate to complete the transfer. the number of sck cycles used will be one more than the value in the mtocnt field. the number of sck cycles defined by mtocnt must be equal to or greater than the frame size. when tsbc is set, mtocnt field has no effect. 8?10 reserved, should be cleared. 11 tsbc timed serial bus configuration the tsbc bit enables the timed serial bus configuration. this configuration allows 32-bit data to be used. it also allows t dt to be programmable. see section 30.9.8, timed serial bus (tsb) for detailed information. 0 timed serial bus configuration disabled 1 timed serial bus configuration enabled if this bit is clear the dspi_dsicr1 register value has no effect. 12 txss transmit data source select the txss bit selects the source of data to be serialized. the source can be either data from host software written to the dspi dsi alternate serialization data register (dspi_asdr), or parallel input pin states latched into the dspi dsi serialization data register (dspi_sdr). 0 source of serialized data is the dspi_sdr 1 source of serialized data is the dspi_asdr 13 tpol trigger polarity the tpol bit selects the active edge of the hardware trigger input signal (ht). initiating dsi frames transfer. see section , dsi transfer initiation control for more information. 0 falling edge will initiate a transfer 1 rising edge will initiate a transfer 14 trre trigger reception enable the trre bit enables the dspi to initiate dsi frames transfer with external trigger signal. see section , dsi transfer initiation control for more information. 0trigger signal reception disabled 1 trigger signal reception enabled 15 cid change in data transfer enable the cid bit enables a change in serialization data to initiate dsi frames transfer. in dsi and csi configurations. when the cid bit is set, dsi frames are initiated when the current dsi data differs from the previous dsi data shifted out. refer to section , dsi transfer initiation control for more information. deserial serial peripheral interface (dspi) RM0029 1296/1740 doc id 15177 rev 8 dspi dsi serialization data register (dspi_sdr) the dspi_sdr contains the states of the parallel input signals. the states of the parallel input signals are latched into the dspi_sdr on the rising edge of every system clock. the dspi_sdr is read-only. when the txss bit in the dspi_dsicr is cleared, the data in the dspi_sdr is used as the source of the dsi frames. 16 dcont dsi continuous peripheral chip select enable the dcont bit enables the pcs signals to remain asserted between transfers. the dcont bit only affects the pcs signals in dsi master mode. see section , continuous selection format for details. when tsbc bit is set, dcont bit has no effect. 0 return peripheral chip select signals to their inactive state after transfer is complete 1 keep peripheral chip select signals asserted after transfer is complete 17?19 dsictas[0:2] dsi clock and transfer attributes select the dsictas field selects which of the dspi_ctar re gisters is used to provide transfer attributes for dsi frames. the dsictas field is used in dsi master mode. in dsi slave mode, the dspi_ctar1 is always selected. 20 dms data match stop. dms bit if set stops dsi frames transmissions if ddif flag is set in the dspi_sr register. 0 ddif flag does not have effect on dsi frames transmissions. 1 ddif flag stops dsi frame transmissions. 21 pes parity error stop. pes bit if set stops dsi operation if the parity error had happened in received dsi frame. 0 parity error does not stop dsi frame transmissions. 1 parity error stops all dsi frame transmissions 22 pe parity enable. pe bit enables parity bit transmission and parity reception check for the dsi frames 0 no parity bit included/checked. 1 parity bit is transmitted instead of last data bit in frame, parity checked for received frame 23 pp parity polarity. pp bit controls polarity of the parity bit transmitted and checked 0 even parity: number of ?1? bits in the transmitted frame is even. the dspi_sr[dpef] bit is set if in the received frame number of ?1? bits is odd. 1 odd parity: number of ?1? bits in the transmitted frame is odd. the dspi_sr[dpef] bit is set if in the received frame number of ?1? bits is even 24?31 dpcs x dsi peripheral chip select 0?7 the dpcs bits select which of the pcs signals to assert during a dsi master mode transfer. 0 negate pcs[x] 1 assert pcs[x] table 697. dspi_dsicr field description (continued) field description RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1297/1740 dspi dsi alternate serialization data register (dspi_asdr) the dspi_asdr provides means for host software to write the data to be serialized. when the txss bit in the dspi_dsicr is set, the data in the dspi_asdr is the source of the dsi frames. writes to the dspi_asdr take effect on the next frame boundary. figure 723. dspi dsi serialization data register (dspi_sdr) address: dspi_base + 0xc0 01 2 3456789101112131415 r ser_data w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ser_data w reset00 00000000000000 table 698. dspi_sdr field description field description 0?31 ser_data [30:31] serialized data the ser_data field contains the signal states of the parallel input signals. figure 724. dspi dsi alternate serialization data register (dspi_asdr) address: dspi_base + 0xc4 01 2 3456789101112131415 r aser_data w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r aser_data w reset00 00000000000000 deserial serial peripheral interface (dspi) RM0029 1298/1740 doc id 15177 rev 8 dspi dsi transmit comparison register (dspi_compr) the dspi_compr holds a copy of the last transmitted dsi data. the dspi_compr is read-only. dsi data is transferred to this register as it is loaded into the tx shift register. dspi dsi deserialization data register (dspi_ddr) the dspi_ddr holds the signal states for the parallel output signals. the dspi_ddr is read-only and host software can read data from incoming dsi frames. table 699. dspi_asdr field description field descriptions 0?31 aser_data [0:31] alternate serialized data the aser_data field holds the alternate data to be serialized. figure 725. dspi dsi transmit comparison register (dspi_compr) address: dspi_base + 0xc8 01 2 3456789101112131415 rcomp_data w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rcomp_data w reset00 00000000000000 table 700. dspi_compr field description field description 0?31 comp_data[0:31 ] compare data the comp_data field holds the last serialized dsi data. RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1299/1740 dspi dsi configuration register 1 (dspi_dsicr1) the dsi configuration register 1 selects various attributes associated with tsb configuration. the user must not write to the dspi_dsicr1 while the dspi is in the running state. if tsbc bit is cleared the register value is ignored. figure 726. dspi deserialization data register (dspi_ddr) address: dspi_base + 0xcc 01 2 3456789101112131415 r deser_data w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r deser_data w reset00 00000000000000 table 701. dspi_ddr field description field descriptions 0?31 deser_dat a[0:31] deserialized data the deser_data field holds deserialized data which is presented as signal states to the parallel output signals. figure 727. dspi dsi configuration register 1 (dspi_dsicr1) address: dspi_base + 0xd0 0123456789101112131415 r0 0 0 tsbcnt 000000 dse1 dse2 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 dpcs1_7 dpcs1_6 dpcs1_5 dpcs1_4 dpcs1_3 dpcs1_2 dpcs1_1 dpcs1_0 w reset0000000000000000 deserial serial peripheral interface (dspi) RM0029 1300/1740 doc id 15177 rev 8 dspi dsi serialization source select register (dspi_ssr) dspi dsi serialization source select register provides means to create combined frame for transmission, containing bits from dspi_asdr register and from dspi_sdr register. each bit in the dspi_ssr register selects corresponding bit to be serialized. when dspi_dsicr[txss] is set, the dspi_ssr register value has no effect. table 702. dspi_dsicr1 field description field description 0?2 reserved, should be cleared. 3?7 tsbcnt[0:4] timed serial bus operation count when tsbc is set, tsbcnt defines the length of the data frame. tsbcnt field valid value is from 3 to 31. the tsbcnt field selects number of data bits to be shifted out during a transfer in tsb mode. the number of data bits in the data frame is one more than the value in the tsbcnt field. 8?13 reserved, should be cleared. 14 dse1 data select enable1. when tbsc bit is set, the dse1 bit controls insertion of the zero bit (data select) in the middle of the data frame. the insertion bit position is defined by fmsz field of dspi_ctarn register, selected by dsictas field of the dspi_dsicr register. 0 no zero bit inserted in the middle of the data frame. 1 zero bit is inserted at the middle of the data frame. total number of bits in the data frame is increased by 1. 15 dse0 data select enable0. when tbsc bit is set, the dse0 bit controls insertion of the zero bit (data select) in the beginning of the data frame. 0 no zero bit inserted in the beginning of the frame. 1 zero bit is inserted at the beginning of the data frame. total number of bits in the data frame is increased by 1. 16?23 reserved, should be cleared. 24?31 dpcs1_ x dsi peripheral chip select 0?7 these bits define the pcss to assert for the second part of the dsi frame when operating in tsb configuration with dual receiver. the dpcs1 bits select which of the pcs signals to assert during the second part of the dsi frame. the dpcs1 bits only control the assertions of the pcs signals in tsb mode. 0 negate pcs[x] 1 assert pcs[x] RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1301/1740 dspi dsi parallel input select registers 0 - 3 (dpsi_pisr0 - dpsi_pisr3) dspi dsi parallel input select registers 0 - 3 provide means to select each data bit for transmitted frame from 16 parallel input pins. each input pin select (ips) field controls one bit in the transmitted frame. each register contains control fields for 8 bits in the frame. the select field value is defined as 4 bits signed integer number. selected parallel input pin number is defined as a sum of the field number and field value. for example, if ips16 is equal binary number 1111 (minus 1 decimal) bit 16 in the frame will be taken from parallel input pin number 15. when the ips0 is equal -1, the bit 0 in the frame is taken from parallel input 31. when the ips0 is equal +1, the bit 0 in the frame is taken from parallel input 1 and etc. please, note that the dspi_pisr0-3 only preselect parallel input pins, final selection to the transmitted frame is done by dspi_ssr register bits or dspi_dsicr[txss] bit. figure 728. dspi dsi serialization source select register (dspi_ssr) address: dspi_base + 0xd4 access: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ss w reset00 00000000000000 1514131211109876543210 r ss w reset00 00000000000000 table 703. dspi_ssr field descriptions field description 31?0 ss[31:0] source select. the ss bits select serialization source for dsi frame. each ss bit selects data for corresponded bit in the transmitted frame. 0 the bit in transmitted frame is taken from parallel input pin; 1 the bit in transmitted frame is taken from dspi_asdr register deserial serial peripheral interface (dspi) RM0029 1302/1740 doc id 15177 rev 8 figure 729. dspi dsi parallel input select register 0 (dspi_pisr0) address: dspi_base + 0xd8 access: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ips7 ips6 ips5 ips4 w reset00 00000000000000 1514131211109876543210 r ips3 ips2 ips1 ips0 w reset00 00000000000000 table 704. dspi_pisr0 field descriptions field description 31?28 ips7 input pin select 7. the ips7 field selects parallel input pin for transmitted frame bit 7. 27?24 ips6 input pin select 6. the ips6 field selects parallel input pin for transmitted frame bit 6. 23?20 ips5 input pin select 5. the ips5 field selects parallel input pin for transmitted frame bit 5. 19?16 ips4 input pin select 4. the ips4 field selects parallel input pin for transmitted frame bit 4. 15?12 ips3 input pin select 3. the ips3 field selects parallel input pin for transmitted frame bit 3. 11?8 ips2 input pin select 2. the ips2 field selects parallel input pin for transmitted frame bit 2. 7?4 ips1 input pin select 1. the ips1 field selects parallel input pin for transmitted frame bit 1. 3?0 ips0 input pin select 0. the ips0 field selects parallel input pin for transmitted frame bit 0. RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1303/1740 figure 730. dspi dsi parallel input select register 1 (dspi_pisr1) address: dspi_base + 0xdc access: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ips15 ips14 ips13 ips12 w reset00 00000000000000 1514131211109876543210 r ips11 ips10 ips9 ips8 w reset00 00000000000000 table 705. dspi_pisr1 field descriptions field description 31?28 ips15 input pin select 15. the ips15 field selects parallel input pin for transmitted frame bit 15. 27?24 ips14 input pin select 14. the ips14 field selects parallel input pin for transmitted frame bit 14. 23?20 ips13 input pin select 13. the ips13 field selects parallel input pin for transmitted frame bit 13. 19?16 ips12 input pin select 12. the ips12 field selects parallel input pin for transmitted frame bit 12. 15?12 ips11 input pin select 11. the ips11 field selects parallel input pin for transmitted frame bit 11. 11?8 ips10 input pin select 10. the ips10 field selects parallel input pin for transmitted frame bit 10. 7?4 ips9 input pin select 9. the ips9 field selects parallel input pin for transmitted frame bit 9. 3?0 ips8 input pin select 8. the ips8 field selects parallel input pin for transmitted frame bit 8. deserial serial peripheral interface (dspi) RM0029 1304/1740 doc id 15177 rev 8 figure 731. dspi dsi parallel input select register 2 (dspi_pisr2) address: dspi_base + 0xe0 access: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ips23 ips22 ips21 ips20 w reset00 00000000000000 1514131211109876543210 r ips19 ips18 ips17 ips16 w reset00 00000000000000 table 706. dspi_pisr2 field descriptions field description 31?28 ips23 input pin select 23. the ips23 field selects parallel input pin for transmitted frame bit 23. 27?24 ips22 input pin select 22. the ips22 field selects parallel input pin for transmitted frame bit 22. 23?20 ips21 input pin select 21. the ips21 field selects parallel input pin for transmitted frame bit 21. 19?16 ips20 input pin select 20. the ips20 field selects parallel input pin for transmitted frame bit 20. 15?12 ips19 input pin select 19. the ips19 field selects parallel input pin for transmitted frame bit 19. 11?8 ips18 input pin select 18. the ips18 field selects parallel input pin for transmitted frame bit 18. 7?4 ips17 input pin select 17. the ips17 field selects parallel input pin for transmitted frame bit 17. 3?0 ips16 input pin select 16. the ips16 field selects parallel input pin for transmitted frame bit 16. RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1305/1740 dspi dsi deserialized data interrupt mask register (dspi_dimr) the dspi dsi deserialized data interrupt mask register selects bits in the received dsi frame to be checked to generate the ddi interrupt. figure 732. dspi dsi parallel input select register 3 (dspi_pisr3) address: dspi_base + 0xe4 access: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ips31 ips30 ips29 ips28 w reset00 00000000000000 1514131211109876543210 r ips27 ips26 ips25 ips24 w reset00 00000000000000 table 707. dspi_pisr3 field descriptions field description 31?28 ips31 input pin select 31. the ips31 field selects parallel input pin for transmitted frame bit 31. 27?24 ips30 input pin select 30. the ips30 field selects parallel input pin for transmitted frame bit 30. 23?20 ips29 input pin select 29. the ips29 field selects parallel input pin for transmitted frame bit 29. 19?16 ips28 input pin select 28. the ips28 field selects parallel input pin for transmitted frame bit 28. 15?12 ips27 input pin select 27. the ips27 field selects parallel input pin for transmitted frame bit 27. 11?8 ips26 input pin select 26. the ips26 field selects parallel input pin for transmitted frame bit 26. 7?4 ips25 input pin select 25. the ips25 field selects parallel input pin for transmitted frame bit 25. 3?0 ips24 input pin select 24. the ips24 field selects parallel input pin for transmitted frame bit 24. deserial serial peripheral interface (dspi) RM0029 1306/1740 doc id 15177 rev 8 dspi dsi deserialized data polarity interrupt register (dspi_dpir) the dspi dsi deserialized data polarity interrupt register defines what data bits value in thereceived dsi frame generates the ddi interrupt. figure 733. dspi dsi deserialized data interrupt mask register (dspi_dimr) address: dspi_base + 0xe8 access: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r mask w reset00 00000000000000 1514131211109876543210 r mask w reset00 00000000000000 table 708. dspi_dimr field descriptions field description 31?0 mask[31:0] mask. the mask bits define which bits in received deserialization data should be checked to produce the deserialized data interrupt (ddi). 0 the bit in received dsi frame does not produce ddi interrupt. 1 the bit in received dsi frame can produce ddi interrupt if the data bit matches to configured polarity. figure 734. dspi dsi deserialized data polarity interrupt register (dspi_dipr) address: dspi_base + 0xec access: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r dp w reset00 00000000000000 1514131211109876543210 r dp w reset00 00000000000000 RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1307/1740 30.9 functional description the deserial serial peripheral interface (dspi) module supports full-duplex, synchronous serial communications between mcus and peripheral devices. the dspi can also be used to reduce the number of pins required for i/o by serializing and deserializing up to 32 parallel input/output signals. all communications are done with spi-like protocol. the dspi has three configurations: spi configuration in which the dspi operates as a basic spi or a queued spi. dsi configuration in which the dspi serializes and deserializes parallel input/output signals or bits from memory mapped register. csi configuration in which the dspi combines the functionality of the spi and dsi configurations. field dspi_mcr[dconf] determines the dspi configuration. see table 682 for the dspi configuration values. registers dspi_ctar0 ? dspi_ctar7 hold clock and transfer attributes. the spi configuration allows to select which dspi_ctar to use on a frame by frame basis by setting a field in the spi command. the dsi configuration statically selects which dspi_ctar to use. in csi configuration priority logic determines if spi data or dsi data is transferred and dictates what dspi_ctar is used for the data transfer. see section , dspi clock and transfer attributes registers 0?7 (dspi_ctar0?dspi_ctar7) for information on the fields of the dspi_ctar registers. typical master to slave connections are shown in figure 735 . when a data transfer operation is performed, data is serially shifted a predetermined number of bit positions. because the modules are linked, data is exchanged between the master and the slave. the data that was in the master shift register is now in the shift register of the slave, and vice versa. at the end of a transfer, bit dspi_sr[tcf] is set to indicate a completed transfer. figure 735. spi and dsi serial protocol overview table 709. dspi_dipr field descriptions field description 31?0 dp[31:0] data polarity. the dp bits define what value of the received deserialization data sets the dspi_sr[ddif] bit. 0 if received bit is 0 the dspi_sr[ddif] bit is set. 1 if received bit is 1 the dspi_sr[ddif] bit is set. shift register baud rate generator shift register sin sin sout sout sck sck ss pcsx dspi master dspi slave deserial serial peripheral interface (dspi) RM0029 1308/1740 doc id 15177 rev 8 generally more than one slave device can be connected to the dspi master. eight peripheral chip select (pcs) signals of the dspi masters can be used to select which of the slaves to communicate with. the three dspi configurations share transfer protocol and timing properties which are described independently of the configuration in section 30.9.6, transfer formats . the transfer rate and delay settings are described in section 30.9.5, dspi baud rate and clock delay generation . 30.9.1 start and stop of dspi transfers the dspi has two operating states: stopped a nd running. the states are independent of dspi configuration. the default state of the dspi is stopped. in the stopped state no serial transfers are initiated in master mode and no transfers are responded to in slave mode. the stopped state is also a safe state for writing the various configuration registers of the dspi without causing undetermined results. in the running state serial transfers take place. bit dspi_sr[txrxs] indicates the dspi?s operating state. the bit is set if the module is in running state. the dspi is started (dspi transitions to running) when all of the following conditions are true: dspi_sr[eoqf] bit is clear device is not in the debug mode is or the dspi_mcr[frz] bit is clear dspi_mcr[halt] bit is clear the dspi stops (transitions from running to sto pped) after the current frame when any one of the following conditions exist: dspi_sr[eoqf] bit is set device in the debug mode and the dspi_mcr[frz] bit is set dspi_mcr[halt] bit is set state transitions from running to stopped occur on the next frame boundary if a transfer is in progress, or immediately if no transfers are in progress. 30.9.2 serial peripheral in terface (spi) configuration the spi configuration transfers data serially using a shift register and a selection of programmable transfer attributes. the dspi is in spi configuration when field dspi_mcr[dconf] is 0b00. the spi frames can be from 4 to 16 bits long. host cpu or a dma controller transfer the spi data from the external to dspi ram queues to a transmit first-in first-out (tx fifo) buffer. the received data is stored in entries in the receive fifo (rx fifo) buffer. host cpu or the dma controller transfer the received data from the rx fifo to memory external to the dspi. the fifo buffers operation is described in section , transmit first-in first-out (tx fifo) buffering mechanism and section , receive first-in first-out (rx fifo) buffering mechanism . the interrupt and dma request conditions are described in section 30.9.10, interrupts/dma requests . the spi configuration supports two module-specific modes: master mode and slave mode. the fifo operations are similar for both modes. the main difference is that in master mode the dspi initiates and controls the transfer according to the fields in the spi command field of the tx fifo entry. in slave mode the dspi only responds to transfers initiated by a bus master external to the dspi and the spi command field space is used for the 16 most significant bits of the transmit data. RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1309/1740 master mode in spi master mode the dspi initiates the serial transfers by controlling the serial communications clock (sck) and the peripheral chip select (pcs) signals. the spi command field in the executing tx fifo entry determines which of the dspi_ctar registers will be used to set the transfer attributes and which pcs signal to assert. the command field also contains various bits that help with queue management and transfer protocol. see section , dspi push tx fifo register (dspi_pushr) for details on the spi command fields. the data field in the executing tx fifo entry is loaded into the shift register and shifted out on the serial out (sout) pin. in spi master mode, each spi frame to be transmitted has a command associated with it allowing for transfer attribute control on a frame by frame basis. slave mode in spi slave mode the dspi responds to transfers initiated by a spi bus master. the dspi does not initiate transfers. certain transfer attributes such as clock polarity, clock phase and frame size must be set for successful communication with a spi master. the spi slave mode transfer attributes are set in the dspi_ctar0. fifo disable operation the fifo disable mechanisms allow spi transfers without using the tx fifo or rx fifo. the dspi operates as a double-buffered simplified spi when the fifos are disabled. the fifos are disabled separately; setting the dspi_mcr[dis_txf] bit disables the tx fifo, and setting the dspi_mcr[dis_rxf] bit disables the rx fifo. the fifo disable mechanisms are transparent to the user and to host software; transmit data and commands are written to the dspi_pushr and received data is read from the dspi_popr. when the tx fifo is disabled the tfff, tfuf and txctr fields in dspi_sr behave as if there is a one-entry fifo but the contents of the dspi_txfr registers and txnxtptr are undefined. likewise, when the rx fifo is disabled, the rfdf, rfof and rxctr fields in the dspi_sr behave as if there is a one-entry fifo, but the contents of the dspi_rxfr registers and popnxtptr are undefined. transmit first-in first-out (tx fifo) buffering mechanism the tx fifo functions as a buffer of spi data and spi commands for transmission. the tx fifo holds from 1 to 16 words, each consisting of a command field and a data field. the number of entries in the tx fifo is device specific. spi commands and data are added to the tx fifo by writing to the dspi push tx fifo register (dspi_pushr). tx fifo entries can only be removed from the tx fifo by being shifted out or by flushing the tx fifo. the tx fifo counter field dspi_sr[txctr] indicates the number of valid entries in the tx fifo. field dspi_sr[txctr] is updated every time the dspi _pushr is written or spi data is transferred into the shift register from the tx fifo. field dspi_sr[txnxtptr] indicates which tx fifo entry will be transmitted during the next transfer. field dspi_sr[txnxtptr] contains the positive offset from dspi_txfr0 in number of 32-bit registers. for example, txnxtptr equal to two means that the dspi_txfr2 contains the spi data and command for the next transfer. field dspi_sr[txnxtptr] is incremented every time spi data is transferred from the tx fifo deserial serial peripheral interface (dspi) RM0029 1310/1740 doc id 15177 rev 8 to the shift register. the maximum value of the field is equal to dspi_hcr[txfr] and it rolls over after reaching the maximum. filling the tx fifo host software or other intelligent blocks can add (push) entries to the tx fifo by writing to the dspi_pushr. when the tx fifo is not full, the tx fifo fill flag (tfff) in the dspi_sr is set. the tfff bit is cleared when tx fifo is full and the dma controller indicates that a write to dspi_pushr is complete. writing a ?1? to the tfff bit also clears it. the tfff can generate a dma request or an interrupt request. see section , transmit fifo fill interrupt or dma request for details. the dspi ignores attempts to push data to a full tx fifo, the state of the tx fifo does not change and no error condition is indicated. draining the tx fifo the tx fifo entries are removed (drained) by shifting spi data out through the shift register. entries are transferred from the tx fifo to the shift register and shifted out as long as there are valid entries in the tx fifo. every time an entry is transferred from the tx fifo to the shift register, the tx fifo counter decrements by one. at the end of a transfer, bit dspi_sr[tcf] is set to indicate the completion of a transfer. the tx fifo is flushed by writing a ?1? to bit dspi_mcr[clr_txf]. if an external bus master initiates a transfer with a dspi slave while the slave?s dspi tx fifo is empty, the transmit fifo underflow flag (tfuf) in the slave?s dspi_sr is set. see section , transmit fifo underflow interrupt request for details. receive first-in first-out (rx fifo) buffering mechanism the rx fifo functions as a buffer for data received on the sin pin. the rx fifo holds from 1 to 16 received spi data frames. the number of entries in the rx fifo is device specific. spi data is added to the rx fifo at the completion of a transfer when the received data in the shift register is transferred into the rx fifo. spi data are removed (popped) from the rx fifo by reading the dspi pop rx fifo register (dspi_popr). rx fifo entries can only be removed from the rx fifo by reading the dspi_popr or by flushing the rx fifo. the rx fifo counter field dspi_sr[rxctr] indicates the number of valid entries in the rx fifo. field dspi_sr[rxctr] is updated every time the dspi _popr is read or spi data is copied from the shift register to the rx fifo. field dspi_sr[popnxtptr] points to the rx fifo entry that is returned when the dspi_popr is read. field dspi_sr[popnxtptr] contains the positive offset from dspi_rxfr0 in number of 32-bit registers. for example, popnxtptr equal to two means that the dspi_rxfr2 contains the received spi data that will be returned when dspi_popr is read. field dspi_sr[popnxtptr] is incremented every time the dspi_popr is read. the maximum value of the field is equal to dspi_hcr[rxfr] and it rolls over after reaching the maximum. filling the rx fifo the rx fifo is filled with the received spi data from the shift register. while the rx fifo is not full, spi frames from the shift register are transferred to the rx fifo. every time a spi frame is transferred to the rx fifo the rx fifo counter is incremented by one. RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1311/1740 if the rx fifo and shift register are full and a transfer is initiated, the rfof bit in the dspi_sr is set indicating an overflow condition. depending on the state of the rooe bit in the dspi_mcr, the data from the transfer that generated the overflow is either ignored or shifted in to the shift register. if the rooe bit is set, the incoming data is shifted in to the shift register. if the rooe bit is cleared, the incoming data is ignored. draining the rx fifo host cpu or a dma can remove (pop) entries from the rx fifo by reading the dspi pop rx fifo register (dspi_popr). a read of the dspi_popr decrements the rx fifo counter by one. attempts to pop data from an empty rx fifo are ignored and the rx fifo counter remains unchanged. the data, read from the empty rx fifo, is undetermined. when the rx fifo is not empty, the rx fifo drain flag (rfdf) in the dspi_sr is set. the rfdf bit is cleared when the rx_fifo is empty and the dma controller indicates that a read from dspi_popr is complete or by writing a ?1? to it. 30.9.3 deserial serial interface (dsi) configuration the dsi configuration supports pin count reduction by serializing parallel input signals or register bits and shifting them out in a spi-like protocol. the timing and transfer protocol is described in section 30.9.6, transfer formats . the received serial frames are converted to a parallel form (deserialized) and placed on the parallel output signals or in the dspi_ddr. the various features of the dsi configuration are set in the dspi dsi configuration register (dspi_dsicr). the dsi frames can be from 4 to 32 bits. with multiple transfer operation (mto) the dspi supports serial chaining of dspi modules within a device to create dsi frames up to 64 bits, consisting of concatenated bits from multiple dspis. the dspi also supports parallel chaining allowing several dspis and off-chip spi devices to share the same serial communications clock (sck) and peripheral chip select (pcs) signals. see section , multiple transfer operation (mto) for details on the serial and parallel chaining support. dsi master mode in dsi master mode the dspi initiates and controls the dsi transfers. the dsi master has four different conditions that can initiate a transfer: continuous change in data trigger signal trigger signal combined with a change in data the four transfer initiation conditions are described in section , dsi transfer initiation control . transfer attributes are set during initialization. field dspi_dsicr[dsictas] determines which of the dspi_ctar registers will control the transfer attributes. slave mode in dsi slave mode the dspi responds to transfers initiated by a spi or dsi bus master. in this mode the dspi does not initiate dsi transfers. certain transfer attributes such as clock polarity and phase must be set for successful communication with a dsi master. the dsi slave mode transfer attributes are set in the dspi_ctar1. if the cid bit in the dspi_dsicr is set and the data in the dspi_compr differs from the selected source of the serialized data, the slave dspi will assert the mtrig signal. if the deserial serial peripheral interface (dspi) RM0029 1312/1740 doc id 15177 rev 8 slave?s ht signal is asserted and the trre is set, the slave dspi asserts mtrig . these features are included to support chaining of several dspi. details about the mtrig signal is found in section , multiple transfer operation (mto) . dsi serialization in the dsi configuration from 4 to 16 bits can be serialized using 2 different sources. the txss bit in the dspi_dsicr selects between the dspi dsi serialization data register (dspi_sdr) and the dspi dsi alternate serialization data register (dspi_asdr) as the source of the serialized data. the dspi_sdr holds the latest parallel input signal values which is sampled at every rising edge of the system clock. the dspi_asdr is written by host software and used as an alternate source of serialized data. the dspi_pisr0?3 registers allow to change relative position of the parallel input pins in the transmitted frame. each transmitted frame bit can be selected from 16 adjacent parallel inputs by writing ipsn fields. the ipsn field is treated as a 4-bit integer number, representing numbers from ? 8 to 7. the parallel input pin number, selected by ipsn field is defined by the difference between sum ipsn field number (n) and the ipsn field value. if the operation result is negative the number 32 should be added. if the result is higher than 32, 32 should be subtracted from the result. for example, ips0, set to minus 1 (binary 1111), preselects parallel input 1 to 0 position in the transmitted frame. ips6, set to 3 (binary 0011), preselects parallel input 3 to be bit number 6 in the transmitted frame, while the value minus 2 (1110) preselects parallel input 8. ips31, set to minus 8 (binary 1000), preselects parallel input 7 to be bit number 31 in the transmitted frame. (of course, the parallel input pin state, to be transmitted, should be selected by txss and the frame size should be higher than the bit position in the preselected frame.) the dspi_ssr provides additional way to create the frame for transmission. each bit from this register is or?d with the txss bit and controls individual transmitted bit source. this way, the transmitted frame can have any combination of the dspi_sdr and dspi_asdr bits. this feature allows control spi based devices, requiring control and data fields in the frame. control field may come from dspi_asdr, set by the device?s cpu, while data field can be generated by device peripheral modules, such as pwm timers. a copy of the last 32-bit dsi frame shifted out of the shift register is stored in the dspi dsi transmit comparison register (dspi_compr). this register provides added visibility for debugging and it serves as a reference for transfer initiation control. figure 736 shows the dsi serialization logic. RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1313/1740 figure 736. dsi serialization diagram dsi deserialization when all bits in a dsi frame have been shifted in, the frame is copied to the dspi dsi deserialization data register (dspi_ddr). this register presents the deserialized data as parallel output signal values. the dspi_ddr is memory mapped to allow host software to read the deserialized data directly. the received data is bit-wise compared to the value of the dsi deserialized data polarity interrupt register, bit-wise and?ed with dsi deserialized interrupt mask register and the results or?ed to produce the ddif flag in the dspi_sr, which in turn can cause a ddi interrupt request if the ddifre bit of dspi_rser is set. figure 737 shows the dsi deserialization logic. figure 737. dsi deserialization diagram dsi config. sout shift register ht 01 clock logic sck txss 0 1 register control logic dsi transmit comparison register pcs dsi serialization data register 32 32 32 parallel inputs 32 32 x 16 to 1 muxes dspi parallel inputs select registers 0-3 dspi alternate serialization data register slave bus interface dsi serialization source register 32 n sin shift register 01 n-1 control logic dsi deserialization data register 32 32 parallel outputs slave bus interface 32 dsi deserialized data polarity interrupt register dsi deserialized data interrupt mask register ddif deserial serial peripheral interface (dspi) RM0029 1314/1740 doc id 15177 rev 8 dsi transfer initiation control data transfers for a master dspi in dsi configuration are initiated by a condition. the transfer initiation conditions are selected by the trre and cid bits in the dspi_dsicr. ta ble 71 0 lists the four transfer initiation conditions. continuous control for continuous control a new dsi frame shifts out when the previous transfer cycle has completed and the delay after transfer (t dt ) has elapsed. change in data control for change in data control a transfer is initiated when the data to be serialized has changed since the transfer of the last dsi frame. a copy of the previously transferred dsi data is stored in the dspi_compr. when the data selected for the transfer from the dspi_sdr and dspi_asdr registers is different from the data in the dspi_compr a new dsi frame is transmitted. the mtrig output signal is asserted every time a change in data is detected. triggered control for triggered control initiation of a transfer is controlled by the hardware trigger signal (ht). the tpol bit in the dspi_dsicr selects the active edge of ht. for ht to have any affect, the trre bit in the dspi_dsicr must be set. triggered or change in data control for triggered or change in data control initiation of a transfer is controlled by the ht signal or by the detection of a change in data to be serialized. multiple transfer operation (mto) in dsi configuration the mto feature allows for multiple dspis within a device to be chained together in a parallel or serial configuration. the parallel chaining allows multiple dspis internal to a device and multiple spi devices external to a device to share sck and pcs signals thereby helping to minimize device pin count. the serial chaining allows bits from multiple dspis to be concatenated into a single dsi frame. mto is enabled by setting the mtoe bit in the dspi_dsicr. in parallel and serial chaining there is one bus master and multiple bus slaves. the bus master initiates and controls the transfers, but the dspi slaves generate trigger signals for the bus dspi master when an internal condition in the slave warrants a transfer. the dspi table 710. dsi data transfer initiation control dspi_dsicr bits transfer initiation control trre cid 0 0 continuous 0 1 change in data 10 triggered 1 1 triggered or change in data RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1315/1740 slaves also propagate triggers from other slaves to the master. when a dspi slave detects a trigger signal on its ht input, the slave generates a trigger signal on the mtrig output. serial and parallel chaining require multiplexing of signals external to the dspi. note: tsb operation is not available in mto mode. tsbc and mtoe bits of dspi_dsicr should not be set simultaneously. parallel chaining parallel chaining allows the pcs and sck signals from a master dspi to be shared by internal slave dspis and external slave spi devices, thus reducing pin utilization of the spc564a74xx, spc564a80xx mcu. signal sharing reduces dspi pin utilization. an example of a parallel chain is shown in figure 738 . in this example, the sout and sin of the three dspis connect to separate external spi devices, which share a common pcs and sck. figure 738. dspi parallel chaining example in the parallel chaining example, the sout and sin of the three dspis connect to separate external spi devices. all internal and external spi blocks share pcs and sck signals. dspi_b controls and initiates all transfers, but the dspi slaves each have a trigger output signal mtrig that indicates to dspi_b that a trigger condition has occurred in the dspi slaves. when the slave dspi has a change in data to be serialized, it asserts the mtrig signal that propagates to dspi_b which initiates the transfer. sout sout sin sin pcs[x] ss sck sck dspi_b master dspi_c slave ss sck sin sout device sin sck ss sout mtrig ht spi slave device spi slave device sout sin ss sck dspi_d slave sin sck ss sout mtrig spi slave device ht sout_c sin_c sin_b pcs_b[0] sck_b sout_b sout_d sin_d deserial serial peripheral interface (dspi) RM0029 1316/1740 doc id 15177 rev 8 serial chaining serial chaining allows spi operation with an external device that has more bits than one dspi module. in a serial chain, one dspi module operates as a master, the other dspi modules operate as slaves. the data output (sout) of the master is connected to the data input (sin) of the slave. the sout of a slave is connected to the sin of subsequent slaves until the last block in the chain, where the sout is connected to an external pin, which connects to the input of an external spi device. the slave dspi and external spi device use the master peripheral chip select (pcs) and clock (sck). the trigger input of the master allows a slave dspi to trigger a transfer when a data change occurs in the slave dspi and the slave dspi is operating in change in data mode. the trigger input of the master is connected to mtrig output of the slave. the concatenated frames can be from 8 to 64 bits long. figure 739 shows an example of how the blocks can be connected in the spc564a74xx, spc564a80xx. figure 739. dspi serial chaining example the sout of dspi_b is connected to the sin of dspi_c, the sout of dspi_c is connected to the sin of dspi_d and the sout of the dspi_d is connected to the sin of the external spi slave. the sout of the external spi slave is connected to the sin of dspi_b. dspi_b controls and initiates all transfers, but the slave dspis use the trigger output signal mtrig to indicate to dspi_b that a trigger condition has occurred. when an on-chip dspi slave has a change in data to be serialized it can assert the mtrig signal to the dspi sout sout sin sin pcs[x] ss sck sck dspi_b master dspi_c slave ss sck sin sout external spi slave device device mtrig ht sout sin ss sck dspi_d slave mtrig ht sout_d sck_b sin_b pcs_b[0] RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1317/1740 master which initiates the transfer. the dspi slaves also propagate trigger signals from other slaves to the dspi master. field dspi_dsicr[mtocnt] in dspi_b must be written with the total number of bits to be transferred. field dspi_dsicr[mtocnt] must equal the sum of all fmsz fields in the selected dspi_ctar registers for dspi_b and all on-chip dspi slaves. for example, if one 16-bit dsi frame is created by concatenating 8 bits from dspi_b and 4 bits from dspi_c and dspi_d each, then dspi_b?s frame size must be set to 8, and the dspi slaves? frame size must be set to 4 each. field dspi_dsicr[mtocnt] in dspi_b must be set to 16. imux/siu support for serial and parallel chaining to support mto, each dspi in the spc564a74xx, spc564a80xx has multiplexers on the sin, ss , sck, and ht inputs. the internal multiplexers (imux) reside in the siu module on the spc564a74xx, spc564a80xx. 30.9.4 combined serial interface (csi) configuration the csi configuration of the dspi is used to support spi and dsi functions on a frame by frame basis. csi configuration allows interleaving of dsi data frames from the parallel input signals with spi commands and data from the tx fifo. the data returned from the bus slave is either used to drive the parallel output signals or it is stored in the rx fifo. the csi configuration allows serialized data and configuration or diagnostic data to be transferred to a slave device using only one serial link. the dspi is in csi configuration when field dspi_mcr[dconf] is 0b10. figure 740 shows an example of how a dspi can be used with a deserializing peripheral that supports spi control for control and diagnostic frames. figure 740. example of system using dspi in csi configuration in csi configuration the dspi transfers dsi data based on dsi transfer initiation control. when there are spi commands in the tx fifo, the spi data has priority over the dsi frames. when the tx fifo is empty, dsi transfer resumes. two peripheral chip select signals indicate whether dsi data or spi data is transmitted. the user must configure the dspi so that the two dspi_ctar registers associated with dsi data and spi data assert different peripheral chip select signals denoted in the figure as pcsx and pcsy. the csi configuration is only supported in master mode. data returned from the external slave while a dsi frame is transferred is placed on the parallel output signals. data returned from the external slave while a spi frame is shift register sin sin sout sout sck sck ssx pcsx dspi master external slave deserializer ssy pcsy spi frame select logic frame dsi frame shift register spi dsi tx priority control tx fifo deserial serial peripheral interface (dspi) RM0029 1318/1740 doc id 15177 rev 8 transferred is moved to the rx fifo. the tx fifo and rx fifo are fully functional in csi mode. csi serialization serialization in the csi configuration is similar to serialization in dsi configuration. the transfer attributes for spi frames are determined by the dspi_ctar selected by the ctas field in the spi command halfword. the transfer attributes for the dsi frames are determined by the dspi_ctar selected by field dspi_dsicr[dsictas]. the parallel inputs signal states are latched into the dspi dsi serialization data register (dspi_sdr) on the rising edge of every system clock and serialized based on the transfer initiation control settings in the dspi_dsicr. when spi frames are written to the tx fifo they have priority over dsi data from the dspi_sdr and are transferred at the next frame boundary. a copy of the most recently transferred dsi frame is stored in the dspi_compr. the transfer priority logic selects the source of the serialized data and asserts the appropriate pcs signal. csi deserialization the deserialized frames in csi configuratio n goes into the dspi_ddr or the rx fifo based on the transfer priority logic. when dsi frames are transferred the returned frames are deserialized and latched into the dspi_ddr. when spi frames are transferred the returned frames are deserialized and written to the rx fifo. 30.9.5 dspi baud rate a nd clock delay generation the sck frequency and the delay values for serial transfer are generated by dividing the system clock frequency by a prescaler and a scaler with the option for doubling the baud rate. figure 741 shows conceptually how the sck signal is generated. figure 741. communications clock prescalers and scalers baud rate generator the baud rate is the frequency of the serial communication clock (sck). the system clock is divided by a prescaler (pbr) and scaler (br) to produce sck with the possibility of halving the scaler division. the dbr, pbr and br fields in the dspi_ctar registers select the frequency of sck by the formula in the br field description. table 711 shows an example of how to compute the baud rate. table 711. baud rate computation example f sys pbr prescaler br scaler dbr baud rate 100 mhz 0b00 2 0b0000 2 0 25 mb/s 20 mhz 0b00 2 0b0000 2 1 10 mb/s sck system clock prescaler 1 scaler 1+dbr RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1319/1740 pcs to sck delay (t csc ) the pcs to sck delay is the length of time from assertion of the pcs signal to the first sck edge. see figure 743 for an illustration of the pcs to sck delay. the pcssck and cssck fields in the dspi_ctar x registers select the pcs to sck delay by the formula in the cssck field description. table 712 shows an example of how to compute the pcs to sck delay. pcscsk and cssck fields have no effect in tsb configuration. after sck delay (t asc ) the after sck delay is the length of time between the last edge of sck and the negation of pcs. see figure 743 and figure 744 for illustrations of the after sck delay. the pasc and asc fields in the dspi_ctar x registers select the after sck delay by the formula in the asc field description. table 713 shows an example of how to compute the after sck delay. pcasc and asc fields have no effect in tsb configuration. delay after transfer (t dt ) the delay after transfer is the minimum time between negation of the pcs signal for a frame and the assertion of the pcs signal for the next frame. see figure 743 for an illustration of the delay after transfer. the pdt and dt fields in the dspi_ctar x registers select the delay after transfer by the formula in the dt field description. table 714 shows an example of how to compute the delay after transfer. when in non-continuous clock mode the t dt delay is configured according equation 25 . when in continuous clock mode and tsb is not enabled the delay is fixed at 1 sck period. in tsb mode the delay after transfer is equal to a number formed by concatenation of pdt and dt fields plus 1 of the sck clock periods. see detailed information in section 30.9.8, timed serial bus (tsb) . table 712. pcs to sck delay computation example f sys pcssck prescaler cssck scaler pcs to sck delay 100 mhz 0b01 3 0b0100 32 0.96 s table 713. after sck delay computation example f sys pasc prescaler asc scaler after sck delay 100 mhz 0b01 3 0b0100 32 0.96 s table 714. delay after transfer computation example f sys pdt prescaler dt scaler delay after transfer 100 mhz 0b01 3 0b1110 32768 0.98 ms deserial serial peripheral interface (dspi) RM0029 1320/1740 doc id 15177 rev 8 peripheral chip select strobe enable (pcss ) the pcss signal provides a delay to allow the pcs signals to settle after a transition occurs thereby avoiding glitches. when the dspi is in master mode and pcsse bit is set in the dspi_mcr, pcss provides a signal for an external demultiplexer to decode the dspi_x_pcs[0] ? pcs[4] signals into as many as 128 glitch-free pcs signals. figure 742 shows the timing of the pcss signal relative to pcs signals. figure 742. peripheral chip select strobe timing the delay between the assertion of the pcs signals and the assertion of pcss is selected by field dspi_ctar[pcssck] based on the following formula: equation 27 at the end of the transfer the delay between pcss negation and pcs negation is selected by field dspi_ctar[pasc] based on the following formula: equation 28 ta ble 71 5 shows an example of how to compute the t pcssck delay. ta ble 71 6 shows an example of how to compute the t pasc delay. table 715. peripheral chip select strobe assert computation example f sys pcssck prescaler delay before transfer 100 mhz 0b11 7 70.0 ns table 716. peripheral chip select strobe negate computation example f sys pasc prescaler delay after transfer 100 mhz 0b11 7 70.0 ns t pcssck pcss pcsx t pasc t pcssck 1 f sys -------------- pcssck = t pasc 1 f sys -------------- pasc = RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1321/1740 the pcss signal is not supported when continuous serial communication sck or tsb mode are enabled. 30.9.6 transfer formats the spi serial communication is controlled by the serial communications clock (sck) signal and the pcs signals. the sck signal provided by the master device synchronizes shifting and sampling of the data on the sin and sout pins. the pcs signals serve as enable signals for the slave devices. when the dspi is the bus master, the cpol and cpha bits in the dspi clock and transfer attributes registers (dspi_ctarx) select the polarity and phase of the serial clock, sck. the polarity bit selects the idle state of the sck. the clock phase bit selects if the data on sout is valid before or on the first sck edge. when the dspi is the bus slave, cpol and cpha bits in the dspi_ctar0 (spi) or dspi_ctar1 (dsi) select the polarity and phase of the serial clock. even though the bus slave does not control the sck signal, clock polarity, clock phase and number of bits to transfer must be identical for the master and the slave devices to ensure proper transmission. the dspi supports four different transfer formats: classic spi with cpha = 0 classic spi with cpha = 1 modified transfer format with cpha = 0 modified transfer format with cpha = 1 a modified transfer format is supported to allow for high-speed communication with peripherals that require longer setup times. the dspi can sample the incoming data later than halfway through the cycle to give the peripheral more setup time. the mtfe bit in the dspi_mcr selects between classic spi format and modified transfer format. in the spi and dsi configurations, the dspi provides the option of keeping the pcs signals asserted between frames. see section , continuous selection format for details. classic spi transfer format (cpha = 0) the transfer format shown in figure 743 is used to communicate with peripheral spi slave devices where the first data bit is available on the first clock edge. in this format, the master and slave sample their sin pins on the odd-numbered sck edges and change the data on their sout pins on the even-numbered sck edges. deserial serial peripheral interface (dspi) RM0029 1322/1740 doc id 15177 rev 8 figure 743. dspi transfer timing diagram (mtfe = 0, cpha = 0, fmsz = 8) the master initiates the transfer by placing its first data bit on the sout pin and asserting the appropriate peripheral chip select signals to the slave device. the slave responds by placing its first data bit on its sout pin. after the t csc delay elapses, the master outputs the first edge of sck. the master and slave devices use this edge to sample the first input data bit on their serial data input signals. at the second edge of the sck the master and slave devices place their second data bit on their serial data output signals. for the rest of the frame the master and the slave sample their sin pins on the odd-numbered clock edges and changes the data on their sout pins on the even-numbered clock edges. after the last clock edge occurs a delay of t asc is inserted before the master negates the pcs signals. a delay of t dt is inserted before a new frame transfer can be initiated by the master. classic spi transfer format (cpha = 1) this transfer format shown in figure 744 is used to communicate with peripheral spi slave devices that require the first sck edge before the first data bit becomes available on the slave sout pin. in this format the master and slave devices change the data on their sout pins on the odd-numbered sck edges and sample the data on their sin pins on the even- numbered sck edges. t csc sck master and slave pcsx/ss sck msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 master sout/ master sin/ t dt t csc t csc = pcs to sck delay t dt = delay after transfer (minimum cs idle time) (cpol = 0) (cpol = 1) t asc slave sin slave sout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sample t asc = after sck delay RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1323/1740 figure 744. dspi transfer timing diagram (mtfe = 0, cpha = 1, fmsz = 8) the master initiates the transfer by asserting the pcs signal to the slave. after the t csc delay has elapsed, the master generates the first sck edge and at the same time places valid data on the master sout pin. the slave responds to the first sck edge by placing its first data bit on its slave sout pin. at the second edge of the sck the master and slave sample their sin pins. for the rest of the frame the master and the slave change the data on their sout pins on the odd- numbered clock edges and sample their sin pins on the even-numbered clock edges. after the last clock edge occurs a delay of t asc is inserted before the master negates the pcs signal. a delay of t dt is inserted before a new frame transfer can be initiated by the master. modified spi/dsi transfer format (mtfe = 1, cpha = 0) in this modified transfer format both the master and the slave sample later in the sck period than in classic spi mode to allow tolerate more delays in device pads and board traces. these delays become a more significant fraction of the sck period as the sck period decreases with increasing baud rates. the master and the slave place data on the sout pins at the assertion of the pcs signal. after the pcs to sck delay has elapsed the first sck edge is generated. the slave samples the master sout signal on every odd numbered sck edge. the dspi in the slave mode when the mtfe bit is set also places new data on the slave sout on every odd t csc t dt sck sck msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 t csc = pcs to sck delay t dt = delay after transfer (minimum cs negation time) (cpol = 0) (cpol = 1) t asc master sout/ master sin/ slave sin slave sout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pcsx/ss master and slave sample t asc = after sck delay deserial serial peripheral interface (dspi) RM0029 1324/1740 doc id 15177 rev 8 numbered clock edge. regular external slave, configured with cpha = 0 format drives its sout output at every even numbered sck clock edge. the dspi master places its second data bit on the sout line one system clock after odd numbered sck edge if the system frequency to sck frequency ratio is higher than three. if this ratio is below four the master changes sout at odd numbered sck edge. the point where the master samples the sin is selected by field dspi_mcr[smpl_pt]. ta ble 68 2 lists the number of system clock cycles between the active edge of sck and the master sample point. the master sample point can be delayed by one or two system clock cycles. field dspi_mcr[smpl_pt] should be set to ?0? if the system to sck frequency ratio is less than 4. the following timing diagrams illustrate the dspi operation with mtfe = 1. timing delays shown are: t csc = pcs to sck assertion delay t acs = after sck pcs negation delay t su_ms = master sin setup time t hd_ms = master sin hold time t vd_sl = slave data output valid time, time between slave data output sck driving edge and data becomes valid. t su_sl = data setup time on slave data input t hd_sl = data hold time on slave data input t sys = system clock period figure 745 shows the modified transfer format for cpha = 0 and f sys /f sck = 4. only the condition where cpol = 0 is illustrated. solid triangles show the data sampling clock edges. the two possible slave behaviors are shown. signal, marked ?sout of ext slave?, presents regular spi slave serial output. signal, marked ?sout of dspi slave?, presents dspi in the slave mode with mtfe bit set. other mtfe = 1 diagrams show dspi sin input as being driven by a regular external spi slave, configured according dspi master cpha programming. RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1325/1740 figure 745. dspi modified transfer format (mtfe = 1, cpha = 0, f sck = f sys /4) figure 746. dspi modified transfer format (mtfe = 1, cpha = 0, f sck = f sys /2) d0 d1 d2 dn d0 d1 d2 dn d0 d1 d2 dn slave samples sout smpl_pt=2 smpl_pt=1 dspi samples sin, smpl_pt=0 tvd_sl tsys tcsc tvd_sl tasc thd_sl tsu_sl thd_ms tsu_ms 13 24 5 6 2n+2 2n+1 sys clk pcs sout of ext slave sck sout sout of dspi slave d0 d1 d2 dn d0 d1 d2 dn slave samples sout dspi samples sin tcsc tvd_sl tasc thd_sl ts u _ s l ts u _ m s thd_ms sys clk pcs sin sck sout deserial serial peripheral interface (dspi) RM0029 1326/1740 doc id 15177 rev 8 figure 747. dspi modified transfer format (mtfe = 1, cpha = 0, f sck = f sys /3) modified spi/dsi transfer format (mtfe = 1, cpha = 1) figure 748 ? figure 750 show the modified transfer format for cpha = 1. only the condition, where cpol = 0 is shown. at the start of a transfer the dspi asserts the pcs signal to the slave device. after the pcs to sck delay has elapsed the master and the slave put data on their sout pins at the first edge of sck. the slave samples the master sout signal on the even numbered edges of sck. the master samples the slave sout signal on the odd numbered sck edges starting with the third sck edge. the slave samples the last bit on the last edge of the sck. the master samples the last slave sout bit one half sck cycle after the last edge of sck. no clock edge will be visible on the master sck pin during the sampling of the last bit. the sck to pcs delay must be greater or equal to half of the sck period. figure 748. dspi modified transfer format (mtfe = 1, cpha = 1, f sck = f sys /2) d0 d1 d2 dn d0 d1 d2 dn slave samples sout dspi samples sin tc s c tvd_sl tasc thd_sl ts u _ s l thd_ms tsu_ms sys clk pcs sin sck sout d0 d1 d2 dn d0 d1 d2 dn slave samples sout dspi samples sin tcsc tvd_sl ta s c thd_sl ts u _ s l thd_ms tsu_ms sys clk pcs sin sck sout 1 2 3 4 5 6 7 8 2n+1 2n+2 RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1327/1740 figure 749. dspi modified transfer format (mtfe = 1, cpha = 1, f sck = f sys /3) figure 750. dspi modified transfer format (mtfe = 1, cpha = 1, f sck = f sys /4) continuous selection format some peripherals must be deselected between every transfer. other peripherals must remain selected between several sequential serial transfers. the continuous selection format provides the flexibility to handle both cases. the continuous selection format is enabled for the spi configuration by setting the cont bit in the spi command. continuous selection is enabled for the dsi configuration by setting the dcont bit in the dspi_dsicr. the behavior of the pcs signals in the two configurations is identical so only spi configuration will be described. d0 d1 d2 dn d0 d1 d2 dn slave samples sout dspi samples sin tcsc tvd_sl ta s c thd_sl tsu_sl thd_ms ts u _ m s sys clk pcs sin sck sout d0 d1 d2 dn d0 d1 d2 dn slave samples sout dspi samples sin tcsc tvd_sl thd_sl ts u _ s l thd_ms ts u _ m s sys clk pcs sin sck sout ta s c deserial serial peripheral interface (dspi) RM0029 1328/1740 doc id 15177 rev 8 when the cont bit = 0, the dspi drives the asserted chip select signals to their idle states in between frames. the idle states of the chip select signals are selected by the pcsisn bits in the dspi_mcr. figure 751 shows the timing diagram for two 4-bit transfers with cpha = 1 and cont = 0. figure 751. example of non-continuous format (cpha = 1, cont = 0) when the cont bit = 1, the pcs signal remains asserted for the duration of the two transfers. the delay between transfers (t dt) is not inserted between the transfers. figure 752 shows the timing diagram for two 4-bit transfers with cpha = 1 and cont = 1. figure 752. example of continuous transfer (cpha = 1, cont = 1) t csc t dt t csc sck pcsx sck master sout master sin t csc = pcs to sck delay t dt = delay after transfer (minimum cs negation time) (cpol = 0) (cpol = 1) t asc t asc = after sck delay t csc t csc sck pcs sck master sout master sin t csc = pcs to sck delay (cpol = 0) (cpol = 1) t asc t asc = after sck delay RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1329/1740 when using dspi with continuous selection follow these rules: all transmit commands must have the same pcsn bits programming the dspi_ctars, selected by transmit commands, must be programmed with the same transfer attributes. only field fmsz can be programmed differently in these dspi_ctars. note: it is mandatory to fill the txfifo with the number of entries that will be concatenated together under one pcs assertion for both master and slave before the txfifo becomes empty. for example, while transmitting in master mode, it should be ensured that the last entry in the txfifo, after which txfifo becomes empty, must have the cont bit in command frame as deasserted (i.e. cont bit = 0).while operating in slave mode, it should be ensured that when the last-entry in the txfifo is comp.letely transmited (i.e. the corresponding tcf flag is asserted and txfifo is empty) the slave should be deselected for any further serial communication; else an underflow error occurs. 30.9.7 continuous serial communications clock the dspi provides the option of generating a continuous sck signal for slave peripherals that require a continuous clock. continuous sck is enabled by setting bit dspi_mcr[cont_scke]. continuous sck is valid in all configurations. continuous sck is only supported for cpha = 1. clearing cpha is ignored if bit dspi_mcr[cont_scke] is set. continuous sck is supported for modified transfer format. clock and transfer attributes for the continuous sck mode are set according to the following rules: the tx fifo must be cleared before initiating any spi configuration transfer. when the dspi is in spi configuration, ctar0 shall be used initially. at the start of each spi frame transfer, the ctar specified by the ctas for the frame should be ctar0. when the dspi is in dsi configuration, the ctar specified by the dsictas field shall be used at all times. when the dspi is in csi configuration, the ctar selected by the dsictas field shall be used initially. at the start of an spi frame transfer, the ctar specified by the ctas value (which is ctar0) for the frame shall be used. at the start of a dsi frame transfer, the ctar specified by the dsictas field shall be used. in all configurations, the currently selected dspi_ctar remains in use until the start of a frame with a different dspi_ctar specified, or the continuous sck mode is terminated. it is recommended to keep the baud rate the same while using the continuous sck. switching clock polarity between frames while using continuous sck can cause errors in the transfer. continuous sck operation is not guaranteed if the dspi is put into the external stop mode or module disable mode. enabling continuous sck disables the pcs to sck delay and the delay after transfer (t dt ) is fixed to one sck cycle. when tsb configuration is enabled the t dt is programmable from 1 to 65 sck cycles. figure 753 shows timing diagram for continuous sck format with continuous selection disabled. deserial serial peripheral interface (dspi) RM0029 1330/1740 doc id 15177 rev 8 note: when in continuous sck mode, for the spi transfer ctar0 should always be used, and the tx-fifo must be clear using the dspi_mcr[clr_txf] field before initiating transfer. figure 753. continuous sck timing diagram (cont = 0) if the cont bit in the tx fifo entry is set or the dcont in the dspi_dsicr is set, pcs remains asserted between the transfers. under certain conditions, sck can continue with pcs asserted, but with no data being shifted out of sout (sout pulled high). this can cause the slave to receive incorrect data. those conditions include: continuous sck with cont bit set, but no data in the transmit fifo. continuous sck with cont bit set and entering stopped state (refer to section 30.9.1, start and stop of dspi transfers ). continuous sck with cont bit set and entering stop mode or module disable mode. figure 754 shows timing diagram for continuous sck format with continuous selection enabled. figure 754. continuous sck timing diagram (cont = 1) t dt sck pcs sck master sout master sin (cpol = 0) (cpol = 1) sck pcs sck master sout master sin (cpol = 0) (cpol = 1) transfer 1 transfer 2 RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1331/1740 30.9.8 timed serial bus (tsb) the dspi can be programmed in timed serial bus configuration by setting the tsbc bit in the dspi_dsicr. see section , dspi dsi configuration register (dspi_dsicr) for details. tsb configuration provides the micro second channel (msc) downstream channel support. the msc upstream channel is not supported by the dspi, but can be supported by any available serial communication controller (sci or uart) in the device. to work in tsb mode the dspi must be in master mode and in dsi (dconf = 0b01) or csi (dconf = 0b10) configuration. both continuous and non continuous serial communication clock (controlled by bit dspi_mcr[cont_scke]) are supported in the tsb mode. figure 755 shows the signals used in the tsb interface. in the tsb configuration the dspi is able to send from 4 to 34 bits msc data frames (4 to 32 serialized data bits and up to 2 data selection zero bits). the serialized data bits source can be either: the dspi dsi alternate serialization data register (dspi_asdr), written by the host software, parallel input pin states latched into the dspi dsi serialization data register (dspi_sdr). dspi_dsicr txss bit or dspi_ssr bits define the source of the data. the least significant bits of the dspi_asdr or dspi_sdr registers are selected to be serialized if the data frame is set to less than 32 bits. figure 755. dspi usage in the tsb configuration the pcs signals are driven together with sout. the t csc and t asc delays are not available. delay after transfer (dt) is set in sck clock periods as a binary number formed by concatenation of the dspi_ctarn pdt and dt fields plus one, allowing to set dt from 1 to 64 serial clock periods. dt field provides least significant bits and pdt field provides most significant bits of the delay after transfer. sck sout pcs1 pcs2 slave1 slave2 din clk cs clk din cs dspi downstream channel deserial serial peripheral interface (dspi) RM0029 1332/1740 doc id 15177 rev 8 figure 756. tsb downstream frames figure 756 shows the two types of msc downstream frames: command frame and data frame. the first transmitted bit, called the selection bit, determines the frame type: the selection bit ?0? indicates a data frame the selection bit ?1? indicates a command frame data frame may contain up to two selection bits to support two external slave devices, (so called dual receiver configuration) or no selection bits at all. the command frame can be written by software, through spi tx fifo, using one or two fifo entries with help of the cont bit. the data frame consists of up to 32 bits from the dspi_sdr or dspi_asdr registers and up to two zero selection bits. the number of data bits in the data frame is defined by field dspi_dscicr1[tsbcnt]. the selection bit of the msc command frames (1) can be implemented by software. to comply with msc specification, set dspi_ctarn[lsbfe] to transmit the least significant bit first. regardless of the lsbfe bit setting, the data frame selection bits, if enabled, are always transmitted first, before the corresponding data subframes. msc dual receiver support with pcs switchover when in tsb mode it is possible to switch the set of pcs signals that are driven during the first part of the frame to a different set of pcs signals during the second part of the frame. the bit, at which this switchover occurs, is defined by field fmsz of the dspi_ctarn register, which is selected by field dspi_dsicr[dsictas]. number of the bits, not including the data selection bit, in the first part of the frame is equal to value of the fmsz field plus one. during this part of the frame the pcs signal levels are controlled by dspi_dsicr dpcsn bits, after that by dspi_dsicr1 dpcs1_n bits. the pcs switchover occurs at driving edge of the sck clock output. the second data selection bit is inserted after the pcs switchover if enabled. t dt data frame invalid lsb active phase 0 sck pcs master sout t dt = from 1 to 64 t sck invalid command frame t dt command frame = 4 to 32 bits lsb 1 selection bit data frame = 4 to 32 bits (cpol = 0) active phase RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1333/1740 data frame with pcs switchover is shown in figure 757 . figure 757. tsb data frame format for msc dual receiver operation 30.9.9 parity generation and check the dspi module can generate and check parity in the serial frame. the parity bit replaces the last transmitted bit in the frame. the parity is calculated for all transmitted data bits in frame, not including the last, would be transmitted, data bit. the parity generation/control is done on frame basis. the registers fields, setting frame size defines the total number of bits in the frame, including the parity bit. thus, to transmit/receive the same number of data bits with parity check, increase the frame size by one versus the same data size frame without the parity check. parity can be selected as odd or even. parity errors in the received frame set parity error flags in the status register. the parity error interrupt requests are generated if enabled. the dspi module can be programmed to stop spi or/and dsi frame transmission in case of a frame reception with parity error. parity for spi frames when the dspi is in the master mode the parity generation is controlled by pe and pp bits of the tx fifo entries (dspi_pushr). setting the pe bit enables parity generation for transmitted spi frames and parity check for received frames. pp bit defines polarity of the parity bit. when continuous pcs selection is used to transmit spi data, two parity generation scenarios are available: generate/check parity for the whole frame generate/check parity for each subframe separately. to generate/check parity for the whole frame set pe bit only in the last command/tx fifo entry, forming this frame (with the dspi_pushr). to generate/check parity for each subframe set pe bit in each command/tx fifo entry, forming this frame. sck pcs0 sout data sub frame 1 t dt invalid lsb 0 0 data selection bits data frame = 4 to 34 bits pcs1 data sub frame 2 dspi_ctarn[fmsz] + 1 tsbcnt - fmsz deserial serial peripheral interface (dspi) RM0029 1334/1740 doc id 15177 rev 8 if the parity error occurs for received spi frame, the dspi_sr[spef] bit is set. if dspi_mcr[pes] bit is set, the dspi stops spi frames transmission. to resume spi operation clear the dspi_sr[spef] or the dspi_mcr[pes] bits. in slave mode the parity is controlled by the pe and pp bits of the dspi_ctar0 register similar to the master mode parity generation without continuous pcs selection. parity for dsi frames parity generation is controlled by pe and pp bits of the dspi_dsicr similar to the spi frames. the parity is calculated and checked for each dsi frame. (dspi_dsicr[dcont] bit has no effect on parity generation.) if the parity error occurs for received dsi frame, the dspi_sr[dpef] bit is set. to resume dsi operation clear the dspi_sr[dpef] bit. 30.9.10 interrupts/dma requests the dspi has several conditions that can generate interrupt requests and two conditions that can generate both interrupt or dma requests. table 717 lists these conditions. the ?x? in the request type columns indicates which signals are connected on the spc564a74xx, spc564a80xx. each condition has a flag bit in the dspi status register (dspi_sr) and an request enable bit in the dspi dma/interrupt request select and enable register (dspi_rser). the tx fifo fill flag (tfff) and rx fifo drain flag (rfdf) generate interrupt requests or dma requests depending on the tfffdirs and rfdfdirs bits in the dspi_rser. the dspi module also provides a global interrupt request line, which is asserted when any of individual interrupt requests lines is asserted. end of queue interrupt request the end of queue request indicates that the end of a transmit queue is reached. the end of queue request is generated when the eoq bit in the executing spi command is set and bit dspi_rser[eoqfre] is set. table 717. interrupt and dma request conditions condition flag request type interrupt dma end of queue (eoq) eoqf x tx fifo fill tfff x x transfer complete tcf x tx fifo underflow tfuf x rx fifo drain rfdf x x rx fifo overflow rfof x spi parity error spef x dsi parity error dpef x dsi deserialized data match ddif x RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1335/1740 transmit fifo fill interrupt or dma request the transmit fifo fill request indicates that the tx fifo is not full. the transmit fifo fill request is generated when the number of entries in the tx fifo is less than the maximum number of possible entries, and the tfffre bit in the dspi_rser is set. the tfffdirs bit in the dspi_rser selects whether a dma request or an interrupt request is generated. transfer complete interrupt request the transfer complete request indicates the end of the transfer of a serial frame. the transfer complete request is generated at the end of each frame transfer when the tcf_re bit is set in the dspi_rser. transmit fifo underflow interrupt request the transmit fifo underflow request indicates that an underflow condition in the tx fifo has occurred. the transmit underflow condition is detected only for the dspi, operating in slave mode and spi configuration. the tfuf bit is set when the tx fifo of a dspi is empty, and a transfer is initiated from an external spi master. if the tfuf bit is set while the tfufre bit in the dspi_rser is set, an interrupt request is generated. receive fifo drain interrupt or dma request the receive fifo drain request indicates that the rx fifo is not empty. the receive fifo drain request is generated when the number of entries in the rx fifo is not zero, and the rfdfre bit in the dspi_rser is set. the rfdfdirs bit in the dspi_rser selects whether a dma request or an interrupt request is generated. receive fifo overflow interrupt request the receive fifo overflow request indicates that an overflow condition in the rx fifo has occurred. a receive fifo overflow request is generated when rx fifo and shift register are full and a transfer is initiated. the rfofre bit in the dspi_rser must be set for the interrupt request to be generated. depending on the state of the rooe bit in the dspi_mcr, the data from the transfer that generated the overflow is either ignored or shifted in to the shift register. if the rooe bit is set, the incoming data is shifted in to the shift register. if the rooe bit is cleared, the incoming data is ignored. spi frame parity error interrupt request the spi frame parity error flag indicates that a spi frame with parity error had been received. the spefre bit in the dspi_rser must be set for the interrupt request to be generated. dsi frame parity error interrupt request the dsi frame parity error flag indicates that a dsi frame with parity error has been received. the dpefre bit in the dspi_rser must be set for the interrupt request to be generated. deserialized data match interrupt request the deserialized data match flag (ddif) i ndicates that a dsi frame with data matches dspi_dpir data, masked with dspi_dimr, had been received. the ddifre bit in the dspi_rser must be set for the interrupt request to be generated. deserial serial peripheral interface (dspi) RM0029 1336/1740 doc id 15177 rev 8 30.9.11 buffered spi operation the dspi can use a fifo buffering mechanism to transmit and receive commands and data to and from external devices. the transmit fifo buffers spi commands and data to be transferred. the receive fifo buffers incoming serial data. both fifos are four entries deep. the tx fifo stores 32-bit words when the dspis are configured for master mode. the 32-bit words are composed of 16-bit command fields and data fields up to 16 bits wide. the rx fifos store 16-bit words of received data from external devices. when the dspi is configured for slave mode, the dspi ignores the spi command in the tx fifo. for queued operations, the spi queues reside in system memory external to the dspi. data transfers between the memory and the dspi fifos are accomplished through the use of the edma controller or through host software. see figure 758 for a conceptual diagram of the queue data transfer control in the spc564a74xx, spc564a80xx mcu. figure 758. dspi queue transfer control in the spc564a74xx, spc564a80xx 30.9.12 continuous peripheral chip select for peripherals that must remain selected between sequential serial transfers, the dspi provides the option of having the pcs signals asserted between transfers. for spi transfers, the cont bit in the spi command fields selects the continuous pcs feature. for dsi and csi transfers, the dcont bit in the dspi_dsicr selects the continuous pcs feature. 30.9.13 peripheral chip select expansion and deglitching the dspi supports up to 256 peripheral chip select signals with the use of an external demultiplexer. up to 128 peripheral chip select signals can be used if deglitching is desired. the pcss signal provides the appropriate timing to enable and disable the demultiplexer for the dspi_x_pcs[0:7] signals. figure 759 shows how an external 8-to-256 demultiplexer (on-board decoder) can be connected to the dspi. system ram dspi dma controller/host tx queue rx fifo tx fifo shift register data data address rx queue data data address dma control/ host RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1337/1740 figure 759. dspi pcs expansion and deglitching 30.9.14 dma and interrupt conditions the dspi has six conditions that can generate interrupt requests and two conditions that can generate both interrupt or dma requests. table 718 lists the conditions. the ?x? in the request type columns indicates which signals are connected on the spc564a74xx, spc564a80xx. all request conditions are detected in the spi configuration and in the csi configuration. in dsi configuration only the transfer of current frame complete condition is detected. transmit fifo underflow flag (tfuf) the transmit fifo underflow flag indicates that an underflow condition in the tx fifo has occurred. the transmit underflow condition is detected only for dspi modules operating in slave mode and spi configuration. the transmit underflow condition is detected when the tx fifo of a dspi operating as a spi slave is empty, and a transfer is initiated from an external spi master. receive fifo overflow flag (rfof) the receive fifo overflow flag indicates that an overflow condition in the rx fifo has occurred, and that data may be lost. the receive fifo overflow flag is asserted when the dspi pcs0-pcs7 pcss pcs0 pcs1 pcs256 8 table 718. dspi interrupt and dma request conditions condition flag request type interrupt dma end of queue reached eoqf x tx fifo is not full tfff x x transfer of current frame complete tcf x attempt to transmit with an empty transmit fifo tfuf x rx fifo is not empty rfdf x x frame received while receive fifo is full rfof x deserial serial peripheral interface (dspi) RM0029 1338/1740 doc id 15177 rev 8 rx fifo is full, a new frame has been received in the shift register, and a transfer is initiated. 30.9.15 modified spi transfer format in modified transfer format, the slave peripheral has more time to place data on the sout pin before the dspi samples the data. in the modified transfer format, the master samples the incoming data towards the end of the transfer cycle. for correct operation of the modified transfer format, the user must thoroughly analyze the spi link timing budget. 30.9.16 lvds pad usage the differential transmitter pad driver lvds support data rate up to 40 mhz. figure 760 describes the pad signals interface. figure 760. lvds transmitter pad block diagram signals lvds_opt0 and lvds_opt1 control the voltage swing on the lvds pad. these two signals are controlled by bits src[1:0] of the respective siu_pcr. tab le 7 19 gives the configuration for these bits. 30.9.17 dspi connections to etpu_a, emios and siu the three dspi modules connect to the input and output channels of the etpus and the emios. some of the dspi outputs connect to the external interrupt input multiplexing sub- block in the siu. see section , external interrupts and section 16.6.19, external irq input select register (siu_eiisr) for details on how the dspi deserialized outputs can be used to trigger external interrupt requests. table 719. lvds pads voltage swing siu_pcrx current flowing in the driver differential voltage across pad_p and pad_n src[0] src[1] 0 0 normal default 0 1 increased increased 1 0 decreased decreased 1 1 normal same as default vref_lvds v_iref_lvds lvds transmitter ipp_do lvds_obe pad_n pad_p lvds_opt0 lvds_opt1 RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1339/1740 dspi_b connectivity the dspi_b connects to the emios, etpu_a and siu as shown in figure 761 . figure 761. dspi_b connectivity ta ble 72 0 lists the dspi_b connections. dspi_b out 14 out 15 emios ch 13 ch 12 etpu_a emios ch [16:23] ch [24:29] ch [30:31] ch [15:12] etpu_a ch 29 ch 24 ch [8:11] in [3:0] in [10:4] in [7:0] in [13:8] in [15:14] in [19:16] out 8 out 13 out 0 out 15 ch [23] in [11] in [15:12] ch [12:15] in1 irq[0] siu/imux in1 irq[15] ch [11:0] in [31:20] in [16] ch [8:15] in [24:17] in [31:25] ch [0:6] ch [0:6] ch [23] table 720. dspi_b connectivity table dspi_b input connected to: dspi_b output connected to: 0 emios output channel 11 etpu_a output channel 23 gpdo350 0 input 1 on imux for external irq[0] 1 emios output channel 10 etpu_a output channel 22 gpdo351 1 input 1 on imux for external irq[1] 2 emios output channel 9 etpu_a output channel 21 gpdo352 2 input 1 on imux for external irq[2] 3 emios output channel 8 etpu_a output channel 20 gpdo353 3 input 1 on imux for external irq[3] 4 emios output channel 6 etpu_a output channel 19 gpdo354 4 input 1 on imux for external irq[4] deserial serial peripheral interface (dspi) RM0029 1340/1740 doc id 15177 rev 8 5 emios output channel 5 etpu_a output channel 18 gpdo355 5 input 1 on imux for external irq[5] 6 emios output channel 4 etpu_a output channel 17 gpdo356 6 input 1 on imux for external irq[6] 7 emios output channel 3 etpu_a output channel 16 gpdo357 7 input 1 on imux for external irq[7] 8 emios output channel 2 etpu_a output channel 29 gpdo358 8 etpu_a input channel 29, input 1 on imux for external irq[8] 9 emios output channel 1 etpu_a output channel 28 gpdo359 9 etpu_a input channel 28, input 1 on imux for external irq[9] 10 emios output channel 0 etpu_a output channel 27 gpdo360 10 etpu_a input channel 27, input 1 on imux for external irq[10] 11 emios output channel 23 etpu_a output channel 26 gpdo361 11 etpu_a input channel 26, input 1 on imux for external irq[11] 12 emios output channel 15 etpu_a output channel 25 gpdo362 12 etpu_a input channel 25, input 1 on imux for external irq[12] 13 emios output channel 14 etpu_a output channel 24 gpdo363 13 etpu_a input channel 24, input 1 on imux for external irq[13] 14 emios output channel 13 etpu_a output channel 31 gpdo364 14 emios input channel 13, input 1 on imux for external irq[14] 15 emios output channel 12 etpu_a output channel 30 gpdo365 15 emios input channel 12, input 1 on imux for external irq[15] 16 emios output channel 23 etpu_a output channel 12 gpdo366 16 nc 17 emios output channel 15 etpu_a output channel 13 gpdo367 17 nc table 720. dspi_b connectivity table (continued) dspi_b input connected to: dspi_b output connected to: RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1341/1740 18 emios output channel 14 etpu_a output channel 14 gpdo368 18 nc 19 emios output channel 13 etpu_a output channel 15 gpdo369 19 nc 20 emios output channel 12 etpu_a output channel 0 gpdo370 20 nc 21 emios output channel 11 etpu_a output channel 1 gpdo371 21 nc 22 emios output channel 10 etpu_a output channel 2 gpdo372 22 nc 23 emios output channel 9 etpu_a output channel 3 gpdo373 23 nc 24 emios output channel 8 etpu_a output channel 4 gpdo374 24 nc 25 emios output channel 6 etpu_a output channel 5 gpdo375 25 nc 26 emios output channel 5 etpu_a output channel 6 gpdo376 26 nc 27 emios output channel 4 etpu_a output channel 7 gpdo377 27 nc 28 emios output channel 3 etpu_a output channel 8 gpdo378 28 nc 29 emios output channel 2 etpu_a output channel 9 gpdo379 29 nc table 720. dspi_b connectivity table (continued) dspi_b input connected to: dspi_b output connected to: deserial serial peripheral interface (dspi) RM0029 1342/1740 doc id 15177 rev 8 dspi_c connectivity the dspi_c connects to etpu_a and siu as shown in figure 763 . figure 762. dspi_c connectivity ta ble 72 2 lists the dspi_c connections. 30 emios output channel 1 etpu_a output channel 10 gpdo380 30 nc 31 emios output channel 0 etpu_a output channel 11 gpdo381 31 nc table 720. dspi_b connectivity table (continued) dspi_b input connected to: dspi_b output connected to: dspi_c out 1 out 15 in2 irq[0] siu/imux in2 irq[14] out 0 in2 irq[15] emios ch [15:12] ch [11:0] ch [16:23] ch [24:29] etpu_a ch [15:12] in [3:0] in [4] in [3:0] in [15:4] in [23:16] in [29:24] ch [6:0] in [11:5] in [15:12] ch [11:8] ch [30:31] in [31:30] in [22:16] ch [15:8] in [30:23] in [31] ch [23] ch [23] ch [6:0] RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1343/1740 table 721. dspi_c connectivity table dspi_c input connected to: dspi_c output connected to: 0 emios output channel 7 emios output channel 12 etpu_a output channel 12 gpdo382 0 input 2 on imux for external irq[15] 1 emios output channel 16 emios output channel 13 etpu_a output channel 13 gpdo383 1 input 2 on imux for external irq[0] 2 emios output channel 17 emios output channel 14 etpu_a output channel 14 gpdo384 2 input 2 on imux for external irq[1] 3 emios output channel 18 emios output channel 15 etpu_a output channel 15 gpdo385 3 input 2 on imux for external irq[2] 4 emios output channel 19 emios output channel 23 etpu_a output channel 0 gpdo386 4 input 2 on imux for external irq[3] 5 emios output channel 20 emios output channel 0 etpu_a output channel 1 gpdo387 5 input 2 on imux for external irq[4] 6 emios output channel 21 emios output channel 1 etpu_a output channel 2 gpdo388 6 input 2 on imux for external irq[5] 7 emios output channel 22 emios output channel 2 etpu_a output channel 3 gpdo389 7 input 2 on imux for external irq[6] 8 emios output channel 3 etpu_a output channel 4 gpdo390 8 input 2 on imux for external irq[7] 9 emios output channel 4 etpu_a output channel 5 gpdo391 9 input 2 on imux for external irq[8] 10 emios output channel 5 etpu_a output channel 6 gpdo392 10 input 2 on imux for external irq[9] deserial serial peripheral interface (dspi) RM0029 1344/1740 doc id 15177 rev 8 11 emios output channel 6 etpu_a output channel 7 gpdo393 11 input 2 on imux for external irq[10] 12 emios output channel 8 etpu_a output channel 8 gpdo394 12 input 2 on imux for external irq[11] 13 emios output channel 9 etpu_a output channel 9 gpdo395 13 input 2 on imux for external irq[12] 14 emios output channel 10 etpu_a output channel 10 gpdo396 14 input 2 on imux for external irq[13] 15 emios output channel 11 etpu_a output channel 11 gpdo397 15 input 2 on imux for external irq[14] 16 emios output channel 0 etpu_a output channel 23 gpdo398 16 nc 17 emios output channel 1 etpu_a output channel 22 gpdo399 17 nc 18 emios output channel 2 etpu_a output channel 21 gpdo400 18 nc 19 emios output channel 3 etpu_a output channel 20 gpdo401 19 nc 20 emios output channel 4 etpu_a output channel19 gpdo402 20 nc 21 emios output channel 5 etpu_a output channel 18 gpdo403 21 nc 22 emios output channel 6 etpu_a output channel 17 gpdo404 22 nc 23 emios output channel 8 etpu_a output channel 16 gpdo405 23 nc table 721. dspi_c connectivity table (continued) dspi_c input connected to: dspi_c output connected to: RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1345/1740 dspi_d connectivity the dspi_d connects to siu as shown in figure 763 . 24 emios output channel 9 etpu_a output channel 29 gpdo406 24 nc 25 emios output channel 10 etpu_a output channel 28 gpdo407 25 nc 26 emios output channel 11 etpu_a output channel 27 gpdo408 26 nc 27 emios output channel 12 etpu_a output channel 26 gpdo409 27 nc 28 emios output channel 13 etpu_a output channel 25 gpdo410 28 nc 29 emios output channel 14 etpu_a output channel 24 gpdo411 29 nc 30 emios output channel 15 etpu_a output channel 31 gpdo412 30 nc 31 emios output channel 23 etpu_a output channel 30 gpdo413 31 nc table 721. dspi_c connectivity table (continued) dspi_c input connected to: dspi_c output connected to: deserial serial peripheral interface (dspi) RM0029 1346/1740 doc id 15177 rev 8 figure 763. dspi_d connectivity ta ble 72 2 lists the dspi_d connections. dspi_d out 4 out 15 in3 irq[2] siu/imux in3 irq[13] out 1 in3 irq[15] out 0 in3 irq[14] table 722. dspi_d connectivity table dspi_d input connected to: dspi_d output connected to: 0 nc 0 input 3 on imux for external irq[14] 1 nc 1 input 3 on imux for external irq[15] 2nc 2 nc 3nc 3 nc 4 nc 4 input 3 on imux for external irq[2] 5 nc 5 input 3 on imux for external irq[3] 6 nc 6 input 3 on imux for external irq[4] 7 nc 7 input 3 on imux for external irq[5] 8 nc 8 input 3 on imux for external irq[6] 9 nc 9 input 3 on imux for external irq[7] 10 nc 10 input 3 on imux for external irq[8] 11 nc 11 input 3 on imux for external irq[9] 12 nc 12 input 3 on imux for external irq[10] 13 nc 13 input 3 on imux for external irq[11] 14 nc 14 input 3 on imux for external irq[12] 15 nc 15 input 3 on imux for external irq[13] 16?31 nc 16?31 nc RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1347/1740 30.9.18 power saving features the dspi supports two power-saving strategies: external stop mode module disable mode?clock gating of non-memory mapped logic stop mode (external stop mode) the dspi supports the stop mode protocol. when a request is made to enter external stop mode, the dspi module acknowledges the request. if a serial transfer is in progress, the dspi waits until it reaches the frame boundary before it is ready to have its clocks shut off. while the clocks are shut off, the dspi memory-mapped logic is not accessible. the states of the interrupt and dma request signals cannot be changed while in external stop mode. module disable mode module disable mode is a module-specific mode that the dspi can enter to save power. host cpu can initiate the module disable mode by setting bit dspi_mcr[mdis]. the module disable mode can also be initiated by hardware. when the mdis bit is set, the dspi negates clock enable signal at the next frame boundary. if implemented, the clock enable signal can stop the clock to the non-memory mapped logic. when clock enable is negated, the dspi is in a dormant state, but the memory mapped registers are still accessible. certain read or write operations have a different effect when the dspi is in the module disable mode. reading the rx fifo pop register does not change the state of the rx fifo. likewise, writing to the tx fifo push register does not change the state of the tx fifo. clearing either of the fifos has no effect in the module disable mode. changes to the dis_txf and dis_rxf fields of the dspi_mcr have no effect in the module disable mode. in the module disable mode, all status bits and register flags in the dspi return the correct values when read, but writing to them has no effect. writing to the dspi_tcr during module disable mode has no effect. interrupt and dma request signals cannot be cleared while in the module disable mode. 30.10 initialization/application information 30.10.1 how to manage dspi queues the queues are not part of the dspi, but the dspi includes features in support of queue management. queues are primarily supported in spi configuration. deserial serial peripheral interface (dspi) RM0029 1348/1740 doc id 15177 rev 8 1. when dspi executes last command word from a queue, the eoq bit in the command word is set to indicate to the dspi that this is the last entry in the queue. 2. at the end of the transfer, corresponding to the command word with eoq set is sampled, the eoq flag dspi_sr[eoqf] is set. 3. the setting of the eoq flag disables serial transmission and reception of data, putting the dspi in the stopped state. the txrxs bit is cleared to indicate the stopped state. 4. the dma can continue to fill tx fifo until it is full or step 5 occurs. 5. disable dspi dma transfers by disabling the dma enable request for the dma channel assigned to tx fifo and rx fifo. this is done by clearing the corresponding dma enable request bits in the dma controller. 6. ensure all received data in rx fifo has been transferred to memory receive queue by reading dspi_sr[rxcnt] or by checking dspi_sr[rfdf] after each read operation of the dspi_popr. 7. modify dma descriptor of tx and rx channels for new queues 8. flush tx fifo by writing a ?1? to bit dspi_mcr[clr_txf]. flush rx fifo by writing a ?1? to bit dspi_mcr[clr_rxf]. 9. clear transfer count either by setting ctcnt bit in the command word of the first entry in the new queue or via cpu writing directly to field dspi_tcr[tcnt]. 10. enable dma channel by enabling the dma enable request for the dma channel assigned to the dspi tx fifo, and rx fifo by setting the corresponding dma set enable request bit. 11. enable serial transmission and serial reception of data by clearing the eoqf bit. 30.10.2 switching master and slave mode when changing modes in the dspi, follow the steps below to guarantee proper operation. 1. halt the dspi by setting dspi_mcr[halt]. 2. clear the transmit and receive fifos by writing a 1 to the clr_txf and clr_rxf bits in dspi_mcr. 3. set the appropriate mode in dspi_mcr[mstr] and enable the dspi by clearing dspi_mcr[halt]. 30.10.3 baud rate settings ta ble 72 3 shows the baud rate that is generated based on the combination of the baud rate prescaler pbr and the baud rate scaler br in the dspi_ctar registers. the values calculated assume a 100 mhz system frequency and the double baud rate dbr bit is clear. RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1349/1740 30.10.4 delay settings ta ble 72 4 shows the values for the delay after transfer (t dt ) and cs to sck delay (t csc ) that can be generated based on the prescaler values and the scaler values set in the dspi_ctar registers. the values calculated assume a 100 mhz system frequency. ta ble 72 4 does not apply for tsb continuous mode. table 723. baud rate values (bit/s) baud rate divider prescaler values 2357 baud rate scaler values 2 25.0m 16.7m 10.0m 7.14m 4 12.5m 8.33m 5.00m 3.57m 6 8.33m 5.56m 3.33m 2.38m 8 6.25m 4.17m 2.50m 1.79m 16 3.12m 2.08m 1.25m 893k 32 1.56m 1.04m 625k 446k 64 781k 521k 312k 223k 128 391k 260k 156k 112k 256 195k 130k 78.1k 55.8k 512 97.7k 65.1k 39.1k 27.9k 1024 48.8k 32.6k 19.5k 14.0k 2048 24.4k 16.3k 9.77k 6.98k 4096 12.2k 8.14k 4.88k 3.49k 8192 6.10k 4.07k 2.44k 1.74k 16384 3.05k 2.04k 1.22k 872 32768 1.53k 1.02k 610 436 deserial serial peripheral interface (dspi) RM0029 1350/1740 doc id 15177 rev 8 30.10.5 calculation of fifo pointer addresses complete visibility of the tx and rx fifo contents is available through the fifo registers, and valid entries can be identified through a memory mapped pointer and a memory mapped counter for each fifo. the pointer to the first-in entry in each fifo is memory mapped. for the tx fifo the first-in pointer is the transmit next pointer (txnxtptr). for the rx fifo the first-in pointer is the pop next pointer (popnxtptr). figure 764 illustrates the concept of first-in and last-in fifo entries along with the fifo counter. the tx fifo is chosen for the illustration, but the concepts carry over to the rx fifo. see section , transmit first-in first-out (tx fifo) buffering mechanism and section , receive first-in first-out (rx fifo) buffering mechanism for details on the fifo operation. table 724. delay values delay prescaler values 1357 delay scaler values 2 20.0 ns 60.0 ns 100.0 ns 140.0 ns 4 40.0 ns 120.0 ns 200.0 ns 280.0 ns 8 80.0 ns 240.0 ns 400.0 ns 560.0 ns 16 160.0 ns 480.0 ns 800.0 ns 1.1 s 32 320.0 ns 960.0 ns 1.6 s 2.2 s 64 640.0 ns 1.9 s 3.2 s 4.5 s 128 1.3 s 3.8 s 6.4 s 9.0 s 256 2.6 s 7.7 s 12.8 s 17.9 s 512 5.1 s 15.4 s 25.6 s 35.8 s 1024 10.2 s 30.7 s 51.2 s 71.7 s 2048 20.5 s 61.4 s 102.4 s 143.4 s 4096 41.0 s 122.9 s 204.8 s 286.7 s 8192 81.9 s 245.8 s 409.6 s 573.4 s 16384 163.8 s 491.5 s 819.2 s 1.1 ms 32768 327.7 s 983.0 s1.6 ms 2.3 ms 65536 655.4 s 2.0 ms 3.3 ms 4.6 ms RM0029 deserial serial peripheral interface (dspi) doc id 15177 rev 8 1351/1740 figure 764. tx fifo pointers and counter address calculation for the first-in entry and last-in entry in the tx fifo the memory address of the first-in entry in the tx fifo is computed by the following equation: equation 29 the memory address of the last-in entry in the tx fifo is computed by the following equation: equation 30 tx fifo base: base address of tx fifo txctr: tx fifo counter txnxtptr: transmit next pointer tx fifo depth: transmit fifo depth, implementation-specific address calculation for the first-in entry and last-in entry in the rx fifo the memory address of the first-in entry in the rx fifo is computed by the following equation: equation 31 push tx fifo register transmit next data pointer shift register sout +1 -1 tx fifo counter tx fifo base ? ? entry a (first-in) entry b entry c entry d (last-in) ? ? first-in entry address tx fifo base 4 txnxtptr () + = last-in entry address tx fifo base 4 txctr txnxtptr 1 ? + () mod txfifodepth () + = first-in entry address rx fifo base 4 popnxtptr () + = deserial serial peripheral interface (dspi) RM0029 1352/1740 doc id 15177 rev 8 the memory address of the last-in entry in the rx fifo is computed by the following equation: equation 32 rx fifo base: base address of rx fifo rxctr: rx fifo counter popnxtptr: pop next pointer rx fifo depth: receive fifo depth, implementation specific last-in entry address rx fifo base 4 rxctr popnxtptr 1 ? + () mod (rxfifodepth) + = RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1353/1740 31 enhanced serial communication interface (esci) 31.1 introduction the esci block is an enhanced sci block with a lin master interface layer and dma support. the lin master layer complies with the specifications lin 1.3, lin 2.0, lin 2.1, and sae j2602/1. 31.1.1 bibliography lin specification package revision 1.3; december 12, 2002 lin specification package revision 2.0; september 23, 2003 lin network for vehicle applications, sae j2602/1, september 1, 2005 lin specification package revision 2.1; november 24, 2006 31.1.2 acronyms and abbreviations ta ble 72 5 contains acronyms and abbreviations used in this document. 31.1.3 glossary table 725. acronyms and abbreviations term description esci enhanced sci block with lin support and dma support sci serial communications interface lin local interconnect network - a protocol for low-cost automobile networks lin pe lin protocol engine, finite state machine to control logic of the lin hardware. mclk module clock, defined in section , module clock tclk transmitter clock, defined in section , transmitter clock rclk receiver clock, defined in section , receiver clock rsc receiver sample counter, defined in section , receiver clock table 726. glossary term definition logic level one the voltage that corresponds to boolean true (1) state. logic level zero the voltage that corresponds to boolean false (0) state. set to set a bit or bits means to establish logic level one on the bit or bits. clear to clear a bit or bits means to establish logic level zero on the bit or bits. asserted a signal that is asserted is in its active state. an active low signal changes from logic level one to logic level zero when asserted, and an active high signal changes from logic level zero to logic level one. enhanced serial communication interface (esci) RM0029 1354/1740 doc id 15177 rev 8 31.1.4 overview the esci block allows asynchronous serial communications with peripheral devices and other cpus. it includes special support to interface to lin slave devices. figure 765. esci block diagram preamble the term preamble describes an idle character which is transmitted by the esci module. bit time duration of a single bit in a transmitted byte field or character, equivalent to the duration of one transmitter clock cycle defined in section , transmitter clock frame entity that consists of the start bit followed by payload bits followed by one ore more stop bits lin byte field special instance of a frame sci frame special instance of a frame lin frame sequence of break character followed by lin byte fields lin tx frame a lin frame with the frame header, data byte fields, and checksum field transmitted by the esci module lin rx frame a lin frame with the header field transmitted by the esci module and the data byte fields and checksum field received by the esci module module is idle module is idle, described in section , module idle condition table 726. glossary (continued) term definition receive shift register 16 rxd polarity control baud rate generator receive data register txd transmit data register transmit shift register internal data bus receive control wake up control frame format control transmit control internal data bus interrupt generation loop control cpu irq rx dma channel dma ctrl tx dma channel dma ctrl lin pe tclk rclk bus clk RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1355/1740 31.1.5 features the esci block includes these distinctive features: full-duplex operation standard mark/space non-return-to-zero (nrz) format 13-bit baud rate selection programmable frame, payload, and character format support of 2 stop bits in receiver path hardware parity generation and checking ? programmable even or odd parity programmable polarity of rxd pin separately enabled transmitter and receiver two receiver wake-up methods: ? idle line wake up ? address mark wake up interrupt-driven operation with eight flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framing error detection 1/16 bit-time noise detection 2 channel dma interface lin support ? lin master node functionality (master and slave task) ? compatible with lin slaves from revisions 1.x and 2.0 of the lin standard ? detection of bit errors, physical bus errors and checksum errors ? all status bit can generate maskable interrupts ? application layer crc support ? programmable crc polynom ? detection and generation of wake-up characters ? programmable wake-up delimiter time ? programmable slave timeout ? can be configured to include header bits in checksum ? lin dma interface 31.1.6 modes of operation the esci module has two functional operational modes, sci and lin mode, and low power modes. the availability of register bits and fields depends on the selected operational mode. enhanced serial communication interface (esci) RM0029 1356/1740 doc id 15177 rev 8 module idle condition some modes can only be entered if the module is idle. the module is idle if all five active status bits tact, and raf in the interrupt flag and status register are 0, and no interrupt request is pending, i.e either the interrupt flag or its related interrupt enable is 0. to ensure that the module goes idle, the application should clear all interrupt enable bits before triggering the mode change. sci mode the sci mode is the default functional operational mode and is described in section 31.4.5, sci mode . lin mode the lin mode is the second functional operational mode and is described in section 31.4.6, lin mode . disabled mode in the disabled mode the esci module indicates to the clocking system, that all module clocks can be turned off. the esci module is in the disabled mode, if the mdis bit in the control register 2 (esci_cr2) is set and the module is idle. 31.2 external signal description the esci module is connected two a total of two external pins. 31.2.1 detailed signal descriptions esci transmit pin (txd) this pin serves as transmit data output and as the receive data input of esci. esci receive pin (rxd) this pin serves as receive data input of the esci. 31.3 memory map and register definition this section provides the memory map and a detailed description of the memory mapped registers. RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1357/1740 31.3.1 memory map ta ble 72 8 provides a key for register figures and tables. 31.3.2 register descriptions this section consists of register descriptions in address order. each description includes a standard register diagram with an associated figure number. writes to a reserved register location do not have any effect and reads of these locations return a zero. details of register bit and field function follow the register diagrams, in bit orderptions table 727. esci 32-bit memory map offset register 0x0000 baud rate register (esci_brr) control register 1 (esci_cr1) 0x0004 control register 2 (esci_cr2) sci data register (esci_dr) 0x0008 interrupt flag and status register 1 (esci_ifsr1) interrupt flag and status register 2 (esci_ifsr2) 0x000c lin control register 1 (esci_lcr1) lin control register 2 (esci_lcr2) 0x0010 lin transmit register (esci_ltr) reserved 0x0014 lin receive register (esci_lrr) reserved 0x0018 lin crc polynomial register (esci_lpr) control register 3 (esci_cr3) 0x001c reserved table 728. register conventions convention description depending on its placement in the read or write ro w, indicates that the bit is not readable or not writeable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types rwm a read/write bit that may be modified by a esci module in some fashion other than by a reset. w1c write one to clear. a flag bit that can be read, is cleared by writing a one, writing 0 has no effect. reset values 0 resets to zero. 1 resets to one. enhanced serial communication interface (esci) RM0029 1358/1740 doc id 15177 rev 8 baud rate register (esci_brr) this register provides the control value for the serial baud rate. the baud rate and clock generation is specified in section 31.4.3, baud rate and clock generation . a byte write access to only the upper byte of this register (esci_brr[0:715:8]) will not change the content of the register, instead, the written byte is stored internally into a shadow register. a subsequent byte write access to only the lower byte of this register (esci_brr[8:157:0]) updates the lower byte and copies the content of the shadow register into the upper byte. a byte write access to only the lower byte of this register (esci_brr[8:157:0]) without a preceding byte write access to only the upper byte copies a value of all zero into the upper byte. a word write access to this register updates both the lower and upper byte immediately and is the recommended write access type for this register table 729. esci_brr field descriptions control register 1 (esci_cr1) this register provides bits to configure the functionality of the module, provides the interrupt enable bits for the interrupt flags provided in interrupt flag and status register 1 (esci_ifsr1) and provides the control bits for the transmitter and receiver. figure 766. baud rate register (esci_brr) esci_base + 0x0000 write: anytime 1514131211109876543210 0123456789101112131415 r r sbr w reset0000000000000100 field description r reserved. these bits are reserved. they are read as 0. application must not write 1 to these bits. sbr serial baud rate. this field provides the baud rate control value sbr. RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1359/1740 figure 767. control register 1 (esci_cr1) esci_base + 0x0000 write: anytime 0123456789101112131415 r0 0 0 sbr w reset0000000000000100 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r loops r rsr c m wake 0 pe pt tie tcie rie ilie te re rwu sbk w rwm reset0000000000000000 table 730. esci_cr1 field descriptions field description sbr serial baud rate. this field provides the baud rate control value sbr. loops loop mode select. this control bit together with the rsrc control bit defines the receiver source mode. the mode coding is defined in table 731 and the modes are described in section , receiver input mode selection . rsrc receiver source control. this control bit together with the loops control bit defines the receiver source mode. the mode coding is defined in table 1-9 and the modes are described in section , receiver input mode selection m frame format mode. this control bit together with the m2 bit of the control register 3 (esci_cr3) controls the frame format used. the supported frame formats and the related settings are defines in section 31.4.2, frame formats . wake receiver wake-up condition. this control bit defines the wake-up condition for the receiver. the receiver wake-up is described in section , multiprocessor communication . 0 idle line wake-up. 1 address mark wake-up pe parity enable. this control bit enables the parity bit generation and checking. the location of the parity bits is shown in section 31.4.2, frame formats . 0 parity bit generation and checking disabled. 1 parity bit generation and checking enabled. pt parity type. this control bit defines whether even or odd parity has to be used. 0 even parity (even number of ones in character clears the parity bit). 1 odd parity (odd number of ones in character clears the parity bit). tie transmitter interrupt enable. this bit controls the esci_sr[trde] interrupt request generation. 0 tdre interrupt request generation disabled. 1 tdre interrupt request generation enabled. enhanced serial communication interface (esci) RM0029 1360/1740 doc id 15177 rev 8 tcie transmission complete interrupt enable. this bit controls the esci_sr[tc] interrupt request generation. 0 tc interrupt request generation disabled. 1 tc interrupt request generation enabled. rie receiver full interrupt enable. this bit controls the esci_sr[rdrf] interrupt request generation. 0 rdrf interrupt request generation disabled. 1 rdrf interrupt request generation enabled. ilie idle line interrupt enable. this bit controls theesci_sr[idle] interrupt request generation. 0 idle interrupt request generation disabled. 1 idle interrupt request generation enabled. te transmitter enable. this control bit enables and disables the transmitter. the control features of the transmitter are described in section , transmitter states and transitions . 0 transmitter disabled. 1 transmitter enabled. re receiver enable.this control bit enables and disables the receiver. the control features of the receiver are described in section , receiver states and transitions . 0 receiver disabled. 1 receiver enabled. rwu receiver wake-up mode. this bit controls and indicates the receiver wake-up mode, which is described in section , multiprocessor communication . 0 normal receiver operation. 1 receiver is in wake-up mode. this bit should be set in sci mode only. sbk send break character. this bit controls the transmission of break characters, which is described in section , break character transmission . 0 no break characters will be transmitted. 1 break characters will be transmitted. this bit should be set in sci mode only. table 730. esci_cr1 field descriptions (continued) (continued) field description table 731. receive source mode selection loops rscr receiver input mode 0 0 dual wire mode 01 reserved 1 0 loop mode 1 1 single wire mode RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1361/1740 control register 2 (esci_cr2) this register provides bits to configure the functionality of the module, and interrupt enable bits for the interrupt flags provided in interrupt flag and status register 1 (esci_ifsr1) , interrupt flag and status register 2 (esci_ifsr2) and control bits for the transmitter and receiver. figure 768. control register 2 (esci_cr2) esci_base + 0x0004 write: anytime 0123456789101112131415 r mdis fbr bstp ieberr rxdma txdma bircl reserved besm bestp rxpol pmsk orie nfie feie pfie w reset0010000000000000 table 732. esci_cr2 field descriptions field description mdis module disabled mode. this bit controls the module mode of operation, which is described in section 31.1.6, modes of operation . 0 module is not in disabled mode. 1 module is in disabled mode, if module is idle. fbr fast bit error detection. this bit controls the bit error detection mode. 0 standard bit error detection performed as described in section , standard bit error detection . 1 fast bit error detection performed as described in section , fast bit error detection . this bit is used in lin mode only. bstp dma stop on bit error or physical bus error. this bit controls the transmit dma requests generation in case of bit errors or physical bus errors. bit errors are indicated by the berr flag in the interrupt flag and status register 1 (esci_ifsr1) and physical bus errors are indicated by the pberr flag in the interrupt flag and status register 2 (esci_ifsr2) . 0 transmit dma requests generated regardless of bit errors or physical bus errors. 1 transmit dma requests are not generated if esci_sr[berr] flag or esci_sr[pberr] flags are set. this bit is used in lin mode only. berrie bit error interrupt enable. this bit controls the berr interrupt request generation. 0 berr interrupt request generation disabled. 1 berr interrupt request generation enabled. rxdma receive dma control. this bit enables the receive dma feature. when this bit is cleared, a pending receive dma request is deasserted. 0 receive dma disabled. 1 receive dma enabled. txdma transmit dma control. this bit enables the transmit dma feature. when this bit is cleared, a pending transmit dma request is deasserted. 0 transmit dma disabled. 1 transmit dma enabled. enhanced serial communication interface (esci) RM0029 1362/1740 doc id 15177 rev 8 sci data register (esci_dr) brcl break character length. this bit is used to define the length of the break character to be transmitted. the settings are specified in section , break character formats . besm fast bit error detection sample mode. this bit defines the sample point for the fast bit error detection mode. 0 sample point is rs9. 1 sample point is rs13. note: this bit is used in lin mode only. bestp bit error transmit stop. this control bit defines the behavior of the esci transmit pin txd while the bit error flag esci_sr[berr] is 1. 0 application data values driven onto txd pin. 1 recessive data value 1 driven onto txd pin. note: this bit is used in lin mode only. rxpol rxd pin polarity. this bit controls the polarity of the rxd pin. see section , inverted data frame formats . 0 normal polarity. 1 inverted polarity. pmsk parity bit masking. this bit defines whether the received parity bit is presented in the related bit position in the sci data register (esci_dr) . 0 the received parity bit is presented in the bit position related to the parity bit. 1 the value 0 is presented in the bit position related to the parity bit. orie overrun interrupt enable. this bit controls the esci_sr[or] interrupt request generation. 0 or interrupt request generation disabled. 1 or interrupt request generation enabled. nfie noise interrupt enable. this bit controls the esci_sr[nf] interrupt request generation. 0 nf interrupt request generation disabled. 1 nf interrupt request generation enabled. feie frame error interrupt enable. this bit controls the esci_sr[fe] interrupt request generation. 0 fe interrupt request generation disabled. 1 fe interrupt request generation enabled. pfie parity error interrupt enable. this bit controls the esci_sr[pf] interrupt request generation. 0 pf interrupt request generation disabled. 1 pf interrupt request generation enabled. table 732. esci_cr2 field descriptions (continued) field description figure 769. sci data register (esci_dr) esci_base + 0x0006 write: anytime 1514131211109876543210 0123456789101112131415 rrn tn err 0 rd[11:8] rd[7] rd[6:0] w td[7] td[6:0] reset0000000000000000 RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1363/1740 in sci mode this register is used to provide transmit data and retrieve received data. in lin mode any write access to this register is ignored and any read access returns unspecified data. in case of data transmission this register is used to provide a part of the transmit data. in case of data reception this register provides a part of the received data and related error information.if the application writes to the lower byte of this register (esci_dr[8:15]), the internal commit flag icmt, which is not visible to the application, is set to indicate that the register has been updated and ready to transmit new data. if the application reads from the lower byte of this register (esci_dr[8:15]), a signal is send to the internal receiver unit to indicate that the register was read and is ready to receive new data. the read access will not change the content of any register. table 733. esci_dr field descriptions field description rn received most significant bit. the semantic of this bit depends on the frame format selected by esci_cr3[m2], esci_cr1[m], and esci_cr1[pe]. [m2=0,m=1,pe=0]: value of received data bit 8 or address bit. [m2=0,m=1,pe=1]: value of received parity bit if esci_cr2[pmsk]=0, 0 otherwise. [m2=1,m=0,pe=1]: value of received parity bit if esci_cr2[pmsk]=0, 0 otherwise. [m2=1,m=1,pe=1]: value of received parity bit if esci_cr2[pmsk]=0, 0 otherwise. it is 0 for all other frame formats. tn transmit most significant bit. the semantic of this bit depends on the frame format selected by esci_cr3[m2], esci_cr1[m], and esci_cr1[pe]. [m2=0,m=1,pe=0]: value to be transmitted as data bit 8 or address bit. it is not used for all other frame formats. err receive error bit. this bit indicates the occurrence of the errors selected by the control register 3 (esci_cr3) during the reception of the frame presented in sci data register (esci_dr) . in case of an overrun error for subsequent frames this bit is set too. 0 none of the selected errors occured. 1 at least one of the selected errors occured. rd[11:8] received data. the semantic of this field depends on the frame format selected by esci_cr3[m2] and esci_cr1[m]. [m2=1,m=1]: value of the received data bits 11:8. (rx=bitx). it is all 0 for all other frame formats. rd[7] received bit 7. the semantic of this bit depends on the format selected by esci_cr3[m2], esci_cr1[m], and esci_cr1[pe]. [m2=0,m=0,pe=0]: value of received bit7 or addr bit. [m2=0;m=0,pe=1]: value of received parity bit if esci_cr2[pmsk]=0, 0 otherwise. for all other frame formats it is the value of received bit7. td[7] transmit bit 7. the semantic of this bit depends on the format selected by esci_cr3[m2], esci_cr1[m], and esci_cr1[pe]. [m2=0,m=0,pe=0]: value of transmit bit7 or addr bit. [m2=0;m=0,pe=1]: not used. parity bit is generated internally before transmission. for all other frame formats it is the value of transmit bit7. rd[6:0] received bits 6 to 0. value of received bitx is shown in bit rx td[6:0] transmit bits 6 to 0. value of bit tx is transmitted in bitx enhanced serial communication interface (esci) RM0029 1364/1740 doc id 15177 rev 8 interrupt flag and status register 1 (esci_ifsr1) this register provides interrupt flags that indicate the occurrence of module events. the related interrupt enable bits are located in control register 1 (esci_cr1) and control register 2 (esci_cr2) . figure 770. interrupt flag and status register 1 (esci_ifsr1) esci_base + 0x0008 write: anytime 1514131211109876543210 0123456789101112131415 r tdre tc rdrf idle or nf fe pf dact berr wact lact tact ract w w1c w1c w1c w1c w1c w1c w1c w1c w1c reset1000000000000000 table 734. esci_ifsr1 field descriptions field description tdre transmit data register empty interrupt flag. this interrupt flag is set when the content of the sci data register (esci_dr) was transferred into internal shift register. this flag is set in sci mode only. tc transmit complete interrupt flag. this interrupt flag is set when a frame, break or idle character transmission has been completed and no data were written into sci data register (esci_dr) after the last setting of the tdre flag and the sbk bit in control register 1 (esci_cr1) is 0. this flag is set in lin mode, if the preamble was transmitted after the enabling of the transmitter. rdrf receive data register full interrupt flag. this interrupt flag is set when the payload data of a received frame was transferred into the sci data register (esci_dr) and the receive dma is disabled. this flag is set in sci mode only. idle idle line interrupt flag. this interrupt flag is set when an idle character was detected and the receiver is not in the wake-up state. this flag is set in sci mode only. or overrun interrupt flag. this interrupt flag is set when an overrun was detected as described in section , receiver overrun . this flag is set in sci mode only. nf noise interrupt flag. this interrupt flag is set when the receiver has detected noise during the reception of a frame, as described in section , bit sampling . fe framing error interrupt flag. this interrupt flag is set when the payload data of a received frame was transferred into the sci data register (esci_dr) or lin receive register (esci_lrr) and the receiver has detected a framing error during the reception of that frame, as described in section , stop bit verification . pf parity error interrupt flag. this interrupt flag is set when the payload data of a received frame was transferred into the sci data register (esci_dr) and the receiver has detected a parity error for the character, as described in section , reception error reporting this flag is set in sci mode only. RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1365/1740 interrupt flag and status register 2 (esci_ifsr2) this register provides interrupt flags that indicate the occurrence of lin related events. the related interrupt enable bits are located in lin control register 1 (esci_lcr1) and lin control register 2 (esci_lcr2) . all interrupt flags in this register will be set in lin mode only. dact dma active. the status bit is set when a transmit or receive dma request is pending. 0 no dma request pending 1 dma request pending. berr bit error interrupt flag. this flag is set when a bit error was detected as described in section , standard bit error detection . note: this flag is set in lin mode only. wact lin wake-up active. the status bit is set as long as the lin wakeup engine receives a lin wake-up signal. 0 no lin wakeup signal reception in progress. 1 lin wakeup signal reception in progress. lact lin active. this status bit is set as long as the lin protocol engine is about to transmit or receive lin frames. 0 no lin frame transmission or reception in progress. 1 lin frame transmission or reception in progress. tact transmitter active. this status bit is set as long as the transmission of a frame or special character is ongoing. 0 no transmission in progress. 1 transmission in progress. ract receiver active. this status bit is set as long as the receive is active. the set and clear conditions for the sci mode are described in section , receiver states and transitions .the set and clear conditions for the lin mode are described in section , lin byte field reception . 0 no reception in progress. 1 reception in progress. table 734. esci_ifsr1 field descriptions (continued) field description figure 771. interrupt flag and status register 2 (esci_ifsr2) esci_base + 0x000a write: anytime 1514131211109876543210 0123456789101112131415 r rxrdy txrdy lwake sto pberr cerr ckerr frc000000ureqovfl w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0100000000000000 enhanced serial communication interface (esci) RM0029 1366/1740 doc id 15177 rev 8 lin control register 1 (esci_lcr1) this register provides control bits to control and configure the lin hardware. this register provides the interrupt enable bits for the interrupt flags in interrupt flag and status register 2 (esci_ifsr2) . table 735. esci_ifsr2 field descriptions field description rxrdy receive data ready interrupt flag. this interrupt flag is set when the payload data of a received frame was transferred into the lin receive register (esci_lrr) and the receive dma is disabled. txrdy transmit data ready interrupt flag. this interrupt flag is set when a) the content of the lin transmit register (esci_ltr) was processed by the lin pe to generate frame header or frame transmit data, or b) when the module has transmitted a lin wakeup signal frame. lwake lin wake-up received interrupt flag. this interrupt flag is set when a lin wake-up character was received, as described in section , lin wake up . sto slave timeout interrupt flag. this interrupt flag is set when a slave-not-responding-error is detected. a detailed description is given in section , slave-not-responding-error detection . pberr physical bus error interrupt flag. this interrupt flag is set when the receiver input remains unchanged for at least 31 rclk clock cycles after the start of a byte transmission, as described in section , lin error reporting . cerr crc error interrupt flag. this interrupt flag is set when an incorrect crc pattern was detected for a received lin frame. ckerr checksum error interrupt flag. this interrupt flag is set when a checksum error was detected for a received lin frame. frc frame complete interrupt flag. this interrupt flag is set when a lin tx frame has been completely transmitted or a lin rx frame has been completely received. ureq unrequested data received interrupt flag. this interrupt flag is set when unrequested activity has been detected on the lin bus, as described in section , lin error reporting . ovfl overflow interrupt flag. this interrupt flag is set when an overflow as described in section , overflow detection was detected. figure 772. lin control register 1 (esci_lcr1) esci_base + 0x000c write: anytime 1514131211109876543210 0123456789101112131415 r lres 0 wud 00 prty lin rxie txie wuie stie pbie cie ckie fcie wwu reset0000000000000000 RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1367/1740 table 736. esci_lcr1 field descriptions field description lres lin protocol engine stop and reset. this bit is used to stop and reset the lin protocol engine as described in section , lin protocol engine stop and reset . 0 lin protocol engine is operational. 1 lin protocol engine is reset and stopped. wu lin bus wake-up trigger. this bit is used to trigger the generation of a wake-up signal frame on the lin bus, as described in section , lin wake up . 0 write has no effect. 1 write triggers the generation of a wake-up signal. wud lin bus wake-up delimiter time. this field determines how long the lin protocol engine waits after the end of the transmitted wake-up signal, before starting the next lin frame transmission. 00 3 bit times. 01 7 bit times. 10 31 bit times. 11 63 bit times. prty parity generation control. this bit controls the generation of the two parity bits in the lin header. 0 parity bits generation disabled. 1 parity bits generation enabled. lin lin mode control. this bit controls whether the device is in sci or lin mode. 0sci mode. 1 lin mode. rxie receive data ready interrupt enable. this bit controls the esci_ifsr2[rxrdy] interrupt request generation. 0 rxrdy interrupt request generation disabled. 1 rxrdy interrupt request generation enabled. txie transmit data ready interrupt enable. this bit controls the esci_ifsr2[txrdy] interrupt request generation. 0 txrdy interrupt request generation disabled. 1 txrdy interrupt request generation enabled. wuie lin wake-up received interrupt enable. this bit controls the esci_ifsr2[lwake] interrupt request generation. 0 lwake interrupt request generation disabled. 1 lwake interrupt request generation enabled. stie slave timeout flag interrupt enable. this bit controls the esci_ifsr2[sto] interrupt request generation. 0 sto interrupt request generation disabled. 1 sto interrupt request generation enabled. pbie physical bus error interrupt enable. this bit co ntrols the esci_ifsr2[pberr] interrupt request generation. 0 pberr interrupt request generation disabled. 1 pberr interrupt request generation enabled. cie crc error interrupt enable. this bit controls the esci_ifsr2[cerr] interrupt request generation. 0 cerr interrupt request generation disabled. 1 cerr interrupt request generation enabled. enhanced serial communication interface (esci) RM0029 1368/1740 doc id 15177 rev 8 lin control register 2 (esci_lcr2) this register provides the interrupt enable bits for the interrupt flags in interrupt flag and status register 2 (esci_ifsr2). ckie checksum error interrupt enable. this bit controls the esci_ifsr2[ckerr] interrupt request generation. 0 ckerr interrupt request generation disabled. 1 ckerr interrupt request generation enabled. fcie frame complete interrupt enable. this bit controls the esci_ifsr2[frc] interrupt request generation. 0 frc interrupt request generation disabled. 1 frc interrupt request generation enabled. table 736. esci_lcr1 field descriptions field description figure 773. lin control register 2 (esci_lcr2) esci_base + 0x000e write: anytime 1514131211109876543210 0123456789101112131415 r000000 uqie ofie 00000000 w reset0000000000000000 table 737. esci_lcr2 field descriptions field description uqie unrequested data received interrupt enable. this bit controls the esci_ifsr2[ureq] interrupt request generation. 0 ureq interrupt request generation disabled. 1 ureq interrupt request generation enabled. ofie overflow interrupt enable. this bit controls the esci_ifsr2[ovfl] interrupt request generation. 0 ovfl interrupt request generation disabled. 1 ovfl interrupt request generation enabled. RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1369/1740 lin transmit register (esci_ltr) this register is used by the application to initiate the lin frame header generation for both lin tx frames and lin rx frames. if a lin tx frame is generated, this register is used to provide the payload data for the lin tx frame. if the lin pe is in the idle state (esci_lcr[lres] = 1) or performs a wakeup, each write access to this register is ignored. in case of an read access, the register provides the last data written into this register in the data field. if the application initiates a lin tx frame transfer, i.e the td bit is set to 1, the content and usage shown in lin transmit register (esci_ltr) - lin tx frame generation applies. the initiation and transmit of a tx frame is described in section , lin tx frame generation . if the application initiates an lin rx frame, i.e the td bit is set to 0, the content and usage shown in lin transmit register (esci_ltr) - lin rx frame generation applies. the initiation and transmit of a rx frame is described in section , lin rx frame generation . each successful write access to this register increments the internal write access counter and enables the writing to the next field. the write access counter is reset if the lin pe is in the idle state (esci_lcr[lres] = 1) a lin tx frame was completely transmitted (esci_sr[frc] was set to 1) a lin rx frame was completely received (esci_sr[frc] was set to 1) figure 774. lin transmit register (esci_ltr) - lin tx frame generation esci_base + 0x0010 write: lin mode 01234567 rdata 1st w p id 2nd w len 3rd w csm cse crc td (=1) to (ignored) 4th+ w d reset00000000 figure 775. lin transmit register (e sci_ltr) - lin rx frame generation 01234567 rdata 1st w p[1:0] id[5:0] 2nd w len 3rd w csm cse crc td (=0) to[11:8] 4th w to[7:0] reset00000000 enhanced serial communication interface (esci) RM0029 1370/1740 doc id 15177 rev 8 lin receive register (esci_lrr) this register provides the data bytes of received in case of an lin rx frame was initiated. table 738. esci_ltr field descriptions field description data value written in the most recent successful write access. p identifier parity. this field provides the identifier parity which is used to create the protected identifier if the automatic identifier parity generation is disabled, i.e the prty bit in lin control register 1 (esci_lcr1) is 0. id identifier. this field is used for the identifier field in the protected identifier. len frame length. this field defines the number of data bytes to be transmitted or received. csm checksum model. this bit controls the checksum calculation model used. 0 classic checksum model (lin 1.3). 1 enhanced checksum model (lin 2.0). cse checksum enable. this bit control the generation and checking of the checksum byte. 0 no generation and checking of checksum byte. 1 generation and checking of checksum byte. crc crc enable. this bit controls the generation of checking standard or enhanced lin frames, which are described in section , lin frame formats 0 standard lin frame generation and checking. 1 enhanced lin frame generation and checking. td transfer direction. this bit control the transfer direction of the data, crc, and checksum byte fields. 0 data, crc, and checksum byte fields received, described in section , lin rx frame generation . 1 data, crc, and checksum byte fields transmitted, described in section , lin tx frame generation . to timeout value. the content of the field depends on the transfer direction. rx frame: defines the time available for a complete rx frame transfer, as described in section , slave-not-responding-error detection tx frame: must be set to 0. d transmit data . data bits for transmission. figure 776. lin receive register (esci_lrr) esci_base + 0x0014 read only 01234567 rd w reset00000000 RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1371/1740 lin crc polynomial register (esci_lpr) control register 3 (esci_cr3) this register is used to control the frame formats and the generation of the err bit in the sci data register (esci_dr) . table 739. esci_lrr field descriptions field description d receive data . this field provides the data bytes of received lin rx frames. figure 777. lin crc polynomial register (esci_lpr) this register provides the crc polynom for gen eration and processing of crc-enhanced lin frames. esci_base + 0x0018 write: anytime 0123456789101112131415 r p w reset1100010110011001 table 740. esci_lpr field descriptions field description p polynomial bit x p[n] . used to define the lin polynomial. reset value results in x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1, which is the polynomial used for the can protocol. figure 778. control register 3 (esci_cr3) esci_base + 0x001a write: anytime 0123456789101112131415 r0 0 0 0 ero e erfe erpe m2 00000000 w reset0000000000000000 enhanced serial communication interface (esci) RM0029 1372/1740 doc id 15177 rev 8 table 741. esci_cr3 field descriptions field description 3 eroe err flag overrun enable. 0 esci_dr[err] flag not affected by overrun detection. 1 esci_dr[err] flag is set on overrun detection during frame reception. 2 erfe err flag frame error enable. 0 esci_dr[err] flag not affected by frame error detection. 1 esci_dr[err] flag is set on frame error detection for the data provided in esci_dr. 1 erpe err flag parity error enable. 0 esci_dr[err] flag not affected by parity error detection. 1 esci_dr[err] flag is set on parity error detection for the data provided in esci_dr. 0 m2 frame format mode 2. this control bit together with the m bit of the control register 1 (esci_cr1) controls the frame format used. the supported frame formats and the related settings are defines in section 31.4.2, frame formats . RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1373/1740 31.4 functional description this section provides a complete functional description of the esci block, detailing the operation of the design from the end user perspective in a number of subsections. 31.4.1 module control the operational mode of the module is controlled by the mdis bit in the control register 2 (esci_cr2) . the module can transmit and receives data when it is enabled, i.e mdis=0. 31.4.2 frame formats the esci module uses the standard nrz mark/space data format. the esci supports three basic frame types, which are the data frames, break characters, and idle characters. data frame formats each data frame contains a character that is surrounded by a start bit, an optional parity or address bit, and one or two stop bits. the supported data frame formats for transmission and reception are specified in table 742 . the supported data frame formats for reception only are specified in table 743 . table 742. supported data frame formats for rx and tx control frame content esci_cr3 esci_cr1 start bits payload bits stop bits m2 m pe wake character bits address bits (1) parity bits lin byte fields ( figure 779 ) 000018001 sci frames (8 payload bits)( figure 780 ) 000018001 000117101 001017011 sci frames (9 payload bits) ( figure 781 ) 010019001 010118101 011018011 1. the address bit identifies the frame as an address character. see section , multiprocessor communication . enhanced serial communication interface (esci) RM0029 1374/1740 doc id 15177 rev 8 the structure of the lin byte fields in normal polarity is shown in figure 779 . figure 779. lin byte field format the structures of the supported sci frame formats with 8 payload bits are shown in figure 780 . figure 780. sci frame formats (8 payload bits) the structures of the supported sci frame formats with 9 payload bits are shown in figure 781 . figure 781. sci frame formats (9 payload bits) the structures of the supported sci frame formats with 2 stop bits in normal polarity are shown in figure 782 . this frame format is supported for reception only. table 743. supported data frame formats for rx only control frame content esci_cr3 esci_cr1 start bits payload bits stop bits m2 m pe wake character bits address bits parity bits sci frames (2 stop bits) (see figure 782 ) 101018012 11101120 1 2 bit0 start bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 start bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit0 start bit addr bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 start bit parity bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit0 start bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 start bit addr bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit0 start bit parity bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1375/1740 figure 782. sci frame formats (2 stop bits) inverted data frame formats the structures of the supported data frame formats in inverted polarity are shown in figure 783 . these frame types are supported for reception only. the polarity of the rxd pin is controlled by the rxpol bit in the control register 2 (esci_cr2) . figure 783. inverted sci frame formats break character formats the supported break character formats are specified in ta ble 74 4 . the structure and content of the lin break symbols is shown in figure 784 . bit0 start bit parity bit stop bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit0 start bit parity bit stop bit stop bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 table 744. supported break character formats control (1) 1. all codings which are not listed are reserved and must not be used. break character content esci_cr3 esci_cr1 esci_cr2 start bit character bits delemit bits m2 m brcl lin break symbol (see figure 784 ) 000191 001 1 12 1 sci break character (see figure 785 ) 000190 001 1 12 0 010 1 10 0 011 1 13 0 start bit stop bit start bit stop bit stop bit enhanced serial communication interface (esci) RM0029 1376/1740 doc id 15177 rev 8 figure 784. lin break symbol format the structure and content of the sci break characters is shown in figure 785 . figure 785. sci break character formats idle character formats an idle character is a sequence of bits with the value 1. the supported idle character formats are specified in table 745 . the preamble has the same structure and content as an idle character. the structure and content of the idle characters is shown in figure 786 . bit0 start bit break delemit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit0 start bit break delemit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit0 start bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit0 start bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit0 start bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit0 start bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit12 table 745. supported idle character formats control idle character length esci_cr3[m2] esci_cr1[m] idle characters (see figure 786 ) 00 10 01 11 10 12 11 16 RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1377/1740 figure 786. idle character formats 31.4.3 baud rate and clock generation a 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. the value written to the sbr field in the baud rate register (esci_brr) determines the module clock divisor. the baud rate clock is synchronized with the bus clock and drives the receiver. the baud rate clock divided by 16 drives the transmitter. the receiver has an acquisition rate of 16 samples per bit time. the baud rate generator is enabled when the te bit or re bit in the control register 1 (esci_cr1) is set to 1 for the first time. the baud rate generator is disabled when sbr = 0. baud rate generation is subject to one source of error: integer division of the module clock may not give the exact required target baud rate. figure 746 lists some examples of achieving target baud rates with a module clock frequency of mclk = 10.2 mhz. module clock the module clock mclk is derived from the system bus clock. it has the same phase and frequency. bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit10 bit9 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit10 bit9 bit11 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit10 bit9 bit11 bit12 bit13 bit14 bit14 table 746. baud rates error example (mclk = 10.2 mhz) esci_brr[sbr] rclk (hz) tclk (hz) target baud rate error (%) 17 600,000.0 37,500.0 38,400 2.3 33 309,090.9 19,318.2 19,200 .62 66 154,545.5 9659.1 9600 .62 133 76,691.7 4793.2 4800 .14 266 38,345.9 2396.6 2400 .14 531 19,209.0 1200.6 1200 .11 1062 9604.5 600.3 600 .05 2125 4800.0 300.0 300 .00 4250 2400.0 150.0 150 .00 5795 1760.1 110.0 110 .00 enhanced serial communication interface (esci) RM0029 1378/1740 doc id 15177 rev 8 transmitter clock the transmitter clock tclk is used to drive the data to the serial bus via the txd pin. it is derived from the system bus clock by the baud rate generator. the baud rate generator is controlled by the value of the sbr field in the baud rate register (esci_brr) . the frequency of the transmitter clock is determined by equation 33 and defines the length of the transmitted bits, which is denoted as the bit time . equation 33 receiver clock the receiver clock rclk is used to sample the data received on the rxd or txd pin. it is derived from the system bus clock by the baud rate generator. the baud rate generator is controlled by the value of the sbr field in the baud rate register (esci_brr) . the frequency of the receiver sample clock is determined by equation 34 . equation 34 the frequency of the receiver clock is 16 times the frequency of the transmitter clock, this each bit is sampled with 16 samples. each of the 16 samples of a bit has a sample number assigned, which is defined by the receiver sample counter rsc. the n-th sample is denoted by rsn. the receiver sample counter rsc is updated with each rising edge of the receiver clock rclk. 31.4.4 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples rs8, rs9, and rs10 to fall outside the actual stop bit. a noise error will occur if the stop bit sample rs8, rs9, and rs10 samples are not all the same logical value 1. a framing error will occur if the receiver clock is misaligned in such a way that the majority of the rs8, rs9, and rs10 stop bit samples are a logic zero. faster receiver tolerance in this case the receiver has a higher baud rate than the transmitter, thus the stop bit sampling starts already in the last transmitted payload bit. to ensure the correct, noise and framing error free reception of the stop bit, the samples rs8, rs9, and rs10 must be located in the transmitted stop bit as shown in figure 787 . f tclk f mclk 16 sbr ? ----------------------- - = f rt f mclk sbr ---------------- = RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1379/1740 figure 787. faster receiver the maximum tolerance that ensures error free reception can be calculated with the assumption, that rs7 is sampled during the last transmitted payload bit and rs8 is sampled in the stop bit. for an frame with n payload bits the transmitter starts the transmission of the stop bit equation 35 after the start of the transmission of the start bit. for an frame with n payload bits the receiver samples the rs8 sample of the stop bit equation 36 after the successful qualification of the start bit. to ensure error free reception of the stop bit, the transmitter must start the transmission of the stop bit before the receiver samples rsc8. equation 37 the maximum percent difference between the receiver baud rate and the transmitter baud rate is: equation 38 the maximum percent differences for the supported frames is given in table 747 rclk start bit rxd start bit qualification 6 7 8 2 1 3 rsc 8 9 10 data voting payload stop bit 6 7 tx stop n1 + () = 16 rt tr ?? rx stop n1 + () = 16 rt re 7rt re ? + ?? tx stop rx stop < baudrate rx stop tx stop ? rx stop --------------------------------------------- - ?? ?? ?? 100 enhanced serial communication interface (esci) RM0029 1380/1740 doc id 15177 rev 8 slower receiver tolerance in this case the receiver has a slower baud rate than the transmitter, thus the stop bit sampling is still running while the next start bit is already transmitted. to ensure the correct, noise and framing error free reception of the stop bit, the samples rs8, rs9, and rs10 must be located in the transmitted stop bit as shown in figure 788 . figure 788. slower receiver the maximum tolerance that ensures error free reception can be calculated with the assumption, that rs11 is sampled in the transmitted start bit and rs10 is sampled in the last stop bit. for an frame with n payload bits and s stop bits, the transmitter starts the transmission of the next start bit equation 39 after the start of the transmission of the previous start bit. for an frame with n payload bits and s stop bits, the receiver samples the rs10 sample of the last stop bit equation 40 after the successful qualification of the start bit. table 747. faster receiver maximum tolerance payload bits max baudrate difference tx stop rx stop 8 4.63% 144 151 9 4.19% 160 167 13 3.03% 224 231 rclk start bit rxd start bit qualification 6 7 8 2 1 3 rsc 8 9 10 data voting last stop bit 11 tx start ns1 ++ () = 16 rt tr ?? + () = 16 rt re 9rt re ? + ?? RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1381/1740 to ensure error free reception of the last stop bit, the transmitter must start the transmission of the start bit after the receiver samples rs10. equation 41 the maximum percent difference between the receiver baud rate and the transmitter baud rate is: equation 42 the maximum percent differences for the supported frames is given in table 748 31.4.5 sci mode sci mode configuration the application must configure the following bits and fields in order to achieve correct sci operation. enable sci mode ? lin control register 1 (esci_lcr1) [lin]:= 0 select baud rate ? baud rate register (esci_brr) [sbr] select receiver input mode ? control register 1 (esci_cr1) [loops] ? control register 1 (esci_cr1) [rsrc] select frame format ? control register 1 (esci_cr1) [m] ? control register 1 (esci_cr1) [pe] ? control register 1 (esci_cr1) [wake] ? control register 3 (esci_cr3) [m2] select parity type ? control register 1 (esci_cr1) [pt] table 748. slower receiver maximum tolerance payload bits stop bits max baudrate difference rx stop tx start 8 1 4.37% 153 160 9 1 3.97% 169 176 9 2 3.57% 185 196 13 2 2.73% 249 256 rx stop tx start < tx start rx stop ? tx start ------------------------------------------------- ?? ?? ?? 100 enhanced serial communication interface (esci) RM0029 1382/1740 doc id 15177 rev 8 transmitter the transmitter supports the transmission of all frame types defined in table 742 , of all break characters defined in table 744 , and of all idle characters defined in ta ble 74 5 . transmitter states and transitions the transmitter has four basic states which are shown and described in table 749 . the state transitions that can triggered by the application commands are shown in table 750 . the state transitions that can triggered by the module are shown in ta ble 75 1 . the state diagram of the transmitter is shown in figure 789 . figure 789. transmitter state diagram the current state of the transmitter can be determined by the te control bit in the control register 1 (esci_cr1) and the tact status bit in interrupt flag and status register 1 (esci_ifsr1) . the application triggers a transition described in table 750 when it issues a command by writing to the te bit in the control register 1 (esci_cr1) . the transition is triggered only if the conditions are fulfilled. as a result of the transition the state of the transmitter is changed as shown in figure 789 and the action given in table 750 is executed. ready en start idle reset_state run stop dis dis en halt done table 749. transmitter states state indication description esci_cr1[te] esci_ifsr1[tact] idle 0 0 transmitter is disabled and no transmission is running ready 1 0 transmitter is enabled and no transmission is running run 1 1 transmitter is enabled and transmission is running stop 0 1 transmitter is disabled and transmission is running table 750. transmitter application transitions transition command precondition action description en esci_cr1[te]:=1 esci_cr1[te]=0 ipre:=1 transmitter is enabled by application command. dis esci_cr1[te]:=0 esci_cr1[te]=1 transmitter is disabled by application command RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1383/1740 the module transition shown in table 751 are triggered when the described condition or event occurs. the send break bit sbk in the control register 1 (esci_cr1) is check for the start condition. the internal commit bit icmt, the transmitter active bit tact in the interrupt flag and status register 1 (esci_ifsr1) , the tdre, and the tc flag in the interrupt flag and status register 1 (esci_ifsr1) are changed as a action result of the transition. frame and character transmission the transmitter starts the transmission of a data frame or special character when the condition for the start transition as described in ta ble 75 1 is fulfilled. there are three source for data or character transmission. the priority among these source are specified in ta ble 75 2 . all three sources can be available at one point in time. cpu controlled sci data frame transmission the transmission of a data frame is started when the transmitter is in its ready state and only the commit bit icmt is set. as the first step, the content of the sci data register (esci_dr) is transferred into the internal transmitter shift register. when this transfer is finished, the internal commit bit icmt is cleared and the transmit data register empty flag tdre in the interrupt flag and status register 1 (esci_ifsr1) is set. if the transmit interrupt enable bit tie in the control register 1 (esci_cr1) is also set, the tdre flag generates a transmitter interrupt request. the transmitter shift register then shifts a frame out through the txd output signal, which is prefaced with a start bit and appended with the parity bit, if configured, and the configured number of stop bits. table 751. transmitter module transitions transition condition action description start (state=ready) and (sbk=1 or ipre=1 or icmt=1) tact:=1 start of transmission of data frame or special character when data are available or character transmission request is pending. done state=run and last stop bit transmitted tact:=0 tc:= (sbk=0 & ipre=0 & icmt=0) finished transmission of data frame or special character and transmitter still enabled. transmission is complete if no transmit request is pending. halt state=stop and last stop bit transmitted tact:=0 tc:=1 icmt:=0 finished transmission of data frame or special character and transmitter was disabled. table 752. transmit source priority priority indication transmission source (highest) 0 ipre=1 preamble. 1 esci_cr1[sbk]=1 break character. (lowest) 2 icmt=1 sci data register (esci_dr) frame. enhanced serial communication interface (esci) RM0029 1384/1740 doc id 15177 rev 8 when the last stop bit has been transmitted and the application has not disabled the transmitter, the transmitter returns to the ready state via the done transition. if no frame or character transmit request is pending, the transfer complete flag tc in the interrupt flag and status register 1 (esci_ifsr1) is set. if the application has disabled the transmitter while the frame is transmitted and stop bit has been transmitted, the transmitter goes into the idle state via the halt transition. the transfer complete flag tc in the interrupt flag and status register 1 (esci_ifsr1) is set and the internal commit bit icmt is cleared. dma controlled sci data frame transmission in this mode, the esci module handles the generation of data frames internally. when new data required for transmission, the module generates the transmit dma request and the dma controller delivers the required data via write accesses to sci data register (esci_dr) . the write access to the low byte of sci data register (esci_dr) triggers the transmission of the data. the write access to the high byte of sci data register (esci_dr) triggers no internal operation. the application request the esci module to enter this mode by setting the txdma bit in the control register 2 (esci_cr2) . from this point in time, the module start the generation of dma requests and frame transmission. before entering this mode, the application should perform the following actions: 1. configure the module for sci mode. 2. enable the transmitter by setting te in control register 1 (esci_cr1) to 1. 3. setup the dma controller channel and provide frame data in system memory a block diagram which presents an overview of the dma controlled date frame transmission is shown in figure 790 . figure 790. dma controlled sci data frame generation dma controller esci tx dma channel data 2 data n system memory data 1 data n sci data frame data 1 RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1385/1740 parity generation the esci module generates the parity bit in transmitted data frame when the parity enable bit pe in the control register 1 (esci_cr1) is set. the parity type bit pt in the control register 1 (esci_cr1) defines whether the odd or even parity is generated. preamble transmission the transmission of a preamble is started when the transmitter is in ready state, the internal ipre bit, which is not visible to the application, is set, and the sbk in the control register 1 (esci_cr1) is clear. after the transmission of the stop bit and if the application has not disabled the transmitter, the transmitter returns to the ready state via the done transition. if no frame or character transmit request is pending, the transfer complete flag tc in the interrupt flag and status register 1 (esci_ifsr1) is set. if the application has disabled the transmitter while the preamble is transmitted and if the stop bit has been transmitted, the transmitter goes into the idle state via the halt transition. the transfer complete flag tc in the interrupt flag and status register 1 (esci_ifsr1) is set and the internal commit bit icmt is cleared. break character transmission the transmission of a break character is started when the transmitter is in ready state and the send break character bit sbk in the control register 1 (esci_cr1) is set. after the transmission of the break character and if the application has not disabled the transmitter, the transmitter returns to the ready state via the done transition and restarts the transmission. as long as sbk bit remains set, the transmitter continues to send break characters. when the application has cleared the sbk bit or has disabled the transmitter, the transmitter continues to transmit the current break character and after it has finished the transmission of this break character it transmits a stop bit. the stop bit at the end of a break character sequence guarantees the recognition of the start bit of the next data frame. after the transmission of the stop bit and if the application has not disabled the transmitter, the transmitter returns to the ready state via the done transition. if no frame or character transmit request is pending, the transfer complete flag tc in the interrupt flag and status register 1 (esci_ifsr1) is set. if the application has disabled the transmitter while the break character is transmitted and if the stop bit has been transmitted, the transmitter goes into the idle state via the halt transition. the transfer complete flag tc in the interrupt flag and status register 1 (esci_ifsr1) is set and the internal commit bit icmt is cleared. receiver the receiver supports the reception of all data frame types defined in table 742 and ta ble 74 3 , of all break character defined in table 744 , and of all idle characters defined in ta ble 74 5 . receiver states and transitions the receiver has four basic states which are shown and described in table 750 . the state transitions that can triggered by the application commands are shown in table 750 . the enhanced serial communication interface (esci) RM0029 1386/1740 doc id 15177 rev 8 state transitions that can triggered by the module are shown in table 751 . the state diagram of the transmitter is shown in figure 789 . figure 791. receiver state diagram the current state of the receiver can be determined by the re and rwu bit in the control register 1 (esci_cr1) and the ract status bit in interrupt flag and status register 1 (esci_ifsr1) . the application triggers a transition described in table 754 when it issues a command by writing to the re bit in the control register 1 (esci_cr1) . the transition is triggered only if the conditions are fulfilled. as a result of the transition the state of the receiver is changed as shown in figure 791 and the action given in table 754 is executed. the module transitions shown in table 755 are triggered when the described event occurs. ready en start idle reset_state dis dis done run wake-up slp slp wake0 wake1 table 753. receiver states state indication description re ract rwu idle 0 0 0 receiver is disabled and no reception is running ready 1 0 0 receiver is enabled and no reception is running run 1 1 0 receiver is enabled and reception is running wake-up 1 - 1 receiver is in wake-up mode table 754. receiver application transition transition command condition action description en re:=1 re=0 receiver is enabled by application command. dis re:=0 re=1 receiver is disabled by application command slp rwu:=1 re=1 receiver is set into wake-up mode RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1387/1740 receiver input mode selection this section describes the three receiver input modes supported by the esci module. the modes are selected by the loops and rsrc control bits in the control register 1 (esci_cr1) . dual wire mode in dual wire mode, the esci uses the txd pin for transmitting and the rxd pin for data receiving. table 755. receiver module transition transition condition action description start (state=ready,run) and (start bit qualified) ract:=1 start of reception of data frame or break character. done (state=run) and (start bit not verified or idle character received) ract:=0 start bit not verified or idle character received. wake0 (state=wake-up) and (idle character received) rwu:=0 wake-up idle character received. wake1 (state=wake-up) and (address frame received) rwu:=0 wake-up address frame received. enhanced serial communication interface (esci) RM0029 1388/1740 doc id 15177 rev 8 figure 792. dual wire mode single wire mode in single wire mode, the rxd pin is disconnected from the esci module and the txd pin is used for both receiving and transmitting. figure 793. single wire mode loop mode in loop mode, the input of the receiver is driven by the output of the transmitter. the rxd pin is disconnected from the esci module. figure 794. loop mode frame and character reception the receiver is started when it is in ready or wake-up state and on the selected receiver input (see section , receiver input mode selection ) an active signal is sampled. the receiver enters the run or wake-up state. the received bits are recovered by the bit sampling described in section , bit sampling . during the reception, the received bits are shifted into the internal shift register. break character detection the receiver does not provide any means to detect the reception of a break character. instead, break characters are processed as data frames. due to the received 0 at the stop rxd transmitter receiver txd transmitter receiver rxd txd transmitter receiver rxd txd RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1389/1740 bit location, the reception of a break character causes at least a framing error. the error reporting is performed as described in section , reception error reporting . idle character detection the idle character detection starts after the reception of the last stop bit. cpu controlled sci data frame reception this section describes the reception process when the receiver is in the run state. when the required number of frame bits have been received, the payload bits of the received frame are transferred into sci data register (esci_dr) if the rdrf flag is 0. the receive data register full flag rdrf in interrupt flag and status register 1 (esci_ifsr1) is set. if the receive interrupt enable bit rie in the interrupt flag and status register 1 (esci_ifsr1) is set, the rdrf interrupt request is generated. if an idle character has been detected, the idle flag in the interrupt flag and status register 1 (esci_ifsr1) is set. if the idle line interrupt enable bit ilie in the control register 1 (esci_cr1) is set, the idle interrupt request is generated. if any of the receiver errors described in section , reception error reporting ? have been occurred, that corresponding flags will be set. if the application disabled the receiver by clearing the receiver enable bit re in the interrupt flag and status register 1 (esci_ifsr1) the current frame is discarded and no flags will be updated. dma controlled sci data frames reception in this mode, the esci module controls the reception of sci data frames automatically and utilizes the connected dma channels. a block diagram which presents an overview of the dma controlled sci data frame reception is shown in figure 795 . the rx dma channel is used to transfer the received frame data into the memory. when new data was received, the module generates the receive dma request and the dma controller retrieves the provided data from the sci data register (esci_dr) . the read access from the low byte of the sci data register (esci_dr) signals the end of the dma cycle for the current data and triggers the reception of new data. the read access from the sci data register (esci_dr) triggers no internal action. the application request the esci module to enter this mode by setting the rxdma bit in the control register 2 (esci_cr2) . from this point in time, the module start the generation of dma requests and frame transmission and reception. before entering this mode, the application should perform the following actions: 1. configure the module for sci mode. 2. enable the receiver by setting re in control register 1 (esci_cr1) to 1. 3. setup the dma controller channel. enhanced serial communication interface (esci) RM0029 1390/1740 doc id 15177 rev 8 figure 795. dma controlled sci data frame reception receiver overrun when the esci module has received a frame and attempts to transfer the payload data of the received frame into the sci data register (esci_dr) but neither the application nor the dma controller has read the sci data register (esci_dr) since its last update, the overrun flag or in the interrupt flag and status register 1 (esci_ifsr1) is set. the data contained in sci data register (esci_dr) are not changed and the received data are lost. wake-up frame reception this section describes the reception process when the receiver is in the wake-up state. when the required number of frame bits have been received, the payload bits of the received frame are transferred into sci data register (esci_dr) if the rdrf flag is 0. if the address-mark wake-up mode is selected and the received frame has the address bit set, the receive data register full flag rdrf in interrupt flag and status register 1 (esci_ifsr1) is set. if the receive interrupt enable bit rie in the interrupt flag and status register 1 (esci_ifsr1) is set, the rdrf interrupt request is generated. the rwu bit is cleared, and the receiver enters the run state via the wake1 transition. if the idle line wake-up mode is selected and the receiver has detected an idle character, the rwu bit is cleared, and the receiver enters the ready state via the wake0 transition. if any of the receiver errors described in section , reception error reporting have been occurred, that corresponding flags will be set. bit sampling the receiver samples the selected receiver input (see section , receiver input mode selection ) with the receiver clock rclk. the bit sampling for start bit detection is shown in figure 796 , the bit sampling for data and stop bit reception is shown in figure 797 . the samples indicated by dashed arrows are not used by the receiver. the received data bits are transferred into the internal shift register after the data strobing. if noise or framing errors were detected, this is flagged as described in section , reception error reporting . dma controller esci system memory data 1 data n sci data frame rx dma channel data 2 data n data 1 RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1391/1740 bit synchronization to adjust for baud rate mismatch, a synchronization of the cyclic receive sample counter rsc is performed during start bit reception as described in section , start bit sampling . start bit sampling figure 796. start bit sampling and strobing the sampling of the start bit consists of three phases, the start bit qualification, the start bit verification, and the start bit noise detection. start bit qualification to adjust for baud rate mismatch, the cyclic receive sample counter rsc is re-synchronized after a successful start bit qualification. a start bit is successfully qualified if the start qualification is active, and a low sample is read, and the low sample was preceded by three consecutive high samples. the start bit qualification becomes active after module reset, or after receiver disable and subsequent enable, or after the 7-th sample if the start bit verification failed, or after the 10-th sample of last stop bit of the preceding frame (example shown in figure 796 ). the start bit qualification becomes inactive after successful start bit qualification. start bit verification after the successful start bit qualification the receiver starts to verify the start bit by a two out of three samples majority voting. a start bit is verified if at least two out of the three sample rsc3, rsc5, and rsc7 are sampled low. noise is detected when exactly one out of the three samples is high. in this sampled value rclk start bit receiver input start bit qualification 1 1 1 11000 0 0 00 6 7 8 9 10 1 2 sample counter reset 3 rsc 4 5 6 7 0 8 9 10 11 12 13 14 15 16 1 00 start bit verification start bit noise detection data strobing 01 0 01 000 2 sample counter wrap enhanced serial communication interface (esci) RM0029 1392/1740 doc id 15177 rev 8 case, the noise flag esci_ifsr1[nf] is set. the result of the start bit verification is summarized in table 756 . if the start bit verification was not successful , the receiver activates the start bit qualification. if the start bit verification was successful , the receiver continues sampling to perform data noise detection on the samples at rsc8, rsc9, and rsc10. the result of the start bit data noise detection is summarized in table 757 . if noise is detected, the noise flag esci_ifsr1[nf] is set. table 756. start bit verification result [rsc3, rsc5, rsc7] start bit verified verification noise detected 000 yes no 001 yes yes 010 yes yes 100 yes yes 011 no no 101 no no 110 no no 111 no no table 757. start bit noise detection [rsc8, rsc9, rsc10] noise detected 000 no 001 yes 010 yes 100 yes 011 yes 101 yes 110 yes 111 yes RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1393/1740 data bit sampling figure 797. data and stop bit sampling and strobing to determine the value of a data bit and to detect noise, a two out of three majority voting is performed on the samples rsc8, rsc9, and rsc10. tab le 7 58 summarizes the results of the data bit sample. the receiver detects the number of data bit according to the selected frame format. if noise is detected, the noise flag esci_ifsr1[nf] is set. stop bit verification the reception of a valid stop bit is verified if at least two out of the sample rsc8, rsc9, and rsc10 are sampled high. if this is not that case, a framing error is detected. noise is detected if not all of the samples are of the same value. in this case, the noise flag esci_ifsr1[nf] is set. the result of the stop bit verification is summarized in table 759 . sampled value rclk data / stop bit receiver input 1 1 1 11000 0 0 00 2 3 rsc 4 5 6 7 0 8 9 10 11 12 13 14 15 16 1 00 data voting data strobing 01 0 01 000 2 sample counter wrap 1 12 13 14 15 16 sample counter wrap table 758. data bit sampling [rsc8, rsc9, rsc10] data bit value noise detected 000 0 no 001 0 yes 010 0 yes 100 0 yes 011 1 yes 101 1 yes 110 1 yes 111 1 no table 759. stop bit verification [rsc8, rsc9, rsc10] stop bit verified framing error detected noise detected 000noyesno 001noyesyes enhanced serial communication interface (esci) RM0029 1394/1740 doc id 15177 rev 8 parity checking the esci module calculates the parity of a received character and checks is versus the received parity bit in the received data frame when the parity enable bit pe in the control register 1 (esci_cr1) is set. the parity type bit pt in the control register 1 (esci_cr1) defines whether to check for odd or even parity is generated. if an parity error is detected, this is reported as described in section , reception error reporting . reception error reporting the receiver can detect four error types: parity errors, framing errors, noise errors, and the overrun error. the receiver reports the errors detected during frame reception at the end of the reception of the last stop bit of a frame. for error reporting the receiver utilizes the or, nf, fe, and pf flags in the interrupt flag and status register 1 (esci_ifsr1) . if the receiver has detected an overrun as described in section , receiver overrun , only the or flag is set. all other error flags are not updated. if the receiver has detected noise as described in section , bit sampling the nf flag is set. if the receiver has not detected an overrun and has detected a framing error as described in section , bit sampling the fe flag is set. if the receiver has not detected an overrun and has detected a parity error as described in section , parity checking the pf flag is set. multiprocessor communication the multiprocessor communication allows one processor to send blocks of frames to other processors on the same serial link. to avoid the received data interrupt for frames not intended for the processor, the esci receiver can be put into the wake-up state. if the receiver is in the wake-up state, the esci will still load the received data into the sci data register (esci_dr) , but will not set the rdrf flag and consequently not request the rdrf interrupt. the receiver leaves the wake-up state and clears the rwu bit in the control register 1 (esci_cr1) when the wake-up pattern configured by wake bit in control register 1 (esci_cr1) is received. the esci module supports two types of wake-up patterns, the idle-line wakup pattern and the address-mark wake-up pattern. 010noyesyes 100noyesyes 011 yes no yes 101 yes no yes 110 yes no yes 111 yes no no table 759. stop bit verification (continued) [rsc8, rsc9, rsc10] stop bit verified framing error detected noise detected RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1395/1740 idle-line wake up the idle-line wake-up mode is selected when the wake bit in control register 1 (esci_cr1) is 0. in this mode, the receiver leaves the wake-up state, when an idle character is detected as described in section , idle character detection . the next received frame is the address frame that contains address information which can be evaluated by the application. if the application decides not to receive the frame block, it can set the rwu bit in the control register 1 (esci_cr1) and return the receiver to the wake-up state. figure 798. idle-line wake up address-mark wake up the address-mark wake-up mode is selected when the wake bit in control register 1 (esci_cr1) is 1. if the wake bit is set, the address bit is added to the frame format. in this mode, the receiver leaves the wake-up state, when a data frame with the address bit value of 1 was received. this frame is the address frame and contains address information which can be evaluated by the application. if the application decides not to receive the frame block, it can set the rwu bit in the control register 1 (esci_cr1) and return the receiver to the wake-up state. all data frames that belong to the frame block must have the address bit cleared. figure 799. address-mark wake up 31.4.6 lin mode the esci provides support for the lin protocol. it can be used to automate most tasks of a lin master. in conjunction with the dma interface it is possible to transmit entire lin frames and sequences of lin frames as well as to receive data from lin slaves without application intervention. there is no special support for lin slave mode. frame block frame block idle character receiver wake up address frame frame block frame block receiver wake up address frame (addr bit = 1) address frame (addr bit = 1) receiver wake up ignored idle times enhanced serial communication interface (esci) RM0029 1396/1740 doc id 15177 rev 8 lin mode configuration the application must configure the following bits and fields in order to achieve correct lin operation. the configuration of bits and fields not mentioned in this section depend on the connected lin slaves and the current application. enable lin mode ? lin control register 1 (esci_lcr1) [lin]:= 1 select rxd pin as receiver input ? control register 1 (esci_cr1) [loops]:= 0 ? control register 1 (esci_cr1) [rsrc]:= 0 select lin byte fields as used frame format ? control register 1 (esci_cr1) [m]:= 0 ? control register 1 (esci_cr1) [pe]:= 0 ? control register 1 (esci_cr1) [wake]:= 0 ? control register 3 (esci_cr3) [m2]:= 0 select break character length of 13 bit as required by lin 2.0 ? control register 2 (esci_cr2) [brcl]:= 1 select transmission stop on bit error detection ? control register 2 (esci_cr2) [bestp]:= 1 select transmission dma stop on bit error detection ? control register 2 (esci_cr2) [bstp]:= 1 enable both transmitter and receiver ? control register 1 (esci_cr1) [te]:= 1 ? control register 1 (esci_cr1) [re]:= 1 lin frame formats the term lin frame refers to a sequence of lin byte fields preceded by a break character, both are described in section 31.4.2, frame formats . the esci module allows to generate lin frames for lin slaves of lin standards 1.3 and 2.0. lin byte field reception the reception of a lin byte field starts with the successful start bit qualification and is finished with the reception of the 16-th sample of the stop bit when no start bit start bit qualification pattern has been detected. if a start bit start bit qualification pattern has been detected at or after the 10-th sample of the stop bit, the reception ends at this sample. an ongoing reception is indicated by the ract status bit in interrupt flag and status register 1 (esci_ifsr1) . the ract flag is set if all of the following conditions are fulfilled, 1. the receiver is enabled (esci_cr1[re] = 1), and 2. the lin task is not in reset (esci_lcr1[lres] = 0), and 3. the start bit start bit qualification pattern has been received (see section , start bit sampling ). the ract flag is cleared if at least one of the following conditions is fulfilled, RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1397/1740 1. the receiver is disabled (esci_cr1[re] = 0), or 2. the lin task is in reset (esci_lcr1[lres] = 1), or 3. the start bit verification fails at sample 7 according to table 756 , or 4. the 16-th sample of the stop bit has been received and no start bit qualification pattern has been detected at or after the 10-th sample. standard lin frames a standard lin frame, shown in figure 800 consists of a break character, a sync field, an id field, zero or more data fields, and a checksum field. the data fields and the checksum field are generated by the lin master for tx lin frames and generated by the lin slave for rx lin frames. the header fields will always be generated by the lin master. figure 800. standard lin frame format crc enhanced lin frames the crc enhanced lin frames shown in figure 801 contain two additional crc byte fields. these fields are located between the last data field and the checksum field. the value of the crc is calculated on the same byte fields as the checksum is calculated on. the polynom used for the crc calculation is defined by lin crc polynomial register (esci_lpr) . the esci module generates the crc fields for tx frames and checks the crc fields for rx frames if the crc bit in the lin transmit register (esci_ltr) was written with a value of 1. figure 801. crc enhanced lin frame format the crc enhanced lin frames are not part of the lin standard. lin tx frame generation the esci module supports two modes of lin tx frame generation, the cpu controlled mode and the dma controlled mode. in the cpu controlled mode, the application provides the required frame configuration and frame data by subsequent cpu write accesses to the lin transmit register (esci_ltr) . in the dma controlled mode, the dma controller provides the required frame configuration and frame data in response to dma requests generated by the esci module. cpu controlled lin tx frame generation in this mode, the application initiates the generation of an lin tx frame and provides the data to be transmitted by a sequence of subsequent cpu write accesses to the lin transmit register (esci_ltr) . when the esci module has processed the data written into lin transmit register (esci_ltr) , the txrdy interrupt flag in the interrupt flag and status register 2 (esci_ifsr2) will be set. break synch identifier data 1 data 2 data n checksum break synch identifier data 1 data 2 data n checksum crc1 crc2 enhanced serial communication interface (esci) RM0029 1398/1740 doc id 15177 rev 8 the application should clear the txrdy interrupt flag before writing data into the lin transmit register (esci_ltr) because the esci module will set the txrdy one clock cycle after the write access. the first data written to the lin transmit register (esci_ltr) provides the identifier and identifier parity fields. the second data written defines the number of data bytes to be transmitted. the third data written defines the crc and checksum generation. the td bit has to set to 1 in order to invoke the lin tx frame generation. the value of the to field is ignored by the esci module for lin tx frames. after the third data was written the generation of a lin tx frame is started. firstly, a break field is transmitted, then the synch field and the protected identifier field. all subsequent write accesses to the lin transmit register (esci_ltr) provide data bytes to be transmitted via the lin bus. a data byte field will be transmitted as soon as data are available. after the last data byte, defined by the value written to the len field, was send out, the configured crc and checksum fields will be send out. after the transmission of the checksum field of the lin tx frame, the write access counter for the lin transmit register (esci_ltr) is reset and the frc interrupt flag in the interrupt flag and status register 2 (esci_ifsr2) is set. dma controlled lin tx frame generation in this mode, the esci module controls the generation of an lin tx frame. when new data required for transmission, the esci module generates the transmit dma request and the dma controller delivers the required data. the application request the esci module to enter this mode by setting the txdma bit in the control register 2 (esci_cr2) . from this point in time, the module start the generation of dma requests and initiates the frame transmission. before entering this mode, the application should perform the following actions: 1. configure the module for lin mode. 2. enable the transmitter by setting te in control register 1 (esci_cr1) to 1. 3. setup the dma controller channel and provide frame data in system memory a block diagram which presents an overview of the dma controlled lin tx frame is shown in figure 802 . the content of the fields in the memory is the same as described in lin transmit register (esci_ltr) - lin tx frame generation . RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1399/1740 figure 802. dma controlled lin tx frame generation lin rx frame generation the esci module supports two modes of lin rx frame generation and reception, the cpu controlled mode and the dma controlled mode. in the cpu controlled mode, the application provides the required data by subsequent cpu write accesses to the lin transmit register (esci_ltr) and retrieves the received data by subsequent cpu read accesses to the lin receive register (esci_lrr) . in the dma controlled mode, the dma controller provides the required frame configuration data in response to dma requests generated by the esci module and transfers the received frame data to the memory in response to dma requests generated by the esci module. cpu controlled lin rx frames generation in this mode, the application initiates the generation of an lin rx frame by a sequence of subsequent cpu write accesses to the lin transmit register (esci_ltr) . when the esci module has processed the data written into lin transmit register (esci_ltr) , the txrdy interrupt flag in the interrupt flag and status register 2 (esci_ifsr2) will be set. the application should clear the txrdy interrupt flag before writing data into the lin transmit register (esci_ltr) because the esci module will set the txrdy one clock cycle after the write access. the first data written to the lin transmit register (esci_ltr) provides the identifier and identifier parity fields. the second data written defines the number of data bytes requested from the lin slave. the third data written defines the crc and checksum generation. the td bit has to set to 0 to invoke the rx frame generation. the to field defines the upper part of the timeout value. the fourth byte written defines the lower part of the timeout value. after the fourth byte was written the generation of a lin rx frame is started. firstly, a break field is transmitted, then the synch field and the protected identifier field. after the transmission of the protected identifier, the esci module starts to receive the frame data transmitted by the lin slave. when the module has received a complete byte field, the received data are transferred into the lin receive register (esci_lrr) and the receive data ready flag rxrdy in the interrupt flag and status register 2 (esci_ifsr2) is set. dma controller esci csm tx dma channel id[5:0] p[1:0] len 1 cse crc td 2 0 data 1 data 2 data n system memory 1 len must be set to n 2 td must be set to 1 break synch identifier data 1 data n checksum lin tx frame enhanced serial communication interface (esci) RM0029 1400/1740 doc id 15177 rev 8 the application can retrieve the received data by subsequent read access from lin receive register (esci_lrr) after checking the rxrdy flag. the application should clear the rxrdy flag immediately after reading the lin receive register (esci_lrr) . after the reception of the configured number of data from the slave, the module starts the reception of the configured crc and checksum byte fields. these dat a are not transferred into the lin receive register (esci_lrr) . the crc and checksum checking is performed internally. in case of errors, they will be reported as described in section , lin error reporting ? after the reception of the checksum field of the lin rx frame, the frc interrupt flag in the interrupt flag and status register 2 (esci_ifsr2) is set. dma controlled lin rx frames generation in this mode, the esci module controls the generation of lin rx frame header and the reception of the frame data automatically and utilizes the two connected dma channels. a block diagram which presents an overview of the dma controlled lin rx frame generation and reception is shown in figure 802 . the content of the header fields in the memory is the same as described in lin transmit register (esci_ltr) - lin rx frame generation . the tx dma channel is used the fetch the lin rx frame header and control information. the rx dma channel is used to transfer the received frame data into the memory. when new data required for transmission, the module generates the transmit dma request and the dma controller delivers the required data. when new data was received, the module generates the receive dma request and the dma controller retrieves the provided data. the application request the esci module to enter this mode by setting the rxdma bit in the control register 2 (esci_cr2) . from this point in time, the module start the generation of dma requests and frame transmission and reception. before entering this mode, the application should perform the following actions: 1. configure the module for lin mode. 2. enable transmitter and receiver by setting te and re in control register 1 (esci_cr1) to 1. 3. setup the two dma controller channels and provide frame header data in system memory. RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1401/1740 figure 803. dma controlled lin rx frame generation and reception lin error reporting this section describes error checking and the signaling of detected errors in lin mode. physical bus error detection if the receiver input is sampled 0 for at least 31 sample clock cycles after the start of the transmission of a lin frame, the physical bus error flag pberr in the interrupt flag and status register 2 (esci_ifsr2) will be set. unrequested activity detection if an unrequested byte is received (i.e. a byte which is not part of an rx frame) which is not recognized as a wake-up or break character, the bit error flag berr in the interrupt flag and status register 2 (esci_ifsr2) is set. in addition the rxrdy flag will also be set, the linrx register must be read before normal operations can proceed. standard bit error detection the standard bit error detection is enabled when the fast bit error detection control bit fbr in the control register 2 (esci_cr2) is 0. the standard bit error detection is performed after each lin byte field transmission. during the transmission of the lin frame header and lin frame data, the receiver is running and receives the signal values on the serial bus. after the complete transmission and the related reception of a lin byte field, the esci compares the data that was transmitted and the data that has been received. if they do not match, the bit error interrupt flag berr in the interrupt flag and status register 2 (esci_ifsr2) is set. fast bit error detection fast bit error detection has been designed to allow flagging of lin bit errors while they occur, rather than flagging them after a byte transmission has completed (see figure 804 ). dma controller esci csm tx dma channel id[5:0] p[1:0] len 1 cse crc td 2 to[11:8] data 1 data 2 data n system memory 1 len must be set to n 2 td must be set to 0 break synch identifier data 1 data n checksum lin rx frame to[7:0] rx dma channel from lin master from lin slave enhanced serial communication interface (esci) RM0029 1402/1740 doc id 15177 rev 8 figure 804. fast bit error detection on a lin bus if fast bit error detection bit fbr in the control register 2 (esci_cr2) is set the esci will compare the transmitted and the received data stream while the transmitter is active (not idle). once a mismatch between the transmitted data and the received data is detected the following actions are performed the bit error flag berr will be set. to adjust to different bus loads the sample point at which the incoming bit is compared to the one which was transmitted can be selected with the besm bit in the control register 2 (esci_cr2) . if esci_cr2[besm] = 1, the comparison will be performed with sample rs13, otherwise with rs9 (see figure 805 ) (also see section , bit sampling ). figure 805. timing diagram fast bit error detection note: to calculate the exact position of the sample point with regard to the rx pin, the delays through the pads and the two bus clock cycle delay through the input synchronizer also needs to be taken into account. slave-not-responding-error detection the slave-not-responding-error is defined in lin specification package revision 1.3; december 12, 2002 ; 6 error and exception handling. the lin specification requires that a no_response_error has to be detected if a message frame is not fully txd pin rxd pin lin physical interface synchronizer stage bus clock receive shift register transmit shift register lin bus compare sample point bit error output transmit shift register 1 2 3 4 5 6 7 8 9 10111213141516 input receive shift register esci_cr2[besm] = 0 esci_cr2[besm] = 1 compare sample points RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1403/1740 completed within the maximum length t frame_max by any slave task upon transmission of the synch and identifier fields. the maximum frame length tframe_max is defined in lin specification package revision 1.3; december 12, 2002 ; 3.3 length of message frame and bus sleep detect, as equation 43 where n data is the number of data byte fields of the message frame. the sto interrupt flag in the interrupt flag and status register 2 (esci_ifsr2) will be set, if an lin rx frame was not fully received in the amount of time specified in the timeout value field to in the lin transmit register (esci_ltr) . the time period starts with the falling edge of the transmitted lin break character and is specified in units of transmit bits. to achieve lin compliant slave-not-responding-error detection, the timeout value to in the lin transmit register (esci_ltr) field has to be set to t frame_max when a lin rx frame is initiated. checksum error detection if the checksum enable bit cse in the lin transmit register (esci_ltr) was set, the checksum checking is performed based on the received checksum byte. the checksum mode is selected by the csm bit in the lin transmit register (esci_ltr) . if the value received in the checksum bytes did not match the calculated checksum, the checksum error flag ckerr in the interrupt flag and status register 2 (esci_ifsr2) will be set. crc error detection the crc checking is performed on the two received crc bytes crc1 and crc2 if the crc enhanced lin frame format was selected by the crc bit in the lin transmit register (esci_ltr) . if the value received in the two crc bytes did not match the calculated crc pattern, the crc error flag cerr in the interrupt flag and status register 2 (esci_ifsr2) will be set. overflow detection when the receiver has received the next byte field, which should be transferred into the lin receive register (esci_lrr) , but neither the application nor the rx dma channel have read data from this register since the last update, the received data overflow flag ovfl in the interrupt flag and status register 2 (esci_ifsr2) will be set. in this case the content of the lin receive register (esci_lrr) is not changed. the data received most recently are lost. lin wake up the section describes the lin wake up behavior of the esci module. lin wake-up request generation the esci module can cause the lin bus to exit the sleep mode by sending a wake-up signal frame, which consists of a wake-up signal 0x80 (consisting of 8 dominant bits followed by 1 recessive bit), followed by the wake-up delimiter period as defined by the wud field in the lin control register 1 (esci_lcr1) . t frame_max 10 n data ? 45 + () 1.4 ? = enhanced serial communication interface (esci) RM0029 1404/1740 doc id 15177 rev 8 figure 806. lin wake-up signal frame the application triggers the transmission of a wake-up signal frame by writing 1 to the lin bus wake-up trigger wu in the lin control register 1 (esci_lcr1) . the lin specification 2.0 requires the generation of lin wake-up signals as dominant pulses longer than 250 s and shorter than 5 ms. to achieve this, the esci module has to programmed to a baud rate between 32 kbaud and 1.6 kbaud. with each of these baud rate settings, the wake-up signal is transmitted as a dominant pulse longer than 250 s and shorter than 5 ms. lin wake-up request detection the esci module detects a lin wake-up requests when e) one of the characters 0x00, 0x80, or 0xc0 has been received, f) followed by zero or more low bits, g) followed by at least one high bit, and h) no lin frame transmission or reception is started or running during the reception above if a lin wake-up request has been detected, the lin wake-up flag lwake in the interrupt flag and status register 2 (esci_ifsr2) will be set after the reception of the first high bit. the lin specification 2.0 requires the detection of lin wake-up requests as dominant pulses longer than 150 s. to achieve this, the esci module has to programmed to the maximum baud rate that is not greater than 43.77 kbaud. with this baud rate setting, any dominant pulse longer than 150 s is decoded as at least 7 dominant bits (one start and 6 data bits) and consequently as one of the characters 0xc0, 0x80, or 0x00. lin protocol engine stop and reset the lin protocol engine is stopped and reset when the application set the lres control bit in the lin control register 1 (esci_lcr1) to 1. in this case, the lin protocol engine will stop immediately. no new transmissions or receptions are initiated, the lin serial bus is driven with the recessive value 1. additionally to the stop and reset of the lin protocol engine the receiver and transmitter modules are stopped and reset as well, and the receive and transmit dma requests are deasserted. in order to start the lin protocol engine with idle transmitter and receiver processes, the lres bit should be asserted until all of the status bits dact, lact, tact, and ract in the interrupt flag and status register 1 (esci_ifsr1) are cleared. theses status bits are cleared within one bit time after assertion of the lres bit. 31.4.7 interrupts this section describes the interrupt sources and interrupt request generation. bit0 start bit bit1 bit2 bit3 bit4 bit5 bit6 bit7 break wake-up signal wake-up delimiter lin frame wake-up signal frame RM0029 enhanced serial communication interface (esci) doc id 15177 rev 8 1405/1740 interrupt flags and enables all interrupt sources, interrupt flags, and interrupt enable bits are listed in table 760 . this table indicates the operational modes, where the interrupt flags can be set by the esci module. interrupt request generation the esci module provides one hardware interrupt request signal to the systems interrupt controller. this interrupt request signal is asserted if and only if at least one of the interrupt flags and the corresponding interrupt enables are set to 1. otherwise the interrupt line is deasserted. 31.5 application information 31.5.1 sci data frames separated by preamble to separate sci data frame with preambles with minimum idle line time, use this sequence between messages: table 760. esci interrupt flags and interrupt enable bits interrupt source operational mode interrupt flag interrupt enable bit transmitter sci esci_ifsr1[tdre] esci_cr1[tie] transmitter sci, lin esci_ifsr1[tc] esci_cr1[tcie] receiver sci esci_ifsr1[rdrf] esci_cr1[rie] receiver sci esci_ifsr1[idle] esci_cr1[ilie] receiver sci esci_ifsr1[or] esci_cr2[orie] receiver sci, lin esci_ifsr1[nf] esci_cr2[nfie] receiver sci, lin esci_ifsr1[fe] esci_cr2[feie] receiver sci esci_ifsr1[pf] esci_cr2[pfie] receiver lin esci_ifsr1[berr] esci_cr2[berrie] receiver lin esci_ifsr2[rxrdy] esci_lcr1[rxie] transmitter lin esci_ifsr2[txrdy] esci_lcr1[txie] receiver lin esci_ifsr2[lwake] esci_lcr1[wuie] receiver lin esci_ifsr2[sto] esci_lcr1[stie] receiver lin esci_ifsr2[pberr] esci_lcr1[pbie] receiver lin esci_ifsr2[cerr] esci_lcr1[cie] receiver lin esci_ifsr2[ckerr] esci_lcr1[ckie] receiver lin esci_ifsr2[frc] esci_lcr1[fcie] receiver lin esci_ifsr2[ureq] esci_lcr2[urie] transmitter, receiver lin esci_ifsr2[ovfl] esci_lcr2[ofie] enhanced serial communication interface (esci) RM0029 1406/1740 doc id 15177 rev 8 1. write to sci data register (esci_dr) ? this sets the internal icmt bit which requests the data transmission 2. wait until tdre in interrupt flag and status register 1 (esci_ifsr1) is set ? this indicates the start of transmission; the icmt bit was cleared 3. clear and subsequently set the te bit in control register 1 (esci_cr1) ? this set the internal ipre bit which requests the preamble transmission 4. write to sci data register (esci_dr) ? this sets the internal icmt bit which requests the data transmission the priority scheme of the transmitter which is described in table 752 ensures, that the preamble is transmitted before the data frame. RM0029 flexcan module doc id 15177 rev 8 1407/1740 32 flexcan module 32.1 information specific to this device this section presents device-specific parameterization and customization information not specifically referenced in the remainder of this chapter. 32.1.1 device-specific features 3 flexcan modules with 64 message buffers each the device has 3 controller area network (flexcan) blocks referred as flexcan_a, flexcan_b and flexcan_c. ? each flexcan module contains an embedded memory capable of storing 64 message buffers (mb). ? although the flexcan module provides a differentiation between supervisor and user access types, all accesses will be always considered of the supervisor type. as a consequence, the supv bit in the module configuration register (mcr) register has no effect on the module behavior. ? all 4 flexcan functional modes are supported: normal, freeze, listen-only and loop-back. ? only two power modes are supported, the disable and stop mode. doze mode is not supported. ? low-pass filter (glitch filter) 32.2 introduction the flexcan module is a communication controller implementing the can protocol according to the can 2.0b protocol specification. the block diagram in figure 807 shows the main sub-blocks implemented in the flexcan module. support for up to 64 message buffers is provided. the functions of the submodules are described in subsequent sections. flexcan module RM0029 1408/1740 doc id 15177 rev 8 figure 807. flexcan block diagram f osc system configuration device peripheral bus interrupt controller cr[clksrc] cr[presdiv] divider mcr[mdis] can engine tx shifter protocol engine rx shifter wake up detection wake up mcr[slf_wak] cr[lpb] 1 0 vddehx cr[lpb | lom] message buffers (mb) mb 0 mb 8 mb n-1 control and status registers timer 16 bit free running timer reset timer synchronization cr[tsyn] mcr[fen] t q 01 bus off error tx warning rx warning wake up n n 1 1 1 1 1 1 cr[errmsk] cr[boffmsk] cr[twrnmsk] cr[rwrnmsk] mcr[wak_msk] n imrh | imrl[buffxm] message buffer interrupts notes: 1: pins can be configurable. ch eck device system configuration 2: check interrupt controller which interrupts have been used and regrouped. interrupts can be additionally enabled/disabled 3: please check device system confi guration for further clock divider, muxing and low power configuration. see the section for the n = no. of message buffers implemented flexcan a: n = 64 flexcan b: n = 64 f sys cantx canrx 1 1 2 3 flexcan c: n = 64 in the interrupt controller siu_sysdiv[can 2:1] for the additional system clock pre- divider. RM0029 flexcan module doc id 15177 rev 8 1409/1740 32.2.1 overview the can protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. the flexcan module is a full implementation of the can protocol specification, version 2.0 b, which supports both standard and extended message frames. a flexible number of message buffers (16, 32 or 64) is also supported. the message buffers are stored in an embedded ram dedicated to the flexcan module. the can protocol interface (cpi) submodule manages the serial communication on the can bus, requesting ram access for receiving and transmitting message frames, validating received messages and performing error handling. the message buffer management (mbm) submodule handles message buffer selection for reception and transmission, taking care of arbitration and id matching algorithms. the bus interface unit (biu) submodule controls the access to and from the internal interface bus, in order to establish connection to the cpu and to other blocks. clocks, address and data buses, interrupt outputs and test signals are accessed through the bus interface unit. a typical can system is shown below in figure 808 . each can station is connected physically to the can bus through a transceiver. the transceiver provides the transmit drive, waveshaping, and receive/compare functions required for communicating on the can bus. it can also provide protection against damage to the flexcan caused by a defective can bus or defective stations. figure 808. typical can system cantx canrx flexcan microcontroller tranceiver can station 1 can station 2 can station n can bus flexcan module RM0029 1410/1740 doc id 15177 rev 8 32.2.2 flexcan module features the flexcan module includes these distinctive features: full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? zero to eight bytes data length ? programmable bit rate up to 1 mbit/s ? content-related addressing flexible message buffers (up to 64) of zero to eight bytes data length each message buffer configurable as rx or tx, all supporting standard and extended messages individual rx mask registers per message buffer includes either 1056 bytes (64 message buffers), 544 bytes (32 message buffers) or 288 bytes (16 message buffers) of ram used for message buffer storage includes either 256 bytes (64 message buffers), 128 bytes (32 message buffers) or 64 bytes (16 message buffers) of ram used for individual rx mask registers full featured rx fifo with storage capacity for 6 frames and internal pointer handling powerful rx fifo id filtering, capable of matching incoming ids against either 8 extended, 16 standard or 32 partial (8 bits) ids, with individual masking capability selectable backwards compatibility with previous flexcan version programmable clock source to the can protocol interface, either bus clock or crystal oscillator unused message buffer and rx mask register space can be used as general purpose ram space listen only mode capability programmable loop-back mode supporting self-test operation programmable transmission priority scheme: lowest id, lowest buffer number or highest priority time stamp based on 16-bit free-running timer global network time, synchronized by a specific message maskable interrupts independent of the transmission medium (an external transceiver is assumed) short latency time due to an arbitration scheme for high-priority messages low power modes, with programmable wake up on bus activity RM0029 flexcan module doc id 15177 rev 8 1411/1740 32.2.3 modes of operation the flexcan module has four functional modes: normal mode (user and supervisor), freeze mode, listen-only mode and loop-back mode. there are also two low power modes: disable mode and stop mode. normal mode (user or supervisor): in normal mode, the module operates receiving and/or transmitting message frames, errors are handled normally and all the can protocol functions are enabled. user and supervisor modes differ in the access to some restricted control registers. freeze mode: it is enabled when mcr[frz] is asserted. if enabled, freeze mode is entered when mcr[halt] is set or when debug mode is requested at mcu level. in this mode, no transmission or reception of frames is done and synchronicity to the can bus is lost. see section , freeze mode for more information. listen-only mode: the module enters this mode when cr[lom] is asserted. in this mode, transmission is disabled, all error counters are frozen and the module operates in a can error passive mode. only messages acknowledged by another can station will be received. if flexcan detects a message that has not been acknowledged, it will flag a bit0 error (without changing the rec), as if it was trying to acknowledge the message. loop-back mode: the module enters this mode when cr[lpb] is asserted. in this mode, flexcan performs an internal loop back that can be used for self test operation. the bit stream output of the transmitter is internally fed back to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessive state (logic ?1?). flexcan behaves as it normally does when transmitting and treats its own transmitted message as a message received from a remote node. in this mode, flexcan ignores the bit sent during the ack slot in the can frame acknowledge field to ensure proper reception of its own message. both transmit and receive interrupts are generated. module disable mode: this low power mode is entered when the mdis bit in the mcr register is asserted by the cpu. when disabled, the module sends a request to disable the clocks to the can protocol interface and message buffer management sub-modules. exit from this mode is done by negating mcr[mdis]. see section , module disable mode , for more information. stop mode: this low power mode is entered when stop mode is requested at mcu level. when in stop mode, the module puts itself in an inactive state and then informs the cpu that the clocks can be shut down globally. exit from this mode happens when the stop mode request is removed or when activity is detected on the can bus and the self wake up mechanism is enabled. see section , stop mode , for more information. 32.3 external signal description 32.3.1 overview the flexcan module has two i/o signals connected to the external mcu pins. these signals are summarized in table 761 and described in more detail in the next subsections. flexcan module RM0029 1412/1740 doc id 15177 rev 8 32.3.2 signal descriptions can rx this pin is the receive pin from the can bus transceiver. dominant state is represented by logic level ?0?. recessive state is represented by logic level ?1?. can tx this pin is the transmit pin to the can bus transceiver. dominant state is represented by logic level ?0?. recessive state is represented by logic level ?1?. 32.4 memory map/register definition this section describes the registers and data structures in the flexcan module. the base address of the module depends on the particular memory map of the mcu. the addresses presented here are relative to the base address. the address space occupied by flexcan has 96 bytes for registers starting at the module base address, followed by message buffer storage space in embedded ram starting at address 0x0060, and an extra id mask storage space in a separate embedded ram starting at address 0x0880. 32.4.1 flexcan memory mapping the complete memory map for a flexcan module with 64 message buffers capability is shown in table 762 . each individual register is identified by its complete name and the corresponding mnemonic. the access type can be supervisor (s) or unrestricted (u). most of the registers can be configured to have either supervisor or unrestricted access by programming mcr[supv]. these registers are identified as s/u in the access column of ta ble 76 2 . the ifrh and imrh registers are considered reserved space when flexcan is configured with 16 or 32 message buffers. the rx global mask (rxgmask), rx buffer 14 mask (rx14mask) and the rx buffer 15 mask (rx15mask) registers are provided for backwards compatibility, and are not used when mcr[mbfen] is asserted. the address ranges 0x0060?0x047f and 0x0880?0x097f are occupied by two separate embedded memories. these two ranges are completely occupied by ram (1056 and 256 bytes, respectively) only when flexcan is configured with 64 message buffers. when it is configured with 16 message buffers, the memory sizes are 288 and 64 bytes, so the address ranges 0x0180?0x047f and 0x08c0?0x097f are considered reserved space. when it is configured with 32 message buffers, the memory sizes are 544 and 128 bytes, so the address ranges 0x0280?0x047f and 0x0900?0x097f are considered reserved space. table 761. flexcan signals signal name (1) 1. the actual mcu pins may have different names. direction description can_ x _rx input can receive pin can_ x _tx output can transmit pin RM0029 flexcan module doc id 15177 rev 8 1413/1740 furthermore, if mcr[mbfen] is negated, then the whole rx individual mask registers address range (0x0880?0x097f) is considered reserved space. the flexcan module stores can messages for transmission and reception using a message buffer structure. each individual message buffer is formed by 16 bytes mapped on memory as described in table 763 . table 763 shows a standard/extended message buffer (mb0) memory map, using 16 bytes total (0x80 ? 0x8f space). table 762. module memory map address use access type affected by hard reset affected by soft reset base + 0x0000 module configuration (mcr) s yes yes base + 0x0004 control register (cr) s/u yes no base + 0x0008 free running timer (timer) s/u yes yes base + 0x000c reserved base + 0x0010 rx global mask (rxgmask) s/u yes no base + 0x0014 rx buffer 14 mask (rx14mask) s/u yes no base + 0x0018 rx buffer 15 mask (rx15mask) s/u yes no base + 0x001c error counter register (ecr) s/u yes yes base + 0x0020 error and status register (esr) s/u yes yes base + 0x0024 interrupt masks 2 (imrh) s/u yes yes base + 0x0028 interrupt masks 1 (imrl) s/u yes yes base + 0x002c interrupt flags 2 (ifrh) s/u yes yes base + 0x0030 interrupt flags 1 (ifrl) s/u yes yes base + 0x0034?0x005f reserved base + 0x0060?0x007f reserved base + 0x0080?0x017f message buffers mb0 ? mb15 s/u no no base + 0x0180?0x027f message buffers mb16 ? mb31 s/u no no base + 0x0280?0x047f message buffers mb32 ? mb63 s/u no no base + 0x0480?087f reserved base + 0x0880?0x08bf rx individual mask registers rximr0?rximr15 s/u no no base + 0x08c0?0x08ff rx individual mask registers rximr16?rximr31 s/u no no base + 0x0900?0x097f rx individual mask registers rximr32?rximr63 s/u no no table 763. message buffer mb0 memory mapping address offset mb field 0x80 control and status (c/s) 0x84 identifier field 0x88 ? 0x8f data field 0 ? data field 7 (1 byte each) flexcan module RM0029 1414/1740 doc id 15177 rev 8 32.4.2 message buffer architecture the message buffer architecture is shown in figure 809 . figure 809. flexcan message buffer architecture 32.4.3 message buffer structure the message buffer structure used by the flexcan module is represented in figure 810 . both extended and standard frames (29-bit identifier and 11-bit identifier, respectively) used in the can specification (version 2.0 part b) are supported. the buffer is a 4-word (128-bit) structure summarized in figure 810 . 0 1 0 1 lowest id arbitration lowest id+prio arbitration lowest buffer number arbitration internal tx message buffer arbiter tx serial message buffer data data length id cr[lbuf] mcr[lprio_en] internal tx arbitration data data length time stamp id buffer 0 data data length time stamp id buffer 7 data data length time stamp id buffer 8 data data length time stamp id buffer 9 data data length time stamp id buffer 14 data data length time stamp id buffer 15 data data length time stamp id buffer (n-1) buffers in use are defined by mcr[maxmb] 6 stage rx fifo data data length time stamp id id table 0?7 mcr[fen] = 0 mcr[fen] = 1 same address space message buffer ram cpu memory map base: 0xc3f8_0000 ? 0x344 scan buffers move data used algorithm device peripheral bus move data scan buffers can engine cantx canrx 1 1 protocol engine rx serial message buffer data data length id no queuing queuing rx id matching rx id matching used algorithm mcr[mbfen] tx shifter rx shifter rxgmask rx14mask rx15mask rximr0 rximr7 rximr8 rximr14 rximr15 rximr(n-1) mcr[mbfen] en 2 mcr[fen] mcr[mbfen] 1 0 0 1 0 1 0 1 0 1 0 1 used for used for used for used for used for normal mode legacy mode used for buffer 8 id matching used for buffer 14 id matching used for buffer 15 id matching used for buffer n-1 id matching buffer 14 id matching buffer 15 id matching buffer 0 id matching buffer 7 id matching rx fifo id matching rx fifo id matching buffer 14 & fifo id table 6 id matching buffer 15 & fifo id table 7 id matching all buffer ex. buffer 14 & 15 id matching all buffer ex. buffer 14 & 15 & fifo id table 0?5 id matching 0 1 notes: 1: pins can be configurable. check device system configuration. 2: if disabled the rximrx registers are not memory mapped. co n ti n ued address s pa c e any access in this case will cause data access error. RM0029 flexcan module doc id 15177 rev 8 1415/1740 figure 810. message buffer structure 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0 code srr ide rtr length time stamp 0x4 prio id (standard/extended) id (extended) 0x8 data byte 0 data byte 1 data byte 2 data byte 3 0xc data byte 4 data byte 5 data byte 6 data byte 7 = unimplemented or reserved table 764. message buffer structure (word 0?0x0) field description code this 4-bit field can be accessed (read or write) by the cpu and by the flexcan module itself, as part of the message buffer matching and arbitration process. the encoding for rx buffers is shown in table 765 and the encoding for tx buffers is shown in table 766 . see section 32.5, functional description for additional information. srr substitute remote request fixed recessive bit, used only in extended format. it must be set to ?1? by the user for transmission (tx buffers) and will be stored with the value received on the can bus for rx receiving buffers. it can be received as either recessive or dominant. if flexcan receives this bit as dominant, then it is interpreted as arbitration loss. 1: recessive value is compulsory for transmission in extended format frames 0: dominant is not a valid value for transmission in extended format frames ide id extended bit this bit identifies whether the frame format is standard or extended. 1: frame format is extended 0: frame format is standard rtr remote transmission request this bit is used for requesting transmissions of a data frame. if flexcan transmits this bit as ?1? (recessive) and receives it as ?0? (dominant), it is interpreted as arbitration loss. if this bit is transmitted as ?0? (dominant), then if it is received as ?1? (recessive), the flexcan module treats it as bit error. if the value received matches the value transmitted, it is considered as a successful bit transmission. 1: indicates the current message buffer has a remote frame to be transmitted 0: indicates the current message buffer has a data frame to be transmitted length length of data in bytes this 4-bit field is the length (in bytes) of the rx or tx data, which is located in offset 0x8 through 0xf of the message buffer space (see figure 810 ). in reception, this field is written by the flexcan module, copied from the dlc (data length code) field of the received frame. in transmission, this field is written by the cpu and corresponds to the dlc field value of the frame to be transmitted. when rtr=1, the frame to be transmitted is a remote frame and does not include the data field, regardless of the length field. flexcan module RM0029 1416/1740 doc id 15177 rev 8 time stamp free-running counter time stamp this 16-bit field is a copy of the free-running timer, captured for tx and rx frames at the time when the beginning of the identifier field appears on the can bus. prio local priority this 3-bit field is only used when mcr[lprio_en] is set and it only makes sense for tx buffers. these bits are not transmitted. they are appended to the regular id to define the transmission priority. see section 32.5.3, arbitration process . id frame identifier in standard frame format, only the 11 most significant bits (3 to 13) are used for frame identification in both receive and transmit cases. the 18 least significant bits are ignored. in extended frame format, all bits are used for frame identification in both receive and transmit cases. data data field up to eight bytes can be used for a data frame. for rx frames, the data is stored as it is received from the can bus. for tx frames, the cpu prepares the data field to be transmitted within the frame. table 764. message buffer structure (word 0?0x0) field description table 765. message buffer code for rx buffers rx code before rx new frame description rx code after rx new frame comment 0000 inactive: buffer is not active. ? mb does not participate in the matching process. 0100 empty: buffer is active and empty. 0010 mb participates in the matching process. when a frame is received successfully, the code is automatically updated to full. 0010 full: buffer is full. 0010 the act of reading the c/s word followed by unlocking the mb does not make the code return to empty. it remains full. if a new frame is written to the mb after the c/s word was read and the mb was unlocked, the code still remains full. 0110 if the mb is full and a new frame is overwritten to this mb before the cpu had time to read it, the code is automatically updated to overrun. refer to section 32.5.5, matching process for details about overrun behavior. 0110 overrun: a frame was overwritten into a full buffer. 0010 if the code indicates overrun but the cpu reads the c/s word and then unlocks the mb, when a new frame is written to the mb the code returns to full. 0110 if the code already indicates overrun, and yet another new frame must be written, the mb will be overwritten again, and the code will remain overrun. refer to section 32.5.5, matching process for details about overrun behavior. RM0029 flexcan module doc id 15177 rev 8 1417/1740 32.4.4 rx fifo structure when mcr[fen] is set, the memory area from 0x80 to 0xfc (which is normally occupied by mbs 0 to 7) is used by the reception fifo engine. figure 811 shows the rx fifo data structure. the region 0x80?0x8c contains a message buffer structure which is the port through which the cpu reads data from the fifo (the oldest frame received and not read yet). the region 0x90?0xdc is reserved for internal use of the fifo engine. the region 0xe0?0xfc contains an 8-entry id table that specifies filtering criteria for accepting frames into the fifo. figure 812 shows the three different formats that the elements of the id table 0xy1 (1) busy: flexcan is updating the contents of the mb. the cpu must not access the mb. 0010 an empty buffer was written with a new frame (xy was 01). 0110 a full/overrun buffer was overwritten (xy was 11). 1. note that for tx mbs (see table 766 ), the busy bit should be ignored upon read, except when mcr[aen] is set. table 765. message buffer code for rx buffers rx code before rx new frame description rx code after rx new frame comment table 766. message buffer code for tx buffers rt r initial tx code code after successful transmissio n description x 1000 ? inactive: mb does not participate in the arbitration process. x1001 ? abort: mb was configured as tx and cpu aborted the transmission. this code is only valid when mcr[aen] is asserted. mb does not participate in the arbitration process. 0 1100 1000 transmit data frame unconditionally once. after transmission, the mb automatically returns to the inactive state. 1 1100 0100 transmit remote frame unconditionally once. after transmission, the mb automatically becomes an rx mb with the same id. 0 1010 1010 transmit a data frame whenever a remote request frame with the same id is received. this mb participates simultaneously in both the matching and arbitration processes. the matching process compares the id of the incoming remote request frame with the id of the mb. if a match occurs this mb is allowed to participate in the current arbitration process and the code field is automatically updated to ?1110? to allow the mb to participate in future arbitration runs. when the frame is eventually transmitted successfully, the code automatically returns to ?1010? to restart the process again. 0 1110 1010 this is an intermediate code that is automatically written to the mb by the mbm as a result of match to a remote request frame. the data frame will be transmitted unconditionally once and then the code will automatically return to ?1010?. the cpu can also write this code with the same effect. flexcan module RM0029 1418/1740 doc id 15177 rev 8 can assume, depending on field mcr[idam]. note that all elements of the table must have the same format. see section 32.5.7, rx fifo for more information. figure 811. rx fifo structure 0 3 7 8 9 10 11 12 13 14 15 16 23 24 31 0x80 srr ide rtr length time stamp 0x84 id (standard/extended) id (extended) 0x88 data byte 0 data byte 1 data byte 2 data byte 3 0x8c data byte 4 data byte 5 data byte 6 data byte 7 0x90 reserved to 0xdc 0xe0 id table 0 0xe4 id table 1 0xe8 id table 2 0xec id table 3 0xf0 id table 4 0xf4 id table 5 0xf8 id table 6 0xfc id table 7 = unimplemented or reserved figure 812. id table 0 ? 7 format 0 3 4 7 9 101112 1516 2324 31 a r e m e x t rxida (standard = 29?19, extended = 29?1) b r e m e x t rxidb_0 (standard = 29?19, extended = 29?16) r e m e x t rxidb_1 (standard = 13?3, extended = 13?0) c rxidc_0 (std/ext = 31?24) rxidc_1 (std/ext = 23?16) rxidc_2 (std/ext = 15?8) rxidc_3 (std/ext = 7?0) = unimplemented or reserved RM0029 flexcan module doc id 15177 rev 8 1419/1740 table 767. rx fifo structure field description rem remote frame this bit specifies if remote frames are accepted into the fifo if they match the target id. 1: remote frames can be accepted and data frames are rejected 0: remote frames are rejected and data frames can be accepted ext extended frame specifies whether extended or standard frames are accepted into the fifo if they match the target id. 1: extended frames can be accepted and standard frames are rejected 0: extended frames are rejected and standard frames can be accepted rxida rx frame identifier (format a) specifies an id to be used as acceptance criteria for the fifo. in the standard frame format, only the 11 most significant bits (3 to 13) are used for frame identification. in the extended frame format, all bits are used. rxidb_0, rxidb_1 rx frame identifier (format b) specifies an id to be used as acceptance criteria for the fifo. in the standard frame format, the 11 most significant bits (a full standard id) (3 to 13)are used for frame identification. in the extended frame format, all 14 bits of the field are compared to the 14 most significant bits of the received id. rxidc_0, rxidc_1, rxidc_2, rxidc_3 rx frame identifier (format c) specifies an id to be used as acceptance criteria for the fifo. in both standard and extended frame formats, all 8 bits of the field are compared to the 8 most significant bits of the received id. flexcan module RM0029 1420/1740 doc id 15177 rev 8 32.4.5 register descriptions the flexcan registers are described in this section in ascending address order. module configuration register (mcr) this register defines global system configurations, such as the module operation mode (e.g., low power) and maximum message buffer configuration. most of the fields in this register can be accessed at any time, except the maxmb field, which should only be changed while the module is in freeze mode. figure 813. module configuration register (mcr) base + 0x0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mdis frz fen halt notrdy wak_msk softrst frzack supv slf_wak wrnen mdisack wak_src 0 srxdis mbfen w reset: 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 lprio_en aen 0 0 idam 0 0 maxmb w reset: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 = unimplemented or reserved table 768. module configuration register (mcr) field descriptions field description mdis module disable this bit controls whether flexcan is enabled or not. when disabled, flexcan shuts down the clocks to the can protocol interface and message buffer management submodules. this is the only bit in mcr not affected by soft reset. see section , module disable mode for more information. 1: disable the flexcan module 0: enable the flexcan module frz freeze enable the frz bit specifies the flexcan behavior when mcr[halt] is set or when debug mode is requested at mcu level. when frz is asserted, flexcan is enabled to enter freeze mode. negation of this bit field causes flexcan to exit from freeze mode. 1: enabled to enter freeze mode 0: not enabled to enter freeze mode RM0029 flexcan module doc id 15177 rev 8 1421/1740 fen fifo enable this bit controls whether the fifo feature is enabled or not. when fen is set, mbs 0 to 7 cannot be used for normal reception and transmission because the corresponding memory region (0x80?0xff) is used by the fifo engine. see section 32.4.4, rx fifo structure and section 32.5.7, rx fifo for more information. 1: fifo enabled 0: fifo not enabled halt halt flexcan assertion of this bit puts the flexcan module into freeze mode. the cpu should clear it after initializing the message buffers and control register. no reception or transmission is performed by flexcan before this bit is cleared. while in freeze mode, the cpu has write access to the error counter register, that is otherwise read-only. freeze mode can not be entered while flexcan is in any of the low power modes. see section , freeze mode for more information. 1: enters freeze mode if the frz bit is asserted. 0: no freeze mode request. notrdy flexcan not ready this read-only bit indicates that flexcan is either in disable mode, stop mode or freeze mode. it is negated once flexcan has exited these modes. 1: flexcan module is either in disable mode, stop mode or freeze mode 0: flexcan module is either in normal mode, listen-only mode or loop-back mode wak_msk wake up interrupt mask this bit enables the wake up interrupt generation. 1: wake up interrupt is enabled 0: wake up interrupt is disabled table 768. module configuration register (mcr) field descriptions field description flexcan module RM0029 1422/1740 doc id 15177 rev 8 softrst soft reset when this bit is asserted, flexcan resets its internal state machines and some of the memory mapped registers. the following registers are reset: mcr (except the mdis bit), timer, ecr, esr, imrl, imrh, ifrl, ifrh. configuration registers that control the interface to the can bus are not affected by soft reset. the following registers are unaffected: ? cr ? rximr0?rximr63 ? rxgmask, rx14mask, rx15mask ? all message buffers the softrst bit can be asserted directly by the cpu when it writes to the mcr, but it is also asserted when global soft reset is requested at mcu level. since soft reset is synchronous and has to follow a request/acknowledge procedure across clock domains, it may take some time to fully propagate its effect. the softrst bit remains asserted while reset is pending, and is automatically negated when reset completes. therefore, software can poll this bit to know when the soft reset has completed. soft reset cannot be applied while clocks are shut down in any of the low power modes. the module should be first removed from low power mode, and then soft reset can be applied. 1: resets the registers marked as ?affected by soft reset? in table 762 0: no reset request frzack freeze mode acknowledge this read-only bit indicates that flexcan is in freeze mode and its prescaler is stopped. the freeze mode request cannot be granted until cu rrent transmission or reception processes have finished. therefore the software can poll the frzack bit to know when flexcan has actually entered freeze mode. if freeze mode request is negated, then this bit is negated once the flexcan prescaler is running again. if freeze mode is requested while flexcan is in any of the low power modes, then the frzack bit will only be set when the low power mode is exited. see section , freeze mode for more information. 1: flexcan in freeze mode, prescaler stopped 0: flexcan not in freeze mode, prescaler running supv supervisor mode this bit configures some of the flexcan registers to be either in supervisor or unrestricted memory space. the registers affected by this bit are marked as s/u in the access type column of table 762 . reset value of this bit is ?1?, so the affected registers start with supervisor access restrictions. 1: affected registers are in supervisor memory space. any access without supervisor permission behaves as though the access was done to an unimplemented register location 0: affected registers are in unrestricted memory space table 768. module configuration register (mcr) field descriptions field description RM0029 flexcan module doc id 15177 rev 8 1423/1740 slf_wak self wake up this bit enables the self wake up feature when flexcan is in stop mode. if this bit had been asserted by the time flexcan entered stop mode, then flexcan will look for a recessive to dominant transition on the bus during these modes. if a transition from recessive to dominant is detected during stop mode, then flexcan generates, if enabled to do so, a wake up interrupt to the cpu so that it can resume the clocks globally. this bit can not be written while the module is in stop mode. 1: flexcan self wake up feature is enabled 0: flexcan self wake up feature is disabled wrnen warning interrupt enable when asserted, this bit enables the generation of the twrnint and rwrnint flags in the error and status register. if wrnen is negated, the twrnint and rwrnint flags will always be zero, independent of the values of the error counters, and no warning interrupt will ever be generated. 1: twrnint and rwrnint bits are set when the respective error counter transition from <96 to 96. 0: twrnint and rwrnint bits are zero, independent of the values in the error counters. mdisack low power mode acknowledge this read-only bit indicates that flexcan is either in disable mode or stop mode. either of these low power modes can not be entered until all current transmission or reception processes have finished, so the cpu can poll the mdisack bit to know when flexcan has actually entered low power mode. see section , module disable mode and section , stop mode for more information. 1: flexcan is either in disable mode or stop mode 0: flexcan not in any of the low power modes wak_src wake up source this bit defines whether the integrated low-pass filter is applied to protect the rx can input from spurious wake up. see section , stop mode for more information. 1: flexcan uses the filtered rx input to detect recessive to dominant edges on the can bus 0: flexcan uses the unfiltered rx input to detect recessive to dominant edges on the can bus. srx_dis self reception disable this bit defines whether flexcan is allowed to receive frames transmitted by itself. if this bit is asserted, frames transmitted by the module will not be stored in any message buffer, regardless if the message buffer is programmed with an id that matches the transmitted frame, and no interrupt flag or interrupt signal will be generated due to the frame reception. 1: self reception disabled 0: self reception enabled table 768. module configuration register (mcr) field descriptions field description flexcan module RM0029 1424/1740 doc id 15177 rev 8 mbfen backwards compatibility configuration this bit is provided to support backwards compatibility with previous flexcan versions. when this bit is negated, the following configuration is applied: ? for mcus supporting individual rx id masking, this feature is disabled. instead of individual id masking per message buffer, flexcan uses its previous masking scheme with rxgmask, rx14mask and rx15mask. ? the reception queue feature is disabled. upon receiving a message, if the first message buffer with a matching id that is found is still occupied by a previous unread message, flexcan will not look for another matching message buffer. it will override this message buffer with the new message and set the code field to ?0110? (overrun). upon reset this bit is negated, allowing legacy software to work without modification. 1: individual rx masking and queue feature are enabled. 0: individual rx masking and queue feature are disabled. lprio_en local priority enable this bit is provided for backwards compatibility reasons. it controls whether the local priority feature is enabled or not. it is used to extend the id used during the arbitration process. with this extended id concept, the arbitration process is done based on the full 32-bit word, but the actual transmitted id still has 11-bit for standard frames and 29-bit for extended frames. 1: local priority enabled 0: local priority disabled aen abort enable this bit is supplied for backwards compatibility reasons. when asserted, it enables the tx abort feature. this feature guarantees a safe procedur e for aborting a pending transmission, so that no frame is sent in the can bus without notification. 1: abort enabled 0: abort disabled idam id acceptance mode this 2-bit field identifies the format of the elements of the rx fifo filter table, as shown in table 769 . note that all elements of the table are configured at the same time by this field (they are all the same format). see section 32.4.4, rx fifo structure . maxmb maximum number of message buffers this 6-bit field defines the maximum number of message buffers that will take part in the matching and arbitration processes. the reset value (0x0f) is equivalent to 16 message buffer configuration. this field should be changed only while the module is in freeze mode. maximum message buffers in use = maxmb + 1. maxmb must be programmed with a value smaller or equal to the number of available message buffers, otherwise flexcan can transmit and receive wrong messages. table 768. module configuration register (mcr) field descriptions field description RM0029 flexcan module doc id 15177 rev 8 1425/1740 control register (cr) this register is defined for specific flexcan control features related to the can bus, such as bit-rate, programmable sampling point within an rx bit, loop back mode, listen only mode, bus off recovery behavior and interrupt enabling (bus-off, error, warning). it also determines the division factor for the clock prescaler. most of the fields in this register should only be changed while the module is in disable mode or in freeze mode. exceptions are the boffmsk, errmsk, twrnmsk, rwrnmsk and boffrec bits, that can be accessed at any time. figure 814. control register (cr) table 769. idam coding idam format explanation 00 a one full id (standard or extended) per filter element 01 b two full standard ids or two partial 14-bit extended ids per filter element 10 c four partial 8-bit ids (standard or extended) per filter element 11 d all frames rejected base + 0x0004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r presdiv rjw pseg1 pseg2 w re- set: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r boffmsk errmsk clksrc lpb twrnmsk rwrnmsk 0 0 smp boffrec tsyn lbuf lom propseg w re- set: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved flexcan module RM0029 1426/1740 doc id 15177 rev 8 table 770. cr register field descriptions field description resdiv prescaler division factor this 8-bit field defines the ratio between the cpi clock frequency and the serial clock (sclock) frequency. the sclock period defines the time quantum of the can protocol. for the reset value, the sclock frequency is equal to the cpi clock frequency. the maximum value of this register is 0xff, that gives a minimum sclock frequency equal to the cpi clock frequency divided by 256. for more information refer to section , protocol timing . sclock frequency = cpi clock frequency / (presdiv + 1) prjw resync jump width this 2-bit field defines the maximum number of time quanta (1) that a bit time can be changed by one resynchronization. the valid programmable values are 0 ? 3. resync jump width = rjw + 1. pseg1 phase segment 1 this 3-bit field defines the length of phase buffer segment 1 in the bit time. the valid programmable values are 0 ? 7. phase buffer segment 1 = (pseg1 + 1) x time-quanta. pseg2 phase segment 2 this 3-bit field defines the length of phase buffer segment 2 in the bit time. the valid programmable values are 1 ? 7. phase buffer segment 2 = (pseg2 + 1) x time-quanta. boffmsk bus off mask this bit provides a mask for the bus off interrupt. 1: bus off interrupt enabled 0: bus off interrupt disabled errmsk error mask this bit provides a mask for the error interrupt. 1: error interrupt enabled 0: error interrupt disabled clksrc can engine clock source this bit selects the clock source to the can protocol interface (cpi) to be either the peripheral clock (driven by the pll) or the crystal oscillator clock. the selected clock is the one fed to the prescaler to generate the serial clock (sclock). in order to guarantee reliable operation, this bit should only be changed while the module is in disable mode. see section , protocol timing for more information. 1: the can engine clock source is the bus clock 0: the can engine clock source is the oscillator clock RM0029 flexcan module doc id 15177 rev 8 1427/1740 twrnmsk tx warning interrupt mask this bit provides a mask for the tx warning interrupt associated with the twrnint flag in the error and status register. this bit has no effect if mcr[wrnen] is negated and it is read as zero when mcr[wrnen] is negated. 1: tx warning interrupt enabled 0: tx warning interrupt disabled rwrnmsk rx warning interrupt mask this bit provides a mask for the rx warning interrupt associated with the rwrnint flag in the error and status register. this bit has no effect if mcr[wrnen] is negated and it is read as zero when mcr[wrnen] is negated. 1: rx warning interrupt enabled 0: rx warning interrupt disabled lpb loop back this bit configures flexcan to operate in loop-back mode. in this mode, flexcan performs an internal loop back that can be used for self test op eration. the bit stream output of the transmitter is fed back internally to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessive state (logic ?1?). flexcan behaves as it normally does when transmitting, and treats its own transmitted message as a message received from a remote node. in this mode, flexcan ignores the bit sent during the ack slot in the can frame acknowledge field, generating an internal acknowledge bit to ensure proper reception of its own message. both transmit and receive interrupts are generated. 1: loop back enabled 0: loop back disabled smp sampling mode this bit defines the sampling mode of can bits at the rx input. 1: three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used 0: just one sample is used to determine the bit value boffrec bus off recovery mode this bit defines how flexcan recovers from bus off state. if this bit is negated, automatic recovering from bus off state occurs according to the can specification 2.0b. if the bit is asserted, automatic recovering from bus off is disabled and the module remains in bus off state until the bit is negated by the user. if the negation occurs before 128 sequences of 11 recessive bits are detected on the can bus, then bus off recovery happens as if the boffrec bit had never been asserted. if the negation occurs after 128 sequences of 11 recessive bits occurred, then flexcan will resynchronize to the bus by waiting for 11 recessive bits before joining the bus. after negation, the boffrec bit can be re-asserted again during bus off, but it will only be effective the next time the module enters bus off. if boffrec was negated when the module entered bus off, asserting it during bus off will not be effective for the current bus off recovery. 1: automatic recovering from bus off state disabled 0: automatic recovering from bus off state enabled, according to can spec 2.0 part b table 770. cr register field descriptions field description flexcan module RM0029 1428/1740 doc id 15177 rev 8 free running timer (timer) this register represents a 16-bit free running counter that can be read and written by the cpu. the timer starts from 0x0000 after reset, counts linearly to 0xffff, and wraps around. the timer is clocked by the flexcan bit-clock (which defines the baud rate on the can bus). during a message transmission/reception, it increments by one for each bit that is received or transmitted. when there is no message on the bus, it counts using the previously programmed baud rate. during freeze mode, the timer is not incremented. the timer value is captured at the beginning of the identifier field of any frame on the can bus. this captured value is written into the time stamp entry in a message buffer after a successful reception or transmission of a message. tsyn timer sync mode this bit enables a mechanism that resets the free-running timer each time a message is received in message buffer 0. this feature provides means to synchronize multiple flexcan stations with a special ?sync? message (i.e., global network time). if the fen bit in mcr is set (fifo enabled), mb8 is used for timer synchronization instead of mb0. 1: timer sync feature enabled 0: timer sync feature disabled lbuf lowest buffer transmitted first this bit defines the ordering mechanism for message buffer transmission. when asserted, mcr[lprio_en] does not affect the priority arbitration. 1: lowest number buffer is transmitted first 0: buffer with highest priority is transmitted first lom listen-only mode this bit configures flexcan to operate in listen only mode. in this mode, transmission is disabled, all error counters are frozen and the module operates in a can error passive mode. only messages acknowledged by another can station will be received. if flexcan detects a message that has not been acknowledged, it will flag a bit0 error (without changing the rec), as if it was trying to acknowledge the message. 1: flexcan module operates in listen only mode 0: listen only mode is deactivated propseg propagation segment this 3-bit field defines the length of the propagation segment in the bit time. the valid programmable values are 0 ? 7. propagation segment time = (propseg + 1) * time-quanta. time-quantum = one sclock period. 1. one time quantum is equal to the sclock period. table 770. cr register field descriptions field description RM0029 flexcan module doc id 15177 rev 8 1429/1740 writing to the timer is an indirect operation. the data is first written to an auxiliary register and then an internal request/acknowledge procedure across clock domains is executed. all this is transparent to the user, except for the fact that the data will take some time to be actually written to the register. if desired, software can poll the register to discover when the data was actually written. figure 815. free running timer (timer) rx global mask (rxgmask) this register is provided for legacy support and for mcus that do not have the individual masking per message buffer feature. for mcus supporting individual masks per message buffer, setting mcr[mbfen] causes the rxgmask register to have no effect on the module operation. for mcus not supporting individual masks per message buffer, this register is always effective. rxgmask is used as acceptance mask for all rx message buffers, excluding message buffers 14 ? 15, which have individual mask registers. when mcr[fen] is set (fifo enabled), the rxgmask also applies to all elements of the id filter table, except elements 6?7, which have individual masks. the contents of this register must be programmed while the module is in freeze mode, and must not be modified when the module is transmitting or receiving frames. figure 816. rx global mask register (rxgmask) base + 0x0008 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r timer w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved base + 0x0010 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mi31 mi30 mi29 mi28 mi27 mi26 mi25 mi24 mi23 mi22 mi21 mi20 mi19 mi18 mi17 mi16 w reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mi15 mi14 mi13 mi12 mi11 mi10 mi9 mi8 mi7 mi6 mi5 mi4 mi3 mi2 mi1 mi0 w reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 = unimplemented or reserved flexcan module RM0029 1430/1740 doc id 15177 rev 8 rx 14 mask (rx14mask) this register is provided for legacy support and for low cost mcus that do not have the individual masking per message buffer feature. for mcus supporting individual masks per message buffer, setting mcr[mbfen] causes the rx14mask register to have no effect on the module operation. rx14mask is used as acceptance mask for the identifier in message buffer 14. when mcr[fen] is set (fifo enabled), the rxg14mask also applies to element 6 of the id filter table. this register has the same structure as the rx global mask register. it must be programmed while the module is in freeze mode, and must not be modified when the module is transmitting or receiving frames. address offset: 0x14 reset value: 0xffff_ffff rx 15 mask (rx15mask) this register is provided for legacy support and for low cost mcus that do not have the individual masking per message buffer feature. for mcus supporting individual masks per message buffer, setting mcr[mbfen] causes the rx15mask register to have no effect on the module operation. when mcr[mbfen] is negated, rx15mask is used as acceptance mask for the identifier in message buffer 15. when mcr[fen] is set (fifo enabled), the rxg14mask also applies to element 7 of the id filter table. this register has the same structure as the rx global mask register. it must be programmed while the module is in freeze mode, and must not be modified when the module is transmitting or receiving frames. address offset: 0x18 reset value: 0xffff_ffff error counter register (ecr) this register has two 8-bit fields reflecting the value of two flexcan error counters: transmit error counter (txecnt) and receive error counter (rxecnt). the rules for increasing and decreasing these counters are described in the can protocol and are completely implemented in the flexcan module. both counters are read only except in freeze mode, where they can be written by the cpu. writing to the error counter register while in freeze mode is an indirect operation. the data is first written to an auxiliary register and then an internal request/acknowledge procedure across clock domains is executed. all this is transparent to the user, except for the fact that the data will take some time to be actually written to the register. if desired, software can poll the register to discover when the data was actually written. table 771. rxgmask register field descriptions field description mi31?mi0 mask bits for normal rx message buffers, the mask bits affect the id filter programmed on the message buffer. for the rx fifo, the mask bits affect all bits programmed in the filter table (id, ide, rtr). 1: the corresponding bit in the filter is checked against the one received 0: the corresponding bit in the filter is ?don?t care? RM0029 flexcan module doc id 15177 rev 8 1431/1740 flexcan responds to any bus state as described in the protocol, e.g. transmit ?error active? or ?error passive? flag, delay its transmission start time (?error passive?) and avoid any influence on the bus when in ?bus off? state. the following are the basic rules for flexcan bus state transitions. if the value of txecnt or rxecnt increases to be greater than or equal to 128, esr[fltconf] is updated to reflect ?error passive? state. if the flexcan state is ?error passive?, and either txecnt or rxecnt decrements to a value less than or equal to 127 while the other already satisfies this condition, esr[fltconf] is updated to reflect ?error active? state. if the value of txecnt increases to be greater than 255, esr[fltconf] is updated to reflect ?bus off? state, and an interrupt may be issued. the value of txecnt is then reset to zero. if flexcan is in ?bus off? state, then txecnt is cascaded together with another internal counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. hence, txecnt is reset to zero and counts in a manner where the internal counter counts 11 such bits and then wraps around while incrementing the txecnt. when txecnt reaches the value of 128, esr[fltconf] is updated to be ?error active? and both error counters are reset to zero. at any instance of dominant bit following a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zero without affecting the txecnt value. if during system start-up, only one node is operating, then its txecnt increases in each message it is trying to transmit, as a result of acknowledge errors (indicated by esr[ackerr]). after the transition to ?error passive? state, the txecnt does not increment anymore by acknowledge errors. therefore the device never goes to the ?bus off? state. if the rxecnt increases to a value greater than 127, it is not incremented further, even if more errors are detected while being a receiver. at the next successful message reception, the counter is set to a value between 119 and 127 to resume to ?error active? state. figure 817. error counter register (ecr) error and status register (esr) this register reflects various error conditions, some general status of the device and it is the source of four interrupts to the cpu. the reported error conditions (bits 16?21) are those base + 0x001c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rxecnt txecnt w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved flexcan module RM0029 1432/1740 doc id 15177 rev 8 that occurred since the last time the cpu read this register. the cpu read action clears bits16?21. bits 22?28 are status bits. most bits in this register are read only, except twrnint, rwrnint, boffint, wakint and errint, that are interrupt flags that can be cleared by writing ?1? to them (writing ?0? has no effect). see section 32.5.10, interrupts for more details. figure 818. error and status register (esr) base + 0x0020 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 twrnint rwrnint w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bit1err bit0err ackerr crcerr frmerr stferr txwrn rxwrn idle txrx fltconf 0 boffint errint wakint w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 772. esr register field descriptions field description twrnint tx warning interrupt flag if the wrnen bit in mcr is asserted, the twrnint bit is set when the txwrn flag transition from ?0? to ?1?, meaning that the tx error counter reached 96. if the corresponding mask bit (cr[twrnmsk]) is set, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 1: the tx error counter transition from < 96 to 96 0: no such occurrence rwrnint rx warning interrupt flag if the wrnen bit in mcr is asserted, the rwrnint bit is set when the rxwrn flag transition from ?0? to ?1?, meaning that the rx error counters reached 96. if the corresponding mask bit (cr[rwrnmsk]) is set, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 1: the rx error counter transition from < 96 to 96 0: no such occurrence RM0029 flexcan module doc id 15177 rev 8 1433/1740 bit1err bit1 error this bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 1: at least one bit sent as recessive is received as dominant 0: no such occurrence this bit is not set by a transmitter in case of arbitr ation field or ack slot, or in case of a node sending a passive error flag that detects dominant bits. bit0err bit0 error this bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 1: at least one bit sent as dominant is received as recessive 0: no such occurrence ackerr acknowledge error this bit indicates that an acknowledge error has been detected by the transmitter node, i.e., a dominant bit has not been detected during the ack slot. 1: an ack error occurred since last read of this register 0: no such occurrence crcerr cyclic redundancy check error this bit indicates that a crc error has been detected by the receiver node, i.e., the calculated crc is different from the received. 1: a crc error occurred since last read of this register. 0: no such occurrence frmerr form error this bit indicates that a form error has been detected by the receiver node, i.e., a fixed-form bit field contains at least one illegal bit. 1: a form error occurred since last read of this register 0: no such occurrence stferr stuffing error this bit indicates that a stuffing error has been detected. 1: a stuffing error occurred since last read of this register. 0: no such occurrence. txwrn tx error warning this bit indicates when repetitive errors are occurring during message transmission. 1: tx_err_counter 96 0: no such occurrence table 772. esr register field descriptions field description flexcan module RM0029 1434/1740 doc id 15177 rev 8 rxwrn rx warning this bit indicates when repetitive errors are occurring during message reception. 1: rx_err_counter 96 0: no such occurrence idle can bus idle state this bit indicates when can bus is in idle state. 1: can bus is now idle 0: no such occurrence txrx current flexcan status (transmitting/receiving) this bit indicates if flexcan is transmitting or receiving a message when the can bus is not in idle state. this bit has no meaning when idle is asserted. 1: flexcan is transmitting a message (idle=0) 0: flexcan is receiving a message (idle=0) fltconf fault confinement state this 2-bit field indicates the confinement state of the flexcan module. 00: error active 01: error passive 1x: bus off if the lom bit in the control register is asserted, the fltconf field will indicate ?error passive?. since the control register is not affected by soft reset, the fltconf field will not be affected by soft reset if the lom bit is asserted. boffint bus off? interrupt this bit is set when flexcan enters ?bus off? state. if the corresponding mask bit (cr[boffmsk]) is set, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 1: flexcan module entered ?bus off? state 0: no such occurrence table 772. esr register field descriptions field description RM0029 flexcan module doc id 15177 rev 8 1435/1740 interrupt masks 2 register (imrh) this register allows any number of a range of 32 message buffer interrupts to be enabled or disabled. it contains one interrupt mask bit per buffer, enabling the cpu to determine which buffer generates an interrupt after a successful transmission or reception (i.e. when the corresponding bit in the ifrh register is set). figure 819. interrupt masks 2 register (imrh) errint error interrupt this bit indicates that at least one of the error bits (bits 16?21) is set. if the corresponding mask bit (cr[errmsk]) is set, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?.writing ?0? has no effect. 1: indicates setting of any error bit in the error and status register 0: no such occurrence wakint wake-up interrupt when flexcan is in stop mode and a recessive to dominant transition is detected on the can bus and if mcr[wak_msk] is set, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 1: indicates a recessive to dominant transition received on the can bus when the flexcan module is in stop mode 0: no such occurrence table 772. esr register field descriptions field description base + 0x0024 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r buf 63m buf 62m buf 61m buf 60m buf 59m buf 58m buf 57m buf 56m buf 55m buf 54m buf 53m buf 52m buf 51m buf 50m buf 49m buf 48m w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 47m buf 46m buf 45m buf 44m buf 43m buf 42m buf 41m buf 40m buf 39m buf 38m buf 37m buf 36m buf 35m buf 34m buf 33m buf 32m w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 flexcan module RM0029 1436/1740 doc id 15177 rev 8 interrupt masks 1 register (imrl) this register allows to enable or disable any number of a range of 32 message buffer interrupts. it contains one interrupt mask bit per buffer, enabling the cpu to determine which buffer generates an interrupt after a successful transmission or reception (i.e., when the corresponding bit in the ifrl register is set). figure 820. interrupt masks 1 register (imrl) interrupt flags 2 register (ifrh) this register defines the flags for 32 message buffer interrupts. it contains one interrupt flag bit per buffer. each successful transmission or reception sets the corresponding bit in ifrh. table 773. imrh register field descriptions field description buf63m? buf32m buffer mb i mask each bit enables or disables the respective flexcan message buffer (mb32 to mb63) interrupt. 1: the corresponding buffer interrupt is enabled 0: the corresponding buffer interrupt is disabled setting or clearing a bit in the imrh register can assert or negate an interrupt request, if the corresponding bit in the ifrh register is set. base + 0x0028 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r buf 31m buf 30m buf 29m buf 28m buf 27m buf 26m buf 25m buf 24m buf 23m buf 22m buf 21m buf 20m buf 19m buf 18m buf 17m buf 16m w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 15m buf 14m buf 13m buf 12m buf 11m buf 10m buf 9m buf 8m buf 7m buf 6m buf 5m buf 4m buf 3m buf 2m buf 1m buf 0m w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 774. imrl register field descriptions field description buf31m? buf0m buffer mb i mask each bit enables or disables the respective flexcan message buffer (mb0 to mb31) interrupt. 1: the corresponding buffer interrupt is enabled 0: the corresponding buffer interrupt is disabled setting or clearing a bit in the imrl register c an assert or negate an interrupt request, if the corresponding bit in the ifrl register is set. RM0029 flexcan module doc id 15177 rev 8 1437/1740 if the corresponding bit in imrh is set, an interrupt will be generated. the interrupt flag must be cleared by writing it to ?1?. writing ?0? has no effect. when mcr[aen] is set (abort enabled), while the ifrh bit is set for a message buffer configured as tx, the writing access done by cpu into the corresponding message buffer will be blocked. figure 821. interrupt flags 2 register (ifrh) interrupt flags 1 register (ifrl) this register defines the flags for 32 message buffer interrupts and fifo interrupts. it contains one interrupt flag bit per buffer. each successful transmission or reception sets the corresponding bit in the ifrl register. if the corresponding bit in the imrl register is set, an interrupt will be generated. the interrupt flag must be cleared by writing it to ?1?. writing ?0? has no effect. when mcr[aen] is set (abort enabled), while the bit in the ifrl is set for a message buffer configured as tx, the writing access done by cpu into the corresponding message buffer will be blocked. when mcr[fen] is set (fifo enabled), the function of the 8 least significant interrupt flags (buf7i? buf0i) is changed to support the fifo operation. buf7i, buf6i and buf5i indicate operating conditions of the fifo, while buf4i to buf0i are not used. base + 0x002c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r buf 63i buf 62i buf 61i buf 60i buf 59i buf 58i buf 57i buf 56i buf 55i buf 54i buf 53i buf 52i buf 51i buf 50i buf 49i buf 48i w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 47i buf 46i buf 45i buf 44i buf 43i buf 42i buf 41i buf 40i buf 39i buf 38i buf 37i buf 36i buf 35i buf 34i buf 33i buf 32i w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 775. ifrh register field descriptions field description buf32i? buf63i buffer mb i interrupt each bit flags the respective flexcan message buffer (mb32 to mb63) interrupt. 1: the corresponding buffer has successfully completed transmission or reception 0: no such occurrence flexcan module RM0029 1438/1740 doc id 15177 rev 8 figure 822. interrupt flags 1 register (ifrl) base + 0x0030 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r buf 31i buf 30i buf 29i buf 28i buf 27i buf 26i buf 25i buf 24i buf 23i buf 22i buf 21i buf 20i buf 19i buf 18i buf 17i buf 16i w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 15i buf 14i buf 13i buf 12i buf 11i buf 10i buf 9i buf 8i buf 7i buf 6i buf 5i buf 4i buf 3i buf 2i buf 1i buf 0i w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 776. ifrl register field descriptions field description buf31i? buf8i buffer mb i interrupt each bit flags the respective flexcan message buffer (mb8 to mb31) interrupt. 1: the corresponding message buffer has successfully completed transmission or reception 0: no such occurrence buf7i buffer mb7 interrupt or ?fifo overflow? if the fifo is not enabled, this bit flags the interrupt for mb7. if the fifo is enabled, this flag indicates an overflow condition in the fifo (frame lost because fifo is full). 1: mb7 completed transmission/ reception or fifo overflow 0: no such occurrence buf6i buffer mb6 interrupt or ?fifo warning? if the fifo is not enabled, this bit flags the interrupt for mb6. if the fifo is enabled, this flag indicates that 5 out of 6 buffers of the fifo are already occupied (fifo almost full). 1: mb6 completed transmission/reception or fifo almost full 0: no such occurrence buf5i buffer mb5 interrupt or ?frames available in fifo? if the fifo is not enabled, this bit flags the interrupt for mb5. if the fifo is enabled, this flag indicates that at least one frame is available to be read from the fifo. 1: mb5 completed transmission/recepti on or frames available in the fifo 0: no such occurrence buf4i? buf0i buffer mb i interrupt or ?reserved? if the fifo is not enabled, these bits flag the interrupts for mb0 to mb4. if the fifo is enabled, these flags are not used and must be considered as reserved locations. 1: corresponding message buffer completed transmission/reception 0: no such occurrence RM0029 flexcan module doc id 15177 rev 8 1439/1740 rx individual mask registers (rximr0 ? rximr63) these registers are used as acceptance masks for id filtering in rx message buffers and the fifo. if the fifo is not enabled, one mask register is provided for each available message buffer, providing id masking capability on a per message buffer basis. when the fifo is enabled (mcr[fen] is set), the first eight mask registers apply to the eight elements of the fifo filter table (on a one-to-one correspondence), while the rest of the registers apply to the regular message buffers, starting from mb8. the individual rx mask registers are implemented in ram, so they are not affected by reset and must be explicitly initialized prior to any reception. furthermore, they can only be accessed by the cpu while the module is in freeze mode. out of freeze mode, write accesses are blocked and read accesses will return ?all zeros?. furthermore, if mcr[mbfen] is negated, any read or write operation to these registers results in access error. figure 823. rx individual mask registers (rximr0 ? rximr63) 32.5 functional description 32.5.1 overview the flexcan module is a can protocol engine with a very flexible mailbox system for transmitting and receiving can frames. the mailbox system is composed by a set of up to 64 message buffers (mb) that store configuration and control data, time stamp, message id and data (see section 32.4.3, message buffer structure ). the memory corresponding to the first eight message buffers can be configured to support a fifo reception scheme with a powerful id filtering mechanism, capable of checking incoming frames against a table of ids (up to eight extended ids or sixteen standard ids or thirty-two 8-bit id slices), each one with its own individual mask register. simultaneous reception through fifo and mailbox is supported. for mailbox reception, a matching algorithm makes it possible to store received base + 0x0880?0x097f 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mi31 mi30 mi29 mi28 mi27 mi26 mi25 mi24 mi23 mi22 mi21 mi20 mi19 mi18 mi17 mi16 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mi15 mi14 mi13 mi12 mi11 mi10 mi9 mi8 mi7 mi6 mi5 mi4 mi3 mi2 mi1 mi0 table 777. rximr0 ? rximr63 register field descriptions field description mi31?mi0 mask bits for normal rx message buffers, the mask bits affect the id filter programmed on the message buffer. for the rx fifo, the mask bits affect all bits programmed in the filter table (id, ide, rtr). 1: the corresponding bit in the filter is checked against the one received 0: the corresponding bit in the filter is ?don?t care? flexcan module RM0029 1440/1740 doc id 15177 rev 8 frames only into message buffers that have the same id programmed on its id field. a masking scheme makes it possible to match the id programmed on the message buffer with a range of ids on received can frames. for transmission, an arbitration algorithm decides the prioritization of message buffers to be transmitted based on the message id (optionally augmented by three local priority bits) or the message buffer ordering. before proceeding with the functional description, an important concept must be explained. a message buffer is said to be ?active? at a given time if it can participate in the matching and arbitration algorithms that are happening at that time. an rx message buffer with a ?0000? code is inactive (refer to table 765 ). similarly, a tx message buffer with a ?1000? or ?1001? code is also inactive (refer to table 766 ). a message buffer not programmed with ?0000?, ?1000? or ?1001? will be temporarily deactivated (will not participate in the current arbitration or matching run) when the cpu writes to the c/s field of that message buffer (see section , message buffer deactivation ). 32.5.2 transmit process in order to transmit a can frame, the cpu must prepare a message buffer for transmission by executing the following procedure: if the message buffer is active (transmission pending), write ?1000? to the code field to inactivate the message buffer.the deactivated message buffer can transmit without setting iflag and without updating the code field (see section , message buffer deactivation ). write the id word. write the data bytes. write the length, control and code fields of the control and status word to activate the message buffer. once the message buffer is activated in the fourth step, it will participate into the arbitration process and eventually be transmitted according to its priority. at the end of the successful transmission, the value of the free running timer is written into the time stamp field, the code field in the control and status word is updated, a status flag is set in the interrupt flag register and an interrupt is generated if allowed by the corresponding interrupt mask register bit. the new code field after transmission depends on the code that was used to activate the message buffer in step four (see table 765 and table 766 in section 32.4.3, message buffer structure ). when the abort feature is enabled (mcr[aen] is asserted), after the interrupt flag is asserted for a message buffer configured as transmit buffer, the message buffer is blocked, therefore the cpu is not able to update it until the interrupt flag be negated by cpu. it means that the cpu must clear the corresponding ifrl or ifrh register before starting to prepare this message buffer for a new transmission or reception. 32.5.3 arbitration process the arbitration process is an algorithm executed by the mbm that scans the whole message buffer memory looking for the highest priority message to be transmitted. all message buffers programmed as transmit buffers will be scanned to find the lowest id (bg) or the bg. actually, if cr[lbuf] is negated, the arbitration consi ders not only the id, but also the rtr and ide bits placed inside the id at the same positions they are transmitted in the can frame. RM0029 flexcan module doc id 15177 rev 8 1441/1740 lowest mb number or the highest priority, depending on bits cr[lbuf] and mcr[lprio_en]. the arbitration process is triggered in the following events: during the crc field of the can frame during the error delimiter field of the can frame during intermission, if the winner message buffer defined in a previous arbitration was deactivated, or if there was no message buffer to transmit, but the cpu wrote to the c/s word of any message buffer after the previous arbitration finished when mbm is in idle or bus off state and the cpu writes to the c/s word of any message buffer upon leaving freeze mode when cr[lbuf] is asserted, mcr[lprio_en] has no effect and the lowest number buffer is transmitted first. when cr[lbuf] and mcr[lprio_en] are both negated, the message buffer with the lowest id is transmitted first but if cr[lbuf] is negated and mcr[lprio_en] is asserted, the prio bits augment the id used during the arbitration process. with this extended id concept, arbitration is done based on the full 32-bit id and the prio bits define which message buffer should be transmitted first, therefore message buffers with prio = 000 have higher priority. if two or more message buffers have the same priority, the regular id will determine the priority of transmission. if two or more message buffers have the same priority (three extra bits) and the same regular id, the lowest message buffer will be transmitted first. once the highest priority message buffer is selected, it is transferred to a temporary storage space called serial message buffer (smb), which has the same structure as a normal message buffer but is not user accessible. this operation is called ?move-out? and after it is done, write access to the corresponding message buffer is blocked (if mcr[aen] is asserted). the write access is released in the following events: after the message buffer is transmitted flexcan enters in halt or bus off flexcan loses the bus arbitration or there is an error during the transmission at the first opportunity window on the can bus, the message on the smb is transmitted according to the can protocol rules. flexcan transmits up to eight data bytes, even if the dlc (data length code) value is bigger. 32.5.4 receive process to be able to receive can frames into the mailbox message buffers, the cpu must prepare one or more message buffers for reception by executing the following steps: 1. if the message buffer has a pending transmission, write an abort code (?1001?) to the code field of the control and status word to request an abortion of the transmission, then read back the code field and the ifrl or ifrh register to check if the transmission was aborted (see section , transmission abort mechanism ). if backwards compatibility is desired (aen in mcr negated), just write ?1000? to the code field to inactivate the message buffer, but then the pending frame may be transmitted without notification (see section , message buffer deactivation ). if the message buffer already programmed as a receiver, just write ?0000? to the code field of the control and status word to keep the message buffer inactive. 2. write the id word 3. write ?0100? to the code field of the control and status word to activate the message buffer flexcan module RM0029 1442/1740 doc id 15177 rev 8 once the message buffer is activated in the third step, it will be able to receive frames that match the programmed id. at the end of a successful reception, the message buffer is updated by the mbm as follows: 1. the value of the free running timer is written into the time stamp field 2. the received id, data (8 bytes at most) and length fields are stored 3. the code field in the control and status word is updated (see table 765 and table 766 in section 32.4.3, message buffer structure ) 4. a status flag is set in the interrupt flag register and an interrupt is generated if allowed by the corresponding interrupt mask register bit upon receiving the mb interrupt, the cpu should service the received frame using the following procedure: 1. read the control and status word (mandatory ? activates an internal lock for this buffer) 2. read the id field (optional ? needed only if a mask was used) 3. read the data field 4. read the free running timer (optional ? releases the internal lock) upon reading the control and status word, if the busy bit is set in the code field, then the cpu should defer the access to the message buffer until this bit is negated. reading the free running timer is not mandatory. if not executed the message buffer remains locked, unless the cpu reads the c/s word of another message buffer. note that only a single message buffer is locked at a time. the only mandatory cpu read operation is the one on the control and status word to assure data coherency (see section 32.5.6, data coherence ). the cpu should synchronize to frame reception by the status flag bit for the specific message buffer in the corresponding ifrl or ifrh register and not by the code field of that message buffer. polling the code field does not work because once a frame was received and the cpu services the message buffer (by reading the c/s word followed by unlocking the message buffer), the code field will not return to empty. it will remain full, as explained in table 765 . if the cpu tries to workaround this behavior by writing to the c/s word to force an empty code after reading the message buffer, the message buffer is actually deactivated from any currently ongoing matching process. as a result, a newly received frame matching the id of that message buffer may be lost. in summary: never do polling by reading directly the c/s word of the message buffers. instead, read the corresponding ifrl or ifrh register . note that the received id field is always stored in the matching message buffer, thus the contents of the id field in a message buffer may change if the match was due to masking. note also that flexcan does receive frames transmitted by itself if there exists an rx matching message buffer, provided mcr[srx_dis] is not asserted. if mcr[srx_dis] is asserted, flexcan will not store frames transmitted by itself in any message buffer, even if it contains a matching message buffer, and no interrupt flag or interrupt signal will be generated due to the frame reception. to be able to receive can frames through the fifo, the cpu must enable and configure the fifo during freeze mode (see section 32.5.7, rx fifo ). upon receiving the frames available interrupt from fifo, the cpu should service the received frame using the following procedure: RM0029 flexcan module doc id 15177 rev 8 1443/1740 1. read the control and status word (optional ? needed only if a mask was used for ide and rtr bits) 2. read the id field (optional ? needed only if a mask was used) 3. read the data field 4. clear the frames available interrupt (mandatory ? release the buffer and allow the cpu to read the next fifo entry) 32.5.5 matching process the matching process is an algorithm executed by the mbm that scans the message buffer memory looking for rx message buffers programmed with the same id as the one received from the can bus. if the fifo is enabled, the 8-entry id table from fifo is scanned first and then, if a match is not found within the fifo table, the other message buffers are scanned. in the event that the fifo is full, the matching algorithm will always look for a matching message buffer outside the fifo region. when the frame is received, it is temporarily stored in a hidden auxiliary message buffer called serial message buffer (smb). the matching process takes place during the crc field of the received frame. if a matching id is found in the fifo table or in one of the regular message buffers, the contents of the smb will be transferred to the fifo or to the matched message buffer during the 6th bit of the end-of-frame field of the can protocol. this operation is called ?move-in?. if any protocol error (crc, ack, etc.) is detected, than the move-in operation does not happen. for the regular mailbox message buffers, a message buffer is said to be ?free to receive? a new frame if the following conditions are satisfied: the message buffer is not locked (see section , message buffer lock mechanism ) the code field is either empty or else it is full or overrun but the cpu has already serviced the message buffer (read the c/s word and then unlocked the message buffer) if the first message buffer with a matching id is not ?free to receive? the new frame, then the matching algorithm keeps looking for another free message buffer until it finds one. if it can not find one that is free, then it will overwrite the last matching message buffer (unless it is locked) and set the code field to overrun (refer to ta ble 76 5 and ta ble 76 6 ). if the last matching message buffer is locked, then the new message remains in the smb, waiting for the message buffer to be unlocked (see section , message buffer lock mechanism ). suppose, for example, that the fifo is disabled and there are two message buffers with the same id, and flexcan starts receiving messages with that id. let us say that these message buffers are the second and the fifth in the array. when the first message arrives, the matching algorithm will find the first match in mb number 2. the code of this message buffer is empty, so the message is stored there. when the second message arrives, the matching algorithm will find mb number 2 again, but it is not ?free to receive?, so it will keep looking and find mb number 5 and store the message there. if yet another message with the same id arrives, the matching algorithm finds out that there are no matching message buffers that are ?free to receive?, so it decides to overwrite the last matched message buffer, which is number 5. in doing so, it sets the code field of the message buffer to indicate overrun. the ability to match the same id in more than one message buffer can be exploited to implement a reception queue (in addition to the full featured fifo) to allow more time for the cpu to service the message buffers. by programming more than one message buffer with the same id, received messages will be queued into the message buffers. the cpu can flexcan module RM0029 1444/1740 doc id 15177 rev 8 examine the time stamp field of the message buffers to determine the order in which the messages arrived. the matching algorithm described above can be changed to be the same one used in previous versions of the flexcan module. when the mbfen bit in mcr is negated, the matching algorithm stops at the first message buffer with a matching id that it founds, whether this message buffer is free or not. as a result, the message queueing feature does not work if the mbfen bit is negated. matching to a range of ids is possible by using id acceptance masks. flexcan supports individual masking per message buffer. please refer to section , rx individual mask registers (rximr0?rximr63) . during the matching algorithm, if a mask bit is asserted, then the corresponding id bit is compared. if the mask bit is negated, the corresponding id bit is ?don?t care?. please note that the individual mask registers are implemented in ram, so they are not initialized out of reset. also, they can only be programmed if the mbfen bit is asserted and while the module is in freeze mode. flexcan also supports an alternate masking scheme with only three mask registers (rgxmask, rx14mask and rx15mask) for backwards compatibility. this alternate masking scheme is enabled when mcr[mbfen] is negated. 32.5.6 data coherence in order to maintain data coherency and flexcan proper operation, the cpu must obey the rules described in section 32.5.2, transmit process and section 32.5.4, receive process . any form of cpu accessing a message buffer structure within flexcan other than those specified may cause flexcan to behave in an unpredictable way. transmission abort mechanism the abort mechanism provides a safe way to request the abortion of a pending transmission. a feedback mechanism is provided to inform the cpu if the transmission was aborted or if the frame could not be aborted and was transmitted instead. in order to maintain backwards compatibility, the abort mechanism must be explicitly enabled by asserting mcr[aen]. in order to abort a transmission, the cpu must write a specific abort code (1001) to the code field of the control and status word. when the abort mechanism is enabled, the active message buffers configured as transmission must be aborted first and then they may be updated. if the abort code is written to a message buffer that is currently being transmitted, or to a message buffer that was already loaded into the smb for transmission, the write operation is blocked and the message buffer is not deactivated, but the abort request is captured and kept pending until one of the following conditions are satisfied: the module loses the bus arbitration there is an error during the transmission the module is put into freeze mode if none of conditions above are reached, the message buffer is transmitted correctly, the interrupt flag is set in the corresponding ifrl or ifrh register and an interrupt to the cpu is generated (if enabled). the abort request is automatically cleared when the interrupt flag is set. in the other hand, if one of the above conditions is reached, the frame is not transmitted, therefore the abort code is written into the code field, the interrupt flag is set in the corresponding ifrl or ifrh register and an interrupt is (optionally) generated to the cpu. RM0029 flexcan module doc id 15177 rev 8 1445/1740 if the cpu writes the abort code before the transmission begins internally, then the write operation is not blocked, therefore the message buffer is updated and no interrupt flag is set. in this way the cpu just needs to read the abort code to make sure the active message buffer was deactivated. although the aen bit is asserted and the cpu wrote the abort code, in this case the message buffer is deactivated and not aborted, because the transmission did not start yet. one message buffer is only aborted when the abort request is captured and kept pending until one of the previous conditions are satisfied. the abort procedure can be summarized as follows: cpu writes 1001 into the code field of the c/s word cpu reads the code field and compares it to the value that was written if the code field that was read is different from the value that was written, the cpu must read the corresponding ifrl or ifrh register to check if the frame was transmitted or it is being currently transmitted. if the corresponding ifrl or ifrh is set, the frame was transmitted. if the corresponding ifrl or ifrh is reset, the cpu must wait for it to be set, and then the cpu must read the code field to check if the message buffer was aborted (code = 1001) or it was transmitted (code = 1000). note: an abort request to a txmb can block any write operation into its code field. as a consequence, the txmb cannot be aborted or deactivated anymore until it completes the transmission by winning the can bus arbitration. message buffer deactivation deactivation is mechanism provided to maintain data coherence when the cpu writes to the control and status word of active message buffers out of freeze mode. any cpu write access to the control and status word of a message buffer causes that message buffer to be excluded from the transmit or receive processes during the current matching or arbitration round. the deactivation is temporary, affecting only for the current match/arbitration round. the purpose of deactivation is data coherency. the match/arbitration process scans the message buffers to decide which message buffer to transmit or receive. if the cpu updates the message buffer in the middle of a match or arbitration process, the data of that message buffer may no longer be coherent, therefore deactivation of that message buffer is done. even with the coherence mechanism described above, writing to the control and status word of active message buffers when not in freeze mode may produce undesirable results. examples are: matching and arbitration are one-pass processes. if message buffers are deactivated after they are scanned, no re-evaluation is done to determine a new match/winner. if an rx message buffer with a matching id is deactivated during the matching process after it was scanned, then this message buffer is marked as invalid to receive the frame, and flexcan will keep looking for another matching message buffer within the ones it has not scanned yet. if it can not find one, then the message will be lost. suppose, for example, that two message buffers have a matching id to a received frame, and the user deactivated the first matching message buffer after flexcan has scanned the second. the received frame will be lost even if the second matching message buffer was ?free to receive?. if a tx message buffer containing the lowest id is deactivated after flexcan has scanned it, then flexcan will look for another winner within the message buffers that it has not scanned yet. therefore, it may transmit a message buffer with id that may not flexcan module RM0029 1446/1740 doc id 15177 rev 8 be the lowest at the time because a lower id might be present in one of the message buffers that it had already scanned before the deactivation. there is a point in time until which the deactivation of a tx message buffer causes it not to be transmitted (end of move-out). after this point, it is transmitted but no interrupt is issued and the code field is not updated. in order to avoid this situation, the abort procedures described in section , transmission abort mechanism should be used. message buffer lock mechanism besides message buffer deactivation, flexcan has another data coherence mechanism for the receive process. when the cpu reads the control and status word of an ?active not empty? rx message buffer, flexcan assumes that the cpu wants to read the whole message buffer in an atomic operation, and thus it sets an internal lock flag for that message buffer. the lock is released when the cpu reads the free running timer (global unlock operation), or when it reads the control and status word of another message buffer. the message buffer locking is done to prevent a new frame to be written into the message buffer while the cpu is reading it. note: the locking mechanism only applies to rx message buffers which have a code different than inactive (?0000?) or empty (bh) (?0100?). also, tx message buffers can not be locked. suppose, for example, that the fifo is disabled and the second and the fifth message buffers of the array are programmed with the same id, and flexcan has already received and stored messages into these two message buffers. suppose now that the cpu decides to read mb number 5 and at the same time another message with the same id is arriving. when the cpu reads the control and status word of mb number 5, this mb is locked. the new message arrives and the matching algorithm finds out that there are no ?free to receive? message buffers, so it decides to override mb number 5. however, this message buffer is locked, so the new message can not be written there. it will remain in the smb waiting for the message buffer to be unlocked, and only then will be written to the message buffer. if the message buffer is not unlocked in time and yet another new message with the same id arrives, then the new message overwrites the one on the smb and there will be no indication of lost messages either in the code field of the message buffer or in the error and status register. while the message is being moved-in from the smb to the message buffer, the busy bit on the code field is asserted. if the cpu reads the control and status word and finds out that the busy bit is set, it should defer accessing the message buffer until the busy bit is negated. note: if the busy bit is asserted or if the message buffer is empty, then reading the control and status word does not lock the message buffer. deactivation takes precedence over locking. if the cpu deactivates a locked rx message buffer, then its lock status is negated and the message buffer is marked as invalid for the current matching round. any pending message on the smb will not be transferred anymore to the message buffer. bh. in previous flexcan versions, reading the c/s word locked t he message buffer even if it was empty. in current flexcan versions, this behavior is maintained when the mbfen bit is negated. RM0029 flexcan module doc id 15177 rev 8 1447/1740 32.5.7 rx fifo the receive-only fifo is enabled by asserting mcr[fen]. the reset value of this bit is zero to maintain software backwards compatibility with previous versions of the module that did not have the fifo feature. when the fifo is enabled, the memory region normally occupied by the first eight message buffers (0x80?0xff) is now reserved for use of the fifo engine (see section 32.4.4, rx fifo structure ). management of read and write pointers is done internally by the fifo engine. the cpu can read the received frames sequentially, in the order they were received, by repeatedly accessing a message buffer structure at the beginning of the memory. the fifo can store up to 6 frames pending service by the cpu. an interrupt is sent to the cpu when new frames are available in the fifo. upon receiving the interrupt, the cpu must read the frame (accessing a message buffer in the 0x80 address) and then clear the interrupt. the act of clearing the interrupt triggers the fifo engine to replace the message buffer in 0x80 with the next frame in the queue, and then issue another interrupt to the cpu. if the fifo is full and more frames continue to be received, an overflow interrupt is issued to the cpu and subsequent frames are not accepted until the cpu creates space in the fifo by reading one or more frames. a warning interrupt is also generated when 5 frames are accumulated in the fifo. a powerful filtering scheme is provided to accept only frames intended for the target application, thus reducing the interrupt servicing work load. the filtering criteria is specified by programming a table of 8 32-bit registers that can be configured to one of the following formats (see also section 32.4.4, rx fifo structure ): format a: 8 extended or standard ids (including ide and rtr) format b: 16 standard ids or 16 extended 14-bit id slices (including ide and rtr) format c: 32 standard or extended 8-bit id slices note: a chosen format is applied to all 8 registers of the filter table. it is not possible to mix formats within the table. the eight elements of the filter table are individually affected by the first eight individual mask registers (rximr0 ? rximr7), allowing very powerful filtering criteria to be defined. the rest of the rximr, starting from rxim8, continue to affect the regular message buffers, starting from mb8. if the mbfen bit is negated (or if the rximr are not available for the particular mcu), then the fifo filter table is affected by the legacy mask registers as follows: element 6 is affected by rx14mask, element 7 is affected by rx15mask and the other elements (0 to 5) are affected by rxgmask. flexcan module RM0029 1448/1740 doc id 15177 rev 8 precautions when using global mask and individual mask registers 32.5.8 can protocol related features remote frames remote frame is a special kind of frame. the user can program a message buffer to be a request remote frame by writing the message buffer as transmit with the rtr bit set to ?1?. after the remote request frame is transmitted successfully, the message buffer becomes a receive message buffer, with the same id as before. when a remote request frame is received by flexcan, its id is compared to the ids of the transmit message buffers with the code field ?1010?. if there is a matching id, then this message buffer frame will be transmitted. note that if the matching message buffer has the rtr bit set, then flexcan will transmit a remote frame as a response. a received remote request frame is not stored in a receive buffer. it is only used to trigger a transmission of a frame in response. the mask registers are not used in remote frame matching, and all id bits (except rtr) of the incoming received frame should match. in the case that a remote request frame was received and matched a message buffer, this message buffer immediately enters the internal arbitration process, but is considered as normal tx message buffer, with no higher priority. the data length of this frame is independent of the dlc field in the remote frame that initiated its transmission. if the rx fifo is enabled (bit fen set in mcr), flexcan will not generate an automatic response for remote request frames that match the fifo filtering criteria. if the remote table 778. recommended fen and bcc settings case mcr[fen] rxfifo mcr[bcc] rx individual mask notes case 1 fen = 0 bcc = 0 rxgmask, rx14mask, and rx15mask can safely be used. this allows backwards compatibility to older devices (e.g., devices without the individual masks feature). in this case, individual masks are not used. case 2 fen = 1 bcc = 0 1st alternative: do not use rxgmask, rx14mask, and rx15mask in this case, leave the masks in their reset state. case 3 fen = 1 bcc = 0 2nd alternative: do not configure any mb as rx (i.e., let all mbs as either tx or inactive). in this case, rxgmask, rx14mask, and rx15mask can be used to affect id tables without affecting the filtering process for rx mbs. case 4 don?t care bcc = 1 if mcr[bcc] = 1, then the rximrs are enabled. thus, rxgmask, rx14mask, and rx15mask are not used. particularly, when mcr[fen] = 0, rxfifo is disabled; rxgmask, rx14mask, and rx15mask do not affect filtering. individual masks are used. RM0029 flexcan module doc id 15177 rev 8 1449/1740 frame matches one of the target ids, it will be stored in the fifo and presented to the cpu. note that for filtering formats a and b, it is possible to select whether remote frames are accepted or not. for format c, remote frames are always accepted (if they match the id). overload frames flexcan does transmit overload frames due to detection of following conditions on can bus: detection of a dominant bit in the first/second bit of intermission detection of a dominant bit at the 7th bit (last) of end of frame field (rx frames) detection of a dominant bit at the 8th bit (last) of error frame delimiter or overload frame delimiter time stamp the value of the free running timer is sampled at the beginning of the identifier field on the can bus, and is stored at the end of ?move-in? in the time stamp field, providing network behavior with respect to time. note that the free running timer can be reset upon a specific frame reception, enabling network time synchronization. refer to tsyn description in section , control register (cr) . protocol timing figure 824 shows the structure of the clock generation circuitry that feeds the can protocol interface (cpi) submodule. the clock source bit (clksrc) in the cr register defines whether the internal clock is connected to the output of a crystal oscillator (oscillator clock) or to the peripheral clock (generally from a pll). in order to guarantee reliable operation, the clock source should be selected while the module is in disable mode (bit mdis set in the module configuration register). figure 824. can engine clocking scheme the crystal oscillator clock should be selected whenever a tight tolerance (up to 0.1%) is required in the can bus timing. the crystal oscillator clock has better jitter performance than pll generated clocks. the flexcan module supports a variety of means to setup bit timing parameters that are required by the can protocol. the control register has various fields used to control bit timing parameters: presdiv, propseg, pseg1, pseg2 and rjw. see section , control register (cr) . peripheral clock (pll) oscillator clock (xtal) clksrc prescaler (1 .. 256) sclock cpi clock flexcan module RM0029 1450/1740 doc id 15177 rev 8 the presdiv field controls a prescaler that generates the serial clock (sclock), whose period defines the ?time quantum? used to compose the can waveform. a time quantum is the atomic unit of time handled by the can engine. a bit time is subdivided into three segments (bi) (reference figure 825 and table 779 ): sync_seg: this segment has a fixed length of one time quantum. signal edges are expected to happen within this section time segment 1: this segment includes the propagation segment and the phase segment 1 of the can standard. it can be programmed by setting the propseg and the pseg1 fields of the cr register so that their sum (plus 2) is in the range of 4 to 16 time quanta time segment 2: this segment represents the phase segment 2 of the can standard. it can be programmed by setting the pseg2 field of the cr register (plus 1) to be 2 to 8 time quanta long figure 825. segments within the bit time bi. for further explanation of the underly ing concepts please refer to iso/dis 11519 ? 1, section 10.3. reference also the bosch can 2.0a/b protocol spec ification dated september 1991 for bit timing. f tq f canclk prescaler v alue t () ------------------------------------------------------- = bit rate f tq number of time quanta tt t () ---------------------------------------------------------------------------------------- - = t sync_seg time segment 1 time segment 2 1 4 ... 16 2 ... 8 8 ... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + pseg1 + 2) (pseg2 + 1) transmit point RM0029 flexcan module doc id 15177 rev 8 1451/1740 ta ble 78 0 gives an overview of the can compliant segment settings and the related parameter values. note: it is the user?s responsibility to ensure the bit time settings are in compliance with the can standard. for bit time calculations, use an ipt (information processing time) of 2, which is the value implemented in the flexcan module. arbitration and matching timing during normal transmission or reception of frames, the arbitration, matching, move-in and move-out processes are executed during certain time windows inside the can frame, as shown in figure 826 . figure 826. arbitration, match and move time windows table 779. time segment syntax syntax description sync_seg system expects transitions to occur on the bus during this period. transmit point a node in transmit mode transfers a new value to the can bus at this point. sample point a node samples the bus at this point. if the three samples per bit option is selected, then this point marks the position of the third sample. table 780. can standard compliant bit time segment settings time segment 1 time segment 2 resynchronization jump width 5 .. 10 2 1 .. 2 4 .. 11 3 1 .. 3 5 .. 12 4 1 .. 4 6 .. 13 5 1 .. 4 7 .. 14 6 1 .. 4 8 .. 15 7 1 .. 4 9 .. 16 8 1 .. 4 crc (15) eof (7) interm start move matching/arbitration window (24 bits) move (bit 6) window flexcan module RM0029 1452/1740 doc id 15177 rev 8 when doing matching and arbitration, flexcan needs to scan the whole message buffer memory during the available time slot. in order to have sufficient time to do that, the following requirements must be observed: a valid can bit timing must be programmed, as indicated in table 780 the peripheral clock frequency can not be smaller than the oscillator clock frequency, i.e. the pll can not be programmed to divide down the oscillator clock there must be a minimum ratio between the peripheral clock frequency and the can bit rate, as specified in ta ble 78 1 a direct consequence of the first requirement is that the minimum number of time quanta per can bit must be 8, so the oscillator clock frequency should be at least 8 times the can bit rate. the minimum frequency ratio specified in table 781 can be achieved by choosing a high enough peripheral clock frequency when compared to the oscillator clock frequency, or by adjusting one or more of the bit timing parameters (presdiv, propseg, pseg1, pseg2). as an example, taking the case of 64 message buffers, if the oscillator and peripheral clock frequencies are equal and the can bit timing is programmed to have 8 time quanta per bit, then the prescaler factor (presdiv + 1) should be at least 2. for prescaler factor equal to one and can bit timing with 8 time quanta per bit, the ratio between peripheral and oscillator clock frequencies should be at least 2. 32.5.9 modes of operation details freeze mode this mode is entered by asserting mcr[halt] or when the mcu is put into debug mode. in both cases it is also necessary that mcr[frz] is asserted and the module is not in either of the low power modes (disable or stop). when freeze mode is requested during transmission or reception, flexcan does the following: waits to be in either intermission, passive error, bus off or idle state waits for all internal activities like arbitration, matching, move-in and move-out to finish ignores the rx input pin and drives the tx pin as recessive stops the prescaler, thus halting all can protocol activities grants write access to the error counters register, which is read-only in other modes sets the notrdy and frzack bits in mcr after requesting freeze mode, the user must wait for mcr[frzack] to be asserted before executing any other action, otherwise flexcan may operate in an unpredictable way. in freeze mode, all memory mapped registers are accessible. exiting freeze mode is done in one of the following ways: cpu negates mcr[frz ] the mcu is removed from debug mode and/or the halt bit is negated table 781. minimum ratio between peripheral clock frequency and can bit rate number of message buffers minimum ratio 16 8 32 8 64 16 RM0029 flexcan module doc id 15177 rev 8 1453/1740 once out of freeze mode, flexcan tries to resynchronize to the can bus by waiting for 11 consecutive recessive bits. module disable mode this low power mode is entered when the mdis bit in the mcr register is asserted. if the module is disabled during freeze mode, the module sends a request to disable the clocks to the can protocol interface (cpi) and message buffer management (mbm) sub-modules, sets the lpm_ack bit and negates the frz_ack bit. if the module is disabled during transmission or reception, flexcan does the following: waits to be in either idle or bus off state, or else waits for the third bit of intermission and then checks it to be recessive waits for all internal activities like arbitration, matching, move-in and move-out to finish ignores its rx input pin and drives its tx pin as recessive shuts down the clocks to the cpi and mbm submodules sets the notrdy and mdisack bits in mcr the bus interface unit continues to operate, enabling the cpu to access memory mapped registers, except the free running timer, the error counter register and the message buffers, which cannot be accessed when the module is in disable mode. exiting from this mode is done by negating mcr[mdis], which will resume the clocks and negate mcr[mdisack]. stop mode this is a system low power mode in which all mcu clocks are stopped for maximum power savings. if flexcan receives the global stop mode request during freeze mode, it sets mcr[mdisack], negates mcr[frzack] and then sends a stop acknowledge signal to the cpu, in order to shut down the clocks globally. if stop mode is requested during transmission or reception, flexcan does the following: waits to be in either idle or bus off state, or else waits for the third bit of intermission and checks it to be recessive waits for all internal activities like arbitration, matching, move-in and move-out to finish ignores its rx input pin and drives its tx pin as recessive sets the notrdy and mdisack bits in mcr sends a stop acknowledge signal to the cpu, so that it can shut down the clocks globally exiting stop mode is done in one of the following ways: cpu resuming the clocks and removing the stop mode request cpu resuming the clocks and stop mode request as a result of the self wake mechanism in the self wake mechanism, if mcr[slf_wak] was set at the time flexcan entered stop mode, then upon detection of a recessive to dominant transition on the can bus, flexcan sets esr[wakint] and, if enabled by mcr[wak_msk], generates a wake up interrupt to the cpu. upon receiving the interrupt, the cpu should resume the clocks and remove the stop mode request. flexcan will then wait for 11 consecutive recessive bits to synchronize to the can bus. as a consequence, it will not receive the frame that woke it up. table 782 details the effect of mcr[slf_wak] and mcr[wak_msk] upon wake-up from stop mode. note that wake-up from stop mode only works when both bits are asserted. flexcan module RM0029 1454/1740 doc id 15177 rev 8 the sensitivity to can bus activity can be modified by applying a low-pass filter function to the rx can input line while in stop mode. see the wak_src bit in section , module configuration register (mcr) . this feature can be used to protect flexcan from waking up due to short glitches on the can bus lines. such glitches can result from electromagnetic interference within noisy environments. 32.5.10 interrupts the module can generate up to 70 interrupt sources (64 interrupts due to message buffers and 6 interrupts due to ored interrupts from message buffers, bus off, error, tx warning, rx warning and wake up). the number of actual sources depends on the configured number of message buffers. each one of the message buffers can be an interrupt source, if its corresponding bit in the imrl or imrh register is set. there is no distinction between tx and rx interrupts for a particular buffer, under the assumption that the buffer is initialized for either transmission or reception. each of the buffers has assigned a flag bit in the ifrl or ifrh register. the bit is set when the corresponding buffer completes a successful transmission/reception and is cleared when the cpu writes it to ?1? (unless another interrupt is generated at the same time). note: it must be guaranteed that the cpu only clears the bit causing the current interrupt. for this reason, bit manipulation instructions (bset) must not be used to clear interrupt flags. these instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine. if the rx fifo is enabled (mcr[fen] set), the interrupts corresponding to mbs 0 to 7 have a different behavior. bit 7 of the ifrl becomes the ?fifo overflow? flag; bit 6 becomes the fifo warning flag, bit 5 becomes the ?frames available in fifo flag? and bits 4?0 are unused. see section , interrupt flags 1 register (ifrl) for more information. a combined interrupt for all message buffers is also generated by an or of all the interrupt sources from message buffers. this interrupt gets generated when any of the message buffers generates an interrupt. in this case the cpu must read the ifrl or ifrh register to determine which message buffer caused the interrupt. the other five interrupt sources (bus off, error, tx warning, rx warning and wake up) generate interrupts like the message buffer ones, and can be read from the error and status register. the bus off, error, tx warning and rx warning interrupt mask bits are located in the control register, and the wake-up interrupt mask bit is located in the mcr. table 782. wake-up from stop mode slf_wak wak_msk mcu clocks enabled wake-up interrupt generated 00 no no 01 no no 10 no no 11 yes yes RM0029 flexcan module doc id 15177 rev 8 1455/1740 32.5.11 bus interface the cpu access to flexcan registers are subject to the following rules: read and write access to supervisor registers in user mode results in access error. read and write access to unimplemented or reserved address space also results in access error. any access to unimplemented message buffer or rx individual mask register locations results in access error. any access to the rx individual mask register space when mcr[mbfen] is negated results in access error. if mcr[maxmb] is programmed with a value smaller than the available number of message buffers, then the unused memory space can be used as general purpose ram space. note that the rx individual mask registers can only be accessed in freeze mode, and this is still true for unused space within this memory. note also that reserved words within ram cannot be used. as an example, suppose flexcan is configured with 64 message buffers and mcr[maxmb] is programmed with zero. the maximum number of message buffers in this case becomes one. the message buffer memory starts at 0x0060, but the space from 0x0060 to 0x007f is reserved (for smb usage), and the space from 0x0080 to 0x008f is used by the one message buffer. this leaves us with the available space from 0x0090 to 0x047f. the available memory in the mask registers space would be from 0x0884 to 0x097f. note: unused message buffer space must not be used as general purpose ram while flexcan is transmitting and receiving can frames. 32.6 initialization/application information this section provide instructions for initializing the flexcan module. 32.6.1 flexcan initialization sequence the flexcan module may be reset in three ways: mcu level hard reset, which resets all memory mapped registers asynchronously mcu level soft reset, which resets some of the memory mapped registers synchronously (refer to tab le 7 62 to see what registers are affected by soft reset) softrst bit in mcr, which has the same effect as the mcu level soft reset soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains. therefore, it may take some time to fully propagate its effects. the softrst bit remains asserted while soft reset is pending, so software can poll this bit to know when the reset has completed. also, soft reset can not be applied while clocks are shut down in any of the low power modes. the low power mode should be exited and the clocks resumed before applying soft reset. the clock source (clksrc bit) should be selected while the module is in disable mode. after the clock source is selected and the module is enabled (mdis bit negated), flexcan automatically goes to freeze mode. in freeze mode, flexcan is unsynchronized to the can bus, the halt and frz bits in the mcr are set, the internal state machines are disabled and the frzack and notrdy bits in the mcr are set. the tx pin is in recessive state and flexcan does not initiate any transmission or reception of can frames. note that the message buffers and the rx individual mask registers are not affected by reset, so they are not automatically initialized. flexcan module RM0029 1456/1740 doc id 15177 rev 8 for any configuration change/initialization it is required that flexcan is put into freeze mode (see section , freeze mode ). the following is a generic initialization sequence applicable to the flexcan module: initialize the module configuration register (mcr) ? enable the individual filtering per message buffer and reception queue features by setting the mbfen bit ? enable the warning interrupts by setting the wrnen bit ? if required, disable frame self reception by setting the srx_dis bit ? enable the fifo by setting the fen bit ? enable the abort mechanism by setting the aen bit ? enable the local priority feature by setting the lprio_en bit initialize the control register (cr) ? determine the bit timing parameters: propseg, pseg1, pseg2, rjw ? determine the bit rate by programming the presdiv field ? determine the internal arbitration mode (bit cr[lbuf]) initialize the message buffers ? the control and status word of all message buffers must be initialized ? if fifo was enabled, the 8-entry id table must be initialized ? other entries in each message buffer should be initialized as required initialize the rx individual mask registers set required interrupt mask bits in the corresponding imrl or imrh register (for all message buffer interrupts), in the cr (for bus off and error interrupts) and in the mcr for wake-up interrupt negate the halt bit in mcr starting with the last event, flexcan attempts to synchronize to the can bus. 32.6.2 flexcan addressing and ram size configurations there are three ram configurations that can be implemented within the flexcan module. the possible configurations are: for 16 message buffers: 288 bytes for message buffer memory and 64 bytes for individual mask registers for 32 message buffers: 544 bytes for message buffer memory and 128 bytes for individual mask registers for 64 message buffers: 1056 bytes for message buffer memory and 256 bytes for individual mask registers in each configuration the user can program the maximum number of message buffers that will take part in the matching and arbitration processes using field mcr[maxmb]: for 16 message buffer configuration, mcr[maxmb] can be any number between 0? 15. for 32 message buffer configuration, mcr[maxmb] can be any number between 0? 31. for 64 message buffer configuration, mcr[maxmb] can be any number between 0 ? 63. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1457/1740 33 flexray communication controller (flexray) 33.1 introduction 33.1.1 reference the following documents are referenced. flexray communications system protocol specification, version 2.1 rev a (bj) flexray communications system electrical physical layer specification, version 2.1 rev a 33.1.2 glossary this section provides a list of terms used in this chapter. bj. the flexray specifications have been developed for automotive applicati ons.the flexray specifications have been neither developed nor tested for non-automotive applications. table 783. list of terms term definition bcu buffer control unit?handles message buffer access bmif bus master interface?provides master access to flexray memory area cc flexray communication controller?module described in this chapter cdc clock domain crosser chi controller host interface cycle length in t the actual length of a cycle in t for the ideal cc (+/- 0 ppm) ebi external bus interface flexray memory area memory area to store the physical message buffer payload data, frame header, frame andslot status, and synchronization frame related tables system memory memory that contains the flexray memory area system bus bus that connects the cc and system memory fss frame start sequence hif host interface?provides host access to the cc host the flexray cc host cpu lut look up table?stores message buffer header index value mb message buffer mbidx message buffer index?the position of a header field entry within the header area. if the header area is accessed as an array, this is the same as the array index of the entry. mbnum message buffer number?position of message buffer configuration registers within the register map. for example, message buffer number 5 corresponds to the mbccs5 register. flexray communication controller (flexray) RM0029 1458/1740 doc id 15177 rev 8 33.1.3 color coding throughout this chapter types of items are highlighted through the use of an italicized color font. flexray protocol parameters, constants and variables are highlighted with blue italics . an example is the parameter gdactionpointoffset . flexray protocol states are highlighted in green italics . an example is the state poc:normal active . 33.1.4 overview the cc is a flexray communication controller that implements the flexray communications system protocol specification, version 2.1 rev a. the cc has three main components: controller host interface (chi) protocol engine (pe) clock domain crossing unit (cdc) a block diagram of the cc with its surrounding modules is given in figure 827 . mcu microcontroller unit t microtick mt macrotick mts media access test symbol nit network idle time pe protocol engine poc protocol operation control?each state of the poc is denoted by poc:state rx reception seq sequencer engine tcu time control unit tx transmission sync frame null frame or message frame with sync frame indicator set to 1 startup frame null frame or message frame with both sync frame indicator and startup frame indicator set to 1 normal frame null frame or message frame with both sync frame indicator and startup frame indicator set to 0 null frame frame with null frame indicator set to 0 message frame frame with null frame indicator set to 1 table 783. list of terms (continued) term definition RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1459/1740 figure 827. flexray block diagram the protocol engine has two transmitter units txa and txb and two receiver units rxa and rxb for sending and receiving frames through the two flexray channels. the time control unit (tcu) is responsible for maintaining global clock synchronization to the flexray network. the overall activity of the pe is controlled by the sequencer engine (seq). the cc host interface provides host access to the module?s configuration, control, and status registers, as well as to the message buffer configuration, control, and status registers. the message buffers themselves, which contain the frame header and payload data received or to be transmitted, and the slot status information, are stored in the flexray memory area. the clock domain crossing unit implements signal crossing from the chi clock domain to the pe clock domain and vice versa, to allow for asynchronous pe and chi clock domains. the cc stores the frame header and payload data of frames received or of frames to be transmitted in the flexray memory area. the application accesses the flexray memory area to retrieve and provide the frames to be processed by the cc. in addition to the frame header and payload data, the cc stores the synchronization frame related tables in the flexray memory area for application processing. the flexray memory area is located in the system memory of the mcu. the cc has access to the flexray memory area via its bus master interface (bmif). the host provides the start address of the flexray memory area within the system memory by programming the system memory base address register (fr_symbadr) . all flexray memory area related offsets are stored in offset registers. the physical address pointer into the flexray memory area of the mcu system memory is calculated using the offset values the flexray memory area base address. note: the cc does not provide a memory protection scheme for the flexray memory area. clock domain crossing pe txa rxa tcu config seq chi hif search lut bcu fr_a_rx fr_b_rx fr_dbg[0] fr_a_tx fr_a_tx_en fr_b_tx fr_b_tx_en fr_dbg[1] fr_dbg[2] fr_dbg[3] flexray peripheral bridge b system memory bmif system bus flexray communication controller (flexray) RM0029 1460/1740 doc id 15177 rev 8 33.1.5 features the cc provides the following features: flexray communications system protocol specification, version 2.1 rev a compliant protocol implementation flexray communications system electrical physical layer specification, version 2.1 rev a compliant bus driver interface single channel support ? flexray port a can be configured to be connected either to physical flexray channel a or physical flexray channel b. flexray bus data rates of 10 mbit/s, 8 mbit/s, 5 mbit/s, and 2.5 mbit/s supported 128 configurable message buffers with ? individual frame id filtering ? individual channel id filtering ? individual cycle counter filtering message buffer header, status and payload data stored in dedicated flexray memory area ? allows for flexible and efficient message buffer implementation ? consistent data access ensured by means of buffer locking scheme ? application can lock multiple buffers at the same time size of message buffer payload data section configurable from 0 up to 254 bytes 2 independent message buffer segments with configurable size of payload data section ? each segment can contain message buffers assigned to the static segment and message buffers assigned to the dynamic segment at the same time zero padding for transmit message buffers in static segment ? applied when the frame payload length exceeds the size of the message buffer data section transmit message buffers configurable with state/event semantics message buffers can be configured as ? receive message buffer ? single buffered transmit message buffer ? double buffered transmit message buffer (combines two single buffered message buffer) individual message buffer reconfiguration supported ? means provided to safely disable individual message buffers ? disabled message buffers can be reconfigured 2 independent receive fifos ? 1 receive fifo per channel ? up to 255 entries for each fifo ? global frame id filtering, based on both value/mask filters and range filters ? global channel id filtering ? global message id filtering for the dynamic segment 4 configurable slot error counters 4 dedicated slot status indicators RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1461/1740 ? used to observe slots without using receive message buffers measured value indicators for the clock synchronization ? internal synchronization frame id and synchronization frame measurement tables can be copied into the flexray memory area fractional macroticks are supported for clock correction maskable interrupt sources provided via individual and combined interrupt lines 1 absolute timer 1 timer that can be configured to absolute or relative secded for protocol engine data ram sedded for chi lookup table ram 33.1.6 modes of operation this section describes the basic operational power modes of the cc. disabled mode the cc enters the disabled mode during hard reset. the cc indicates that it is in the disabled mode by negating the module enable bit men in the module configuration register (fr_mcr) . in the disabled mode no communication is performed on the flexray bus. all registers with the write access conditions any time and disabled mode can be accessed for writing as stated in section 33.5.2, register descriptions . the application configures the cc by accessing the configuration bits and fields in the module configuration register (fr_mcr) . leave disabled mode the cc leaves the disabled mode and enters the normal mode, when the application writes 1 to the module enable bit men in the module configuration register (fr_mcr) . note: once the cc is enabled it can only be disabled via a device reset. normal mode in this mode the cc is fully functional. the cc indicates that it is in normal mode by asserting the module enable bit men in the module configuration register (fr_mcr) . enter normal mode this mode is entered when the application requests the cc to leave the disabled mode. if the normal mode was entered by leaving the disabled mode, the application has to perform the protocol initialization described in section , protocol initialization to achieve full flexray functionality. depending on the values of the scm, cha, and chb bits in the module configuration register (fr_mcr) , the corresponding flexray bus driver ports are enabled and driven. flexray communication controller (flexray) RM0029 1462/1740 doc id 15177 rev 8 33.2 external signal description this section lists and describes the cc signals, connected to external pins. these signals are summarized in table 784 and described in detail in section 33.2.1, detailed signal descriptions . note: the off-chip signals fr_a_rx, fr_a_tx, and fr_a_tx_en are available on each package option. the availability of the other off-chip signals depends on the package option. 33.2.1 detailed signal descriptions this section provides a detailed description of the cc signals, connected to external pins. fr_a_rx ? receive data channel a the fr_a_rx signal carries the receive data for channel a from the corresponding flexray bus driver. fr_a_tx ? transmit data channel a the fr_a_tx signal carries the transmit data for channel a to the corresponding flexray bus driver. fr_a_tx_en ? transmit enable channel a the fr_a_tx_en signal indicates to the flexray bus driver that the cc is attempting to transmit data on channel a. fr_b_rx ? receive data channel b the fr_b_rx signal carries the receive data for channel b from the corresponding flexray bus driver. fr_b_tx ? transmit data channel b the fr_b_tx signal carries the transmit data for channel b to the corresponding flexray bus driver table 784. external signal properties name direction active reset function fr_a_rx input ? ? receive data channel a fr_a_tx output ? 1 transmit data channel a fr_a_tx_en output low 1 transmit enable channel a fr_b_rx input ? ? receive data channel b fr_b_tx output ? 1 transmit data channel b fr_b_tx_en output low 1 transmit enable channel b fr_dbg[0] output ? 0 debug strobe signal 0 fr_dbg[1] output ? 0 debug strobe signal 1 fr_dbg[2] output ? 0 debug strobe signal 2 fr_dbg[3] output ? 0 debug strobe signal 3 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1463/1740 fr_b_tx_en ? transmit enable channel b the fr_b_tx_en signal indicates to the flexray bus driver that the cc is attempting to transmit data on channel b. fr_dbg[3], fr_dbg[2], fr_dbg[1], fr_dbg[0] ? strobe signals these signals provide the selected debug strobe signals. for details on the debug strobe signal selection refer to section 33.6.16, strobe signal support . 33.3 controller host interface clocking the clock for the chi is derived from the system bus clock and has the same phase and frequency as the system bus clock. there are two constraints for the minimum chi clock frequency: the first constraint corresponds to the number of utilized message buffers and is specified in section 33.7.6, number of usable message buffers . the second constraint corresponds to the value of the timeout field in the system memory access time-out register (fr_symator) and is specified in section , configure system memory access time-out register (fr_symator) . 33.4 protocol engine clocking the clock for the protocol engine can be generated by two sources. the first source is the internal crystal oscillator and the second source is an internal pll. the clock source to be used is selected by the clock source select bit clksel in the module configuration register (fr_mcr) . 33.4.1 oscillator clocking if the protocol engine is clocked by the internal crystal oscillator, an 40 mhz crystal or cmos compatible clock must be connected to the oscillator pins. the crystal or clock must fulfill the requirements given by the flexray communications system protocol specification, version 2.1 rev a. 33.4.2 pll clocking if the protocol engine is clocked by the internal pll, the frequency of the pe clock source is system clock / 3. the system clock frequency has to be 120 mhz. 33.5 memory map and register description the cc occupies 1280 bytes of address space starting at the base address of the cc is defined by the memory map of the mcu. 33.5.1 memory map the complete memory map of the cc is shown in table 785 . the addresses presented here are the offsets relative to the cc base address which is defined by the mcu address map. flexray communication controller (flexray) RM0029 1464/1740 doc id 15177 rev 8 table 785. flexray memory map offset register access location module configuration and control 0x0000 module version register (fr_mvr) r on page 33- 1472 0x0002 module configuration register (fr_mcr) r/w on page 33- 1472 0x0004 system memory base address high register (fr_symbadhr) r/w on page 33- 1475 0x0006 system memory base address low register (fr_symbadlr) r/w on page 33- 1475 0x0008 strobe signal control register (fr_stbscr) r/w on page 33- 1475 0x000a reserved r ? 0x000c message buffer data size register (fr_mbdsr) r/w on page 33- 1477 0x000e message buffer segment size and utilization register (fr_mbssutr) r/w on page 33- 1477 pe access registers 0x0010 pe dram access register (fr_pedrar) r/w on page 33- 1478 0x0012 pe dram data register (fr_pedrdr) r/w on page 33- 1479 interrupt and error handling 0x0014 protocol operation control register (fr_pocr) r/w on page 33- 1479 0x0016 global interrupt flag and enable register (fr_gifer) r/w on page 33- 1481 0x0018 protocol interrupt flag register 0 (fr_pifr0) r/w on page 33- 1483 0x001a protocol interrupt flag register 1 (fr_pifr1) r/w on page 33- 1485 0x001c protocol interrupt enable register 0 (fr_pier0) r/w on page 33- 1486 0x001e protocol interrupt enable register 1 (fr_pier1) r/w on page 33- 1488 0x0020 chi error flag register (fr_chierfr) r/w on page 33- 1489 0x0022 message buffer interrupt vector register (fr_mbivec) r on page 33- 1491 0x0024 channel a status error counter register (fr_casercr) r on page 33- 1492 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1465/1740 0x0026 channel b status error counter register (fr_cbsercr) r on page 33- 1492 protocol status 0x0028 protocol status register 0 (fr_psr0) r on page 33- 1493 0x002a protocol status register 1 (fr_psr1) r on page 33- 1494 0x002c protocol status register 2 (fr_psr2) r on page 33- 1495 0x002e protocol status register 3 (fr_psr3) r/w on page 33- 1497 0x0030 macrotick counter register (fr_mtctr) r on page 33- 1499 0x0032 cycle counter register (fr_cyctr) r on page 33- 1499 0x0034 slot counter channel a register (fr_sltctar) r on page 33- 1500 0x0036 slot counter channel b register (fr_sltctbr) r on page 33- 1500 0x0038 rate correction value register (fr_rtcorvr) r on page 33- 1501 0x003a offset correction value register (fr_ofcorvr) r on page 33- 1501 0x003c combined interrupt flag register (fr_cifr) r on page 33- 1502 0x003e system memory access time-out register (fr_symator) r/w on page 33- 1503 sync frame counter and tables 0x0040 sync frame counter register (fr_sfcntr) r on page 33- 1504 0x0042 sync frame table offset register (fr_sftor) r/w on page 33- 1504 0x0044 sync frame table configuration, control, status register (fr_sftccsr) r/w on page 33- 1505 sync frame filter 0x0046 sync frame id rejection filter register (fr_sfidrfr) r/w on page 33- 1506 0x0048 sync frame id acceptance filter value register (fr_sfidafvr) r/w on page 33- 1507 0x004a sync frame id acceptance filter mask register (fr_sfidafmr) r/w on page 33- 1507 table 785. flexray memory map (continued) offset register access location flexray communication controller (flexray) RM0029 1466/1740 doc id 15177 rev 8 network management vector 0x004c network management vector register 0 (fr_nmvr0) r on page 33- 1507 0x004e network management vector register 1 (fr_nmvr1) r on page 33- 1507 0x0050 network management vector register 2 (fr_nmvr2) r on page 33- 1507 0x0052 network management vector register 3 (fr_nmvr3) r on page 33- 1507 0x0054 network management vector register 4 (fr_nmvr4) r on page 33- 1507 0x0056 network management vector register 5 (fr_nmvr5) r on page 33- 1507 0x0058 network management vector length register (fr_nmvlr) r/w on page 33- 1508 timer configuration 0x005a timer configuration and control register (fr_ticcr) r/w on page 33- 1509 0x005c timer 1 cycle set register (fr_ti1cysr) r/w on page 33- 1510 0x005e timer 1 macrotick offset register (fr_ti1mtor) r/w on page 33- 1510 0x0060 timer 2 configuration register 0 (fr_ti2cr0) r/w on page 33- 1511 0x0062 timer 2 configuration register 1 (fr_ti2cr1) r/w on page 33- 1511 slot status configuration 0x0064 slot status selection register (fr_sssr) r/w on page 33- 1512 0x0066 slot status counter condition register (fr_ssccr) r/w on page 33- 1513 slot status 0x0068 slot status register 0 (fr_ssr0) r on page 33- 1515 0x006a slot status register 1 (fr_ssr1) r on page 33- 1515 0x006c slot status register 2 (fr_ssr2) r on page 33- 1515 0x006e slot status register 3 (fr_ssr3) r on page 33- 1515 table 785. flexray memory map (continued) offset register access location RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1467/1740 0x0070 slot status register 4 (fr_ssr4) r on page 33- 1515 0x0072 slot status register 5 (fr_ssr5) r on page 33- 1515 0x0074 slot status register 6 (fr_ssr6) r on page 33- 1515 0x0076 slot status register 7 (fr_ssr7) r on page 33- 1515 0x0078 slot status counter register 0 (fr_sscr0) r on page 33- 1516 0x007a slot status counter register 1 (fr_sscr1) r on page 33- 1516 0x007c slot status counter register 2 (fr_sscr2) r on page 33- 1516 0x007e slot status counter register 3 (fr_sscr3) r on page 33- 1516 mts generation 0x0080 mts a configuration register (fr_mtsacfr) r/w on page 33- 1517 0x0082 mts b configuration register (mtsbcfr) r/w on page 33- 1517 shadow buffer configuration 0x0084 receive shadow buffer index register (fr_rsbir) r/w on page 33- 1518 receive fifo ? configuration 0x0086 receive fifo watermark and selection register (fr_rfwmsr) r/w on page 33- 1520 0x0088 receive fifo start index register (fr_rfsir) r/w on page 33- 1520 0x008a receive fifo depth and size register (rfdsr) r/w on page 33- 1521 receive fifo ? control 0x008c receive fifo a read index register (fr_rfarir) r on page 33- 1521 0x008e receive fifo b read index register (fr_rfbrir) r on page 33- 1522 receive fifo ? filter 0x0090 receive fifo message id acceptance filter value register (fr_rfmidafvr) r/w on page 33- 1523 table 785. flexray memory map (continued) offset register access location flexray communication controller (flexray) RM0029 1468/1740 doc id 15177 rev 8 0x0092 receive fifo message id acceptance filter mask register (fr_rfmidafmr) r/w on page 33- 1523 0x0094 receive fifo frame id rejection filter value register (fr_rffidrfvr) r/w on page 33- 1524 0x0096 receive fifo frame id rejection filter mask register (fr_rffidrfmr) r/w on page 33- 1524 0x0098 receive fifo range filter configuration register (fr_rfrfcfr) r/w on page 33- 1524 0x009a receive fifo range filter control register (fr_rfrfctr) r/w on page 33- 1525 dynamic segment status 0x009c last dynamic transmit slot channel a register (fr_ldtxslar) r on page 33- 1526 0x009e last dynamic transmit slot channel b register (fr_ldtxslbr) r on page 33- 1526 protocol configuration 0x00a0 ... 0x00dc protocol configuration register 0 (fr_pcr0) ... protocol configuration register 30 (fr_pcr30) r/w ? r/w on page 33- 1529 ... on page 33- 1536 0x00de ... 0x00e6 reserved r ? receive fifo ? configuration (cont.) 0x00e8 receive fifo system memory base address high register (fr_rfsymbadhr) r/w on page 33- 1519 0x00ea receive fifo system memory base address low register (fr_rfsymbadlr) r/w on page 33- 1519 0x00ec receive fifo periodic timer register (fr_rfptr) r/w on page 33- 1519 receive fifo ? control (cont.) 0x00ee receive fifo fill level and pop count register (fr_rfflpcr) r/w on page 33- 1522 table 785. flexray memory map (continued) offset register access location RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1469/1740 33.5.2 register descriptions this section provides detailed descriptions of all registers in ascending address order, presented as 16-bit wide entities ta ble 78 6 provides a key for the register figures and register tables. ecc registers 0x00f0 ecc error interrupt flag and enable register (fr_eeifer) r/w on page 33- 1536 0x00f2 ecc error report and injection control register (fr_eericr) r/w on page 33- 1539 0x00f4 ecc error report address register (fr_eerar) r on page 33- 1539 0x00f6 ecc error report data register (fr_eerdr) r on page 33- 1540 0x00f8 ecc error report code register (fr_eercr) r on page 33- 1541 0x00fa ecc error injection address register (fr_eeiar) r/w on page 33- 1541 0x00fc ecc error injection data register (fr_eeidr) r/w on page 33- 1542 0x00fe ecc error injection code register (fr_eeicr) r/w on page 33- 1542 message buffers configuration, control, status 0x0100 message buffer configuration, control, status register 0 (fr_mbccsr0) r/w on page 33- 1543 0x0102 message buffer cycle counter filter register 0 (fr_mbccfr0) r/w on page 33- 1545 0x0104 message buffer frame id register 0 (fr_mbfidr0) r/w on page 33- 1546 0x0106 message buffer index register 0 (fr_mbidxr0) r/w on page 33- 1547 ... ... ... ... 0x04f8 message buffer configuration, control, status register 127 (fr_mbccsr127) r/w on page 33- 1543 0x04fa message buffer cycle counter filter register 127 (fr_mbccfr127) r/w on page 33- 1545 0x04fc message buffer frame id register 127 (fr_mbfidr127) r/w on page 33- 1546 0x04fe message buffer index register 127 (fr_mbidxr127) r/w on page 33- 1547 table 785. flexray memory map (continued) offset register access location flexray communication controller (flexray) RM0029 1470/1740 doc id 15177 rev 8 register reset all registers except the message buffer cycle counter filter registers (fr_mbccfrn) , message buffer frame id registers (fr_mbfidrn) , and message buffer index registers (fr_mbidxrn) are reset to their reset value on system reset. the registers mentioned above are located in physical memory blocks and, thus, they are not affected by reset. for some register fields, additional reset conditions exist. these additional reset conditions are mentioned in the detailed description of the register. the additional reset conditions are explained in table 787 . register write access this section describes the write access restriction terms that apply to all registers. register write access restriction for each register bit and register field, the write access conditions are specified in the detailed register description. a description of the write access conditions is given in ta ble 78 8 . if, for a specific register bit or field, none of the given write access conditions is table 786. register access conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writeable r* reserved bit or field; will not be changed?application must not write any value different from the reset value fieldname identifies the field?its presence in the read or write row indicates that it can be read or written. register field types rwm a read/write bit that may be modified by a hardware in some fashion other than by a reset w1c write one to clear?a flag bit that can be read, is cleared by writing a one; writing 0 has no effect reset value 0 resets to zero 1 resets to one ? not defined after reset and not affected by reset table 787. additional register reset conditions condition description protocol run command the register field is reset when the application writes to run command ?0101? to the poccmd field in the protocol operation control register (fr_pocr) . message buffer disable the register field is reset when the application has disabled the message buffer. this happens when the application writes 1 to the message buffer disable trigger bit fr_mbccsrn[edt] while the message buffer is enabled (fr_mbccsrn[eds] = 1) and the cc grants the disable to the application by clearing the fr_mbccsrn[eds] bit. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1471/1740 fulfilled, any write attempt to this register bit or field is ignored without any notification. the values of the bits or fields are not changed. the condition term [a or b] indicates that the register or field can be written to if at least one of the conditions is fulfilled.the condition term [a and b] indicates that the register or field can be written to if both conditions are fulfilled. register write access requirements all registers can be accessed with 8-bit, 16-bit and 32-bit wide operations. for some of the registers, at least a 16-bit wide write access is required to ensure correct operation. this write access requirement is stated in the detailed register description for each register affected internal register access the following memory mapped registers are used to access multiple internal registers. strobe signal control register (fr_stbscr) slot status selection register (fr_sssr) slot status counter condition register (fr_ssccr) receive shadow buffer index register (fr_rsbir) each of these memory mapped registers provides a sel field and a wmd bit. the sel field is used to select the internal register. the wmd bit controls the write mode. if the wmd bit is set to 0 during the write access, all fields of the internal register are updated. if the wmd bit set to 1, only the sel field is changed. all other fields of the internal register remain unchanged. this allows for reading back the values of the selected internal register in a subsequent read access. table 788. register write access restrictions condition indication description any time ? no write access restriction disabled mode fr_mcr[men] = 0 write access only when cc is in disabled mode normal mode fr_mcr[men] = 1 write access only when cc is in normal mode poc:config fr_psr0[protstate] = poc:config write access only when protocol is in the poc:config state mb_dis fr_mbccsr[eds] = 0 write access only when related message buffer is disabled mb_lck fr_mbccsrn[lcks] = 1 write access only when related message buffer is locked idl fr_eeiricr[bsy] = 0 write access only when ecc configuration is idle flexray communication controller (flexray) RM0029 1472/1740 doc id 15177 rev 8 module version register (fr_mvr) this register provides the cc version number. the module version number is derived from the chi version number and the pe version number. module configuration register (fr_mcr) this register defines the global configuration of the cc. figure 828. module version register (fr_mvr) base + 0x0000 0123456789101112131415 r chiver pever w reset1010001001101000 table 789. fr_mvr field description field description chiver chi version number ? this field provides the version number of the cc host interface. pever pe version number ? this field provides the version number of the protocol engine. figure 829. module configuration register (fr_mcr) base + 0x0002 write: men, sbff, scm, chb, cha, ecce, fum, fam, clksel, bitrate: disabled mode sffe: disabled mode or poc:config 0123456789101112131415 r men sbff scm chb cha sffe ecce 0 fum fam 0 clksel bitrate 0 w reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1473/1740 table 790. fr_mcr field description field description men module enable ? this bit indicates whether or not the cc is in the disabled mode. the application requests the cc to leave the disabled mode by writing 1 to this bit before leaving the disabled mode, the application must configure the scm, sbff, chb, cha, tmode, bitrate values. for details see section 33.1.6, modes of operation . 0 write: ignored, cc disable not possible read: cc disabled 1 write: enable cc read: cc enabled if the cc is enabled it can not be disabled. sbff system bus failure freeze ? this bit controls the behavior of the cc in case of a system bus failure. 0 continue normal operation 1 transition to freeze mode scm single channel device mode ? this control bit defines the channel device mode of the cc as described in section 33.6.10, channel device modes . 0 cc works in dual channel device mode 1 cc works in single channel device mode chb cha channel enable ? protocol related parameter: pchannels the semantic of these control bits depends on the channel device mode controlled by the scm bit and is given table 791 . sffe synchronization frame filter enable ? this bit controls the filtering for received synchronization frames. for details see section 33.6.15, sync frame filtering . 0 synchronization frame filtering disabled 1 synchronization frame filtering enabled ecce ecc functionality enable ? this bit controls the ecc memory error detection functionality. for details see section 33.6.24, memory content error detection . 0 ecc functionality (injection, detection, reporting, response) disabled 1 ecc functionality enabled fum fifo update mode ? this bit controls the fifo update behavior when the interrupt flags fr_gifer[fafaif] and fr_gifer[fafbif] are written by the application (see section , fifo update ) 0 fifoa/fifob is updated on writing 1 to fr_gifer[fafaif] /fr_gifer[fafbif] 1 fifoa/fifob) is not updated on writing 1 to fr_gifer[fafaif]/fr_gifer[fafbif] fam fifo address mode ? this bit controls the location of the system memory base address for the fifos. (see section , fifo configuration ) 0 fifo base address located in system memory base address register (fr_symbadr) 1 fifo base address located in receive fifo system memory base address register (fr_rfsymbadr) flexray communication controller (flexray) RM0029 1474/1740 doc id 15177 rev 8 clksel protocol engine clock source select ? this bit is used to select the clock source for the protocol engine. 0 pe clock source is generated by on-chip crystal oscillator 1 pe clock source is generated by on-chip pll bitrate flexray bus bit rate ? this bit field defines the flexray bus bit rate. 000 10.0 mbit/s 001 5.0 mbit/s 010 2.5 mbit/s 011 8.0 mbit/s 100 reserved 101 reserved 110 reserved 111 reserved table 790. fr_mcr field description (continued) field description table 791. flexray channel selection scm chb cha description dual channel device modes 0 00 ports fr_a_rx, fr_a_tx, and fr_a_tx_en not driven by cc ports fr_b_rx, fr_b_tx, and fr_a_tx_en not driven by cc 01 ports fr_a_rx, fr_a_tx, and fr_a_tx_en driven by cc - connected to flexray channel a ports fr_b_rx, fr_b_tx, and fr_a_tx_en not driven by cc 10 ports fr_a_rx, fr_a_tx, and fr_a_tx_en not driven by cc ports fr_b_rx, fr_b_tx, and fr_a_tx_en driven by cc - connected to flexray channel b 11 ports fr_a_rx, fr_a_tx, and fr_a_tx_en driven by cc - connected to flexray channel a ports fr_b_rx, fr_b_tx, and fr_a_tx_en driven by cc - connected to flexray channel b single channel device mode 1 00 ports fr_a_rx, fr_a_tx, and fr_a_tx_en not driven by cc ports fr_b_rx, fr_b_tx, and fr_a_tx_en not driven by cc 01 ports fr_a_rx, fr_a_tx, and fr_a_tx_en driven by cc - connected to flexray channel a ports fr_b_rx, fr_b_tx, and fr_a_tx_en not driven by cc 10 ports fr_a_rx, fr_a_tx, and fr_a_tx_en driven by cc - connected to flexray channel b ports fr_b_rx, fr_b_tx, and fr_a_tx_en not driven by cc 11reserved RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1475/1740 system memory base address register (fr_symbadr) note: the system memory base address must be set before the cc is enabled. the system memory base address registers define the base address of the flexray memory area within the system memory. the base address is used by the bmif to calculate the physical memory address for system memory accesses. strobe signal control register (fr_stbscr) this register is used to assign the individual protocol timing related strobe signals given in ta ble 79 4 to the external strobe ports. each strobe signal can be assigned to at most one strobe port. each write access to registers overwrites the previously written enb and stbpsel values for the signal indicated by sel. if more than one strobe signal is assigned to one strobe port, the current values of the strobe signals are combined with a binary or and presented at the strobe port. if no strobe signal is assigned to a strobe port, the strobe port carries logic 0. for more detailed and timing information refer to section 33.6.16, strobe signal support . figure 830. system memory base address high register (fr_symbadhr) base + 0x0004 write: disabled mode 0123456789101112131415 r smba[31:16] w reset0000000000000000 figure 831. system memory base address low register (fr_symbadlr) base + 0x0006 write: disabled mode 0123456789101112131415 r smba[15:4] 0000 w reset0000000000000000 table 792. fr_symbadr field description field description smba system memory base address ? this is the value of the system memory base address for the individual message buffers and sync frame table. this is the value of the system memory base address for the receive fifo if the fifo address mode bit fr_mcr[fam] is set to 1. it is defines as a byte address. figure 832. strobe signal control register (fr_stbscr) base + 0x0008 16-bit write access required write: anytime 0123456789101112131415 r0 0 0 0 sel 000 enb 00 stbpsel wwmd reset0000000000000000 flexray communication controller (flexray) RM0029 1476/1740 doc id 15177 rev 8 note: in single channel device mode, channel b related strobe signals are undefined and should not be assigned to the strobe ports. .; table 793. fr_stbscr field description field description wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel field only on write access. sel strobe signal select ? this control field selects one of the strobe signals given in table 794 to be enabled or disabled and assigned to one of the four strobe ports given in table 794 . enb strobe signal enable ? the control bit is used to enable and to disable the strobe signal selected by stbssel. 0 strobe signal is disabled and not assigned to any strobe port. 1 strobe signal is enabled and assigned to the strobe port selected by stbpsel. stbpsel strobe port select ? this field selects the strobe port that the strobe signal selected by the sel is assigned to. all strobe signals that are enabled and assigned to the same strobe port are combined with a binary or operation. 00 assign selected signal to fr_dbg[0] 01 assign selected signal to fr_dbg[1] 10 assign selected signal to fr_dbg[2] 11 assign selected signal to fr_dbg[3] table 794. strobe signal mapping sel description channel type offset (1) reference dec hex 0 0x0 arm ? value +1 mt start 1 0x1 mt ? value +1 mt start 2 0x2 cycle start ? pulse 0 mt start 3 0x3 minislot start ? pulse 0 mt start 40x4 slot start a pulse 0 mt start 50x5 b 60x6 receive data after glitch filtering a value +4 fr_a_rx 7 0x7 b fr_b_rx 80x8 channel idle indicator a level +5 fr_a_rx 9 0x9 b fr_b_rx 10 0xa syntax error detected a pulse +4 fr_a_rx 11 0xb b fr_b_rx 12 0xc content error detected a level +4 fr_a_rx 13 0xd b fr_b_rx RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1477/1740 message buffer data size register (fr_mbdsr) this register defines the size of the message buffer data section for the two message buffer segments in a number of two-byte entities. the cc provides two independent segments for the individual message buffers. all individual message buffers within one segment have to have the same size for the message buffer data section. this size can be different for the two message buffer segments. message buffer segment size and utilization register (fr_mbssutr) this register is used to define the last individual message buffer that belongs to the first message buffer segment and the number of the last used individual message buffer. 14 0xe receive fifo almost-full interrupt signals a value n.a. rx fifo a almost full interrupt 15 0xf b rx fifo b almost full interrupt 1. given in pe clock cycles table 794. strobe signal mapping sel description channel type offset (1) reference dec hex figure 833. message buffer data size register (fr_mbdsr) base + 0x000c write: poc:config 0123456789101112131415 r0 mbseg2ds 0 mbseg1ds w reset0000000000000000 table 795. fr_mbdsr field description field description mbseg2ds message buffer segment 2 data size ? the field defines the size of the message buffer data section in two-byte entities for message buffers within the second message buffer segment. mbseg1ds message buffer segment 1 data size ? the field defines the size of the message buffer data section in two-byte entities for message buffers within the first message buffer segment. figure 834. message buffer segment size and utilization register (fr_mbssutr) base + 0x000e write: poc:config 0123456789101112131415 r0 last_mb_seg1 0 last_mb_util w reset0111111101111111 flexray communication controller (flexray) RM0029 1478/1740 doc id 15177 rev 8 pe dram access register (fr_pedrar) this register is used to trigger write and read operations on the pe data memory (pe dram). these operations are used for memory error injection and memory error observation. each write access to this registers initiates a read or write operation on the pe dram. the access done status bit dad is cleared after the write access and is set if the pe dram access has been finished. in case of an pe dram write access, the data provided in pe dram data register (fr_pedrdr) are written into the pe dram, read back from the pe dram and are stored into the pe dram data register (fr_pedrdr) . in case of an pe dram read access, the requested data are read from pe dram and stored into the pe dram data register (fr_pedrdr) . for a detailed description refer to section 33.6.24, memory content error detection . table 796. fr_mbssutr field description field description last_mb_seg1 last message buffer in segment 1 ? this field defines the message buffer number of the last individual message buffer that is assigned to the first message buffer segment. the individual message buffers in the first segment correspond to the message buffer control registers fr_mbccsrn, fr_mbccfrn, fr_mbfidrn, fr_mbidxrn with n < last_mb_seg1. the first message buffer segment contains last_mb_seg1 + 1 individual message buffers. the first message buffer segment contains at least one individual message buffer. the individual message buffers in the second message buffer segment correspond to the message buffer control registers fr_mbccsrn, fr_mbccfrn, fr_mbfidrn, fr_mbidxrn with last_mb_seg1 < n < 128. if last_mb_seg1 = 127 all individual message buffers belong to the first message buffer segment and the second message buffer segment is empty. last_mb_util last message buffer utilized ? this field defines the message buffer number of last utilized individual message buffer. the message buffer search engine examines all individual message buffer with a message buffer number n < last_mb_util. if last_mb_util=last_mb_seg1 all individual message buffers belong to the first message buffer segment and the second message buffer segment is empty. figure 835. pe dram access register (fr_pedrar) base + 0x0010 16-bit write access required write: normal mode 0123456789101112131415 r inst addr dad w reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1479/1740 pe dram data register (fr_pedrdr) this register provides the data to be written to or read from the pe dram by the access initiated by write access to the pe dram access register (fr_pedrar) . protocol operation control register (fr_pocr) the application uses this register to issue protocol control commands external clock correction commands protocol control commands are issued by writing to the poccmd field. for more information on protocol control commands, see section 33.7.7, protocol control command execution . external clock correction commands are issued by writing to the eoc_ap and erc_ap fields. for more information on external clock correction, refer to section 33.6.11, external clock synchronization . table 797. fr_pedrar field description field description inst pe dram access instruction ? this field defines the operation to be executed on the pe dram. 0011 pe dram write: write fr_pedrdr[data] to pe dram address addr (16 bit) 0101 pe dram read: read data from pe dram address addr (16 bit) into fr_pedrdr[data] other reserved addr pe dram access address ? this field defines the address in the pe dram to be written to or read from. dad pe dram access done ? this status bit is cleared when the application has written to this register and is set when the pe dram access has finished. 0 pe dram access running 1 pe dram access done figure 836. pe dram data register (fr_pedrdr) base + 0x0012 16-bit write access required write: normal mode 0123456789101112131415 r data w reset0000000000000000 figure 837. protocol operation control register (fr_pocr) base + 0x0014 write: normal mode 0123456789101112131415 r0 0 0 0 eoc_ap erc_ap bsy 0 0 0 poccmd wwme wmc reset0000000000000000 flexray communication controller (flexray) RM0029 1480/1740 doc id 15177 rev 8 table 798. fr_pocr field description field description wme write mode external correction ? this bit controls the write mode of the eoc_ap and erc_ap fields. 0 write to eoc_ap and erc_ap fields on register write. 1 no write to eoc_ap and erc_ap fields on register write. eoc_ap external offset correction application ? this field is used to trigger the application of the external offset correction value defined in the protocol configuration register 29 (fr_pcr29) . 00 do not apply external offset correction value 01 reserved 10 subtract external offset correction value 11 add external offset correction value erc_ap external rate correction application ? this field is used to trigger application of the external rate correction value defined in the protocol configuration register 21 (fr_pcr21) 00 do not apply external rate correction value 01 reserved 10 subtract external rate correction value 11 add external rate correction value bsy wmc protocol control command write busy ? this status bit indicates the acceptance of the protocol control command issued by the application via the poccmd field. the cc sets this status bit when the application has issued a protocol control command via the poccmd field. the cc clears this status bit when protocol control command was accepted by the pe.when the application issues a protocol control command while the bsy bit is asserted, the cc ignores this command, sets the protocol command ignored error flag pcmi_ef in the chi error flag register (fr_chierfr) , and will not change the value of the poccmd field. 0command write idle, command accepted and ready to receive new protocol command. 1command write busy, command not yet accepted, not ready to receive new protocol command. write mode command ? this bit controls the write mode of the poccmd field. 0 write to poccmd field on register write. 1 do not write to poccmd field on register write. poccmd protocol control command ? the application writes to this field to issue a protocol control command to the pe. the cc sends the protocol command to the pe immediately. while the transfer is running, the bsy bit is set. 0000 allow_coldstart ? immediately activate capability of node to cold start cluster. 0001 all_slots ? delayed (1) transition to the all slots transmission mode. 0010 config ? immediately transition to the poc:config state. 0011 freeze ? immediately transition to the poc:halt state. 0100 ready, config_complete ? immediately transition to the poc:ready state. 0101 run ? immediately transition to the poc:startup start state. 0110 default_config ? immediately transition to the poc:default config state. 0111 halt ? delayed transition to the poc:halt state 1000 wakeup ? immediately initiate the wakeup procedure. 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved 1. delayed means on completion of current communication cycle. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1481/1740 global interrupt flag and enable register (fr_gifer) this register provides the means to control some of the interrupt request lines and provides the corresponding interrupt flags. the interrupt flags mif, prif, chif, rbif, and tbif are the outcome of a binary or of the related individual interrupt flags and interrupt enables. the generation scheme for these flags is depicted in figure 986 . for more details on interrupt generation, see section 33.6.20, interrupt support . these flags are cleared automatically when all of the corresponding interrupt flags or interrupt enables in the related interrupt flag and enable registers are cleared by the application. figure 838. global interrupt flag and enable register (fr_gifer) base + 0x0016 write: normal mode 0123456789101112131415 r mif prif chif wupif fafbif fafaif rbif tbif mie prie chie wupie fafbie fafa ie rbie tbie w w1c w1c w1c reset0000000000000000 table 799. fr_gifer field description field description mif module interrupt flag ? this flag is asserted if at least one of the other interrupt flags in this register and its related interrupt enable is asserted. 0 no interrupt flag is asserted or no interrupt enable is set 1 at least one of the other interrupt flags in this register is asserted and the related interrupt bit is asserted, too prif protocol interrupt flag ? this flag is set if at least one of the individual protocol interrupt flags in the protocol interrupt flag register 0 (fr_pifr0) and protocol interrupt flag register 1 (fr_pifr1) is asserted and the related interrupt enable flag is asserted. 0 all individual protocol interrupt flags are equal to 0 or no interrupt enable bit is set. 1 at least one of the individual protocol interrupt flags and the related interrupt enable is equal to 1. chif chi interrupt flag ? this flag is set if at least one of the individual chi error flags in the chi error flag register (fr_chierfr) is asserted and the chi error interrupt enable fr_gifer[chie] is asserted. 0 all chi error flags are equal to 0 or the chi error interrupt is disabled 1 at least one chi error flag is asserted and chi error interrupt is enabled wupif wakeup interrupt flag ? this flag is set when the cc has received a wakeup symbol on the flexray bus. the application can determine on which channel the wakeup symbol was received by reading the related wakeup flags wub and wua in the protocol status register 3 (fr_psr3) . 0 no wakeup condition or interrupt disabled 1 wakeup symbol received on flexray bus and interrupt enabled fafbif receive fifo channel b almost full interrupt flag ? this flag is set when one of the following events occurs a) the current number of fifo b entries is equal to or greater than the watermark defined by the wm field in the receive fifo watermark and selection register (fr_rfwmsr) , and the cc writes a received message into the fifo b, or b) the current number of fifo b entries is at least 1 and the periodic timer as defined by receive fifo periodic timer register (fr_rfptr) expires. 0 no such event 1 fifo b almost full event has occurred flexray communication controller (flexray) RM0029 1482/1740 doc id 15177 rev 8 fafaif receive fifo channel a almost full interrupt flag ? this flag is set when one of the following events occurs a) the current number of fifo a entries is equal to or greater than the watermark defined by the wm field in the receive fifo watermark and selection register (fr_rfwmsr) , and the cc writes a received message into the fifo a, or b) the current number of fifo b entries is at least 1 and the periodic timer as defined by receive fifo periodic timer register (fr_rfptr) expires. 0 no such event 1 fifo a almost full event has occurred rbif receive message buffer interrupt flag ? this flag is set if for at least one of the individual receive message buffers (fr_mbccsrn[mtd] = 0) both the interrupt flag mbif and the interrupt enable bit mbie in the corresponding message buffer configuration, control, status registers (fr_mbccsrn) are asserted. the application can not clear this rbif flag directly. this flag is cleared by the cc when all of the interrupt flags mbif of the individual receive message buffers are cleared by the application or if the application has cleared the interrupt enables bit mbie. 0 none of the individual receive message buffers has the mbif and mbie flag asserted. 1 at least one individual receive message buffer has the mbif and mbie flag asserted. tbif transmit message buffer interrupt flag ? this flag is set if for at least one of the individual single or double transmit message buffers (fr_mbccsrn[mtd] = 1) both the interrupt flag mbif and the interrupt enable bit mbie in the corresponding message buffer configuration, control, status registers (fr_mbccsrn) are equal to 1. the application can not clear this tbif flag directly. this flag is cleared by the cc when either all of the individual interrupt flags mbif of the individual transmit message buffers are cleared by the application or the host has cleared the interrupt enables bit mbie. 0 none of the individual transmit message buffers has the mbif and mbie flag asserted. 1 at least one individual transmit message buffer has the mbif and mbie flag asserted. mie module interrupt enable ? this flag controls if the module interrupt line is asserted when the mif flag is set. 0 disable interrupt line 1 enable interrupt line prie protocol interrupt enable ? this flag controls if the protocol interrupt line is asserted when the prif flag is set. 0 disable interrupt line 1 enable interrupt line chie chi interrupt enable ? this flag controls if the chi interrupt line is asserted when the chif flag is set. 0 disable interrupt line 1 enable interrupt line wupie wakeup interrupt enable ? this flag controls if the wakeup interrupt line is asserted when the wupif flag is set. 0 disable interrupt line 1 enable interrupt line fafbie receive fifo channel b almost full interrupt enable ? this flag controls if the rx fifo b almost full interrupt line is asserted when the fafbif flag is set. 0 disable interrupt line 1 enable interrupt line table 799. fr_gifer field description (continued) field description RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1483/1740 protocol interrupt flag register 0 (fr_pifr0) the register holds one set of the protocol-related individual interrupt flags. fafaie receive fifo channel a almost full interrupt enable ? this flag controls if the rx fifo a almost full interrupt line is asserted when the fafaif flag is set. 0 disable interrupt line 1 enable interrupt line rbie receive message buffer interrupt enable ? this flag controls if the receive message buffer interrupt line is asserted when the rbif flag is set. 0 disable interrupt line 1 enable interrupt line tbie transmit message buffer interrupt enable ? this flag controls if the transmit message buffer interrupt line is asserted when the tbif flag is set. 0 disable interrupt line 1 enable interrupt line table 799. fr_gifer field description (continued) field description figure 839. protocol interrupt flag register 0 (fr_pifr0) base + 0x0018 write: normal mode 0123456789101112131415 r fatl_if intl_if ilcf_if csa_if mrc_if moc_if ccl_if mxs_if mtx_if ltxb_if ltxa_if tbvb_if tbva_if ti2_if ti1_if cys_if w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 table 800. fr_pifr0 field description field description fatl_if fatal protocol error interrupt flag ? this flag is set when the protocol engine has detected a fatal protocol error. in this case, the protocol engine goes into the poc:halt state immediately. the fatal protocol errors are: 1) platesttx violation, as described in the mac process of the flexray protocol 2) transmission across slot boundary violation, as described in the fsp process of the flexray protocol 0 no such event. 1 fatal protocol error detected. intl_if internal protocol error interrupt flag ? this flag is set when the protocol engine has detected an internal protocol error. in this case, the protocol engine goes into the poc:halt state immediately. an internal protocol error occurs when the protocol engine has not finished a calculation and a new calculation is requested. this can be caused by a hardware error. 0 no such event. 1 internal protocol error detected. flexray communication controller (flexray) RM0029 1484/1740 doc id 15177 rev 8 ilcf_if illegal protocol configuration interrupt flag ? this flag is set when the protocol engine has detected an illegal protocol configuration parameter setting. in this case, the protocol engine goes into the poc:halt state immediately. the protocol engine checks the listen_timeout value programmed into the protocol configuration register 14 (fr_pcr14) and protocol configuration register 15 (fr_pcr15) when the config_complete command was sent by the application via the protocol operation control register (fr_pocr) . if the value of listen_timeout is equal to zero, the protocol configuration setting is considered as illegal. 0 no such event. 1 illegal protocol configuration detected. csa_if cold start abort interrupt flag ? this flag is set when the configured number of allowed cold start attempts is reached and none of these attempts was successful. the number of allowed cold start attempts is configured by the coldstart_attempts field in the protocol configuration register 3 (fr_pcr3) . 0 no such event. 1 cold start aborted and no more coldstart attempts allowed. mrc_if missing rate correction interrupt flag ? this flag is set when an insufficient number of measurements is available for rate correction at the end of the communication cycle. 0 no such event 1 insufficient number of measurements for rate correction detected moc_if missing offset correction interrupt flag ? this flag is set when an insufficient number of measurements is available for offset correction. this is related to the missing_term event in the csp process for offset correction in the flexray protocol. 0 no such event. 1 insufficient number of measurements for offset correction detected. ccl_if clock correction limit reached interrupt flag ? this flag is set when the internal calculated offset or rate calculation values have reached or exceeded its configured thresholds as given by the offset_coorection_out field in the protocol configuration register 9 (fr_pcr9) and the rate_correction_out field in the protocol configuration register 14 (fr_pcr14) . 0 no such event. 1 offset or rate correction limit reached. mxs_if max sync frames detected interrupt flag ? this flag is set when the number of synchronization frames detected in the current communication cycle exceeds the value of the node_sync_max field in the protocol configuration register 30 (fr_pcr30) . 0 no such event. 1 more than node_sync_max sync frames detected. only synchronization frames that have passed the synch ronization frame acceptance and rejection filters are taken into account. mtx_if media access test symbol received interrupt flag ? this flag is set when the mts symbol was received on channel a or channel b. 0 no such event. 1 mts symbol received. ltxb_if platesttx violation on channel b interrupt flag ? this flag is set when the frame transmission on channel b in the dynamic segment exceeds the dynamic segment boundary. this is related to the platesttx violation, as described in the mac process of the flexray protocol. 0 no such event. 1 platesttx violation occurred on channel b. table 800. fr_pifr0 field description (continued) field description RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1485/1740 protocol interrupt flag register 1 (fr_pifr1) the register holds one set of the protocol-related individual interrupt flags. ltxa_if platesttx violation on channel a interrupt flag ? this flag is set when the frame transmission on channel a in the dynamic segment exceeds the dynamic segment boundary. this is related to the platesttx violation as described in the mac process of the flexray protocol. 0 no such event. 1 platesttx violation occurred on channel a. tbvb_if transmission across boundary on channel b interrupt flag ? this flag is set when the frame transmission on channel b crosses the slot boundary. this is related to the transmission across slot boundary violation as described in the fsp process of the flexray protocol. 0 no such event. 1 transmission across boundary violation occurred on channel b. tbva_if transmission across boundary on channel a interrupt flag ? this flag is set when the frame transmission on channel a crosses the slot boundary. this is related to the transmission across slot boundary violation as described in the fsp process of the flexray protocol. 0 no such event. 1 transmission across boundary violation occurred on channel a. ti2_if timer 2 expired interrupt flag ? this flag is set whenever timer 2 expires. 0 no such event. 1 timer 2 has reached its time limit. ti1_if timer 1 expired interrupt flag ? this flag is set whenever timer 1 expires. 0 no such event 1 timer 1 has reached its time limit cys_if cycle start interrupt flag ? this flag is set when a communication cycle starts. 0 no such event 1 communication cycle started. table 800. fr_pifr0 field description (continued) field description figure 840. protocol interrupt flag register 1 (fr_pifr1) base + 0x001a write: normal mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r emc_if ipc_if pecf_if psc_if ssi3_if ssi2_if ssi1_if ssi0_if 00 evt_if odt_if 0000 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 flexray communication controller (flexray) RM0029 1486/1740 doc id 15177 rev 8 protocol interrupt enable register 0 (fr_pier0) this register defines whether or not the individual interrupt flags defined in the protocol interrupt flag register 0 (fr_pifr0) can generate a protocol interrupt request. table 801. fr_pifr1 field description field description emc_if error mode changed interrupt flag ? this flag is set when the value of the errmode bit field in the protocol status register 0 (fr_psr0) is changed by the cc. 0 no such event. 1 errmode field changed. ipc_if illegal protocol control command interrupt flag ? this flag is set when the pe tries to execute a protocol control command, which was issued via the poccmd field of the protocol operation control register (fr_pocr) , and detects that this protocol control command is not allowed in the current protocol state. in this case the command is not executed. for more details, see section 33.7.7, protocol control command execution . 0 no such event. 1 illegal protocol control command detected. pecf_if protocol engine communication failure interrupt flag ? this flag is set if the cc has detected a communication failure between the protocol engine and the cc host interface 0 no such event. 1 protocol engine communication failure detected. psc_if protocol state changed interrupt flag ? this flag is set when the protocol state in the protstate field in the protocol status register 0 (fr_psr0) has changed. 0 no such event. 1 protocol state changed. ssi3_if ssi2_if ssi1_if ssi0_if slot status counter incremented interrupt flag ? each of these flags is set when the slotstatuscnt field in the corresponding slot status counter registers (fr_sscr0? fr_sscr3) is incremented. 0 no such event. 1 the corresponding slot status counter has incremented. evt_if even cycle table written interrupt flag ? this flag is set if the cc has written the sync frame measurement / id tables into the flexray memory area for the even cycle. 0 no such event. 1 sync frame measurement table written odt_if odd cycle table written interrupt flag ? this flag is set if the cc has written the sync frame measurement / id tables into the flexray memory area for the odd cycle. 0 no such event. 1 sync frame measurement table written figure 841. protocol interrupt enable register 0 (fr_pier0) base + 0x001c write: anytime 0123456789101112131415 r fatl_ie intl_ie ilcf_ie csa_ie mrc_ie moc_ie ccl_ie mxs_ie mtx_ie ltxb_ie ltxa_ie tbvb_ie tbva_ie ti2_ie ti1_ie cys_ie w reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1487/1740 table 802. fr_pier0 field description field description fatl_ie fatal protocol error interrupt enable ? this bit controls fatl_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled intl_ie internal protocol error interrupt enable ? this bit controls intl_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ilcf_ie illegal protocol configuration interrupt enable ? this bit controls ilcf_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled csa_ie cold start abort interrupt enable ? this bit controls csa_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled mrc_ie missing rate correction interrupt enable ? this bit controls mrc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled moc_ie missing offset correction interrupt enable ? this bit controls moc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ccl_ie clock correction limit reached interrupt enable ? this bit controls ccl_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled mxs_ie max sync frames detected interrupt enable ? this bit controls mxs_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled mtx_ie media access test symbol received interrupt enable ? this bit controls mtx_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ltxb_ie platesttx violation on channel b interrupt enable ? this bit controls ltxb_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ltxa_ie platesttx violation on channel a interrupt enable ? this bit controls ltxa_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled tbvb_ie transmission across boundary on channel b interrupt enable ? this bit controls tbvb_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled flexray communication controller (flexray) RM0029 1488/1740 doc id 15177 rev 8 protocol interrupt enable register 1 (fr_pier1) this register defines whether or not the individual interrupt flags defined in protocol interrupt flag register 1 (fr_pifr1) can generate a protocol interrupt request. tbva_ie transmission across boundary on channel a interrupt enable ? this bit controls tbva_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ti2_ie timer 2 expired interrupt enable ? this bit controls ti1_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ti1_ie timer 1 expired interrupt enable ? this bit controls ti1_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled cys_ie cycle start interrupt enable ? this bit controls cyc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled table 802. fr_pier0 field description (continued) field description figure 842. protocol interrupt enable register 1 (fr_pier1) base + 0x001e write: anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r emc_ie ipc_ie pecf_ie psc_ie ssi3_ie ssi2_ie ssi1_ie ssi0_ie 00 evt_ie odt_ie 0000 w reset0000000000000000 table 803. fr_pier1 field description field description emc_ie error mode changed interrupt enable ? this bit controls emc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled ipc_ie illegal protocol control command interrupt enable ? this bit controls ipc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled pecf_ie protocol engine communication failure interrupt enable ? this bit controls pecf_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled psc_ie protocol state changed interrupt enable ? this bit controls psc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1489/1740 chi error flag register (fr_chierfr) this register holds the chi related error flags. the interrupt generation for each of these error flags is controlled by the chi interrupt enable bit chie in the global interrupt flag and enable register (fr_gifer) . ssi3_ie ssi2_ie ssi1_ie ssi0_ie slot status counter incremented interrupt enable ? this bit controls ssi[3:0]_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled evt_ie even cycle table written interrupt enable ? this bit controls evt_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled odt_ie odd cycle table written interrupt enable ? this bit controls odt_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled table 803. fr_pier1 field description field description figure 843. chi error flag register (fr_chierfr) base + 0x0020 write: normal mode 0123456789101112131415 r frlb_ef frla_ef pcmi_ef fovb_ef fova_ef mbs_ef mbu_ef lck_ef dbl_ef sbcf_ef (1) fid_ef dpl_ef spl_ef nml_ef nmf_ef ilsa_ef 1 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 1. the flexray controller should be stopped via a freeze or halt command and subsequently restarted when any of the error flags chierfr[sbcf_ef] or chierfr[ilsa_ef] is set. table 804. fr_chierfr field description field description frlb_ef frame lost channel b error flag ? this flag is set if a complete frame was received on channel b but could not be stored in the selected individual message buffer because this message buffer is currently locked by the application. in this case, the frame and the related slot status information are lost. 0 no such event 1 frame lost on channel b detected frla_ef frame lost channel a error flag ? this flag is set if a complete frame was received on channel a but could not be stored in the selected individual message buffer because this message buffer is currently locked by the application. in this case, the frame and the related slot status information are lost. 0 no such error 1 frame lost on channel a detected flexray communication controller (flexray) RM0029 1490/1740 doc id 15177 rev 8 pcmi_ef protocol command ignored error flag ? this flag is set if the application has issued a poc command by writing to the poccmd field in the protocol operation control register (fr_pocr) while the bsy flag is equal to 1. in this case the command is ignored by the cc and is lost. 0 no such error 1 poc command ignored fovb_ef receive fifo overrun channel b error flag ? this flag is set when an overrun of the fifo for channel b occurred. this error occurs if a semantically valid frame was received on channel b and matches the all criteria to be appended to the fifo for channel b but the fifo is full. in this case, the received frame and its related slot status information is lost. 0 no such error 1 fifo overrun on channel b has been detected fova_ef receive fifo overrun channel a error flag ? this flag is set when an overrun of the fifo for channel a occurred. this error occurs if a semantically valid frame was received on channel a and matches the all criteria to be appended to the fifo for channel a but the fifo is full. in this case, the received frame and its related slot status information is lost. 0 no such error 1 fifo overrun on channel b has been detected msb_ef message buffer search error flag ? this flag is set if the message buffer search engine is still running while the next search cycle must be started due to the flexray protocol timing. in this case, not all message buffers are considered while searching. 0 no such event 1 search engine active while search start appears mbu_ef message buffer utilization error flag ? this flag is asserted if the application writes to a message buffer control field that is beyond the number of utilized message buffers programmed in the message buffer segment size and utilization register (fr_mbssutr) . if the application writes to a fr_mbccsrn register with n > last_mb_util, the cc ignores the write attempt and asserts the message buffer utilization error flag mbu_ef in the chi error flag register (fr_chierfr) . 0 no such event 1 non-utilized message buffer enabled lck_ef lock error flag ? this flag is set if the application tries to lock a message buffer that is already locked by the cc due to internal operations. in that case, the cc does not grant the lock to the application. the application must issue the lock request again. 0 no such error 1 lock error detected dbl_ef double transmit message buffer lock error flag ? this flag is set if the application tries to lock the transmit side of a double transmit message buffer. in this case, the cc does not grant the lock to the transmit side of a double transmit message buffer. 0 no such event 1 double transmit buffer lock error occurred sbcf_ef system bus communication failure error flag ? this flag is set if a system bus access was not finished within the required amount of time (see section , system bus access timeout ). 0 no such event 1 system bus access not finished in time table 804. fr_chierfr fiel d description (continued) field description RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1491/1740 message buffer interrupt vector register (fr_mbivec) fid_ef frame id error flag ? this flag is set if the frame id stored in the message buffer header area differs from the frame id stored in the message buffer control register. 0 no such error occurred 1 frame id error occurred dpl_ef dynamic payload length error flag ? this flag is set if the payload length written into the message buffer header field of a single or double transmit message buffer assigned to the dynamic segment is greater than the maximum payload length for the dynamic segment as it is configured in the corresponding protocol configuration register field max_payload_length_dynamic in the protocol configuration register 24 (fr_pcr24) . 0 no such error occurred 1 dynamic payload length error occurred spl_ef static payload length error flag ? this flag is set if the payload length written into the message buffer header field of a single or double transmit message buffer assigned to the static segment is different from the payload length for the static segment as it is configured in the corresponding protocol configuration register field payload_length_static in the protocol configuration register 19 (fr_pcr19) . 0 no such error occurred 1 static payload length error occurred nml_ef network management length error flag ? this flag is set if the payload length written into the header structure of a receive message buffer assigned to the static segment is less than the configured length of the network management vector as configured in the network management vector length register (fr_nmvlr) . in this case the received part of the network management vector will be used to update the network management vector. 0 no such error occurred 1 network management length error occurred nmf_ef network management frame error flag ? this flag is set if a received message in the static segment with a preamble indicator flag pp asserted has its null frame indicator flag nf asserted as well. in this case, the global network management registers (see network management vector registers (fr_nmvr0?fr_nmvr5) ) are not updated. 0 no such error occurred 1 network management frame error occurred ilsa_ef illegal system bus address error flag ? this flag is set if the external system bus subsystem has detected an access to an illegal system bus address from the cc (see section , system bus illegal address access ). 0 no such event 1 illegal system bus address accessed table 804. fr_chierfr fiel d description (continued) field description figure 844. message buffer interrupt vector register (fr_mbivec) base + 0x0022 0123456789101112131415 r 0 tbivec 0 rbivec w reset0000000000000000 flexray communication controller (flexray) RM0029 1492/1740 doc id 15177 rev 8 this register indicates the lowest numbered receive message buffer and the lowest numbered transmit message buffer that have their interrupt status flag mbif and interrupt enable mbie bits asserted. this means that message buffers with lower message buffer numbers have higher priority. channel a status error counter register (fr_casercr) this register provides the channel status error counter for channel a. the protocol engine generates a slot status vector for each static slot, each dynamic slot, the symbol window, and the nit. the slot status vector contains the four protocol related error indicator bits vss!syntaxerror, vss!contenterror, vss!bviolation , and vss!txconflict . the cc increments the status error counter by 1 if, for a slot or segment, at least one error indicator bit is set to 1. the counter wraps around after it has reached the maximum value. for more information on slot status monitoring, see section 33.6.18, slot status monitoring . channel b status error counter register (fr_cbsercr) table 805. fr_mbivec field description field description tbivec transmit buffer interrupt vector ? this field provides the number of the lowest numbered enabled transmit message buffer that has its interrupt status flag mbif and its interrupt enable bit mbie set. if there is no transmit message buffer with the interrupt status flag mbif and the interrupt enable mbie bits asserted, the value in this field is set to 0. rbivec receive buffer interrupt vector ? this field provides the message buffer number of the lowest numbered receive message buffer which has its interrupt flag mbif and its interrupt enable bit mbie asserted. if there is no receive message buffer with the interrupt status flag mbif and the interrupt enable mbie bits asserted, the value in this field is set to 0. figure 845. channel a status error counter register (fr_casercr) base + 0x0024 a dditional reset: run command 0123456789101112131415 r status_err_cnt w reset0000000000000000 table 806. fr_casercr field description field description status_err_cnt channel status error counter ? this field provides the current value channel status error counter. the counter value is updated within the first macrotick of the following slot or segment. figure 846. channel b status error counter register (fr_cbsercr) base + 0x0026 additional reset: run command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r status_err_cnt w reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1493/1740 this register provides the channel status error counter for channel b. the protocol engine generates a slot status vector for each static slot, each dynamic slot, the symbol window, and the nit. the slot status vector contains the four protocol related error indicator bits vss!syntaxerror , vss!contenterror , vss!bviolation , and vss!txconflict . the cc increments the status error counter by 1 if, for a slot or segment, at least one error indicator bit is set to 1. the counter wraps around after it has reached the maximum value. for more information on slot status monitoring see section 33.6.18, slot status monitoring . protocol status register 0 (fr_psr0) this register provides information about the current protocol status. table 807. fr_cbsercr field description field description status_err_cnt channel status error counter ? this field provides the current channel status error count. the counter value is updated within the first macrotick of the following slot or segment. figure 847. protocol status register 0 (fr_psr0) base + 0x0028 01 2 3 456789101112131415 r errmode slotmode 0 protstate startupstate 0 wakeupstatus w reset00 0 0 000000000000 table 808. fr_psr0 field description field description errmode error mode ? protocol related variable: vpoc!errormode . this field indicates the error mode of the protocol. 00 active 01 passive 10 comm_halt 11 reserved slotmode slot mode ? protocol related variable: vpoc!slotmode . this field indicates the slot mode of the protocol. 00 single 01 all_pending 10 all 11 reserved protstate protocol state ? protocol related variable: vpoc!state. this field indicates the state of the protocol. 000 poc:default config 001 poc:config 010 poc:wakeup 011 poc:ready 100 poc:normal passive 101 poc:normal active 110 poc:halt 111 poc:startup flexray communication controller (flexray) RM0029 1494/1740 doc id 15177 rev 8 protocol status register 1 (fr_psr1) startup state startup state ? protocol related variable: vpoc!startupstate. this field indicates the current substate of the startup procedure. 0000 reserved 0001 reserved 0010 poc:coldstart collision resolution 0011 poc:coldstart listen 0100 poc:integration consistency check 0101 poc:integrationi listen 0110 reserved 0111 poc:initialize schedule 1000 reserved 1001 reserved 1010 poc:coldstart consistency check 1011 reserved 1100 reserved 1101 poc:integration coldstart check 1110 poc:coldstart gap 1111 poc:coldstart join wakeup status wakeup status ? protocol related variable: vpoc!wakeupstatus . this field provides the outcome of the execution of the wakeup mechanism. 000 undefined 001 received_header 010 received_wup 011 collision_header 100 collision_wup 101 collision_unknown 110 transmitted 111 reserved table 808. fr_psr0 field description (continued) field description figure 848. protocol status register 1 (fr_psr1) base + 0x002a additional reset: csaa, csp, cpn: run command write: normal mode 0123456789101112131415 r csaa csp 0remcsat cpn hhr frz aptac ww1c reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1495/1740 protocol status register 2 (fr_psr2) this register provides a snapshot of status information about the network idle time nit, the symbol window and the clock synchronization. the nit related status bits nbvb, nseb, table 809. fr_psr1 field description field description csaa cold start attempt aborted flag ? protocol related event: ?set coldstart abort indicator in chi? this flag is set when the cc has aborted a cold start attempt. 0 no such event 1 cold start attempt aborted csp leading cold start path ? this status bit is set when the cc has reached the poc:normal active state via the leading cold start path. this indicates that this node has started the network 0 no such event 1 poc:normal active reached from poc:startup state via leading cold start path remcsat remaining coldstart attempts ? protocol related variable: vremainingcoldstartattempts this field provides the number of remaining cold start attempts that the cc will execute. cpn leading cold start path noise ? protocol related variable: vpoc!coldstartnoise this status bit is set if the cc has reached the poc:normal active state via the leading cold start path under noise conditions. this indicates there was some activity on the flexray bus while the cc was starting up the cluster. 0 no such event 1 poc:normal active state was reached from poc:startup state via noisy leading cold start path hhr host halt request pending ? protocol related variable: vpoc!chihaltrequest this status bit is set when cc receives the halt command from the application via the protocol operation control register (fr_pocr) . the cc clears this status bit after a hard reset condition or when the protocol is in the poc:default config state. 0 no such event 1 halt command received frz freeze occurred ? protocol related variable: vpoc!freeze this status bit is set when the cc has reached the poc:halt state due to the host freeze command or due to an internal error condition requiring immediate halt. the cc clears this status bit after a hard reset condition or when the protocol is in the poc:default config state. 0 no such event 1 immediate halt due to freeze or internal error condition aptac allow passive to active counter ? protocol related variable: vpoc!vallowpassivetoactive this field provides the number of consecutive even/odd communication cycle pairs that have passed with valid rate and offset correction terms, but the protocol is still in the poc:normal passive state due to an application configured delay to enter poc:normal active state. this delay is defined by the allow_passive_to_active field in the protocol configuration register 12 (fr_pcr12) . figure 849. protocol status register 2 (fr_psr2) base + 0x002c additional reset: run command 0123456789101112131415 r nbvb nseb stcb sbvb sseb mtb nbva nsea stca sbva ssea mta clkcorrfailcnt w reset0000000000000000 flexray communication controller (flexray) RM0029 1496/1740 doc id 15177 rev 8 nbva, and nsea are updated by the cc after the end of the nit and before the end of the first slot of the next communication cycle. the symbol window related status bits stcb, sbvb, sseb, mtb, stca, sbva, sseb, and mta are updated by the cc after the end of the symbol window and before the end of the current communication cycle. if no symbol window is configured, the symbol window related status bits remain in their reset state. the clock synchronization related clkcorrfailcnt is updated by the cc after the end of the static segment and before the end of the current communication cycle. table 810. fr_psr2 field description field description nbvb nit boundary violation on channel b ? protocol related variable: vss!bviolation for nit on channel b this status bit is set when there was some media activity on the flexray bus channel b at the end of the nit. 0 no such event 1 media activity at boundaries detected nseb nit syntax error on channel b ? protocol related variable: vss!syntaxerror for nit on channel b this status bit is set when a syntax error was detected during nit on channel b. 0 no such event 1 syntax error detected stcb symbol window transmit conflict on channel b ? protocol related variable: vss!txconflict for symbol window on channel b this status bit is set if there was a transmission conflict during the symbol window on channel b. 0 no such event 1 transmission conflict detected sbvb symbol window boundary violation on channel b ? protocol related variable: vss!bviolation for symbol window on channel b this status bit is set if there was some media activity on the flexray bus channel b at the start or at the end of the symbol window. 0 no such event 1 media activity at boundaries detected sseb symbol window syntax error on channel b ? protocol related variable: vss!syntaxerror for symbol window on channel b this status bit is set when a syntax error was detected during the symbol window on channel b. 0 no such event 1 syntax error detected mtb media access test symbol mts received on channel b ? protocol related variable: vss!validmts for symbol window on channel b this status bit is set if the media access test symbol mts was received in the symbol window on channel b. 0 no such event 1 mts symbol received nbva nit boundary violation on channel a ? protocol related variable: vss!bviolation for nit on channel a this status bit is set when there was some media activity on the flexray bus channel a at the end of the nit. 0 no such event 1 media activity at boundaries detected RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1497/1740 protocol status register 3 (fr_psr3) this register provides aggregated channel status information as an accrued status of channel activity for all communication slots, regardless of whether they are assigned for nsea nit syntax error on channel a ? protocol related variable: vss!syntaxerror for nit on channel a this status bit is set when a syntax error was detected during nit on channel a. 0 no such event 1 syntax error detected stca symbol window transmit conflict on channel a ? protocol related variable: vss!txconflict for symbol window on channel a this status bit is set if there was a transmission conflicts during the symbol window on channel a. 0 no such event 1 transmission conflict detected sbva symbol window boundary violation on channel a ? protocol related variable: vss!bviolation for symbol window on channel a this status bit is set if there was some media activity on the flexray bus channel a at the start or at the end of the symbol window. 0 no such event 1 media activity at boundaries detected ssea symbol window syntax error on channel a ? protocol related variable: vss!syntaxerror for symbol window on channel a this status bit is set when a syntax error was detected during the symbol window on channel a. 0 no such event 1 syntax error detected mta media access test symbol mts received on channel a ? protocol related variable: vss!validmts for symbol window on channel a this status bit is set if the media access test symbol mts was received in the symbol window on channel a. 1 mts symbol received 0 no such event clkcorr- failcnt clock correction failed counter ? protocol related variable: vclockcorrectionfailed this field provides the number of consecutive even/odd communication cycle pairs that have passed without clock synchronization having performed an offset or a rate correction due to lack of synchronization frames. it is not incremented when it has reached the configured value of either max_without_clock_correction_fatal or max_without_clock_correction_passive as defined in the protocol configuration register 8 (fr_pcr8) . the cc resets this counter on a hard reset condition, when the protocol enters the poc:normal active state, or when both the rate and offset correction terms have been calculated successfully. table 810. fr_psr2 field description (continued) field description figure 850. protocol status register 3 (fr_psr3) base + 0x002e additional reset: run command write: normal mode 0123456789101112131415 r0 0 wub abvb aacb aceb aseb avfb 00 wua abva aaca acea asea avfa w w1cw1cw1cw1cw1cw1c w1cw1cw1cw1cw1cw1c reset0000000000000000 flexray communication controller (flexray) RM0029 1498/1740 doc id 15177 rev 8 transmission or subscribed for reception. it provides accrued information for the symbol window, the nit, and the wakeup status. table 811. fr_psr3 field description field description wub wakeup symbol received on channel b ? this flag is set when a wakeup symbol was received on channel b. 0 no wakeup symbol received 1 wakeup symbol received abvb aggregated boundary violation on channel b ? this flag is set when a boundary violation has been detected on channel b. boundary violations are detected in the communication slots, the symbol window, and the nit. 0 no boundary violation detected 1 boundary violation detected aacb aggregated additional communication on channel b ? this flag is set when at least one valid frame was received on channel b in a slot that also contained an additional communication with either syntax error, content error, or boundary violations. 0 no additional communication detected 1 additional communication detected aceb aggregated content error on channel b ? this flag is set when a content error has been detected on channel b. content errors are detected in the communication slots, the symbol window, and the nit. 0 no content error detected 1 content error detected aseb aggregated syntax error on channel b ? this flag is set when a syntax error has been detected on channel b. syntax errors are detected in the communication slots, the symbol window and the nit. 0 no syntax error detected 1 syntax errors detected avfb aggregated valid frame on channel b ? this flag is set when a syntactically correct valid frame has been received in any static or dynamic slot through channel b. 1 at least one syntactically valid frame received 0 no syntactically valid frames received wua wakeup symbol received on channel a ? this flag is set when a wakeup symbol was received on channel a. 0 no wakeup symbol received 1 wakeup symbol received abva aggregated boundary violation on channel a ? this flag is set when a boundary violation has been detected on channel a. boundary violations are detected in the communication slots, the symbol window, and the nit. 0 no boundary violation detected 1 boundary violation detected aaca aggregated additional communication on channel a ? this flag is set when a valid frame was received in a slot on channel a that also contained an additional communication with either syntax error, content error, or boundary violations. 0 no additional communication detected 1 additional communication detected RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1499/1740 macrotick counter register (fr_mtctr) this register provides the macrotick count of the current communication cycle. cycle counter register (fr_cyctr) this register provides the number of the current communication cycle. acea aggregated content error on channel a ? this flag is set when a content error has been detected on channel a. content errors are detected in the communication slots, the symbol window, and the nit. 0 no content error detected 1 content error detected asea aggregated syntax error on channel a ? this flag is set when a syntax error has been detected on channel a. syntax errors are detected in the communication slots, the symbol window, and the nit. 0 no syntax error detected 1 syntax errors detected avfa aggregated valid frame on channel a ? this flag is set when a syntactically correct valid frame has been received in any static or dynamic slot through channel a. 0 no syntactically valid frames received 1 at least one syntactically valid frame received table 811. fr_psr3 field description (continued) field description figure 851. macrotick counter register (fr_mtctr) base + 0x0030 0123456789101112131415 r0 0 mtct w reset0000000000000000 table 812. fr_mtctr field description field description mtct macrotick counter ? protocol related variable: vmacrotick this field provides the macrotick count of the current communication cycle. figure 852. cycle counter register (fr_cyctr) base + 0x0032 0123456789101112131415 r 0 0 0 0 0 0 0 0 0 0 cyccnt w reset0000000000000000 flexray communication controller (flexray) RM0029 1500/1740 doc id 15177 rev 8 slot counter channel a register (fr_sltctar) this register provides the number of the current slot in the current communication cycle for channel a. slot counter channel b register (fr_sltctbr) this register provides the number of the current slot in the current communication cycle for channel b. table 813. fr_cyctr field description field description cyccnt cycle counter ? protocol related variable: vcyclecounter this field provides the number of the current communication cycle. if the counter reaches the maximum value of 63, the counter wraps and starts from zero again. figure 853. slot counter channel a register (fr_sltctar) base + 0x0034 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r00000 slotcnta w reset0000000000000000 table 814. fr_sltctar field description field description slotcnta slot counter value for channel a ? protocol related variable: vslotcounter for channel a this field provides the number of the current slot in the current communication cycle. figure 854. slot counter channel b register (fr_sltctbr) base + 0x0036 0123456789101112131415 r00000 slotcntb w reset0000000000000000 table 815. fr_sltctbr field description field description slotcnta slot counter value for channel b ? protocol related variable: vslotcounter for channel b this field provides the number of the current slot in the current communication cycle. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1501/1740 rate correction value register (fr_rtcorvr) this register provides the sign extended rate correction value in microticks as it was calculated by the clock synchronization algorithm. the cc updates this register during the nit of each odd numbered communication cycle. offset correction value register (fr_ofcorvr) this register provides the sign extended offset correction value in microticks as it was calculated by the clock synchronization algorithm. the cc updates this register during the nit. figure 855. rate correction value register (fr_rtcorvr) base + 0x0038 additional reset: run command 0123456789101112131415 rratecorr w reset0000000000000000 table 816. fr_rtcorvr field description field description ratecorr rate correction value ? protocol related variable: vratecorrection (before value limitation and external rate correction) this field provides the sign extended rate correction value in microticks as it was calculated by the clock synchronization algorithm. the value is represented in 2?s complement format. this value does not include the value limitation and the application of the external rate correction. if the magnitude of the internally calculated rate correction value exceeds the limit given by rate_correction_out in the protocol configuration register 13 (fr_pcr13) , the clock correction reached limit interrupt flag ccl_if is set in the protocol interrupt flag register 0 (fr_pifr0) . if the cc was not able to calculate a new rate correction term due to a lack of synchronization frames, the ratecorr value is not updated. figure 856. offset correction value register (fr_ofcorvr) base + 0x003a additional reset: run command 0123456789101112131415 r offsetcorr w reset0000000000000000 flexray communication controller (flexray) RM0029 1502/1740 doc id 15177 rev 8 combined interrupt flag register (fr_cifr) this register provides five combined interrupt flags and a copy of three individual interrupt flags. the combined interrupt flags are the result of a binary or of the values of other interrupt flags regardless of the state of the interrupt enable bits. the generation scheme for the combined interrupt flags is depicted in figure 988 . the individual interrupt flags wupif, fafbif, and fafaif are copies of corresponding flags in the global interrupt flag and enable register (fr_gifer) and are provided here to simplify the application interrupt flag check. to clear the individual interrupt flags, the application must use the global interrupt flag and enable register (fr_gifer) . note: the meanings of the combined status bits mif, prif, chif, rbif, and tbif are different from those mentioned in the global interrupt flag and enable register (fr_gifer) . table 817. fr_ofcorvr field description field description offsetcorr offset correction value ? protocol related variable: voffsetcorrection (before value limitation and external offset correction) this field provides the sign extended offset correction value in microticks as it was calculated by the clock synchronization algorithm. the value is represented in 2?s complement format. this value does not include the value limitation and the application of the external offset correction. if the magnitude of the internally calculated rate correction value exceeds the limit given by offset_correction_out field in the protocol configuration register 29 (fr_pcr29) , the clock correction reached limit interrupt flag ccl_if is set in the protocol interrupt flag register 0 (fr_pifr0) . if the cc was not able to calculate an new offset correction term due to a lack of synchronization frames, the offsetcorr value is not updated. figure 857. combined interrupt flag register (fr_cifr) base + 0x003c 0123456789101112131415 r00000000 mif prif chif wupif fafbif fafaif rbif tbif w reset0000000000000000 table 818. fr_cifr field description field description mif module interrupt flag ? this flag is set if there is at least one interrupt source that has its interrupt flag asserted. 0 no interrupt source has its interrupt flag asserted 1 at least one interrupt source has its interrupt flag asserted prif protocol interrupt flag ? this flag is set if at least one of the individual protocol interrupt flags in the protocol interrupt flag register 0 (fr_pifr0) or protocol interrupt flag register 1 (fr_pifr1) is equal to 1. 0 all individual protocol interrupt flags are equal to 0 1 at least one of the individual protocol interrupt flags is equal to 1 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1503/1740 system memory access time-out register (fr_symator) chif chi interrupt flag ? this flag is set if at least one of the individual chi error flags in the chi error flag register (fr_chierfr) is equal to 1. 0 all chi error flags are equal to 0 1 at least one chi error flag is equal to 1 wupif wakeup interrupt flag ? provides the same value as fr_gifer[wupif] fafbif receive fifo channel b almost full interrupt flag ? provides the same value as fr_gifer[fafbif] fafaif receive fifo channel a almost full interrupt flag ? provides the same value as fr_gifer[fafaif] rbif receive message buffer interrupt flag ? this flag is set if for at least one of the individual receive message buffers (fr_mbccsrn[mtd] = 0) the interrupt flag mbif in the corresponding message buffer configuration, control, status registers (fr_mbccsrn) is equal to 1. 0 none of the individual receive message buffers has the mbif flag asserted. 1 at least one individual receive message buffers has the mbif flag asserted. tbif transmit message buffer interrupt flag ? this flag is set if for at least one of the individual single or double transmit message buffers (fr_mbccsrn[mtd] = 1) the interrupt flag mbif in the corresponding message buffer configuration, control, status registers (fr_mbccsrn) is equal to 1. 0 none of the individual transmit message buffers has the mbif flag asserted. 1 at least one individual transmit message buffers has the mbif flag asserted. table 818. fr_cifr field description (continued) field description figure 858. system memory access time-out register (fr_symator) base + 0x003e write: disabled mode 0123456789101112131415 r00000000 timeout w reset0000000000000110 table 819. fr_symator field description field description timeout system memory access time-out ? this value defines when a system bus access timeout is detected. for a detailed description see section , configure system memory access time-out register (fr_symator) and section , system bus access timeout . flexray communication controller (flexray) RM0029 1504/1740 doc id 15177 rev 8 sync frame counter register (fr_sfcntr) this register provides the number of synchronization frames that are used for clock synchronization in the last even and in the last odd numbered communication cycle. this register is updated after the start of the nit and before 10 mt after offset correction start. note: if the application has locked the even synchronization table at the end of the static segment of an even communication cycle, the cc will not update the fields sfevb and sfeva. if the application has locked the odd synchronization table at the end of the static segment of an odd communication cycle, the cc will not update the values sfodb and sfoda. sync frame table offset register (fr_sftor) this register defines the flexray memory area related offset for sync frame tables. for more details, see section 33.6.12, sync frame id and sync frame deviation tables . figure 859. sync frame counter register (fr_sfcntr) base + 0x0040 additional reset: run command 0123456789101112131415 r sfevb sfeva sfodb sfoda w reset0000000000000000 table 820. fr_sfcntr field description field description sfevb sync frames channel b, even cycle ? protocol related variable: size of ( vssyncidlistb for even cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. sfevb sync frames channel a, even cycle ? protocol related variable: size of ( vssyncidlista for even cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. sfodb sync frames channel b, odd cycle ? protocol related variable: size of ( vssyncidlistb for odd cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. sfoda sync frames channel a, odd cycle ? protocol related variable: size of ( vssyncidlista for odd cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. figure 860. sync frame table offset register (fr_sftor) base + 0x0042 write: poc:config 0123456789101112131415 r sft_offset[15:1] 0 w reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1505/1740 sync frame table configuration, control, status register (fr_sftccsr) this register provides configuration, control, and status information related to the generation and access of the clock sync id tables and clock sync measurement tables. for a detailed description, see section 33.6.12, sync frame id and sync frame deviation tables . table 821. fr_sftor field description field description sft_offset sync frame table offset ? the offset of the sync frame tables in the flexray memory area. this offset is required to be 16-bit aligned. thus stf_offset[0] is always 0. figure 861. sync frame table configuration, control, status register (fr_sftccsr) base + 0x0044 write: normal mode 0123456789101112131415 r 0 0 cycnum elks olks eval oval 00 sdven siden w elkt olkt opt reset0000000000000000 table 822. fr_sftccsr field description field description elkt even cycle tables lock/unlock trigger ? this trigger bit is used to lock and unlock the even cycle tables. 0no effect 1 triggers lock/unlock of the even cycle tables. olkt odd cycle tables lock/unlock trigger ? this trigger bit is used to lock and unlock the odd cycle tables. 0no effect 1 triggers lock/unlock of the odd cycle tables. cycnum cycle number ? this field provides the number of the cycle in which the currently locked table was recorded. if none or both tables are locked, this value is related to the even cycle table. elks even cycle tables lock status ? this status bit indicates whether the application has locked the even cycle tables. 0 application has not locked the even cycle tables. 1 application has locked the even cycle tables. olks odd cycle tables lock status ? this status bit indicates whether the application has locked the odd cycle tables. 0 application has not locked the odd cycle tables. 1 application has locked the odd cycle tables. eval even cycle tables valid ? this status bit indicates whether the sync frame id and sync frame deviation tables for the even cycle are valid. the cc clears this status bit when it starts updating the tables, and sets this bit when it has finished the table update. 0 tables are not valid (update is ongoing) 1 tables are valid (consistent). flexray communication controller (flexray) RM0029 1506/1740 doc id 15177 rev 8 sync frame id rejection filter register (fr_sfidrfr) this register defines the sync frame rejection filter id. the application must update this register outside of the static segment. if the application updates this register in the static segment, it can appear that the cc accepts the sync frame in the current cycle. oval odd cycle tables valid ? this status bit indicates whether the sync frame id and sync frame deviation tables for the odd cycle are valid. the cc clears this status bit when it starts updating the tables, and sets this bit when it has finished the table update. 0 tables are not valid (update is ongoing) 1 tables are valid (consistent). opt one pair trigger ? this trigger bit controls whether the cc writes continuously or only one pair of sync frame tables into the flexray memory area. if this trigger is set to 1 while sdven or siden is set to 1, the cc writes only one pair of the enabled sync frame tables corresponding to the next even-odd-cycle pair into the flexray memory area. in this case, the cc clears the sdven or siden bits immediately. if this trigger is set to 0 while sdven or siden is set to 1, the cc writes continuously the enabled sync frame tables into the flexray memory area. 0 write continuously pairs of enabled sync frame tables into flexray memory area. 1 write only one pair of enabled sync frame tables into flexray memory area. sdven sync frame deviation table enable ? this bit controls the generation of the sync frame deviation tables. the application must set this bit to request the cc to write the sync frame deviation tables into the flexray memory area. 0 do not write sync frame deviation tables 1 write sync frame deviation tables into flexray memory area if sdven is set to 1, then siden must also be set to 1. siden sync frame id table enable ? this bit controls the generation of the sync frame id tables. the application must set this bit to 1 to request the cc to write the sync frame id tables into the flexray memory area. 0 do not write sync frame id tables 1 write sync frame id tables into flexray memory area table 822. fr_sftccsr field description (continued) field description figure 862. sync frame id rejection filter register (fr_sfidrfr) base + 0x0046 16-bit write access required write: normal mode 0123456789101112131415 r000000 synfrid w reset0000000000000000 table 823. fr_sfidrfr field description field description synfrid sync frame rejection id ? this field defines the frame id of a frame that must not be used for clock synchronization. for details see section , sync frame rejection filtering . RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1507/1740 sync frame id acceptance filter value register (fr_sfidafvr) this register defines the sync frame acceptance filter value. for details on filtering, see section 33.6.15, sync frame filtering . sync frame id acceptance filter mask register (fr_sfidafmr) this register defines the sync frame acceptance filter mask. for details on filtering see section , sync frame acceptance filtering . network management vector registers (fr_nmvr0?fr_nmvr5) figure 863. sync frame id acceptance filter value register (fr_sfidafvr) base + 0x0048 write: poc:config 0123456789101112131415 r000000 fval w reset0000000000000000 table 824. fr_sfidafvr field description field description fval filter value ? this field defines the value for the sync frame acceptance filtering. figure 864. sync frame id acceptance filter mask register (fr_sfidafmr) base + 0x004a write: poc:config 0123456789101112131415 r000000 fmsk w reset0000000000000000 table 825. fr_sfidafmr field description field description fmsk filter mask ? this field defines the mask for the sync frame acceptance filtering. figure 865. network management vector registers (fr_nmvr0?fr_nmvr5) base + 0x004c (fr_nmvr0) base + 0x004e (fr_nmvr1) base + 0x0050 (fr_nmvr2) base + 0x0052 (fr_nmvr3) base + 0x0054 (fr_nmvr4) base + 0x0056 (fr_nmvr5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r nmvp[15:8] nmvp[7:0] w reset0000000000000000 flexray communication controller (flexray) RM0029 1508/1740 doc id 15177 rev 8 each of these six registers holds one part of the network management vector. the length of the network management vector is configured in the network management vector length register (fr_nmvlr) . if fr_nmvlr is programmed with a value that is less than 12 bytes, the remaining bytes of the network management vector registers (fr_nmvr0? fr_nmvr5) , which are not used for the network management vector accumulating, will remain 0. the nmvr provides accrued information over all received nmvs in the last communication cycle. all nmvs received in one cycle are ored into the nmvr. the nmvr is updated at the end of the communication cycle. network management vector length register (fr_nmvlr) this register defines the length of the network management vector in bytes. table 826. nmvr[0:5] field description field description nmvp network management vector part ? the mapping between the network management vector registers (fr_nmvr0?fr_nmvr5) and the receive message buffer payload bytes in nmv[0:11] is depicted in table 827 . table 827. mapping of nmvrn to the received payload bytes nmvn nmvrn register nmvn received payload fr_nmvr0[nmvp[15:8]] nmv0 fr_nmvr0[nmvp[7:0]] nmv1 fr_nmvr1[nmvp[15:8]] nmv2 fr_nmvr1[nmvp[7:0]] nmv3 ... fr_nmvr5[nmvp[15:8]] nmv10 fr_nmvr5[nmvp[7:0]] nmv11 figure 866. network management vector length register (fr_nmvlr) base + 0x0058 write: poc:config 0123456789101112131415 r000000000000 nmvl w reset0000000000000000 table 828. fr_nmvlr field description field description nmvl network management vector length ? protocol related variable: gnetworkmanagementvectorlength this field defines the length of the network management vector in bytes. legal values are between 0 and 12. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1509/1740 timer configuration and control register (fr_ticcr) this register is used to configure and control the two timers t1 and t2. for timer details, see section 33.6.17, timer support . the timer t1 is an absolute timer. the timer t2 can be configured as an absolute or relative timer. figure 867. timer configuration and control register (fr_ticcr) base + 0x005a write: t2_cfg: poc:config t2_rep, t1_rep, t1sp, t2sp, t1tr, t2tr: normal mode 0123456789101112131415 r0 0 t2_cfg t2_rep 000 t2st 000 t1_rep 000 t1st w t2sp t2tr t1sp t1tr reset0000000000000000 table 829. fr_ticcr field description field description t2_cfg timer t2 configuration ? this bit configures the timebase mode of timer t2. 0 t2 is absolute timer. 1 t2 is relative timer. t2_rep timer t2 repetitive mode ? this bit configures the repetition mode of timer t2. 0 t2 is non repetitive 1 t2 is repetitive t2sp timer t2 stop ? this trigger bit is used to stop timer t2. 0 no effect 1 stop timer t2 t2tr timer t2 trigger ? this trigger bit is used to start timer t2. 0 no effect 1 start timer t2 t2st timer t2 state ? this status bit provides the current state of timer t2. 0 timer t2 is idle 1 timer t2 is running t1_rep timer t1 repetitive mode ? this bit configures the repetition mode of timer t1. 0 t1 is non repetitive 1 t1 is repetitive t1sp timer t1 stop ? this trigger bit is used to stop timer t1. 0 no effect 1 stop timer t1 t1tr timer t1 trigger ? this trigger bit is used to start timer t1. 0 no effect 1 start timer t1 t1st timer t1 state ? this status bit provides the current state of timer t1. 0 timer t1 is idle 1 timer t1 is running flexray communication controller (flexray) RM0029 1510/1740 doc id 15177 rev 8 note: both timers are deactivated immediately when the protocol enters a state different from poc:normal active or poc:normal passive . timer 1 cycle set register (fr_ti1cysr) this register defines the cycle filter value and the cycle filter mask for timer t1. for a detailed description of timer t1, refer to section , absolute timer t1 . note: if the application modifies the value in this register while the timer is running, the change becomes effective immediately and timer t1 will expire according to the changed value. timer 1 macrotick offset register (fr_ti1mtor) this register holds the macrotick offset value for timer t1. for a detailed description of timer t1, refer to section , absolute timer t1 . note: if the application modifies the value in this register while the timer is running, the change becomes effective immediately and timer t1 will expire according to the changed value. figure 868. timer 1 cycle set register (fr_ti1cysr) base + 0x005c write: anytime 0123456789101112131415 r0 0 t1_cyc_val 00 t1_cyc_msk w reset0000000000000000 table 830. fr_ti1cysr field description field description t1_cyc_val timer t1 cycle filter value ? this field defines the cycle filter value for timer t1. t1_cyc_msk timer t1 cycle filter mask ? this field defines the cycle filter mask for timer t1. figure 869. timer 1 macrotick offset register (fr_ti1mtor) base + 0x005e write: anytime 0123456789101112131415 r0 0 t1_mtoffset w reset0000000000000000 table 831. fr_ti1mtor field description field description t1_mtoffset timer 1 macrotick offset ? this field defines the macrotick offset value for timer 1. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1511/1740 timer 2 configuration register 0 (fr_ti2cr0) the content of this register depends on the value of the t2_cfg bit in the timer configuration and control register (fr_ticcr) . for a detailed description of timer t2, refer to section , absolute / relative timer t2 . note: if timer t2 is configured as an absolute timer and the application modifies the values in this register while the timer is running, the change becomes effective immediately and timer t2 will expire according to the changed values. if timer t2 is configured as a relative timer and the application changes the values in this register while the timer is running, the change becomes effective when the timer has expired according to the old values. timer 2 configuration register 1 (fr_ti2cr1) the content of this register depends on the value of the t2_cfg bit in the timer configuration and control register (fr_ticcr) . for a detailed description of timer t2, refer to section , absolute / relative timer t2 . figure 870. timer 2 configuration register 0 (fr_ti2cr0) base + 0x0060 write: anytime 0123456789101112131415 r r* t2_cyc_val r* t2_cyc_msk w r t2_mtcnt[31:16] w reset0000000000000000 table 832. fr_ti2cr0 field description field description fields for absolute timer t2 (fr_ticcr[t2_cfg] = 0) t2_cyc_val timer t2 cycle filter value ? this field defines the cycle filter value for timer t2. t2_cyc_msk timer t2 cycle filter mask ? this field defines the cycle filter mask for timer t2. fields for relative timer t2 (fr_ticcr[t2_cfg = 1) t2_mtcnt[31:16] timer t2 macrotick high word ? this field defines the high word of the macrotick count for timer t2. figure 871. timer 2 configuration register 1 (fr_ti2cr1) base + 0x0062 write: anytime 0123456789101112131415 r r* t2_mtoffset w r t2_mtcnt[15:0] w reset0000000000000000 flexray communication controller (flexray) RM0029 1512/1740 doc id 15177 rev 8 note: if timer t2 is configured as an absolute timer and the application modifies the values in this register while the timer is running, the change becomes effective immediately and the timer t2 will expire according to the changed values. if timer t2 is configured as a relative timer and the application changes the values in this register while the timer is running, the change becomes effective when the timer has expired according to the old values. slot status selection register (fr_sssr) this register is used to access the four internal non memory-mapped slot status selection registers fr_sssr0 to fr_sssr3. each internal registers selects a slot, or symbol window/nit, whose status vector will be saved in the corresponding slot status registers (fr_ssr0?fr_ssr7) according to table 835 . for a detailed description of slot status monitoring, refer to section 33.6.18, slot status monitoring . note: slot status information of the message buffers should not be used when any one of the the error flags fr_chierfr[sbcf_ef] or fr_chierfr[ilsa_ef] is set. table 833. fr_ti2cr1 field description field description fields for absolute timer t2 (fr_ticcr[t2_cfg] = 0) t2_mtoffset timer t2 macrotick offset ? this field holds the macrotick offset value for timer t2. fields for relative timer t2 (fr_ticcr[t2_cfg] = 1) t2_mtcnt[15:0] timer t2 macrotick low word ? this field defines the low word of the macrotick value for timer t2. figure 872. slot status selection register (fr_sssr) base + 0x0064 16-bit write access required write: anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0 0 sel 0 slotnumber wwmd reset0000000000000000 table 834. fr_sssr field description field description wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel field only on write access. sel selector ? this field selects one of the four internal slot status selection registers for access. 00 select fr_sssr0. 01 select fr_sssr1. 10 select fr_sssr2. 11 select fr_sssr3. slotnumber slot number ? this field specifies the number of the slot whose status will be saved in the corresponding slot status registers. if this value is set to 0, the related slot status r egister provides the status of the symbol window after the nit start, and provides the status of the nit after the cycle start. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1513/1740 slot status counter condition register (fr_ssccr) this register is used to access and program the four internal non-memory mapped slot status counter condition registers fr_ssccr0 to fr_ssccr3. each of these four internal slot status counter condition registers defines the mode and the conditions for incrementing the counter in the corresponding slot status counter registers (fr_sscr0? fr_sscr3) . the correspondence is given in table 837 . for a detailed description of slot status counters, refer to section , slot status counter registers . table 835. mapping between fr_sssrn and fr_ssrn internal slot status selection register write the slot status of the slot selected by fr_sssrn for each even communication cycle odd communication cycle for channel b to for channel a to for channel b to for channel a to fr_sssr0 fr_ssr0[15:8] fr_ssr0[7:0] fr_ssr1[15:8] fr_ssr1[7:0] fr_sssr1 fr_ssr2[15:8] fr_ssr2[7:0] fr_ssr3[15:8] fr_ssr3[7:0] fr_sssr2 fr_ssr4[15:8] fr_ssr4[7:0] fr_ssr5[15:8] fr_ssr5[7:0] fr_sssr3 fr_ssr6[15:8] fr_ssr6[7:0] fr_ssr7[15:8] fr_ssr7[7:0] figure 873. slot status counter condition register (fr_ssccr) base + 0x0066 16-bit write access required write: anytime 0123456789101112131415 r0 0 sel 0 cntcfg mcy vfr syf nuf suf statusmask[3:0] wwmd reset0000000000000000 table 836. fr_ssccr field description field description wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel field only on write access. sel selector ? this field selects one of the four internal slot counter condition registers for access. 00 select fr_ssccr0. 01 select fr_ssccr1. 10 select fr_ssccr2. 11 select fr_ssccr3. cntcfg counter configuration ? these bit field controls the channel related incrementing of the slot status counter. 00 increment by 1 if condition is fulfilled on channel a. 01 increment by 1 if condition is fulfilled on channel b. 10 increment by 1 if condition is fulfilled on at least one channel. 11 increment by 2 if condition is fulfilled on both channels channel. increment by 1 if condition is fulfilled on only one channel. flexray communication controller (flexray) RM0029 1514/1740 doc id 15177 rev 8 mcy multi cycle selection ? this bit defines whether the slot status counter accumulates over multiple communication cycles or provides information for the previous communication cycle only. 0 the slot status counter provides information for the previous communication cycle only. 1 the slot status counter accumulates over multiple communication cycles. vfr valid frame restriction ? this bit is used to restrict the counter to received valid frames. 0 the counter is not restricted to valid frames only. 1 the counter is restricted to valid frames only. syf sync frame restriction ? this bit is used to restrict the counter to received frames with the sync frame indicator bit set to 1. 0 the counter is not restricted with respect to the sync frame indicator bit. 1 the counter is restricted to frames with the sync frame indicator bit set to 1. nuf null frame restriction ? this bit is used to restrict the counter to received frames with the null frame indicator bit set to 0. 0 the counter is not restricted with respect to the null frame indicator bit. 1 the counter is restricted to frames with the null frame indicator bit set to 0. suf startup frame restriction ? this bit is used to restrict the counter to received frames with the startup frame indicator bit set to 1. 0 the counter is not restricted with respect to the startup frame indicator bit. 1 the counter is restricted to received frames with the startup frame indicator bit set to 1. status mask[3:0] slot status mask ? this bit field is used to enable the counter with respect to the four slot status error indicator bits. statusmask[3] ? this bit enables the counting for slots with the syntax error indicator bit set to 1. statusmask[2] ? this bit enables the counting for slots with the content error indicator bit set to 1. statusmask[1] ? this bit enables the counting for slots with the boundary violation indicator bit set to 1. statusmask[0] ? this bit enables the counting for slots with the transmission conflict indicator bit set to 1. table 836. fr_ssccr field description field description table 837. mapping between internal fr_ssccrn and fr_sscrn condition register condition defined for register fr_ssccr0 fr_sscr0 fr_ssccr1 fr_sscr1 fr_ssccr2 fr_sscr2 fr_ssccr3 fr_sscr3 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1515/1740 slot status registers (fr_ssr0?fr_ssr7) each of these eight registers holds the status vector of the slot specified in the corresponding internal slot status selection register, which can be programmed using the slot status selection register (fr_sssr) . each register is updated after the end of the corresponding slot as shown in figure 984 . the register bits are directly related to the protocol variables and described in more detail in section 33.6.18, slot status monitoring . figure 874. slot status registers (fr_ssr0?fr_ssr7) base + 0x0068 (fr_ssr0) base + 0x006a (fr_ssr1) base + 0x006c (fr_ssr2) base + 0x006e (fr_ssr3) base + 0x0070 (fr_ssr4) base + 0x0072 (fr_ssr5) base + 0x0074 (fr_ssr6) base + 0x0076 (fr_ssr7) 0123456789101112131415 r vfb syb nfb sub seb ceb bvb tcb vfa sya nfa sua sea cea bva tca w reset0000000000000000 table 838. fr_ssr0?fr_ssr7 field description field description vfb valid frame on channel b ? protocol related variable: vss!validframe channel b 0 vss!validframe = 0 1 vss!validframe = 1 syb sync frame indicator channel b ? protocol related variable: vrf!header!syfindicator channel b 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfb null frame indicator channel b ? protocol related variable: vrf!header!nfindicator channel b 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sub startup frame indicator channel b ? protocol related variable: vrf!header!sufindicator channel b 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 seb syntax error on channel b ? protocol related variable: vss!syntaxerror channel b 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 ceb content error on channel b ? protocol related variable: vss!contenterror channel b 0 vss!contenterror = 0 1 vss!contenterror = 1 bvb boundary violation on channel b ? protocol related variable: vss!bviolation channel b 0 vss!bviolation = 0 1 vss!bviolation = 1 flexray communication controller (flexray) RM0029 1516/1740 doc id 15177 rev 8 slot status counter registers (fr_sscr0?fr_sscr3) each of these four registers provides the slot status counter value for the previous communication cycle(s) and is updated at the cycle start. the provided value depends on the control bits and fields in the related internal slot status counter condition register tcb transmission conflict on channel b ? protocol related variable: vss!txconflict channel b 0 vss!txconflict = 0 1 vss!txconflict = 1 vfa valid frame on channel a ? protocol related variable: vss!validframe channel a 0 vss!validframe = 0 1 vss!validframe = 1 sya sync frame indicator channel a ? protocol related variable: vrf!header!syfindicator channel a 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfa null frame indicator channel a ? protocol related variable: vrf!header!nfindicator channel a 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sua startup frame indicator channel a ? protocol related variable: vrf!header!sufindicator channel a 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 sea syntax error on channel a ? protocol related variable: vss!syntaxerror channel a 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 cea content error on channel a ? protocol related variable: vss!contenterror channel a 0 vss!contenterror = 0 1 vss!contenterror = 1 bva boundary violation on channel a ? protocol related variable: vss!bviolation channel a 0 vss!bviolation = 0 1 vss!bviolation = 1 tca transmission conflict on channel a ? protocol related variable: vss!txconflict channel a 0 vss!txconflict = 0 1 vss!txconflict = 1 table 838. fr_ssr0?fr_ssr7 field description field description figure 875. slot status counter registers (fr_sscr0?fr_sscr3) base + 0x0078 (fr_sscr0) base + 0x007a (fr_sscr1) base + 0x007c (fr_sscr2) base + 0x007e (fr_sscr3) additional reset: run command 0123456789101112131415 rslotstatuscnt w reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1517/1740 fr_ssccrn, which can be programmed by using the slot status counter condition register (fr_ssccr) . for more details, see section , slot status counter registers . note: if the counter has reached its maximum value 0xffff and is in the multicycle mode, that is, fr_ssccrn[mcy] = 1, the counter is not reset to 0x0000. the application can reset the counter by clearing the fr_ssccrn[mcy] bit and waiting for the next cycle start, when the cc clears the counter. subsequently, the counter can be set into the multicycle mode again. mts a configuration register (fr_mtsacfr) this register controls the transmission of the media access test symbol mts on channel a. for more details, see section 33.6.13, mts generation . mts b configuration register (mtsbcfr) this register controls the transmission of the media access test symbol mts on channel b. for more details, see section 33.6.13, mts generation . table 839. fr_sscr0?fr_sscr3 field description field description slotstatuscnt slot status counter ? this field provides the current value of the slot status counter. figure 876. mts a configuration register (fr_mtsacfr) base + 0x0080 write: mte: anytime cyccntmsk,cyccntval: poc:config 0123456789101112131415 r mte 0 cyccntmsk 00 cyccntval w reset0000000000000000 table 840. fr_mtsacfr field description field description mte media access test symbol transmission enable ? this control bit is used to enable and disable the transmission of the media access test symbol in the selected set of cycles. 0 mts transmission disabled 1 mts transmission enabled cyccntmsk cycle counter mask ? this field provides the filter mask for the mts cycle count filter. cyccntval cycle counter value ? this field provides the filter value for the mts cycle count filter. figure 877. mts b configuration register (mtsbcfr) base + 0x0082 write: mte: anytime cyccntmsk,cyccntval: poc:config 0123456789101112131415 r mte 0 cyccntmsk 00 cyccntval w reset0000000000000000 flexray communication controller (flexray) RM0029 1518/1740 doc id 15177 rev 8 receive shadow buffer index register (fr_rsbir) this register is used to provide and retrieve the indices of the message buffer header fields currently associated with the receive shadow buffers. for more details on the receive shadow buffer concept, refer to section , receive shadow buffers concept . table 841. mtsbcfr field description field description mte media access test symbol transmission enable ? this control bit is used to enable and disable the transmission of the media access test symbol in the selected set of cycles. 0 mts transmission disabled 1 mts transmission enabled cyccntmsk cycle counter mask ? this field provides the filter mask for the mts cycle count filter. cyccntval cycle counter value ? this field provides the filter value for the mts cycle count filter. figure 878. receive shadow buff er index register (fr_rsbir) base + 0x0084 16-bit write access required write: wmd, sel: any time rsbidx: poc:config 0123456789101112131415 r0 0 sel 0000 rsbidx wwmd reset0000000000000000 table 842. fr_rsbir field description field description wmd write mode ? this bit controls the write mode for this register. 0 update sel and rsbidx field on register write 1 update only sel field on register write sel selector ? this field is used to select the internal receive shadow buffer index register for access. 00 fr_rsbir_a1 ? receive shadow buffer index register for channel a, segment 1 01 fr_rsbir_a2 ? receive shadow buffer index register for channel a, segment 2 10 fr_rsbir_b1 ? receive shadow buffer index register for channel b, segment 1 11 fr_rsbir_b2 ? receive shadow buffer index register for channel b, segment 2 rsbidx receive shadow buffer index ? this field contains the current index of the message buffer header field of the receive shadow message buffer selected by the sel field. the cc uses this index to determine the physical location of the shadow buffer header field in the flexray memory area. the cc will update this field during receive operation.the application provides initial message buffer header index value in the configuration phase. cc: updates the message buffer header index after successful reception. application: provides initial message buffer header index. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1519/1740 receive fifo system memory base address register (fr_rfsymbadr) these registers define the system memory base address for the receive fifo if the fifo address mode bit fr_mcr[fam] is set to 1. the system memory base address is used by the bmif to calculate the physical memory address for system memory accesses for the fifos. receive fifo periodic timer register (fr_rfptr) this register holds periodic timer duration for the periodic fifo timer. the periodic timer applies to both fifos (see section , fifo periodic timer ). figure 879. receive fifo system memory base address high register (fr_rfsymbadhr) base + 0x00e8 write: disabled mode 0123456789101112131415 r smba[31:16] w reset0000000000000000 figure 880. receive fifo system memory base address low register (fr_rfsymbadlr) base + 0x00ea write: disabled mode 0123456789101112131415 r smba[15:4] 0000 w reset0000000000000000 table 843. fr_rfsymbadr field description field description smba system memory base address ? this is the value of the system memory base address for the receive fifo if the fifo address mode bit fr_mcr[fam] is set to 1. it is defines as a byte address. figure 881. receive fifo periodic timer register (fr_rfptr) base + 0x00ec write: poc:config 0123456789101112131415 r0 0 ptd w reset0000000000000000 table 844. fr_rfptr field description field description ptd periodic timer duration ? this value defines the periodic timer duration in terms of macroticks. 0000 timer stays expired 3fff timer never expires other timer expires after specified number of macroticks, expires and is restarted at each cycle start flexray communication controller (flexray) RM0029 1520/1740 doc id 15177 rev 8 receive fifo watermark and selection register (fr_rfwmsr) this register is used to select a receiver fifo for subsequent programming access through the receiver fifo configuration registers summarized in table 845 . to define the watermark for the selected fifo. receive fifo start index register (fr_rfsir) figure 882. receive fifo watermark and selection register (fr_rfwmsr) base + 0x0086 write: wm a /wm b : poc:config, sel: anytime 0123456789101112131415 r wm a/ /wm b 0000000 sel w reset0000000000000000 table 845. sel controlled receiver fifo registers register receive fifo start index register (fr_rfsir) receive fifo depth and size register (rfdsr) receive fifo message id acceptance filter value register (fr_rfmidafvr) receive fifo message id acceptance filter mask register (fr_rfmidafmr) receive fifo frame id rejection filter value register (fr_rffidrfvr) receive fifo frame id rejection filter mask register (fr_rffidrfmr) receive fifo range filter configuration register (fr_rfrfcfr) receive fifo range filter control register (fr_rfrfctr) table 846. fr_rfwmsr field description field description wm a wm b watermark ? this field defines the watermark value for the selected fifo. this value is used to control the generation of the almost full interrupt flags. sel select ? this control bit selects the receiver fifo for subsequent programming. 0 receiver fifo for channel a selected 1 receiver fifo for channel b selected figure 883. receive fifo start index register (fr_rfsir) base + 0x0088 write: poc:config 0123456789101112131415 r000000 sidx a /sidx b w reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1521/1740 this register defines the message buffer header index of the first message buffer of the selected fifo. receive fifo depth and size register (rfdsr) this register defines the structure of the selected fifo, that is, the number of entries and the size of each entry. receive fifo a read index register (fr_rfarir) this register provides the message buffer header index of the next available fifo a entry that the application can read. table 847. fr_rfsir field description field description sidx a sidx b start index ? this field defines the number of the message buffer header field of the first message buffer of the selected fifo. the cc uses the value of the sidx field to determine the physical location of the receiver fifo?s first message buffer header field. figure 884. receive fifo depth and size register (rfdsr) base + 0x008a write: poc:config 0123456789101112131415 r fifo_depth a /fifo_depth b 0 entry_size a /entry_size b w reset0000000000000000 table 848. rfdsr field description field description fifo_depth a fifo_depth b fifo depth ? this field defines the depth of the selected fifo, that is, the number of entries. note : if the fifo_depth is configured to 0, fr_rffidrfmr[fidrfmsk] must be configured to 0 too, to ensure that no frames are received into the fifo. entry_size a entry_size b entry size ? this field defines the size of the frame data sections for the selected fifo in 2 byte entities. figure 885. receive fifo a read index register (fr_rfarir) base + 0x008c 0123456789101112131415 r000000 rdidx w reset0000000000000000 flexray communication controller (flexray) RM0029 1522/1740 doc id 15177 rev 8 note: if the fifo is empty, the rdidx field points to an physical message buffer with invalid content. receive fifo b read index register (fr_rfbrir) this register provides the message buffer header index of the next available fifo b entry that the application can read. note: if the fifo is empty, the rdidx field points to an physical message buffer with invalid content. receive fifo fill level and pop count register (fr_rfflpcr) this register provides the current fill level of the two receiver fifos and is used to pop a number of entries from the fifos. table 849. fr_rfarir field description field description rdidx read index ? this field provides the message buffer header index of the next available fifo message buffer that the application can read. if the old style fifo mode is configured (fr_mcr[fimd] = 0), the cc updates this index by 1 entry, when the application writes to the fafaif flag in the global interrupt flag and enable register (fr_gifer) . if the new style fifo mode is configured (fr_mcr[fimd] = 1), the cc updates this index by pca entries, when the application writes to the receive fifo fill level and pop count register (fr_rfflpcr) . figure 886. receive fifo b read index register (fr_rfbrir) base + 0x008e 0123456789101112131415 r 0 0 0 0 0 0 rdidx w reset0000000000000000 table 850. fr_rfbrir field description field description rdidx read index ? this field provides the message buffer header index of the next available fifo message buffer that the application can read. figure 887. receive fifo fill level and pop count register (fr_rfflpcr) base + 0x00ee 0123456789101112131415 rflb fla wpcb pca reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1523/1740 note: if the pop count value pca/pcb is greater than the current fifo fill level flb/fla, than the fifo is empty after the update. no notification is given that not the required number of entries was removed. receive fifo message id acceptance filter value register (fr_rfmidafvr) this register defines the filter value for the message id acceptance filter of the selected fifo. for details on message id filtering see section , fifo filtering . receive fifo message id acceptance filter mask register (fr_rfmidafmr) this register defines the filter mask for the message id acceptance filter of the selected fifo. for details on message id filtering see section , fifo filtering . table 851. fr_rfflpcr field description field description flb fill level fifo b ? this field provides the current number of entries in the fifo b. fla fill level fifo a ? this field provides the current number of entries in the fifo a. pcb pop count fifo b ? this field defines the number of entries to be removed from fifo b. pca pop count fifo a ? this field defines the number of entries to be removed from fifo a. figure 888. receive fifo message id acceptance filter value register (fr_rfmidafvr) base + 0x0090 write: poc:config 0123456789101112131415 r midafval a /midafval b w reset0000000000000000 table 852. fr_rfmidafvr field description field description midafval a midafval b message id acceptance filter value ? filter value for the message id acceptance filter. figure 889. receive fifo message id acceptance filter mask register (fr_rfmidafmr) base + 0x0092 write: poc:config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r midafmsk a /midafmsk b w reset0000000000000000 table 853. fr_rfmidafmr field description field description midafmsk a midafmsk b message id acceptance filter mask ? filter mask for the message id acceptance filter. flexray communication controller (flexray) RM0029 1524/1740 doc id 15177 rev 8 receive fifo frame id rejection filter value register (fr_rffidrfvr) this register defines the filter value for the frame id rejection filter of the selected fifo. for details on frame id filtering see section , fifo filtering . receive fifo frame id rejection filter mask register (fr_rffidrfmr) this register defines the filter mask for the frame id rejection filter of the selected fifo. for details on frame id filtering see section , fifo filtering . receive fifo range filter configuration register (fr_rfrfcfr) figure 890. receive fifo frame id rejection filter value register (fr_rffidrfvr) base + 0x0094 write: poc:config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r00000 fidrfval a /fidrfval b w reset0000000000000000 table 854. fr_rffidrfvr field description field description fidrfval a fidrfval b frame id rejection filter value ? filter value for the frame id rejection filter. figure 891. receive fifo frame id rejection filter mask register (fr_rffidrfmr) base + 0x0096 write: poc:config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r00000 fidrfmsk a /fidrfmsk b w reset0000000000000000 table 855. fr_rffidrfmr field description field description fidrfmsk frame id rejection filter mask ? filter mask for the frame id rejection filter. figure 892. receive fifo range filter configuration register (fr_rfrfcfr) base + 0x0098 16-bit write access required write: wmd, ibd, sel: any time sid: poc:config 0123456789101112131415 r0 ibd sel 0 sid a /sid b wwmd reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1525/1740 this register provides access to the four internal frame id range filter boundary registers of the selected fifo. for details on frame id range filter see section , fifo filtering . receive fifo range filter control register (fr_rfrfctr) this register is used to enable and disable each frame id range filter and to define whether it is running as acceptance or rejection filter. table 856. fr_rfrfcfr field description field description wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel and ibd field only on write access. ibd interval boundary ? this control bit selects the interval boundary to be programmed with the sid value. 0 program lower interval boundary 1 program upper interval boundary sel filter selector ? this control field selects the frame id range filter to be accessed. 00 select frame id range filter 0. 01 select frame id range filter 1. 10 select frame id range filter 2. 11 select frame id range filter 3. sid a sid b slot id ? defines the ibd-selected frame id boundary value for the sel-selected range filter. figure 893. receive fifo range filter control register (fr_rfrfctr) base + 0x009a write: anytime 0123456789101112131415 r0000 f3md f2md f1md f0md 0000 f3en f2en f1en f0en w reset0000000000000000 table 857. fr_rfrfctr field description field description f3md range filter 3 mode ? this control bit defines the filter mode of the frame id range filter 3. 0 range filter 3 runs as acceptance filter 1 range filter 3 runs as rejection filter f2md range filter 2 mode ? this control bit defines the filter mode of the frame id range filter 2. 0 range filter 2 runs as acceptance filter 1 range filter 2 runs as rejection filter f1md range filter 1 mode ? this control bit defines the filter mode of the frame id range filter 1. 0 range filter 1 runs as acceptance filter 1 range filter 1 runs as rejection filter f0md range filter 0 mode ? this control bit defines the filter mode of the frame id range filter 0. 0 range filter 0 runs as acceptance filter 1 range filter 0 runs as rejection filter flexray communication controller (flexray) RM0029 1526/1740 doc id 15177 rev 8 last dynamic transmit slot channel a register (fr_ldtxslar) this register provides the number of the last transmission slot in the dynamic segment for channel a. this register is updated after the end of the dynamic segment and before the start of the next communication cycle. last dynamic transmit slot channel b register (fr_ldtxslbr) f3en range filter 3 enable ? this control bit is used to enable and disable the frame id range filter 3. 0 range filter 3 disabled 1 range filter 3 enabled f2en range filter 2 enable ? this control bit is used to enable and disable the frame id range filter 2. 0 range filter 2 disabled 1 range filter 2 enabled f1en range filter 1 enable ? this control bit is used to enable and disable the frame id range filter 1. 0 range filter 1 disabled 1 range filter 1 enabled f0en range filter 0 enable ? this control bit is used to enable and disable the frame id range filter 0. 0 range filter 0 disabled 1 range filter 0 enabled table 857. fr_rfrfctr field description (continued) field description figure 894. last dynamic transmit slot channel a register (fr_ldtxslar) base + 0x009c 0123456789101112131415 r00000 lastdyntxslota w reset0000000000000000 table 858. fr_ldtxslar field description field description lastdyntx slota last dynamic transmission slot channel a ? protocol related variable: zlastdyntxslot channel a number of the last transmission slot in the dynamic segment for channel a. if no frame was transmitted during the dynamic segment on channel a, the value of this field is set to 0. figure 895. last dynamic transmit slot channel b register (fr_ldtxslbr) base + 0x009e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 lastdyntxslotb w reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1527/1740 this register provides the number of the last transmission slot in the dynamic segment for channel b. this register is updated after the end of the dynamic segment and before the start of the next communication cycle. protocol configuration registers the following configuration registers provide the necessary configuration information to the protocol engine. the individual values in the registers are described in tab le 8 60 . for more details about the flexray related configuration parameters and the allowed parameter ranges, see flexray communications system protocol specification, version 2.1 rev a . table 859. fr_ldtxslbr field description field description lastdyntx slotb last dynamic transmission slot channel b ? protocol related variable: zlastdyntxslot channel b number of the last transmission slot in the dynamic segment for channel b. if no frame was transmitted during the dynamic segment on channel b the value of this field is set to 0. table 860. protocol configuration register fields (sheet 1 of 2) name description (1) min max unit fr_pcr coldstart_attempts gcoldstartattempts number 3 action_point_offset gdactionpointoffset - 1 mt 0 cas_rx_low_max gdcasrxlowmax - 1 gdbit 4 dynamic_slot_idle_phase gddynamicslotidlephase minislot 28 minislot_action_point_offset gdminislotactionpointoffset - 1 mt 3 minislot_after_action_point gdminislot - gdminislotactionpointoffset - 1 mt 2 static_slot_length gdstaticslot mt 0 static_slot_after_action_point gdstaticslot - gdactionpointoffset - 1 mt 13 symbol_window_exists gdsymbolwindow != 0 0 1 bool 9 symbol_window_after_action_point gdsymbolwindow - gdactionpointoffset - 1 mt 6 tss_transmitter gdtsstransmitter gdbit 5 wakeup_symbol_rx_idle gdwakeupsymbolrxidle gdbit 5 wakeup_symbol_rx_low gdwakeupsymbolrxlow gdbit 3 wakeup_symbol_rx_window gdwakeupsymbolrxwindow gdbit 4 wakeup_symbol_tx_idle gdwakeupsymboltxidle gdbit 8 wakeup_symbol_tx_low gdwakeupsymboltxlow gdbit 5 noise_listen_timeout ( glistennoise * pdlistentimeout ) - 1 t16/17 macro_initial_offset_a pmacroinitialoffset[a] mt 6 macro_initial_offset_b pmacroinitialoffset[b] mt 16 macro_per_cycle gmacropercycle mt 10 flexray communication controller (flexray) RM0029 1528/1740 doc id 15177 rev 8 macro_after_first_static_slot gmacropercycle - gdstaticslot mt 1 macro_after_offset_correction gmacropercycle - goffsetcorrectionstart mt 28 max_without_clock_correction_fatal gmaxwithoutclockcorrectionfatal cyclepairs 8 max_without_clock_correction_passi ve gmaxwithoutclockcorrectionpassive cyclepairs 8 minislot_exists gnumberofminislots != 0 0 1 bool 9 minislots_max gnumberofminislots - 1 minislot 29 number_of_static_slots gnumberofstaticslots static slot 2 offset_correction_start goffsetcorrectionstart mt 11 payload_length_static gpayloadlengthstatic 2-bytes 19 max_payload_length_dynamic ppayloadlengthdynmax 2-bytes 24 first_minislot_action_point_offset max( gdactionpointoffset , gdminislotactionpointoffset ) - 1 mt 13 allow_halt_due_to_clock pallowhaltduetoclock bool 26 allow_passive_to_active pallowpassivetoactive cyclepairs 12 cluster_drift_damping pclusterdriftdamping t24 comp_accepted_startup_range_a pdacceptedstartuprange - pdelaycompensation[a] t22 comp_accepted_startup_range_b pdacceptedstartuprange - pdelaycompensation[b] t26 listen_timeout pdlistentimeout - 1 t14/15 key_slot_id pkeyslotid number 18 key_slot_used_for_startup pkeyslotusedforstartup bool 11 key_slot_used_for_sync pkeyslotusedforsync bool 11 latest_tx gnumberofminislots - platesttx minislot 21 sync_node_max gsyncnodemax number 30 micro_initial_offset_a pmicroinitialoffset[a] t20 micro_initial_offset_b pmicroinitialoffset[b] t20 micro_per_cycle pmicropercycle t22/23 micro_per_cycle_min pmicropercycle - pdmaxdrift t24/25 micro_per_cycle_max pmicropercycle + pdmaxdrift t26/27 micro_per_macro_nom_half round( pmicropermacronom / 2) t7 offset_correction_out poffsetcorrectionout t9 rate_correction_out pratecorrectionout t14 single_slot_enabled psingleslotenabled bool 10 wakeup_channel pwakeupchannel see table 861 10 table 860. protocol configuration register fields (sheet 1 of 2) name description (1) min max unit fr_pcr RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1529/1740 protocol configuration register 0 (fr_pcr0) protocol configuration register 1 (fr_pcr1) wakeup_pattern pwakeuppattern number 18 decoding_correction_a pdecodingcorrection + pdelaycompensation[a] + 2 t19 decoding_correction_b pdecodingcorrection + pdelaycompensation[b] + 2 t7 key_slot_header_crc header crc for key slot 0x000 0x7ff number 12 extern_offset_correction pexternoffsetcorrection t29 extern_rate_correction pexternratecorrection t21 1. see flexray communications system protocol specification, version 2.1 rev a for detailed protocol parameter definitions table 860. protocol configuration register fields (sheet 1 of 2) name description (1) min max unit fr_pcr table 861. wakeup channel selection wakeup_channel wakeup channel 0a 1b figure 896. protocol configur ation register 0 (fr_pcr0) base + 0x00a0 write: poc:config 0123456789101112131415 r action_point_offset static_slot_length w reset0000000000000000 figure 897. protocol configur ation register 1 (fr_pcr1) base + 0x00a2 write: poc:config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0 0 macro_after_first_static_slot w reset0000000000000000 flexray communication controller (flexray) RM0029 1530/1740 doc id 15177 rev 8 protocol configuration register 2 (fr_pcr2) protocol configuration register 3 (fr_pcr3) protocol configuration register 4 (fr_pcr4) protocol configuration register 5 (fr_pcr5) protocol configuration register 6 (fr_pcr6) figure 898. protocol configur ation register 2 (fr_pcr2) base + 0x00a4 write: poc:config 0123456789101112131415 r minislot_after_action_point number_of_static_slots w reset0000000000000000 figure 899. protocol configur ation register 3 (fr_pcr3) base + 0x00a6 write: poc:config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r wakeup_symbol_rx_low minislot_action_point_offset[4:0] coldstart_attempts w reset0000000000000000 figure 900. protocol configur ation register 4 (fr_pcr4) base + 0x00a8 write: poc:config 0123456789101112131415 r cas_rx_low_max wakeup_symbol_rx_window w reset0000000000000000 figure 901. protocol configur ation register 5 (fr_pcr5) base + 0x00aa write: poc:config 0123456789101112131415 r tss_transmitter wakeup_symbol_tx_low wakeup_symbol_rx_idle w reset0000000000000000 figure 902. protocol configur ation register 6 (fr_pcr6) base + 0x00ac write: poc:config 0123456789101112131415 r0 symbol_window_after_action_point macro_initial_offset_a w reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1531/1740 protocol configuration register 7 (fr_pcr7) protocol configuration register 8 (fr_pcr8) protocol configuration register 9 (fr_pcr9) protocol configuration register 10 (fr_pcr10) figure 903. protocol configur ation register 7 (fr_pcr7) base + 0x00ae write: poc:config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r decoding_correction_b micro_per_macro_nom_half w reset0000000000000000 figure 904. protocol configur ation register 8 (fr_pcr8) base + 0x00b0 write: poc:config 0123456789101112131415 r max_without_clock_ correction_fatal max_without_clock_ correction_passive wakeup_symbol_tx_idle w reset0000000000000000 figure 905. protocol configur ation register 9 (fr_pcr9) base + 0x00b2 write: poc:config 0 1 23456789101112131415 r mini slot_ exists sym bol_ win dow_ exists offset_correction_out w reset0 0 00000000000000 figure 906. protocol configuration register 10 (fr_pcr10) base + 0x00b4 write: poc:config 0 1 23456789101112131415 rsingle _slot _en abled wake up_ chan nel macro_per_cycle w reset0 0 00000000000000 flexray communication controller (flexray) RM0029 1532/1740 doc id 15177 rev 8 protocol configuration register 11 (fr_pcr11) protocol configuration register 12 (fr_pcr12) protocol configuration register 13 (fr_pcr13) protocol configuration register 14 (fr_pcr14) figure 907. protocol configuration register 11 (fr_pcr11) base + 0x00b6 write: poc:config 0 1 23456789101112131415 rkey_ slot_ used_ for_ start up key_ slot_ used_ for_ sync offset_correction_start w reset0 0 00000000000000 figure 908. protocol configuration register 12 (fr_pcr12) base + 0x00b8 write: poc:config 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r allow_passive_to_active key_slot_header_crc w reset0000000000000000 figure 909. protocol configuration register 13 (fr_pcr13) base + 0x00ba write: poc:config 0123456789101112131415 r first_minislot_action_point_offset static_slot_after_action_point w reset0000000000000000 figure 910. protocol configuration register 14 (fr_pcr14) base + 0x00bc write: poc:config 0123456789101112131415 r rate_correction_out listen_timeout[20:16] w reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1533/1740 protocol configuration register 15 (fr_pcr15) protocol configuration register 16 (fr_pcr16) protocol configuration register 17 (fr_pcr17) protocol configuration register 18 (fr_pcr18) protocol configuration register 19 (fr_pcr19) figure 911. protocol configuration register 15 (fr_pcr15) base + 0x00be write: poc:config 0123456789101112131415 r listen_timeout[15:0] w reset0000000000000000 figure 912. protocol configuration register 16 (fr_pcr16) base + 0x00c0 write: poc:config 0123456789101112131415 r macro_initial_offset_b noise_listen_timeout[24:16] w reset0000000000000000 figure 913. protocol configuration register 17 (fr_pcr17) base + 0x00c2 write: poc:config 0123456789101112131415 r noise_listen_timeout[15:0] w reset0000000000000000 figure 914. protocol configuration register 18 (fr_pcr18) base + 0x00c4 write: poc:config 0123456789101112131415 r wakeup_pattern key_slot_id w reset0000000000000000 figure 915. protocol configuration register 19 (fr_pcr19) base + 0x00c6 write: poc:config 0123456789101112131415 r decoding_correction_a payload_length_static w reset0000000000000000 flexray communication controller (flexray) RM0029 1534/1740 doc id 15177 rev 8 protocol configuration register 20 (fr_pcr20) protocol configuration register 21 (fr_pcr21) protocol configuration register 22 (fr_pcr22) protocol configuration register 23 (fr_pcr23) protocol configuration register 24 (fr_pcr24) figure 916. protocol configuration register 20 (fr_pcr20) base + 0x00c8 write: poc:config 0123456789101112131415 r micro_initial_offset_b micro_initial_offset_a w reset0000000000000000 figure 917. protocol configuration register 21 (fr_pcr21) base + 0x00ca write: poc:config 0123456789101112131415 r extern_rate_ correction latest_tx w reset0000000000000000 figure 918. protocol configuration register 22 (fr_pcr22) base + 0x00cc write: poc:config 0123456789101112131415 r r* comp_accepted_startup_range_a micro_per_cycle[19:16] w reset0000000000000000 figure 919. protocol configuration register 23 (fr_pcr23) base + 0x00ce write: poc:config 0123456789101112131415 r micro_per_cycle[15:0] w reset0000000000000000 figure 920. protocol configuration register 24 (fr_pcr24) base + 0x00d0 write: poc:config 0123456789101112131415 r cluster_drift_damping max_payload_length_dynamic micro_per_cycle_min [19:16] w reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1535/1740 protocol configuration register 25 (fr_pcr25) protocol configuration register 26 (fr_pcr26) protocol configuration register 27 (fr_pcr27) protocol configuration register 28 (fr_pcr28) figure 921. protocol configuration register 25 (fr_pcr25) base + 0x00d2 write: poc:config 0123456789101112131415 r micro_per_cycle_min[15:0] w reset0000000000000000 figure 922. protocol configuration register 26 (fr_pcr26) base + 0x00d4 write: poc:config 0 123456789101112131415 rallow _halt_ due _to_ clock comp_accepted_startup_range_b micro_per_cycle_max [19:16] w reset0 00000000000 0 0 0 0 figure 923. protocol configuration register 27 (fr_pcr27) base + 0x00d6 write: poc:config 0123456789101112131415 r micro_per_cycle_max[15:0] w reset0000000000000000 figure 924. protocol configuration register 28 (fr_pcr28) base + 0x00d8 write: poc:config 0 1 23456789101112131415 r dynamic_slot _idle_phase macro_after_offset_correction w reset0 0 00000000000000 flexray communication controller (flexray) RM0029 1536/1740 doc id 15177 rev 8 protocol configuration register 29 (fr_pcr29) protocol configuration register 30 (fr_pcr30) ecc error interrupt flag and enable register (fr_eeifer) this register provides the means to control the ecc related interrupt request lines and provides the corresponding interrupt flags. the interrupt flags are cleared by writing 1, which resets the corresponding report registers. for a detailed description see section , memory error reporting . figure 925. protocol configuration register 29 (fr_pcr29) base + 0x00da write: poc:config 0123456789101112131415 r extern_offset_ correction minislots_max w reset0000000000000000 figure 926. protocol configuration register 30 (fr_pcr30) base + 0x00dc write: poc:config 0123456789101112131415 r000000000000 sync_node_max w reset0000000000000000 figure 927. ecc error interrupt flag and enable register (fr_eeifer) base + 0x00f0 write: normal mode 0123456789101112131415 r lrne_of lrce_of drne_of drce_of lrne_if lrce_if drne_if drce_if 0 0 0 0 lrne_ie lrce_ie drne_ie drce_ie w w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1537/1740 table 862. fr_eeifer field description field description error overflow flags lrne_of lram non-corrected error overflow flag ? this flag is set to 1 when at least one of the following events appears: a) memory errors are detected but not corrected on chi lram and interrupt flag lrne_if is already 1. b) memory errors are detected but not corrected on at least two banks of chi lram 0 no such event 1 non-corrected error overflow detected on chi lram lrce_of lram corrected error overflow flag ? this flag is set to 1 when at least one of the following events appears: a) memory errors are detected and corrected on chi lram and interrupt flag lrce_if is already 1. b) memory errors are detected and corrected on at least two banks of chi lram 0 no such event 1 corrected error overflow detected on chi lram note: error correction not implemented on chi lram, flag will never be asserted. drne_of dram non-corrected error overflow flag ? this flag is set to 1 when at least one of the following events appears: a) memory errors are detected but not corrected on pe dram and interrupt flag drne_if is already 1. b) memory errors are detected but not corrected on at least two banks of the pe dram 0 no such event 1 non-corrected error overflow detected on pe dram drce_of dram corrected error overflow flag ? this flag is set to 1 when at least one of the following events appears: a) memory errors are detected and corrected on pe dram and interrupt flag drce_if is already 1. b) memory errors are detected and corrected on at least two banks of pe dram 0 no such event 1 corrected error overflow detected on pe dram flexray communication controller (flexray) RM0029 1538/1740 doc id 15177 rev 8 error interrupt flags lrne_if lram non-corrected error interrupt flag ? this interrupt flag is set to 1 when a memory error is detected but not corrected on the chi lram. 0 no such event 1 non-corrected error detected on chi lram lrce_if lram corrected error interrupt flag ? this interrupt flag is set to 1 when a memory error is detected and corrected on the chi lram. 0 no such event 1 corrected error detected on chi lram note: error correction not implemented on chi lram, flag will never be asserted. drne_if dram non-corrected error interrupt flag ? this interrupt flag is set to 1 when a memory error is detected but not corrected on pe dram. 0 no such event 1 non-corrected error detected on pe dram drce_if dram corrected error interrupt flag ? this interrupt flag is set to 1 when a memory error is detected and corrected on pe dram. 0 no such event 1 corrected error detected on pe dram error interrupt enables lrne_ie lram non-corrected error interrupt enable ? this flag controls if the lram non-corrected error interrupt line is asserted when the lrne_if flag is set. 0 disable interrupt line 1 enable interrupt line lrce_ie lram corrected error interrupt enable ? this flag controls if the lram corrected error interrupt line is asserted when the lrce_if flag is set. 0 disable interrupt line 1 enable interrupt line drne_ie dram non-corrected error interrupt enable ? this flag controls if the dram non-corrected error interrupt line is asserted when the drne_if flag is set. 0 disable interrupt line 1 enable interrupt line drce_ie dram corrected error interrupt enable ? this flag controls if the dram corrected error interrupt line is asserted when the drce_if flag is set. 0 disable interrupt line 1 enable interrupt line table 862. fr_eeifer field description field description RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1539/1740 ecc error report and injection control register (fr_eericr) this register configures the error injection and error reporting and provides the selector for the content of the report registers. ecc error report address register (fr_eerar) figure 928. ecc error report and injection control register (fr_eericr) base + 0x00f2 write: ers: anytime erm, eim, eie: idl 0123456789101112131415 rbsy00000 ers 000 erm 00 eim eie w reset0000000000000000 table 863. fr_eericr field description field description bsy register update busy ? this field indicates the current state of the ecc configuration update and controls the register write access condition idl specified in section , register write access 0 ecc configuration is idle 1 ecc configuration is running ers error report select ? this field selects the content of the ecc error reporting registers. 00 show pe dram non-corrected error information 01 show pe dram corrected error information 10 show chi lram non-corrected error information 11 show chi lram corrected error information erm error report mode ? this bit configures the type of data written into the internal error report registers on the detection of a memory error. 0 store data and code as delivered by ecc decoding logic. 1 store data and code as read from the memory. eim error injection mode ? this bit configures the ecc error injection mode. 0 use fr_eeidr[data] and fr_eeicr[code] as xor distortion pattern for error injection. 1 use fr_eeidr[data] and fr_eeicr[code] as write value for error injection. eie error injection enable ? this bit configures the ecc error injection on the memories. 0 error injection disabled 1 error injection enabled when the ecc functionality is required to be disabled (i .e.value of the fr_mcr[ecce] is 0), error injection enable bit fr_eericr[eie] should not be set to 1. figure 929. ecc error report address register (fr_eerar) base + 0x00f4 0123456789101112131415 r mid bank addr w reset0111000000000000 flexray communication controller (flexray) RM0029 1540/1740 doc id 15177 rev 8 this register provides the memory identifier, bank, and address for which the memory error is reported. ecc error report data register (fr_eerdr) this register provides the data related information of the reported memory read access. the assignment of the bits depends on the selected memory and memory bank as shown in ta ble 86 6 . table 864. fr_eerar field description field description mid memory identifier ? this flag provides the memory instance for which the memory error is reported. 0 pe dram 1chi lram bank memory bank ? this field provides the bank for which the memory error is reported. 111 reset value, indicates no error found after reset. for mid = 0: 000 bank0: pe dram [7:0] 001 bank1: pe dram [15:8] others ? not used for mid = 1: 000 bank0: fr_mbccfr(2n) 001 bank1: fr_mbfidr(2n) 010 bank2: fr_mbidxr(2n) 011 bank3: fr_mbccfr(2n+1) 100 bank4: fr_mbfidr(2n+1) 101 bank5: fr_mbidxr(2n+1) others ? not used addr memory address ? this field provides the address of the failing memory location. figure 930. ecc error report data register (fr_eerdr) base + 0x00f6 0123456789101112131415 rdata w reset0000000000000000 table 865. fr_eerdr field description field description data data ? the content of this field depends on the report mode selected by fr_eericr[erm] erm = 0: ecc data, shows data as generated by the ecc decoding logic erm = 1: memory data, shows data as read from the memory RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1541/1740 ecc error report code register (fr_eercr) this register provides the ecc related information of the reported memory read access. ecc error injection address register (fr_eeiar) this register defines the memory module, bank, and address where the ecc error has to be injected. table 866. valid bits in fr_eerdr[data] / fr_eeidr[data] field mem bank1514131211109876543210 pe dram 0 pe dram[7:0] pe dram 1 pe dram[15:8] chi lram 0 fr_mbccfr(2n) chi lram 1 fr_mbfidr(2n) chi lram 2 fr_mbidxr(2n) chi lram 3 fr_mbccfr(2n+1) chi lram 4 fr_mbfidr(2n+1) chi lram 5 fr_mbidxr(2n+1) figure 931. ecc error report code register (fr_eercr) base + 0x00f8 0123456789101112131415 r00000000000 code w reset0000000000000000 table 867. fr_eersr field description field description code code ? the content of this field depends on the report mode selected by fr_eericr[erm] erm = 0: syndrome. shows the ecc syndrome generated by the ecc decoding logic. the coding of the pe dram syndrome is shown in section , pe dram syndrome the coding of the chi lram syndrome is shown in section , chi lram syndrome . erm = 1: checkbits. shows the ecc checkbits read from the memory. figure 932. ecc error injection address register (fr_eeiar) base + 0x00fa write: idl 0123456789101112131415 r mid bank addr w reset0000000000000000 flexray communication controller (flexray) RM0029 1542/1740 doc id 15177 rev 8 ecc error injection data register (fr_eeidr) this register defines the data distortion pattern for the error injection write. the number of valid bits depends on the selected memory and memory bank as shown in table 866 . ecc error injection code register (fr_eeicr) table 868. fr_eeiar field description field description mid memory identifier ? this flag defines the memory instance for ecc error injection. 0 pe dram 1chi lram bank memory bank ? this field defines the memory bank for ecc error injection. for mid = 0: 000 bank0: pe dram [7:0] 001 bank1: pe dram [15:8] others ? reserved for mid = 1: 000 bank0: fr_mbccfr(2n) 001 bank1: fr_mbfidr(2n) 010 bank2: fr_mbidxr(2n) 011 bank3: fr_mbccfr(2n+1) 100 bank4: fr_mbfidr(2n+1) 101 bank5: fr_mbidxr(2n+1) others ? reserved addr memory address ? this flag defines the memory address for ecc error injection. figure 933. ecc error injection data register (fr_eeidr) base + 0x00fc write: idl 0123456789101112131415 r data w reset0000000000000000 table 869. fr_eeidr field description field description data data ? the content of this field depends on the error injection mode selected by fr_eericr[eim]. eim = 0: this field defines the xor distortion pattern for the data written into the memory. eim = 1: this field defines the data to be written into the memory. figure 934. ecc error injection code register (fr_eeicr) base + 0x00fe write: idl 0123456789101112131415 r00000000000 code w reset0000000000000000 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1543/1740 this register defines the ecc code distortion pattern for the error injection write. message buffer configuration, control, status registers (fr_mbccsrn) the content of these registers comprises message buffer configuration data, message buffer control data, message buffer status information, and message buffer interrupt flags. a detailed description of all flags can be found in section 33.6.6, individual message buffer functional description . if the application writes 1 to the edt bit, no write access to the other register bits is performed. if the application writes 0 to the edt bit and 1 to the lckt bit, no write access to the other bits is performed. table 870. fr_eeicr field description field description code code ? the content of this field depends on the error injection mode selected by fr_eericr[eim]. eim = 0: this field defines the xor distortion pattern for the ecc checkbits written into the memory. eim = 1: this field defines the ecc checkbits written into the memory. figure 935. message buffer configuration, control, status registers (fr_mbccsrn) base + 0x0100 (fr_mbccsr0) base + 0x0108 (fr_mbccsr1) ... base + 0x04f8 (fr_mbccsr127) write: mcm, mbt, mtd: poc:config or mb_dis cmt: mb_lck or mb_dis edt, lckt, mbie, mbif: normal mode additional reset: cmt, dup, dval, mbif: message buffer disable 0123456789101112131415 r0 mcm mbt mtd cmt 00 mbie 000 dup dval eds lcks mbif w rwm edt lckt w1c reset0000000000000000 flexray communication controller (flexray) RM0029 1544/1740 doc id 15177 rev 8 table 871. fr_mbccsrn field description field description message buffer configuration mcm message buffer commit mode ? this bit configures the commit mode of a double buffered message buffer. 0 streaming commit mode 1 immediate commit mode mbt message buffer type ? this bit configures the buffering type of a transmit message buffer. 0 single buffered message buffer 1 double buffered message buffer mtd message buffer transfer direction ? this bit configures the transfer direction of a message buffer. 0 receive message buffer 1 transmit message buffer message buffer control cmt commit for transmission ? this bit indicates if the transmit message buffer data are ready for transmission. 0 message buffer data not ready for transmission 1 message buffer data ready for transmission edt enable/disable trigger ? if the application writes 1 to this bit, a message buffer enable or disable is triggered, depending on the current value eds status bit is 0. 0no effect 1 message buffer enable or disable is triggered lckt lock/unlock trigger ? if the application writes 1 to this bit, a message buffer lock or unlock is triggered, depending on the current value of the lcks status bit. 0no effect 1 message buffer lock or unlock is triggered mbie message buffer interrupt enable ? this control bit defines whether the message buffer will generate an interrupt request when its mbif flag is set. 0 interrupt request generation disabled 1 interrupt request generation enabled RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1545/1740 message buffer cycle counter filter registers (fr_mbccfrn) this register contains message buffer configuration data for the transmission mode, the channel assignment, and for the cycle counter filtering. for detailed information on cycle counter filtering, refer to section , message buffer cycle counter filtering . message buffer status dup data updated ? this status bit indicates whether the frame header in the message buffer header field and the data in the message buffer data field were updated after a frame reception. 0 frame header and message buffer data field not updated 1 frame header and message buffer data field updated dval data valid ? for receive message buffers this status bit indicates whether the message buffer data field contains valid frame data. for transmit message buffers the status bit indicates if a message is transferred again due to the state transmission mode of the message buffer. 0 receive message buffer contains no valid frame data / message is transmitted for the first time 1 receive message buffer contains valid frame data / message will be transferred again eds enable/disable status ? this status bit indicates whether the message buffer is enabled or disabled. 0 message buffer is disabled. 1 message buffer is enabled. lcks lock status ? this status bit indicates the current lock status of the message buffer. 0 message buffer is not locked by the application. 1 message buffer is locked by the application. mbif message buffer interrupt flag ? this flag is set when the slot status field of the message buffer was updated after frame transmission or recepti on, or when a transmit message buffer was just enabled by the application. 0 no such event 1 slot status field updated or transmit message buffer just enabled table 871. fr_mbccsrn field description (continued) field description figure 936. message buffer cycle counter filter registers (fr_mbccfrn) base + 0x0102 (fr_mbccfr0) base + 0x010a (fr_mbccfr1) ... base + 0x04fa (fr_mbccfr127) 16-bit write access required write: poc:config or mb_dis 0123456789101112131415 r mtm cha chb ccfe ccfmsk ccfval w reset???????????????? flexray communication controller (flexray) RM0029 1546/1740 doc id 15177 rev 8 . note: if at least one message buffer assigned to a certain slot is assigned to both channels, then all message buffers assigned to this slot have to be assigned to both channels. otherwise, the message buffer configuration is illegal and the result of the message buffer search is not defined. message buffer frame id registers (fr_mbfidrn) table 872. fr_mbccfrn field description field description mtm message buffer transmission mode ? this control bit applies only to transmit message buffers and defines the transmission mode. 0 event transmission mode 1 state transmission mode cha chb channel assignment ? these control bits define the channel assignment and control the receive and transmit behavior of the message buffer according to table 873 . ccfe cycle counter filtering enable ? this control bit is used to enable and disable the cycle counter filtering. 0 cycle counter filtering disabled 1 cycle counter filtering enabled ccfmsk cycle counter filtering mask ? this field defines the filter mask for the cycle counter filtering. ccfval cycle counter filtering value ? this field defines the filter value for the cycle counter filtering. table 873. channel assignment description cha chb transmit message buffer receive message buffer static segment dynamic segment static segment dynamic segment 11 transmit on both channel a and channel b reserved (function not available) store first valid frame received on either channel a or channel b reserved (function not available) 0 1 transmit on channel b transmit on channel b store first valid frame received on channel b store first valid frame received on channel b 1 0 transmit on channel a transmit on channel a store first valid frame received on channel a store first valid frame received on channel a 0 0 no frame transmission no frame transmission no frame stored no frame stored figure 937. message buffer frame id registers (fr_mbfidrn) base + 0x0104 (fr_mbfidr0) base + 0x010c (fr_mbfidr1) ... base + 0x04fc (fr_mbfidr127) 16-bit write access required write: poc:config or mb_dis 0123456789101112131415 r00000 fid w reset00000??????????? RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1547/1740 message buffer index registers (fr_mbidxrn) 33.6 functional description this section provides a detailed description of the functionality implemented in the cc. 33.6.1 message buffer concept the cc uses a data structure called message buffer to store frame data, configuration, control, and status data. each message buffer consists of two parts, the message buffer control data and the physical message buffer. the message buffer control data are located in dedicated registers. the structure of the message buffer control data depends on the message buffer type and is described in section 33.6.3, message buffer types . the physical message buffer is located in the flexray memory area and is described in section 33.6.2, physical message buffer . 33.6.2 physical message buffer all flexray messages and related frame and slot status information of received frames and of frames to be transmitted to the flexray bus are stored in data structures called physical message buffers . the physical message buffers are located in the flexray memory area.the structure of a physical message buffer is depicted in figure 939 . table 874. fr_mbfidrn field description field description fid frame id ? the semantic of this field depends on the message buffer transfer type. ? receive message buffer: this field is used as a filter value to determine if the message buffer is used for reception of a message received in a slot with the slot id equal to fid. ? transmit message buffer: this field is used to determine the slot in which the message in this message buffer should be transmitted. figure 938. message buffer index registers (fr_mbidxrn) base + 0x0106 (fr_mbidxr0) base + 0x010e (fr_mbidxr1) ... base + 0x04fe (fr_mbidxr127) 16-bit write access required write: poc:config or mb_dis 0123456789101112131415 r00000000 mbidx w reset00000000???????? table 875. fr_mbidxrn field description field description mbidx message buffer index ? this field provides the index of the message buffer header field of the physical message buffer that is currently associated with this message buffer. the application writes the index of the initially associated message buffer header field into this register. the cc updates this register after frame reception or transmission. flexray communication controller (flexray) RM0029 1548/1740 doc id 15177 rev 8 a physical message buffer consists of two fields, the message buffer header field and the message buffer data field . the message buffer header field contains the frame header , the data field offset , and the slot status .the message buffer data field contains the frame data . the connection between the two fields is established by the data field offset . figure 939. physical message buffer structure message buffer header field the message buffer header field is a contiguous region in the flexray memory area and occupies ten bytes. it contains the frame header, the data field offset, and the slot status. its structure is shown in figure 939 . the physical start address sadr_mbhf of the message buffer header field must be 16-bit aligned. frame header the frame header occupies the first six bytes in the message buffer header field. it contains all flexray frame header related information according to the flexray communications system protocol specification, version 2.1 rev a . a detailed description of the usage and the content of the frame header is provided in section , frame header description . data field offset the data field offset follows the frame header in the message buffer data field and occupies two bytes. it contains the offset of the corresponding message buffer data field with respect to the cc flexray memory area base address as provided by smba field in the system memory base address register (fr_symbadr) . the data field offset is used to determine the start address sadr_mbdf of the corresponding message buffer data field in the flexray memory area according to equation 44 . equation 44 sadr_mbdf = [data field offset] + smba slot status the slot status occupies the last two bytes of the message buffer header field. it provides the slot and frame status related information according to the flexray communications system protocol specification, version 2.1 rev a . a detailed description of the content and usage of the slot status is provided in section , slot status description . message buffer data field the message buffer data field is a contiguous area of 2-byte entities. this field contains the frame payload data, or a part of it, of the frame to be transmitted to or received from the data field offset frame data message buffer header field message buffer data field slot status frame header sadr_mbdf sadr_mbhf flexray memory RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1549/1740 flexray bus. the minimum length of this field depends on the specific message buffer configuration and is specified in the message buffer descriptions given in section 33.6.3, message buffer types . 33.6.3 message buffer types the cc provides three different types of message buffers. individual message buffers receive shadow buffers receive fifo buffers for each message buffer type the structure of the physical message buffer is identical. the message buffer types differ only in the structure and content of message buffer control data, which control the related physical message buffer. the message buffer control data are described in the following sections. individual message buffers the individual message buffers are used for all types of frame transmission and for dedicated frame reception based on individual filter settings for each message buffer. the cc supports three types of individual message buffers, which are described in section 33.6.6, individual message buffer functional description . each individual message buffer consists of two parts, the physical message buffer, which is located in the flexray memory area, and the message buffer control data, which are located in dedicated registers. the structure of an individual message buffer is given in figure 940 . each individual message buffer has a message buffer number n assigned, which determines the set of message buffer control registers associated to this individual message buffer. the individual message buffer with message buffer number n is controlled by the registers fr_mbccsrn, fr_mbccfrn, fr_mbfidrn, and fr_mbidxrn. the connection between the message buffer control registers and the physical message buffer is established by the message buffer index field mbidx in the message buffer index registers (fr_mbidxrn) . the start address sadr_mbhf of the related message buffer header field in the flexray memory area is determined according to equation 45 . equation 45 sadr_mbhf = (fr_mbidxrn[mbidx] * 10) + smba flexray communication controller (flexray) RM0029 1550/1740 doc id 15177 rev 8 figure 940. individual message buffer structure individual message buffer segments the set of the individual message buffers can be split up into two message buffer segments using the message buffer segment size and utilization register (fr_mbssutr) . all individual message buffers with a message buffer number n< fr_mbssutr[last_mb_seg1] belong to the first message buffer segment. all individual message buffers with a message buffer number n > fr_mbssutr[last_mb_seg1] belong to the second message buffer segment. the following rules apply to the length of the message buffer data field: all physical message buffers associated to individual message buffers that belong to the same message buffer segment must have message buffer data fields of the same length the minimum length of the message buffer data field for individual message buffers in the first message buffer segment is 2 * fr_mbdsr[mbseg1ds] bytes the minimum length of the message buffer data field for individual message buffers assigned to the second segment is 2 * fr_mbdsr[mbseg2ds] bytes. receive shadow buffers the receive shadow buffers are required for the frame reception process for individual message buffers. the cc provides four receive shadow buffers, one receive shadow buffer per channel and per message buffer segment. each receive shadow buffer consists of two parts, the physical message buffer located in the flexray memory area and the receive shadow buffer control registers located in dedicated registers. the structure of a receive shadow buffer is shown in figure 941 . the four internal shadow buffer control registers can be accessed by the receive shadow buffer index register (fr_rsbir) . the connection between the receive shadow buffer control register and the physical message buffer for the selected receive shadow buffer is established by the receive shadow buffer index field rsbidx in the receive shadow buffer index register (fr_rsbir) . the start address sadr_mbhf of the related message buffer header field in the flexray memory area is determined according to equation 46 . fr_mbfidrn message buffer control registers fr_mbccsrn fr_mbccfrn fr_mbidxrn (min) fr_mbdsr[mbseg1ds] * 2 bytes / fr_mbdsr[mbseg2ds] * 2 bytes data field offset frame data message buffer header field message buffer data field slot status frame header sadr_mbdf sadr_mbhf flexray memory RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1551/1740 equation 46 sadr_mbhf = (fr_rsbir[rsbidx] * 10) + smba the length required for the message buffer data field depends on the message buffer segment that the receive shadow buffer is assigned to. for the receive shadow buffers assigned to the first message buffer segment, the length must be the same as for the individual message buffers assigned to the first message buffer segment. for the receive shadow buffers assigned to the second message buffer segment, the length must be the same as for the individual message buffers assigned to the second message buffer segment. the receive shadow buffer assignment is described in receive shadow buffer index register (fr_rsbir) . figure 941. receive shadow buffer structure receive fifo the receive fifo implements a frame reception system based on the fifo concept. the cc provides two independent receive fifos, one per channel. a receive fifo consists of a set of physical message buffers in the flexray memory area and a set of receive fifo control registers located in dedicated registers. the structure of a receive fifo is given in figure 942 . the connection between the receive fifo control registers and the set of physical message buffers is established by the receive fifo start index register (fr_rfsir) , the receive fifo depth and size register (rfdsr) , and the receive fifo a read index register (fr_rfarir) / receive fifo b read index register (fr_rfbrir) . the system memory base address smba is defined by the system memory base address register selected by the fifo address mode bit fr_mcr[fam]. the start byte address sadr_mbhf[1] of the first message buffer header field that belongs to the receive fifo in the flexray memory area is determined according to equation 47 . equation 47 sadr_mbhf[1] = (10 * fr_rfsir[sidx]) + smba fr_rsbidx[3] fr_rsbidx[2] fr_rsbidx[1] fr_rsbidx[0] receive shadow buffer control registers (min) fr_mbdsr[mbseg1ds] * 2 bytes / fr_mbdsr[mbseg2ds] * 2 bytes data field offset frame data message buffer header field message buffer data field slot status frame header sadr_mbdf sadr_mbhf flexray memory flexray communication controller (flexray) RM0029 1552/1740 doc id 15177 rev 8 the start byte address sadr_mbhf[n] of the last message buffer header field that belongs to the receive fifo in the flexray memory area is determined according to equation 48 . equation 48 sadr_mbhf[n] = (10 * (fr_rfsir[sidx] + rfdsr[fifo_depth])) + smba note: all message buffer header fields assigned to a receive fifo must be a contiguous region. figure 942. receive fifo structure message buffer configuration and control data this section describes the configuration and control data for each message buffer type. individual message buffer configuration data before an individual message buffer can be used for transmission or reception, it must be configured. there is a set of common configuration parameters that applies to all individual message buffers and a set of configuration parameters that applies to each message buffer individually. fr_rfbrir fr_rfdsr[b] fr_rfsir[b] fr_rfarir fr_rfdsr[a] fr_rfsir[a] frame header[1] slot status[1] data field offset[1] receive fifo control register message buffer header fields message buffer data fields frame header[n] slot status[n] data field offset[n] (min) rfdsr[entry_size] * 2 bytes rfdsr[fifo_depth] + frame header[i] slot status[i] data field offset[i] frame data[n] sadr_mbdf[n] frame data[i] sadr_mbdf[i] frame data[1] sadr_mbdf[1] rfdsr[fifo_depth] sadr_mbhf[n] sadr_mbhf[i] sadr_mbhf[1] flexray memory RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1553/1740 common configuration data the set of common configuration data for individual message buffers is located in the following registers. message buffer data size register (fr_mbdsr) the mbseg2ds and mbseg1ds fields define the minimum length of the message buffer data field with respect to the message buffer segment. message buffer segment size and utilization register (fr_mbssutr) the last_mb_seg1 and last_mb_util fields define the segmentation of the individual message buffers and the number of individual message buffers that are used. for more details, see section , individual message buffer segments specific configuration data the set of message buffer specific configuration data for individual message buffers is located in the following registers. message buffer configuration, control, status registers (fr_mbccsrn) the mcm, mbt, mtd bits configure the message buffer type. message buffer cycle counter filter registers (fr_mbccfrn) the mtm, cha, chb bits configure the transmission mode and the channel assignment. the ccfe, ccfmsk, and ccfval bits and fields configure the cycle counter filter. message buffer frame id registers (fr_mbfidrn) for a transmit message buffer, the fid field is used to determine the slot in which the message in this message buffer will be transmitted. message buffer index registers (fr_mbidxrn) this mbidx field provides the index of the message buffer header field of the physical message buffer that is currently associated with this message buffer. individual message buffer control data during normal operation, each individual message buffer can be controlled by the control and trigger bits cmt, lckt, edt, and mbie in the message buffer configuration, control, status registers (fr_mbccsrn) . receive shadow buffer configuration data before frame reception into the individual message buffers can be performed, the receive shadow buffers must be configured. the configuration data are provided by the receive shadow buffer index register (fr_rsbir) . for each receive shadow buffer, the application provides the message buffer header index. when the protocol is in the poc:normal active or poc:normal passive state, the receive shadow buffers are under full cc control. receive fifo control and configuration data this section describes the configuration and control data for the two receive fifos. receive fifo configuration data the cc provides two functional independent receive fifos, one per channel. the fifos have a common subset of configuration data: receive fifo system memory base address register (fr_rfsymbadr) receive fifo periodic timer register (fr_rfptr) flexray communication controller (flexray) RM0029 1554/1740 doc id 15177 rev 8 each fifo has its own set of configuration data. the configuration data are located in the following registers: receive fifo watermark and selection register (fr_rfwmsr) receive fifo start index register (fr_rfsir) receive fifo depth and size register (rfdsr) receive fifo message id acceptance filter value register (fr_rfmidafvr) receive fifo message id acceptance filter mask register (fr_rfmidafmr) receive fifo frame id rejection filter value register (fr_rffidrfvr) receive fifo frame id rejection filter mask register (fr_rffidrfmr) receive fifo range filter configuration register (fr_rfrfcfr) receive fifo control data the application can access the fifos at any time using the control bits in the following registers: global interrupt flag and enable register (fr_gifer) receive fifo fill level and pop count register (fr_rfflpcr) receive fifo status data the current status of the receive fifo is provided in the following register: global interrupt flag and enable register (fr_gifer) receive fifo a read index register (fr_rfarir) receive fifo b read index register (fr_rfbrir) receive fifo fill level and pop count register (fr_rfflpcr) 33.6.4 flexray memory area layout the cc supports a wide range of possible layouts for the flexray memory area. two basic layout modes can be selected by the fifo address mode bit fr_mcr[fam]. flexray memory area layout (fr_mcr[fam] = 0) figure 943 shows an example layout for the fifo address mode fr_mcr[fam] = 0. in this mode, the following set of rules applies to the layout of the flexray memory area: the flexray memory area is one contiguous region. the flexray memory area size is maximum 64 kbytes. the flexray memory area starts at a 16 byte boundary the flexray memory area contains three areas: the message buffer header area , the message buffer data area , and the sync frame table area . RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1555/1740 figure 943. example of flexray memory area layout (fr_mcr[fam] = 0) flexray memory area layout (fr_mcr[fam] = 1) figure 944 shows an example layout for the fifo address mode fr_mcr[fam] = 1. the following set of rules applies to the layout of the flexray memory area: the flexray memory area consists of two contiguous regions. the size of each region is maximum 64 kbytes. each region start at a 16 byte boundary. message buffer header area flexray memory area message buffer data area sync frame table area data field offset frame header slot status data field offset frame header slot status message buffer header fields individual message buffers receive shadow buffers data field offset frame header slot status data field offset frame header slot status message buffer header fields receive fifo a data field offset frame header slot status data field offset frame header slot status message buffer header fields receive fifo b data field offset frame header slot status 10 bytes fr_symbadr[smba] system memory flexray communication controller (flexray) RM0029 1556/1740 doc id 15177 rev 8 figure 944. example of flexray memory area layout (fr_mcr[fam] = 1) message buffer header area (fr_mcr[fam] = 0) the message buffer header area contains all message buffer header fields of the physical message buffers for all message buffer types. the following rules apply to the message buffer header fields for the three type of message buffers. 1. the start byte address sadr_mbhf of each message buffer header field for individual message buffers and receive shadow buffers must fulfill equation 49 . equation 49 sadr_mbhf = (i * 10) + fr_symbadr[smba]; (0 < i < 256) 2. the start byte address sadr_mbhf of each message buffer header field for the fifo must fulfill equation 50 . equation 50 sadr_mbhf = (i * 10) + fr_symbadr[smba]; (0 < i < 1024) fifo header area fifo flexray memory data field offset frame header slot status data field offset frame header slot status message buffer header fields receive fifo a data field offset frame header slot status data field offset frame header slot status message buffer header fields receive fifo b fr_rfsymbadr[smba] system memory message buffer header area flexray memory message buffer data area sync frame table area data field offset frame header slot status data field offset frame header slot status message buffer header fields individual message buffers receive shadow buffers data field offset frame header slot status 10 bytes fr_symbadr[smba] fifo message buffer data area RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1557/1740 equation 51 sadr_mbhf = (i * 10) + fr_symbadr[smba]; (0 < i < 1024) 3. the message buffer header fields for each fifo have to be a contiguous area. message buffer header area (fr_mcr[fam] = 1) the message buffer header area contains all message buffer header fields of the physical message buffers for the individual message buffers and receiver shadow buffers. the following rules apply to the message buffer header fields for the two type of message buffers. 1. the start address sadr_mbhf of each message buffer header field for individual message buffers and receive shadow buffers must fulfill equation 52 . equation 52 sadr_mbhf = (i * 10) + fr_symbadr[smba]; (0 < i < 256) fifo message buffer header area (fr_mcr[fam] = 1) the fifo message buffer header area contains all message buffer header fields of the physical message buffers for the fifo. the following rules apply to the fifo message buffer header fields. 1. the start byte address sadr_mbhf of each message buffer header field for the fifo must fulfill equation 53 . equation 53 sadr_mbhf = (i * 10) + fr_rfsymbadr[smba]; (0 < i < 1024) 2. the message buffer header fields for each fifo have to be a contiguous area. message buffer data area the message buffer data area contains all the message buffer data fields of the physical message buffers. each message buffer data field must start at a 16-bit boundary. sync frame table area the sync frame table area is used to provide a copy of the internal sync frame tables for application access. refer to section 33.6.12, sync frame id and sync frame deviation tables for the description of the sync frame table area. 33.6.5 physical message buffer description this section provides a detailed description of the usage and the content of the two parts of a physical message buffer, the message buffer header field and the message buffer data field. message buffer protection and data consistency the physical message buffers are located in the flexray memory area. the cc provides no means to protect the flexray memory area from uncontrolled or illegal host or other client write access. to ensure data consistency of the physical message buffers, the application must follow the write access scheme that is given in the description of each of the physical message buffer fields. flexray communication controller (flexray) RM0029 1558/1740 doc id 15177 rev 8 message buffer header field description this section provides a detailed description of the usage and content of the message buffer header field. a description of the structure of the message buffer header fields is given in section , message buffer header field . each message buffer header field consists of three sections: the frame header section, the data field offset, and the slot status section. for a detailed description of the data field offset, see section , data field offset . frame header description frame header content the semantic and content of the frame header section depends on the message buffer type. for individual receive message buffers and receive fifos, the frame header receives the frame header data of the first valid frame received on the assigned channels. for receive shadow buffers, the frame header receives the frame header data of the current frame received regardless of whether the frame is valid or not. for transmit message buffers, the application writes the frame header of the frame to be transmitted into this location. the frame header will be read out when the frame is transferred to the flexray bus. the structure of the frame header in the message buffer header field for receive message buffers and the receive fifo is given in figure 945 . a detailed description is given in ta ble 87 7 . figure 945. frame header structure (receive message buffer and receive fifo) the structure of the frame header in the message buffer header field for transmit message buffers is given in figure 946 . a detailed description is given in ta ble 87 8 . the checks that will be performed are described in frame header checks . figure 946. frame header structure (transmit message buffer) 0123456789101112131415 0x0 r ppi nuf syf suf fid 0x2 0 0 cyccnt 0 pldlen 0x400000 hdcrc 0123456789101112131415 0x0 r ppi nuf syf suf fid 0x2 cyccnt pldlen 0x4 hdcrc = not used = checked = checked if static slot RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1559/1740 the structure of the frame header in the message buffer header field for transmit message buffers assigned to key slot is given in figure 947 . figure 947. frame header structure (transmit message buffer for key slot) frame header access the frame header is located in the flexray memory area. to ensure data consistency, the application must follow the write access scheme described below. for receive message buffers, receive shadow buffers, and receive fifos, the application must not write to the frame header field. for transmit message buffers, the application must follow the write access restrictions given in ta ble 87 6 . this table shows the condition under which the application can write to the frame header entries without corrupting the flexray message transmission. frame header checks as shown in figure 946 and figure 947 not all fields in the message buffer frame header are used for transmission. some fields in the message buffer frame header are ignored, some are used for transmission, and some of them are checked for correct values. all checks that will be performed are described below. for message buffers assigned to the key slot, no checks will be performed. the value of the fid field must be equal to the value of the corresponding message buffer frame id registers (fr_mbfidrn) . if the cc detects a mismatch while transmitting the frame header, it will set the frame id error flag fid_ef in the chi error flag register 0123456789101112131415 0x0 r ppi nuf syf suf fid 0x2 cyccnt pldlen 0x4 hdcrc = not used table 876. frame header write access constraints (transmit message buffer) field single buffered segments double buffered segments static dynamic static dynamic commit side transmit side commit side transmit side fid poc:config or mb_dis ppi, pldlen , hdcrc poc:config or mb_dis or mb_lck mb_lck flexray communication controller (flexray) RM0029 1560/1740 doc id 15177 rev 8 (fr_chierfr) . the value of the fid field will be ignored and replaced by the value provided in the message buffer frame id registers (fr_mbfidrn) . for transmit message buffers assigned to the static segment, the pldlen value must be equal to the value of the payload_length_static field in the protocol configuration register 19 (fr_pcr19) . if this is not fulfilled, the static payload length error flag spl_ef in the chi error flag register (fr_chierfr) is set when the message buffer is under transmission. a syntactically and semantically correct frame is generated with payload_length_static payload words and the payload length field in the transmitted frame header set to payload_length_static. for transmit message buffers assigned to the dynamic segment, the pldlen value must be less than or equal to the value of the max_payload_length_dynamic field in the protocol configuration register 24 (fr_pcr24) . if this is not fulfilled, the dynamic payload length error flag dpl_ef in the chi error flag register (fr_chierfr) is set when the message buffer is under transmission. a syntactically and semantically correct dynamic frame is generated with pldlen payload words and the payload length field in the frame header set to pldlen. table 877. frame header field description (receive message buffer and receive ffo) field description r reserved bit ? this is the value of the reserved bit of the received frame stored in the message buffer ppi payload preamble indicator ? this is the value of the payload preamble indicator of the received frame stored in the message buffer. nuf null frame indicator ? this is the value of the null frame indicator of the received frame stored in the message buffer. syf sync frame indicator ? this is the value of the sync frame indicator of the received frame stored in the message buffer. suf startup frame indicator ? this is the value of the startup frame indicator of the received frame stored in the message buffer. fid frame id ? this is the value of the frame id field of the received frame stored in the message buffer. cyccnt cycle count ? this is the number of the communication cycle in which the frame stored in the message buffer was received. pldlen payload length ? this is the value of the payload length field of the received frame stored in the message buffer. hdcrc header crc ? this is the value of the header crc field of the received frame stored in the message buffer. table 878. frame header field description (transmit message buffer) field description r reserved bit ? this bit is not used, the value of the reserved bit is generated internally according to flexray communications system protocol specification, version 2.1 rev a . ppi payload preamble indicator ? this bit provides the value of the payload preamble indicator for the frame transmitted from the message buffer. nuf null frame indicator ? this bit is not used, the value of the null frame indicator is generated internally according to flexray communications system protocol specification, version 2.1 rev a . RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1561/1740 data field offset description data field offset content for a detailed description of the data field offset, see section , data field offset . data field offset access the application shall program the data field offset when configuring the message buffers either in the poc:config state or when the message buffer is disabled. slot status description the slot status is a read-only structure for the application and a write-only structure for the cc. the meaning and content of the slot status in the message buffer header field depends on the message buffer type. receive message buffer and receive fifo slot status description this section describes the slot status structure for the individual receive message buffers and receive fifos. the content of the slot status structure for receive message buffers depends on the message buffer type and on the channel assignment for individual receive message buffers as given by table 879 . the meaning of the bits in the slot status structure is explained in table 880 . syf sync frame indicator ? this bit is not used, the value of the sync frame indicator is generated internally according to flexray communications system protocol specification, version 2.1 rev a . suf startup frame indicator ? this bit is not used, the value of the startup frame indicator is generated internally according to flexray communications system protocol specification, version 2.1 rev a . fid frame id ? this field is checked as described in frame header checks . cyccnt cycle count ? this field is not used, the value of the transmitted cycle count field is taken from the internal communication cycle counter. pldlen payload length ? this field is checked and used as described in frame header checks . hdcrc header crc ? this field provides the value of the header crc field for the frame transmitted from the message buffer. table 878. frame header field description (transmit message buffer) field description table 879. receive message buffer slot status content receive message buffer type slot status content individual receive message buffer assigned to both channels fr_mbccfrn[cha] = 1 and fr_mbccfrn[chb] = 1 see figure 948 individual receive message buffer assigned to channel a fr_mbccfrn[cha] = 1 and fr_mbccfrn[chb] = 0 see figure 949 individual receive message buffer assigned to channel b fr_mbccfrn[cha] = 0 and fr_mbccfrn[chb] = 1 see figure 950 receive fifo channel a message buffer see figure 949 receive fifo channel b message buffer see figure 950 flexray communication controller (flexray) RM0029 1562/1740 doc id 15177 rev 8 figure 948. receive message buffer slot status structure (chab) figure 949. receive message buffer slot status structure (cha) figure 950. receive message buffer slot status structure (chb) 0123456789101112131415 r vfb syb nfb sub seb ceb bvb ch vfa sya nfa sua sea cea bva 0 reset???????????????? 0123456789101112131415 r00000000vfasyanfasuaseaceabva0 reset???????????????? 0123456789101112131415 r vfb syb nfb sub seb ceb bvb 1 0 0 0 0 0 0 0 0 reset???????????????? table 880. receive message buffer slot status field description ) field description common message buffer status bits vfb valid frame on channel b ? protocol related variable: vss!validframe channel b 0 vss!validframe = 0 1 vss!validframe = 1 syb sync frame indicator channel b ? protocol related variable: vrf!header!syfindicator channel b 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfb null frame indicator channel b ? protocol related variable: vrf!header!nfindicator channel b 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sub startup frame indicator channel b ? protocol related variable: vrf!header!sufindicator channel b 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 seb syntax error on channel b ? protocol related variable: vss!syntaxerror channel b 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 ceb content error on channel b ? protocol related variable: vss!contenterror channel b 0 vss!contenterror = 0 1 vss!contenterror = 1 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1563/1740 transmit message buffer slot status description this section describes the slot status structure for transmit message buffers. only the tca and tcb status bits are directly related to the transmission process. all other status bits in this structure are related to a receive process that may have occurred. the content of the slot status structure for transmit message buffers depends on the channel assignment as given by table 881 . bvb boundary violation on channel b ? protocol related variable: vss!bviolation channel b 0 vss!bviolation = 0 1 vss!bviolation = 1 ch channel first valid received ? this status bit applies only to receive message buffers assigned to the static segment and to both channels. it indicates the channel that has received the first valid frame in the slot. this flag is set to 0 if no valid frame was received at all in the subscribed slot. 0 first valid frame received on channel a, or no valid frame received at all 0 first valid frame received on channel b vfa valid frame on channel a ? protocol related variable: vss!validframe channel a 0 vss!validframe = 0 1 vss!validframe = 1 sya sync frame indicator channel a ? protocol related variable: vrf!header!syfindicator channel a 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfa null frame indicator channel a ? protocol related variable: vrf!header!nfindicator channel a 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sua startup frame indicator channel a ? protocol related variable: vrf!header!sufindicator channel a 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 sea syntax error on channel a ? protocol related variable: vss!syntaxerror channel a 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 cea content error on channel a ? protocol related variable: vss!contenterror channel a 0 vss!contenterror = 0 1 vss!contenterror = 1 bva boundary violation on channel a ? protocol related variable: vss!bviolation channel a 0 vss!bviolation = 0 1 vss!bviolation = 1 table 880. receive message buffer slot status field description (continued)) field description table 881. transmit message buffer slot status content transmit message buffer type slot status content individual transmit message buffer assigned to both channels fr_mbccfrn[cha] = 1 and fr_mbccfrn[chb] = 1 see figure 951 flexray communication controller (flexray) RM0029 1564/1740 doc id 15177 rev 8 the meaning of the bits in the slot status structure is described in ta ble 88 0 . figure 951. transmit message buffer slot status structure (chab) figure 952. transmit message buffer slot status structure (cha) figure 953. transmit message buffer slot status structure (chb) individual transmit message buffer assigned to channel a fr_mbccfrn[cha] = 1 and fr_mbccfrn[chb] = 0 see figure 952 individual transmit message buffer assigned to channel b fr_mbccfrn[cha] = 0 and fr_mbccfrn[chb] = 1 see figure 953 table 881. transmit message buffer slot status content transmit message buffer type slot status content 0123456789101112131415 r vfb syb nfb sub seb ceb bvb tcb vfa sya nfa sua sea cea bva tca reset???????????????? 0123456789101112131415 r00000000vfasyanfasuaseaceabvatca reset???????????????? 0123456789101112131415 r vfb syb nfb sub seb ceb bvb tcb 0 0 0 0 0 0 0 0 reset???????????????? table 882. transmit message buffer slot status structure field description field description vfb valid frame on channel b ? protocol related variable: vss!validframe channel b 0 vss!validframe = 0 1 vss!validframe = 1 syb sync frame indicator channel b ? protocol related variable: vrf!header!syfindicator channel b 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfb null frame indicator channel b ? protocol related variable: vrf!header!nfindicator channel b 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1565/1740 sub startup frame indicator channel b ? protocol related variable: vrf!header!sufindicator channel b 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 seb syntax error on channel b ? protocol related variable: vss!syntaxerror channel b 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 ceb content error on channel b ? protocol related variable: vss!contenterror channel b 0 vss!contenterror = 0 1 vss!contenterror = 1 bvb boundary violation on channel b ? protocol related variable: vss!bviolation channel b 0 vss!bviolation = 0 1 vss!bviolation = 1 tcb transmission conflict on channel b ? protocol related variable: vss!txconflict channel b 0 vss!txconflict = 0 1 vss!txconflict = 1 vfa valid frame on channel a ? protocol related variable: vss!validframe channel a 0 vss!validframe = 0 1 vss!validframe = 1 sya sync frame indicator channel a ? protocol related variable: vrf!header!syfindicator channel a 0 vrf!header!syfindicator = 0 1 vrf!header!syfindicator = 1 nfa null frame indicator channel a ? protocol related variable: vrf!header!nfindicator channel a 0 vrf!header!nfindicator = 0 1 vrf!header!nfindicator = 1 sua startup frame indicator channel a ? protocol related variable: vrf!header!sufindicator channel a 0 vrf!header!sufindicator = 0 1 vrf!header!sufindicator = 1 sea syntax error on channel a ? protocol related variable: vss!syntaxerror channel a 0 vss!syntaxerror = 0 1 vss!syntaxerror = 1 cea content error on channel a ? protocol related variable: vss!contenterror channel a 0 vss!contenterror = 0 1 vss!contenterror = 1 bva boundary violation on channel a ? protocol related variable: vss!bviolation channel a 0 vss!bviolation = 0 1 vss!bviolation = 1 tca transmission conflict on channel a ? protocol related variable: vss!txconflict channel a 0 vss!txconflict = 0 1 vss!txconflict = 1 table 882. transmit message buffer slot status structure field description field description flexray communication controller (flexray) RM0029 1566/1740 doc id 15177 rev 8 message buffer data field description the message buffer data field is used to store the frame payload data, or a part of it, of the frame to be transmitted to or received from the flexray bus. the minimum required length of this field depends on the message buffer type that the physical message buffer is assigned to and is given in table 883 . the structure of the message buffer data field is given in figure 954 . note: the cc will not access any locations outside the message buffer data field boundaries given by table 883 . figure 954. message buffer data field structure the message buffer data field is located in the flexray memory area; thus, the cc has no means to control application write access to the field. to ensure data consistency, the application must follow a write and read access scheme. message buffer data field read access for transmit message buffers, the cc will not modify the content of the message buffer data field. thus the application can read back the data at any time without any impact on data consistency. for receive message buffers the application must lock the related receive message buffer and retrieve the message buffer header index from the message buffer index registers (fr_mbidxrn) . while the message buffer is locked, the cc will not update the message buffer data field. for receive fifos, the application can read the message buffer indicated by the receive fifo a read index register (fr_rfarir) or the receive fifo b read index register (fr_rfbrir) when the related fill levels in the receive fifo fill level and pop count register (fr_rfflpcr) indicate an non-empty fifo. table 883. message buffer data field minimum length physical message buffer assigned to minimum length defined by individual message buffer in segment 1 fr_mbdsr[mbseg1ds] receive shadow buffer in segment 1 fr_mbdsr[mbseg1ds] individual message buffer in segment 2 fr_mbdsr[mbseg2ds] receive shadow buffer in segment 2 fr_mbdsr[mbseg2ds] receive fifo for channel a fr_rfdsr[entry_size] (fr_rfwmsr[sel] = 0) receive fifo for channel b fr_rfdsr[entry_size] (fr_rfwmsr[sel] = 1) 0123456789101112131415 0x0 data0 / mid0 / nmv0 data1 / mid1 / nmv1 0x2 data2 / nmv2 data3 / nmv3 ... ... ... 0xn-2 data n-2 data n-1 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1567/1740 message buffer data field write access for receive message buffers, receive shadow buffers, and receive fifos, the application must not write to the message buffer data field. for transmit message buffers, the application must follow the write access restrictions given in ta ble 88 4 . 33.6.6 individual message buffer functional description the cc provides three basic types of individual message buffers: 1. single transmit message buffers 2. double transmit message buffers 3. receive message buffers before an individual message buffer can be used, it must be configured by the application. after the initial configuration, the message buffer can be reconfigured later. the set of the configuration data for individual message buffers is given in section , individual message buffer configuration data . individual message buffer configuration the individual message buffer configuration consists of two steps. 1. the first step is the allocation of the required amount of memory for the flexray memory area. 2. the second step is the programming of the message buffer configuration registers, which is described in this section. table 884. frame data write access constraints field single buffered double buffered commit side transmit side data, mid, nmv poc:config or mb_dis or mb_lck poc:config or mb_dis or mb_lck poc:config or mb_dis table 885. frame data field description field description data 0, data 1, ... data n-1 message data ? provides the message data received or to be transmitted. for receive message buffer and receive fifos, this field provides the message data received for this message buffer. for transmit message buffers, the field provides the message data to be transmitted. mid 0, mid 1 message identifier ? if the payload preamble bit ppi is set in the message buffer frame header, the mid field holds the message id of a dynamic frame located in the message buffer. the receive fifo filter uses the received message id for message id filtering. nmv 0, nmv 1, ... nmv 11 network management vector ? if the payload preamble bit ppi is set in the message buffer frame header, the network management vector field holds the network management vector of a static frame located in the message buffer. the mid and nmv bytes replace the corresponding data bytes. flexray communication controller (flexray) RM0029 1568/1740 doc id 15177 rev 8 common configuration data one part of the message buffer configuration data is common to all individual message buffers and the receive shadow buffers. these data can only be set when the protocol is in the poc:config state. the application configures the number of utilized individual message buffers by writing the message buffer number of the last utilized message buffer into the last_mb_util field in the message buffer segment size and utilization register (fr_mbssutr) . the application configures the size of the two segments of individual message buffers by writing the message buffer number of the last message buffer in the first segment into the last_mb_seg1 field in the message buffer segment size and utilization register (fr_mbssutr) the application configures the length of the message buffer data fields for both of the message buffer segments by writing to the mbseg2ds and mbseg1ds fields in the message buffer data size register (fr_mbdsr) . depending on the current receive functionality of the cc, the application must configure the receive shadow buffers. for each segment and for each channel with at least one individual receive message buffer assigned, the application must configure the related receive shadow buffer using the receive shadow buffer index register (fr_rsbir) . specific configuration data the second part of the message buffer configuration data is specific for each message buffer. these data can be changed only when either the protocol is in the poc:config state or the message buffer is disabled, that is, fr_mbccsrn[eds] = 0 the individual message buffer type is defined by the mtd and mbt bits in the message buffer configuration, control, status registers (fr_mbccsrn) as given in table 886 . the message buffer specific configuration data are 1. mcm, mbt, mtd bits in message buffer configuration, control, status registers (fr_mbccsrn) 2. all fields and bits in message buffer cycle counter filter registers (fr_mbccfrn) 3. all fields and bits in message buffer frame id registers (fr_mbfidrn) 4. all fields and bits in message buffer index registers (fr_mbidxrn) table 886. individual message buffer types fr_mbccsrn individual message buffer description mtd mbt 0 0 receive message buffer 01 reserved 1 0 single transmit message buffer 1 1 double transmit message buffer RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1569/1740 the meaning of the specific configuration data depends on the message buffer type, as given in the detailed message buffer type descriptions section , single transmit message buffers , section , receive message buffers , and section , double transmit message buffer . single transmit message buffers the section provides a detailed description of the functionality of single buffered transmit message buffers. a single transmit message buffer is used by the application to provide message data to the cc that will be transmitted over the flexray bus. the cc uses the transmit message buffers to provide information about the transmission process and status information about the slot in which message was transmitted. the individual message buffer with message buffer number n is configured to be a single transmit message buffer by the following settings: fr_mbccsrn[mbt] = 0 (single buffered message buffer) fr_mbccsrn[mtd] = 1 (transmit message buffer) access regions to certain message buffer fields, both the application and the cc have access. to ensure data consistency, a message buffer locking scheme is implemented, which is used to control the access to the data, control, and status bits of a message buffer. the access regions for single transmit message buffers are depicted in figure 955 . a description of the regions is given in table 887 . if an region is active as indicated in table 888 , the access scheme given for that region applies to the message buffer. figure 955. single transmit message buffer access regions message buffer data field: data[0-n] message buffer header field: frame header fr_mbccsrn[cmt] message buffer header field: slot status message buffer header field: data field offset fr_mbccfrn[mtm/cha/chb/ccf*] fr_mbfidrn[fid] fr_mbidxrn[mbidx] fr_mbccsrn[mbt/mtd] tx nf cmt sr cfg msg flexray communication controller (flexray) RM0029 1570/1740 doc id 15177 rev 8 the trigger bits fr_mbccsrn[edt] and fr_mbccsrn[lckt], and the interrupt enable bit fr_mbccsrn[mbie] are not under access control and can be accessed from the application at any time. the status bits fr_mbccsrn[eds] and fr_mbccsrn[lcks] are not under access control and can be accessed from the cc at any time. the interrupt flag fr_mbccsrn[mbif] is not under access control and can be accessed from the application and the cc at any time. cc clear access has higher priority. the cc restricts its access to the regions depending on the current state of the message buffer. the application must adhere to these restrictions in order to ensure data consistency. the transmit message buffer states are given in figure 956 . a description of the states is given in table 888 , which also provides the access scheme for the access regions. the status bits fr_mbccsrn[eds] and fr_mbccsrn[lcks] provide the application with the required message buffer status information. the internal status information is not visible to the application. message buffer states this section describes the transmit message buffer states and provides a state diagram. table 887. single transmit message buffer access regions description region access from region used for application module cfg read/write ? message buffer configuration msg read/write ? message data and slot status access nf ? read-only message header access for null frame transmission tx ? read/write message transmission and slot status update cm ? read-only message buffer validation sr ? read-only message buffer search RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1571/1740 figure 956. single transmit message buffer states hdis reset_state hd he idle sa dss su ccsu ccsa cctx tx hlck hlckccsa ccnf hl hu ccma hl hu hlckccnf hlckccma sss sts he hl sts hu hl dss ma sss hdislck hd hu hl hu sts ma sss sa dss sts dss table 888. single transmit message buffer state description (sheet 1 of 2) state fr_mbccsrn access region description eds lcks appl. module idle 1 0 ? cm, sr idle ? message buffer is idle. included in message buffer search. hdis 0 0 cfg ? dis abled ? message buffer under configuration. excluded from message buffer search. hdislck 0 1 cfg ? dis abled and l ock ed ? message buffer under configuration. excluded from message buffer search. hlck 1 1 msg sr l ock ed ? applications access to data, control, and status. included in message buffer search. ccsa 1 0 ? ? s lot a ssigned ? message buffer assigned to next static slot. ready for null frame transmission. hlckccsa 1 1 msg ? l ock ed and s lot a ssigned ? applications access to data, control, and status.message buffer assigned to next static slot ccnf 1 0 ? nf n ull f rame transmission ? header is used for null frame transmission hlckccnf 1 1 msg nf l ock ed and n ull f rame transmission ? applications access to data, control, and status. header is used for null frame transmission. ccma 1 0 ? cm m essage a vailable ? message buffer is assigned to next slot and cycle counter filter matches. flexray communication controller (flexray) RM0029 1572/1740 doc id 15177 rev 8 message buffer transitions application transitions the application transitions can be triggered by the application using the commands described in table 889 . the application issues the commands by writing to the message buffer configuration, control, status registers (fr_mbccsrn) . only one command can be issued with one write access. each command is executed immediately. if the command is ignored, it must be issued again. message buffer enable and disable the enable and disable commands issued by writing 1 to the trigger bit fr_mbccsrn[edt]. the transition that will be triggered by each of these command depends on the current value of the status bit fr_mbccsrn[eds]. if the command triggers the disable transition hd and the message buffer is in one of the states ccsa , hlckccsa , ccma , hlckccma, ccnf , hlckccnf , or cctx , the disable transition has no effect (command is ignored) and the message buffer state is not changed. no notification is given to the application. if the communication controller is started as a non-coldstart node, and the message buffers are configured and enabled in the poc config state for slot 1, then the message buffer cannot be disabled in the integration_listen state by directly writing 1 to the edt bit. to facilitate this, a freeze command needs to be issued just before running the message buffer disable for slot 1. executing this command enables the message buffer disable during the listen states. message buffer lock and unlock the lock and unlock commands issued by writing 1 to the trigger bit fr_mbccsrn[lckt]. the transition that will be triggered by each of these commands depends on the current value of the status bit fr_mbccsrn[lcks]. if the command triggers the lock transition hl and the message buffer is in the state cctx, the lock transition has no effect (command is ignored) and message buffer state is not changed. in this case, the message buffer lock error flag lck_ef in the chi error flag register (fr_chierfr) is set. hlckccma 1 1 msg ? l ock ed and m essage a vailable ? applications access to data, control, and status. message buffer is assigned to next slot and cycle counter filter matches. cctx 1 0 ? tx message t ransmission ? message buffer data transmit. payload data from buffer transmitted ccsu 1 0 ? tx s tatus u pdate ? message buffer status update. update of status flags, the slot status field, and the header index. table 888. single transmit message buffer stat e description (sheet 1 of 2) (continued) state fr_mbccsrn access region description eds lcks appl. module table 889. single transmit message buffer application transitions transition command condition description he fr_mbccsrn[edt] = 1 fr_mbccsrn[eds] = 0 application triggers message buffer enable hd fr_mbccsrn[eds] = 1 application triggers message buffer disable RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1573/1740 module transitions the module transitions that can be triggered by the cc are described in ta ble 89 0 . each transition will be triggered for certain message buffers when the related condition is fulfilled. transition priorities the application can trigger only one transition at a time. there is no need to specify priorities among them. as shown in the first part of table 891 , the module transitions have a higher priority than the application transitions. for all states except the ccma state, both a lock/unlock transition hl/hd and a module transition can be executed at the same time. the result state is reached by first applying the application transition and subsequently the module transition to the intermediately reached state. for example, if the message buffer is in the hlck state and the application unlocks the message buffer by the hu transition and the module triggers the slot assigned transition sa , the intermediate state is idle and the resulting state is ccsa . the priorities among the module transitions is given in the second part of table 891 . hl fr_mbccsrn[lckt] = 1 fr_mbccsrn[lcks] = 0 application triggers message buffer lock hu fr_mbccsrn[lcks] = 1 application triggers message buffer unlock table 889. single transmit message buffer application transitions (continued) transition command condition description table 890. single transmit me ssage buffer module transitions transition condition description sa slot match and static slot s lot a ssigned ? message buffer is assigned to next static slot. ma slot match and cyclecounter match m essage a vailable ? message buffer is assigned to next slot and cycle counter filter matches. tx slot start and fr_mbccsrn[cmt] = 1 t ransmission slot start ? slot start and commit bit cmt is set. in case of a dynamic slot, platesttx is not exceeded. su status updated s tatus u pdated ? slot status field and message buffer status flags updated. interrupt flag set. sts static slot start st atic slot s tart ? start of static slot. dss dynamic slot start or symbol window start or nit start d ynamic slot or s egment s tart ? start of dynamic slot or symbol window or nit. sss slot start or symbol window start or nit start s lot or s egment s tart ? start of static slot or dynamic slot or symbol window or nit. flexray communication controller (flexray) RM0029 1574/1740 doc id 15177 rev 8 transmit message setup to transmit a message over the flexray bus, the application writes the message data into the message buffer data field and sets the commit bit cmt in the message buffer configuration, control, status registers (fr_mbccsrn) . the physical access to the message buffer data field is described in section , individual message buffers . as indicated by ta ble 88 8 , the application shall write to the message buffer data field and change the commit bit cmt only if the transmit message buffer is in one of the states hdis, hdislck, hlck, hlckccsa, hlckccma, or hlckccma. the application can change the state of a message buffer if it issues the appropriate commands shown in table 889 . the state change is indicated through the fr_mbccsrn[eds] and fr_mbccsrn[lcks] status bits. if the transmit message buffer enters one of the states hdis, hdislck, hlck, hlckccsa, hlckccma, or hlckccma the fr_mbccsrn[dval] flag is negated. message transmission as a result of the message buffer search described in section 33.6.7, individual message buffer search , the cc triggers the message available transition ma for up to two transmit message buffers. this changes the message buffer state from idle to ccma and the message buffers can be used for message transmission in the next slot. the cc transmits a message from a message buffer if both of the following two conditions are fulfilled at the start of the transmission slot: 1. the message buffer is in the message available state ccma 2. the message data are still valid, that is, fr_mbccsrn[cmt] = 1 in this case, the cc triggers the tx transition and changes the message buffer state to cctx . a transmit message buffer timing and state change diagram for message transmission is given in figure 957 . in this example, the message buffer with message buffer number n is idle at the start of the search slot, matches the slot and cycle number of the next slot, and message buffer data are valid, that is, fr_mbccsrn[cmt] = 1. table 891. single transmit message buffer transition priorities state priorities description module versus application idle, hlck sa > hd ma > hd slot assigned > message buffer disable message available > message buffer disable ccma tx > hl transmission start > message buffer lock module internal idle, hlck ma > sa message available > slot assigned ccma tx > sts tx > dss transmission slot start > static slot start transmission slot start > dynamic slot start RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1575/1740 figure 957. message transmission timing figure 958. message transmission from hlck state with unlock the amount of message data read from the flexray memory area and transferred to the flexray bus is determined by the following three items 1. the message buffer segment that the message buffer is assigned to, as defined by the message buffer segment size and utilization register (fr_mbssutr) . 2. the message buffer data field size, as defined by the related field of the message buffer data size register (fr_mbdsr) 3. the value of the pldlen field in the message buffer header field, as described in section , frame header description if a message buffer is assigned to message buffer segment 1, and pldlen > mbseg1ds, then 2 * mbseg1ds bytes will be read from the message buffer data field and zero padding is used for the remaining bytes for the flexray bus transfer. if pldlen < mbseg1ds, the cc reads and transfers 2*pldlen bytes. the same holds for segment 2 and mbseg2ds. null frame transmission a static slot with slot number s is assigned to the cc for channel a, if at least one transmit message buffer is configured with the fr_mbfidrn[fid] set to s and fr_mbccfrn[cha] set to 1. a null frame is transmitted in the static slot s on channel a, if this slot is assigned to the cc for channel a, and all transmit message buffers with fr_mbfidrn[fid] = s and fr_mbccfrn[cha] = 1 are either not committed, that is, fr_mbccsrn[cmt] = 0, or locked by the application, that is, fr_mbccsrn[lcks] = 1, or the cycle counter filter is enabled and does not match. additionally, the application can clear the commit bit of a message buffer that is in the ccma state, which is called uncommit or transmit abort . this message buffer will be used for null frame transmission. as a result of the message buffer search described in section 33.6.7, individual message buffer search , the cc triggers the slot assigned transition sa for up to two transmit message buffers if at least one of the conditions mentioned above is fulfilled for these message buffers. the transition sa changes the message buffer states from either idle to ccsa or from hlck to hlckccsa . in each case, these message buffers will be used for null frame search[s+1] mt start ma slot s tx su ccma cctx slot s+1 idle m t s t a rt idle slot s+2 slot start slot start slot start mt start message transmit sss ccsu search[s+1] m t s t a rt mt st a rt ma slot s tx sss hlckccma cctx slot s+1 hlck mt start idle slot s+2 slot start slot start slot start hu ccma message transmit flexray communication controller (flexray) RM0029 1576/1740 doc id 15177 rev 8 transmission in the next slot. a message buffer timing and state change diagram for null frame transmission from idle state is given in figure 959 . figure 959. null frame transmission from idle state a message buffer timing and state change diagram for null frame transmission from hlck state is given in figure 960 . figure 960. null frame transmission from hlck state if a transmit message buffer is in the ccsa or hlckccsa state at the start of the transmission slot, a null frame is transmitted in any case, even if the message buffer is unlocked or committed before the transmission slot starts. a transmit message buffer timing and state change diagram for null frame transmission for this case is given in figure 961 . figure 961. null frame transmission from hlck state with unlock since the null frame transmission will not use the message buffer data, the application can lock/unlock the message buffer during null frame transmission. a transmit message buffer timing and state change diagram for null frame transmission for this case is given in figure 962 . search[s+1] m t sta r t mt s ta rt sa slot s sts sss ccsa ccnf slot s+1 idle mt sta r t idle slot s+2 slot start slot start slot start null frame transmit search[s+1] m t s ta rt m t s ta rt sa slot s sts sss hlckccsa hlckccnf slot s+1 hlck m t st a rt hlck slot s+2 slot start slot start slot start null frame transmit search[s+1] m t s tar t m t sta r t sa slot s sts sss hlckccsa ccnf slot s+1 hlck mt start idle slot s+2 slot start slot start slot start hu ccsa null frame transmit RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1577/1740 figure 962. null frame transmission from idle state with locking message buffer status update after the end of each slot, the pe generates the slot status vector. depending on the this status, the transmitted frame type, and the amount of transmitted data, the message buffer status is updated. message buffer status update after complete message transmission the term complete message transmission refers to the fact that all payload data stored in the message buffer were send to flexray bus. in this case, the cc updates the slot status field of the message buffer and triggers the status updated transition su . with the su transition, the cc sets the message buffer interrupt flag fr_mbccsrn[mbif] to indicate the successful message transmission. depending on the transmission mode flag fr_mbccfrn[mtm], the cc changes the commit flag fr_mbccsrn[cmt] and the valid flag fr_mbccsrn[dval]. if the fr_mbccfrn[mtm] flag is negated, the message buffer is in the event transmission mode. in this case, each committed message is transmitted only once. the commit flag fr_mbccsrn[cmt] is cleared with the su transition. if the fr_mbccfrn[mtm] flag is asserted, the message buffer is in the state transmission mode . in this case, each committed message is transmitted as long as the application provides new data or locks the message buffers. the cc will not clear the fr_mbccsrn[cmt] flag at the end of transmission and will set the valid flag fr_mbccsrn[dval] to indicate that the message will be transmitted again. message buffer status update after incomplete message transmission the term incomplete message transmission refers to the fact that not all payload data that should be transmitted were send to flexray bus. this may be caused by the following regular conditions in the dynamic segment: 1. the transmission slot starts in a minislot with a minislot number greater than platesttx . 2. the transmission slot did not exist in the dynamic segment at all. additionally, an incomplete message transmission can be caused by internal communication errors. if those error occur, the protocol engine communication failure interrupt flag pecf_if is set in the protocol interrupt flag register 1 (fr_pifr1) . in any of these two cases, the status of the message buffer is not changed at all with the su transition. the slot status field is not updated, the status and control flags are not changed, and the interrupt flag is not set. message buffer status update after null frame transmission after the transmission of a null frame, the status of the message buffer that was used for the null frame transmission is not changed at all. the slot status field is not updated, the status and control flags are not changed, and the interrupt flag is not set. search[s+1] m t star t m t sta r t sa slot s sts sss slot s+1 idle mt start hlck slot s+2 slot start slot start slot start null frame transmit hl ccsa ccnf hlckccnf flexray communication controller (flexray) RM0029 1578/1740 doc id 15177 rev 8 receive message buffers the section provides a detailed description of the functionality of the receive message buffers. if receive message buffers are used it is required to configure the related receive shadow buffer as described in section , receive shadow buffers . a receive message buffer is used to receive a message from the flexray bus based on individual filter criteria. the cc uses the receive message buffer to provide the following data to the application 1. message data received 2. information about the reception process 3. status information about the slot in which the message was received a individual message buffer with message buffer number n is configured as a receive message buffer by the following configuration settings fr_mbccsrn[mbt] = 0 (single buffered message buffer) fr_mbccsrn[mtd] = 0 (receive message buffer) to certain message buffer fields, both the application and the cc have access. to ensure data consistency, a message buffer locking scheme is implemented that is used to control the access to the data, control, and status bits of a message buffer. the access regions for receive message buffers are depicted in figure 963 . a description of the regions is given in ta ble 89 2 . if an region is active as indicated in table 893 , the access scheme given for that region applies to the message buffer. figure 963. receive message buffer access regions message buffer data field: data[0-n] message buffer header field: frame header fr_mbccsrn[dval/dup] message buffer header field: slot status message buffer header field: data field offset fr_mbccfrn[cha/chb/ccf*] fr_mbfidrn[fid] fr_mbidxrn[mbidx] fr_mbccsrn[mtd] rx sr cfg msg RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1579/1740 the trigger bits fr_mbccsrn[edt] and fr_mbccsrn[lckt] and the interrupt enable bit fr_mbccsrn[mbie] are not under access control and can be accessed from the application at any time. the status bits fr_mbccsrn[eds] and fr_mbccsrn[lcks] are not under access control and can be accessed from the cc at any time. the interrupt flag fr_mbccsrn[mbif] is not under access control and can be accessed from the application and the cc at any time. cc set access has higher priority. the cc restricts its access to the regions depending on the current state of the message buffer. the application must adhere to these restrictions in order to ensure data consistency. the receive message buffer states are given in figure 964 . a description of the message buffer states is given in table 888 , which also provides the access scheme for the access regions. the status bits fr_mbccsrn[eds] and fr_mbccsrn[lcks] provide the application with the required status information. the internal status information is not visible to the application. figure 964. receive message buffer states table 892. receive message buffer access region description region access from region used for application module cfg read/write ? message buffer configuration, message data and status access msg read/write ? message data, header, and status access rx ? write-only message reception and status update sr ? read-only message buffer search data hdis reset_state hd he idle bs sns su ccsu ccbs ccrx hlck hlckccbs hlckccrx sss sls he hl hdislck hd hl hu bs sns hl hu hu hl hu sls sss flexray communication controller (flexray) RM0029 1580/1740 doc id 15177 rev 8 message buffer transitions application transitions the application transitions that can be triggered by the application using the commands described in table 894 . the application issues the commands by writing to the message buffer configuration, control, status registers (fr_mbccsrn) . only one command can be issued with one write access. each command is executed immediately. if the command is ignored, it must be issued again. message buffer enable and disable the enable and disable commands issued by writing 1 to the trigger bit fr_mbccsrn[edt]. the transition that will be triggered by each of these command depends on the current value of the status bit fr_mbccsrn[eds]. if the command triggers the disable transition hd and the message buffer is in one of the states ccbs , hlckccbs , or ccrx , the disable transition has no effect (command is ignored) and the message buffer state is not changed. no notification is given to the application. if the communication controller is started as a non-coldstart node, and the message buffers are configured and enabled in the poc config state for slot 1, then the message buffer cannot be disabled in the integration_listen state by directly writing 1 to the edt bit. to facilitate this, a freeze command needs to be issued just before running the message table 893. receive message buffer states and access state fr_mbccsrn access from description eds lcks appl. module idle 1 0 ? sr idle ? message buffer is idle. included in message buffer search. hdis 0 0 cfg ? dis abled ? message buffer under configuration. excluded from message buffer search. hdislck 0 1 cfg ? dis abled and l ock ed ? message buffer under configuration. excluded from message buffer search. hlck 1 1 msg ? l ock ed ? applications access to data, control, and status. included in message buffer search. ccbs 1 0 ? ? b uffer s ubscribed ? message buffer subscribed for reception. filter matches next (slot, cycle, channel) tuple. hlckccbs 1 1 msg ? l ock ed and b uffer s ubscribed ? applications access to data, control, and status. message buffer subscribed for reception. ccrx 1 0 ? ? message r eceive ? message data received into related shadow buffer. hlckccrx 1 1 msg ? l ock ed and message r eceive ? applications access to data, control, and status. message data received into related shadow buffer. ccsu 1 0 ? rx s tatus u pdate ? message buffer status update. update of status flags, the slot status field, and the header index. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1581/1740 buffer disable for slot 1. executing this command enables the message buffer disable during the listen states. message buffer lock and unlock the lock and unlock commands issued by writing ?1? to the trigger bit fr_mbccsrn[lckt]. the transition that will be triggered by each of these commands depends on the current value of the status bit fr_mbccsrn[lcks]. if the command triggers the lock transition hl while the message buffer is in the state ccrx, the lock transition has no effect (command is ignored) and message buffer state is not changed. in this case, the message buffer lock error flag lck_ef in the chi error flag register (fr_chierfr) is set. module transitions the module transitions that can be triggered by the cc are described in ta ble 89 5 . each transition will be triggered for certain message buffers when the related condition is fulfilled. transition priorities the application can trigger only one transition at a time. there is no need to specify priorities among them. as shown in table 896 , the module transitions have a higher priority than the application transitions. for all states except the ccrx state, a module transition and the application lock/unlock transition hl/hu and can be executed at the same time. the result state is reached by first applying the module transition and subsequently the application transition to table 894. receive message buffer application transitions transition host command condition description he fr_mbccsrn[edt] = 1 fr_mbccsrn[eds] = 0 application triggers message buffer enable hd fr_mbccsrn[eds] = 1 application triggers message buffer disable hl fr_mbccsrn[lckt] = 1 fr_mbccsrn[lcks] = 0 application triggers message buffer lock hu fr_mbccsrn[lcks] = 1 application triggers message buffer unlock table 895. receive message buffer module transitions transition condition description bs slot match and cyclecounter match b uffer s ubscribed ? the message buffer filter matches next slot and cycle sls slot start sl ot s tart ? start of either static slot or dynamic slot sns symbol window start or nit start s ymbol window or n it s tart ? start of either symbol window or nit sss slot start or symbol window start or nit start sl ot or s egment s tart ? start of either static slot, dynamic slot, symbol window, or nit su status updated s tatus u pdated ? slot status field, message buffer status flags, header index updated; interrupt flag set flexray communication controller (flexray) RM0029 1582/1740 doc id 15177 rev 8 the intermediately reached state. for example, if the message buffer is in the buffer subscribed state ccbs and the module triggers the slot start transition sls at the same time as the application locks the message buffer by the hl transition, the intermediate state is ccrx and the resulting state is locked buffer subscribed state hlckccrx . message reception as a result of the message buffer search, the cc changes the state of up to two enabled receive message buffers from either idle state idle or locked state hlck to the either subscribed state ccbs or locked buffer subscribed state hlckccbs by triggering the buffer subscribed transition bs. if the receive message buffers for the next slot are assigned to both channels, then at most one receive message buffer is changed to a buffer subscribed state. if more than one matching message buffers assigned to a certain channel, then only the message buffer with the lowest message buffer number is in one of the states mentioned above. with the start of the next static or dynamic slot the module trigger the slot start transition sls . this changes the state of the subscribed receive message buffers from either ccbs to ccrx or from hlckccbs to hlckccrx, respectively. during the reception slot, the received frame data are written into the shadow buffers. for details on receive shadow buffers, see section , receive shadow buffers concept . the data and status of the receive message buffers that are the ccrx or hlckccrx are not modified in the reception slot. message buffer update with the start of the next static or dynamic slot or with the start of the symbol window or nit, the module triggers the slot or segment start transition sss . this transition changes the state of the receiving receive message buffers from either ccrx to ccsu or from hlckccrx to hlck, respectively. if a message buffer was in the locked state hlckccrx , no update will be performed. the received data are lost. this is indicated by setting the frame lost channel a/b error flag frla_ef/frlb_ef in the chi error flag register (fr_chierfr) . if a message buffer was in the ccrx state it is now in the ccsu state. after the evaluation of the slot status provided by the pe the message buffer is updated. the message buffer update depends on the slot status bits and the segment the message buffer is assigned to. this is described in ta ble 89 7 . table 896. receive message buffer transition priorities state priorities description module versus application idle bs > hd buffer subscribed > message buffer disable hlck bs > hd buffer subscribed > message buffer disable ccrx sss > hl slot or segment start > message buffer lock RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1583/1740 note: if the number of the last slot in the current communication cycle on a given channel is n, then all receive message buffers assigned to this channel with fr_mbfidrn[fid] > n will not be updated at all. when the receive message buffer update has finished the status updated transition su is triggered, which changes the buffer state from ccsu to idle . an example receive message buffer timing and state change diagram for a normal frame reception is given in figure 965 . figure 965. message reception timing the amount of message data written into the message buffer data field of the receive shadow buffer is determined by the following two items: table 897. receive message buffer update vss!validframe vrf!header!nfindicator update description 11 valid non-null frame received - message buffer data field updated - frame header field updated - slot status field updated - dup = 1 - dval = 1 - mbif = 1 10 valid null frame received - message buffer data field not updated - frame header field not updated - slot status field updated - dup = 0 - dval not changed - mbif = 1 0x no valid frame received - message buffer data field not updated - frame header field not updated - slot status field updated - dup = 0 - dval not changed - mbif = 1, if the slot was not an empty dynamic slot an empty dynamic slot is indicated by the following frame and slot status bit values: vss!validframe = 0 and vss!syntaxerror = 0 and vss!contenterror = 0 and vss!bviolation = 0. search[s+1] m t s tar t bs slot s sls su ccbs ccrx slot s+1 idle m t s tar t idle slot s+2 slot start slot start m t s tar t message receive to receive shadow buffer sss ccsu slot start flexray communication controller (flexray) RM0029 1584/1740 doc id 15177 rev 8 1. the message buffer segment that the message buffer is assigned to, as defined by the message buffer segment size and utilization register (fr_mbssutr) . 2. the message buffer data field size, as defined by the related field of the message buffer data size register (fr_mbdsr) 3. the number of bytes received over the flexray bus if the message buffer is assigned to the message buffer segment 1, and the number of received bytes is greater than 2*fr_mbdsr.mbseg1ds, the cc writes only 2*fr_mbdsr.mbseg1ds bytes into the message buffer data field of the receive shadow buffer. if the number of received bytes is less than 2*fr_mbdsr.mbseg1ds, the cc writes only the received number of bytes and will not change the trailing bytes in the message buffer data field of the receive shadow buffer. the same holds for the message buffer segment 2 with fr_mbdsr.mbseg2ds. received message access to access the message data received over the flexray bus, the application reads the message data stored in the message buffer data field of the corresponding receive message buffer. the access to the message buffer data field is described in section , individual message buffers . the application can read the message buffer data field if the receive message buffer is one of the states hdis, hdislck, or hlck. if the message buffer is in one of these states, the cc will not change the content of the message buffer. receive shadow buffers concept the receive shadow buffer concept applies only to individual receive message buffers. the intention of this concept is to ensure that only syntactically and semantically valid received non-null frames are presented to the application in a receive message buffer. the basic structure of a receive shadow buffer is described in section , receive shadow buffers . the receive shadow buffers temporarily store the received frame header and message data. after the slot boundary the slot status information is generated. if the slot status information indicates the reception of the valid non-null frame (see table 897 ), the cc writes the slot status into the slot status field of the receive shadow buffer and exchanges the content of the message buffer index registers (fr_mbidxrn) with the content of the corresponding internal shadow buffer index register. in all other cases, the cc writes the slot status into the identified receive message buffer, depending on the slot status and the flexray segment the message buffer is assigned to. the shadow buffer concept, with its index exchange, results in the fact that the flexray memory area located message buffer associated to an individual receive message buffer changes after successful reception of a valid frame. this means that the message buffer area in the flexray memory area accessed by the application for reading the received message is different from the initial setting of the message buffer. therefore, the application must not rely on the index information written initially into the message buffer index registers (fr_mbidxrn) . instead, the index of the message buffer header field must be fetched from the message buffer index registers (fr_mbidxrn) . double transmit message buffer the section provides a detailed description of the functionality of the double transmit message buffers. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1585/1740 double transmit message buffers are used by the application to provide the cc with the message data to be transmitted over the flexray bus. the cc uses this message buffer to provide information to the application about the transmission process, and status information about the slot in which message data was transmitted. in contrast to the single transmit message buffers, the application can provide new transmission data while the transmission of the previously provided message data is running. this scheme is called double buffering and can be considered as a fifo of depth 2. double transmit message buffers are implemented by combining two individual message buffers that form the two sides of an double transmit message buffer. one side is called the commit side and will be accessed by the application to provide the message data. the other side is called the transmit side and is used by the cc to transmit the message data to the flexray bus. the two sides are located in adjacent individual message buffers. the message buffer that implements the commit side has an even message buffer number 2n. the transmit side message buffer follows the commit side message buffer and has the message buffer number 2n+1. the basic structure and data flow of a double transmit message buffer is given in figure 966 . figure 966. double transmit buffer structure and data flow note: both the commit and the transmit side must be configured with identical values except for the message buffer index registers (fr_mbidxrn) . access regions to certain message buffer fields, both the application and the cc have access. to ensure data consistency, a message buffer locking scheme is implemented, which controls the exclusive access to the data, control, and status bits of the message buffer. the access scheme for double transmit message buffers is depicted in figure 967 . the given regions represent fields that can be accessed from both the application and the cc and, thus, require access restrictions. a description of the regions is given in table 898 . commit side transmit side application flexray bus mb# 2n mb# 2n+1 internal message transfer message data message data message data flexray communication controller (flexray) RM0029 1586/1740 doc id 15177 rev 8 figure 967. double transmit message buffer access regions layout the trigger bits fr_mbccsrn[edt] and fr_mbccsrn[lckt], and the interrupt enable bit fr_mbccsrn[mbie] are not under access control and can be accessed from the application at any time. the status bits fr_mbccsrn[eds] and fr_mbccsrn[lcks] are not under access control and can be accessed from the cc at any time. the interrupt flag fr_mbccsrn[mbif] is not under access control and can be accessed from the application and the cc at any time. cc set access has higher priority. the cc restricts its access to the regions, depending on the current state of the corresponding part of the double transmit message buffer. the application must adhere to message buffer data field: data[0-n] message buffer header field: frame header fr_mbccsr(2n)[cmt] message buffer header field: slot status message buffer header field: data field offset fr_mbccfr(2n)[mtm/cha/chb/ccf*] fr_mbfidr(2n)[fid] fr_mbidxr(2n)[mbidx] fr_mbccsr(2n)[mbt/mtd] message buffer data field: data[0-n] message buffer header field: frame header fr_mbccsr(2n+1)[cmt] message buffer header field: slot status message buffer header field: data field offset fr_mbccfr(2n+1)[mtm/cha/chb/ccf*] fr_mbfidr(2n+1)[fid] fr_mbidxr(2n+1)]mbidx] fr_mbccsr(2n+1)[mbt/mtd] commit side transmit side cfg msg cfg itx ss ss sr tx table 898. double transmit message buffer access regions description access description region type application module commit side cfg read/write ? message buffer configuration msg read/write ? message buffer data and control access itx ? read/write internal message transfer ss ? write-only slot status update transmit side cfg read/write ? message buffer configuration sr ? read-only message buffer search tx ? read-only internal message transfer, message transmission ss ? write-only slot status update RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1587/1740 these restrictions in order to ensure data consistency. the states for the commit side of a double transmit message buffer are given in figure 968 . a description of the states is given in table 900 . the states for the transmit side of a double transmit message buffer are given in figure 969 . a description of the states is given in table 900 . the description tables also provide the access scheme for the access regions. the status bits fr_mbccsrn[eds] and fr_mbccsrn[lcks] provide the application with the required message buffer status information. the internal status information is not visible to the application. message buffer states this section describes the transmit message buffer states and provides a state diagram. figure 968. double transmit message buffer state diagram (commit side) a description of the states of the commit side of a double transmit message buffer is given in ta ble 89 9 . hdis reset_state hd he idle is ie ccitx hlck he hl hu hdislck hu hd hl table 899. double transmit message buffer state description (commit side) state fr_mbccsr(2n) access region description eds lcks appl. module common states hdis 0 0 cfg ? dis abled ? message buffer under configuration. commit side can not be used for internal message transfer. ccitx 1 0 ? itx i nternal message t ransfer ? message buffer data transferred from commit side to transmit side. commit side specific states idle 1 0 ? itx, ss idle ? message buffer commit side is idle. commit side can be used for internal message transfer. flexray communication controller (flexray) RM0029 1588/1740 doc id 15177 rev 8 figure 969. double transmit message buffer state diagram (transmit side) a description of the states of the transmit side of a double transmit message buffer is given in ta ble 90 0 . hdislck 0 1 cfg ss dis abled and l ock ed ? message buffer under configuration. commit side can not be used for internal message transfer. hlck 1 1 msg ss l ock ed ? applications access to data, control, and status. commit side can not be used for internal message transfer. table 899. double transmit message buffer state description (commit side) (continued) state fr_mbccsr(2n) access region description eds lcks appl. module hdis reset_state hd he idle sa dss su ccsu ccsa cctx tx ccitx ccsaccitx ccnf is ie ccma is ie ccnfccitx ccmaccitx sss sts is ie sts ie is dss ma sss table 900. double transmit message buffer state description (transmit side) (sheet 2 of 2) state fr_mbccsrn access region description eds lcks appl. module common states hdis 0 0 cfg ? dis abled ? message buffer under configuration. excluded from message buffer search. ccitx 1 0 ? tx i nternal m essage t ransfer ? message buffer data transferred from commit side to transmit side transmit side specific states RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1589/1740 message buffer transitions application transitions the application transitions that can be triggered by the application using the commands described in table 901 . the application issues the commands by writing to the message buffer configuration, control, status registers (fr_mbccsrn) . only one command can be issued with one write access. each command is executed immediately. if the command is ignored, it must be issued again. message buffer enable and disable the enable and disable commands can be issued on the transmit side only. any enable or disable command issued on the commit side will be ignored without notification. the transitions that will be triggered depends on the value of the eds bit. the enable and disable commands will affect both the commit side and the transmit side at the same time. if the application triggers the disable transition hd while the transmit side is in one of the states ccsa , ccsaccitx , ccnf , ccnfccitx , ccma , ccmaccitx, cctx, or ccsu, the idle 1 0 ? sr idle ? message buffer transmit side is idle. transmit side is included in message buffer search. ccsa 1 0 ? ? s lot a ssigned ? message buffer assigned to next static slot. ready for null frame transmission. ccsaccitx 1 0 ? tx s lot a ssigned and i nternal m essage t ransfer ? message buffer assigned to next static slot and message buffer data transferred from commit side to transmit side ccnf 1 0 ? tx n ull f rame transmission ? header is used for null frame transmission ccnfccitx 1 0 ? tx n ull f rame transmission and i nternal m essage t ransfer ? header is used for null frame transmission and message buffer data transferred from commit side to transmit side ccma 1 0 ? ? m essage a vailable ? message buffer is assigned to next slot and cycle counter filter matches ccmaccitx 1 0 ? ? m essage a vailable and i nternal m essage t ransfer ? message buffer is assigned to next slot and cycle counter filter matches and message buffer data transferred from commit side to transmit side. cctx 1 0 ? tx message t ransmission ? message buffer data transmit. payload data from buffer transmitted ccsu 1 0 ? ss s tatus u pdate ? message buffer status update. update of status flags, the slot status field, and the header index. note: the slot status field of the commit side is updated too, even if the application has locked the commit side. table 900. double transmit message buffer state description (transmit side) (sheet 2 of 2) state fr_mbccsrn access region description eds lcks appl. module flexray communication controller (flexray) RM0029 1590/1740 doc id 15177 rev 8 disable transition has no effect (command is ignored) and the message buffer state is not changed. no notification is given to the application. message buffer lock and unlock the lock and unlock commands can be issued on the commit side only. any lock or unlock command issued on the transmit side will be ignored and the double transmit buffer lock error flag dbl_ef in the chi error flag register (fr_chierfr) will be set. the transitions that will be triggered depends on the current value of the lcks bit. the lock and unlock commands will only affect the commit side. if the application triggers the lock transition hl while the commit side is in the state ccitx, the message buffer state will not be changed and the message buffer lock error flag lck_ef in the chi error flag register (fr_chierfr) will be set. module transitions the module transitions that can be triggered by the cc are described in ta ble 90 2 . the transitions c1 and c2 apply to both sides of the message buffer and are applied at the same time. all other cc transitions apply to the transmit side only. table 901. double transmit message buffer host transitions transition host command condition description he fr_mbccsr(2n+1)[edt] = 1 fr_mbccsr(2n+1)[eds] = 0 application triggers message buffer enable hd fr_mbccsr(2n+1)[eds] = 1 application triggers message buffer disable hl fr_mbccsr(2n)[lckt] = 1 fr_mbccsr(2n)[lcks] = 0 application triggers message buffer lock hu fr_mbccsr(2n)[lcks] = 1 application triggers message buffer unlock table 902. double transmit message buffer module transitions transition condition description common transitions is see section , internal message transfer i nternal message transfer s tart ? start transfer of message data from commit side to transmit side ie i nternal message transfer e nd ? stop transfer of message data from commit side to transmit side note: the internal message transfer is stopped before the slot or segment start. transmit side specific transitions sa slot match and static slot s lot a ssigned ? message buffer is assigned to next static slot ma slot match and cyclecounter match m essage a vailable ? message buffer is assigned to next slot and cycle counter filter matches tx slot start and fr_mbccsr(2n + 1) [cmt] = 1 t ransmission slot start ? slot start and commit bit cmt is set. in case of a dynamic slot, platesttx is not exceeded. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1591/1740 transition priorities the application can trigger only one transition at a time. there is no need to specify priorities among them. as shown in the first part of table 903 , the module transitions have a higher priority than the application transitions. the priorities among the cc transitions and the related states are given in the second part of ta ble 90 3 . these priorities apply only to the transmit side. the internal message transmit start transition is has tho lowest priority. message preparation the application provides the message data through the commit side. the transmission itself is executed from the transmit side. the transfer of the message data from the commit side to the transmit side is done by the internal message transfer , which is described in section , internal message transfer to transmit a message over the flexray bus, the application writes the message data into the message buffer data field of the commit side and sets the commit bit cmt in the message buffer configuration, control, status registers (fr_mbccsrn) . the physical access to the message buffer data field is described in section , individual message buffers . as indicated by ta ble 89 9 , the application shall write to the message buffer data field and change the commit bit cmt only if the transmit message buffer is in one of the states hdis, su status updated s tatus u pdated ? slot status field and message buffer status flags updated. interrupt flag set. sts static slot start st atic slot s tart ? start of static slot. dss dynamic slot start or symbol window start or nit start d ynamic slot or s egment s tart ? start of dynamic slot or symbol window or nit sss slot start or symbol window start or nit start s lot or s egment s tart ? start of static slot or dynamic slot or symbol window or nit table 902. double transmit message buffer module transitions transition condition description table 903. double transmit message buffer transition priorities state priority description module versus application idle is > hd is > hl internal message transfer start > message buffer disable internal message transfer start > message buffer lock module internal idle ma > sa message available > slot assigned ccma tx > sts tx > dss transmission slot start > static slot start transmission slot start > dynamic slot start flexray communication controller (flexray) RM0029 1592/1740 doc id 15177 rev 8 hdislck, or hlck . the application can change the state of a message buffer if it issues the appropriate commands shown in table 901 . the state change is indicated through the fr_mbccsrn[eds] and fr_mbccsrn[lcks] status bits. internal message transfer the internal message transfer transfers the message data from the commit side to the transmit side. the internal message transfer is implemented as the swapping of the content of the message buffer index registers (fr_mbidxrn) of the commit side and the transmit side. after the swapping, the commit side cmt bit is cleared, the commit side interrupt flag mbif is set, the transmit side cmt bit is set, and the transmit side dval bit is cleared. the conditions and the point in time when the internal message transfer is started are controlled by the message buffer commit mode bit mcm in the message buffer configuration, control, status registers (fr_mbccsrn) . the mcm bit configures the message buffer for either the streaming commit mode or the immediate commit mode. a detailed description is given in streaming commit mode and immediate commit mode . the internal message transfer is triggered with the transition is . both sides of the message buffer enter one of the cc itx states. the internal message transfer is finished with the transition ie . streaming commit mode the intention of the streaming commit mode is to ensure that each committed message is transmitted at least once . the cc will not start the internal message transfer for a message buffer as long as the message data on the transmit side is not transmitted at least once. the streaming commit mode is configured by clearing the message buffer commit mode bit mcm in the message buffer configuration, control, status registers (fr_mbccsrn) . in this mode, the internal message transfer from the commit side to the transmit side is started for a double transmit message buffer when all of the following conditions are fulfilled 1. the commit side is in the idle state 2. the commit site message data are valid, that is, fr_mbccsr(2n)[cmt] = 1 3. the transmit side is in one of the states idle , ccsa , or ccma 4. the transmit side contains either no valid message data, that is, fr_mbccsr(2n+1)[cmt] = 0 or the message data were transmitted at least once, that is, fr_mbccsr(2n+1)[dval] = 1 an example of a streaming commit mode state change diagram is given in figure 970 . in this example, both the commit and the transmit side do not contain valid message data and the application provides two messages. the message buffer does not match the next slot. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1593/1740 figure 970. internal message transfer in streaming commit mode immediate commit mode the intention of the immediate commit mode is to transmit the latest data provided by the application. this implies that it is not guaranteed that each provided message will be transmitted at least once. the immediate commit mode is configured by setting the message buffer commit mode bit mcm in the message buffer configuration, control, status registers (fr_mbccsrn) . in this mode, the internal message transfer from the commit side to the transmit side is started for one double transmit message buffer when all of the following conditions are fulfilled 1. the commit side is in the idle state 2. the commit site message data are valid, that is, fr_mbccsr(2n)[cmt] = 1 3. the transmit side is in one of the states idle , ccsa , or ccma it is not checked whether the transmit side contains no valid message data or valid message data were transmitted at least once. if message data are valid and not transmitted, they may be overwritten. an example of a streaming commit mode state change diagram is given in figure 971 . in this example, both the commit and the transmit side do not contain valid message data, and the application provides two messages and the first message is gets overwritten. the message buffer does not match the next slot. figure 971. internal message transfer in immediate commit mode idle commit transmit idle hl hlck side side slot s slot s+1 slot s+2 search[s+1] slot start slot start slot start hu ccitx idle is ccitx ie idle hl hlck hu idle idle no internal message transfer, until message transmitted idle commit transmit idle hl hlck side side slot s slot s+1 slot s+2 search[s+1] slot start slot start slot start hu idle is ccitx ie idle hl hlck hu idle idle is ie idle idle internal message transfer overwrites non-transmitted message ccitx ccitx ccitx flexray communication controller (flexray) RM0029 1594/1740 doc id 15177 rev 8 message transmission for double transmit message buffers, the message buffer search checks only the transmit side part. the internal scheduling ensures, that the internal message transfer is stopped on the message buffer search start. thus, the transmit side of message buffer, that is not in its transmission or status update slot, is always in the idle state. the message transmit behavior and transmission state changes of the transmit side of a double transmit message buffer are the same as for single buffered transmit buffers, except that the transmit side of double buffers can not be locked by the application, that is, the hu and hl transition do not exist. therefore, refer to section , message transmission . message buffer status update the message buffer status update behavior of the transmit side of a double transmit message buffer is the same as for single transmit message buffers which is described in section , message buffer status update . additionally, the slot status field of the commit side is update after the update of the slot status field of the transmit side, even if the commit side is locked by the application. this is implemented to provide the slot status of the most recent transmission slot. 33.6.7 individual message buffer search this section provides a detailed description of the message buffer search algorithm. the message buffer search determines for each enabled channel if a slot s in a communication cycle c is assigned for frame or null frame transmission or if it is subscribed for frame reception on that channel. the message buffer search is a sequential algorithm which is invoked at the following protocol related events: 1. nit start 2. slot start in the static segment 3. minislot start in the dynamic segment the message buffer search within the nit searches for message buffers assigned or subscribed to slot 1. the message buffer search within slot n searches for message buffers assigned or subscribed to slot n+1 . in general, the message buffer search for the next slot n considers only message buffers which are 1. enabled, that is, fr_mbccsrn[eds] = 1, and 2. matches the next slot n , that is, fr_mbfidrn[fid] = n , and 3. are the transmit side buffer in case of a double transmit message buffer. on top of that, for the static segment only those message buffers are considered, that match the condition of at least one row of table 904 . for the dynamic segment only those message buffers are considered, that match the condition of at least one row of table 905 . these message buffers are called matching message buffers. for each enabled channel the message buffer search may identify multiple matching message buffers. among all matching message buffers the message buffers with highest priority according to ta ble 90 4 for the static segment and according to ta ble 90 5 for the dynamic segment are selected. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1595/1740 if there are multiple message buffer with highest priority, the message buffer with the lowest message buffer number is selected. all message buffer which have the highest priority must have a consistent channel assignment as specified in section , message buffer channel assignment consistency . depending on the message buffer channel assignment the same message buffer can be found for both channel a and channel b. in this case, this message buffer is used as described in section , individual message buffers . message buffer cycle counter filtering the message buffer cycle counter filter is a value-mask filter defined by the ccfe, ccfmsk, and ccfval fields in the message buffer cycle counter filter registers (fr_mbccfrn) . this filter determines a set of communication cycles in which the message buffer is considered for message reception or message transmission. if the cycle counter filter is disabled, that is, ccfe = 0, this set of cycles consists of all communication cycles. if the cycle counter filter of a message buffer does not match a certain communication cycle number, this message buffer is not considered for message transmission or reception in that communication cycle. in case of a transmit message buffer assigned to a slot in the static segment, though, this buffer is added to the matching message buffers to indicate the slot assignment and to trigger the null frame transmission. the cycle counter filter of a message buffer matches the communication cycle with the number cyccnt if at least one of the following conditions evaluates to true: table 904. message buffer search priority (static segment) priority mtd lcks cmt ccfm (1) description transition (highest) 01011 transmit buffer, matches cycle count, not locked and committed ma 1 1?0 1 transmit buffer, matches cycle count, not committed sa 1 1 ? 1 transmit buffer, matches cycle count, locked sa 2 1 ? ? ? transmit buffer sa 3 0 0 n/a 1 receive buffer, matches cycle count, not locked sb (lowest) 4 0 1 n/a 1 receive buffer, matches cycle count, locked sb 1. cycle counter filter match, see section , message buffer cycle counter filtering . table 905. message buffer search priority (dynamic segment) priority mtd lcks cmt ccfm (1) description transition (highest) 01011 transmit buffer, matches cycle count, not locked and committed ma 1 0 0 n/a 1 receive buffer, matches cycle count, not locked sb (lowest) 2 0 1 n/a 1 receive buffer, matches cycle count, locked sb 1. cycle counter filter match, see section , message buffer cycle counter filtering . flexray communication controller (flexray) RM0029 1596/1740 doc id 15177 rev 8 equation 54 equation 55 message buffer channel assignment consistency the message buffer channel assignment given by the cha and chb bits in the message buffer cycle counter filter registers (fr_mbccfrn) defines the channels on which the message buffer will receive or transmit. the message buffer with number n transmits or receives on channel a if fr_mbccfrn[cha] = 1 and transmits or receives on channel b if fr_mbccfrn[chb] = 1. to ensure correct message buffer operation, all message buffers assigned to the same slot and with the same priority must have a consistent channel assignment. that means they must be either assigned to one channel only, or must be assigned to both channels. the behavior of the message buffer search is not defined, if both types of channel assignments occur for one slot and priority. an inconsistent channel assignment for message buffer 0 and message buffer 1 is depicted in figure 972 . figure 972. inconsistent channel assignment node related slot multiplexing the term node related slot multiplexing applies to the dynamic segment only and refers to the functionality if there are transmit as well as receive message buffers are configured for the same slot. according to table 905 the transmit buffer is only found if the cycle counter filter matches, and the buffer is not locked and committed. in all other cases, the receive buffer will be found. thus, if the block has no data to transmit in a dynamic slot, it is able to receive frames on that slot. message buffer search error if the message buffer search is running while the next message buffer search start event appears, the message buffer search is stopped and the message buffer search error flag msb_ef is set in the chi error flag register (fr_chierfr) . this appears only if the chi frequency is too low to search through all message buffers within the nit or a minislot. the message buffer result is not defined in this case. for more details see section 33.7.6, number of usable message buffers . mbccfrn ccfe [] 0 = cyccnt & mbccfrn ccfmsk [] mbccfrn ccfval [] & mbccfrn ccfmsk [] = mb0 fr_mbccfr0[cha] = 1, fr_mbccfr0[chb] = 0 mb1 dual channel assignment single channel assignment fr_mbfidr0[fid] = 10 fr_mbfidr1[fid] = 10 fr_mbccfr1[cha] = 1, fr_mbccfr1[chb] = 1 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1597/1740 33.6.8 individual message buffer reconfiguration the initial configuration of each individual message buffer can be changed even when the protocol is not in the poc:config state. this is referred to as individual message buffer reconfiguration . the configuration bits and fields that can be changed are given in the section on specific configuration data . the common configuration data given in the section on specific configuration data can not be reconfigured when the protocol is out of the poc:config state. reconfiguration schemes depending on the target and destination basic state of the message buffer that is to be reconfigured, there are three reconfiguration schemes. basic type not changed (rc1) a reconfiguration will not change the basic type of the individual message buffer, if both the message buffer transfer direction bit fr_mbccsrn[mtd] and the message buffer type bit fr_mbccsrn[mbt] are not changed. this type of reconfiguration is denoted by rc1 in figure 973 . single transmit and receive message buffers can be rc1-reconfigured when in the hdis or hdislck state. double transmit message buffers can be rc1-reconfigured if both the transmit side and the commit side are in the hdis state. buffer type not changed (rc2) a reconfiguration will not change the buffer type of the individual message buffer if the message buffer buffer type bit fr_mbccsrn[mbt] is not changed. this type of reconfiguration is denoted by rc2 in figure 973 . it applies only to single transmit and receive message buffers. single transmit and receive message buffers can be rc2- reconfigured when in the hdis or hdislck state. buffer type changed (rc3) a reconfiguration will change the buffer type of the individual message buffer if the message buffer type bit fr_mbccsrn[mbt] is changed. this type of reconfiguration is denoted by rc3 in figure 973 . the rc3 reconfiguration splits one double buffer into two single buffers or combines two single buffer into one double buffer. in the later case, the two single message buffers must have consecutive message buffer numbers and the smaller one must be even. message buffers can be rc3 reconfigured if they are in the hdis state. figure 973. message buffer reconfiguration scheme single rx single tx double tx (commit side) double tx (transmit side) rc1 rc1 rc1 rc2 rc3 rc3 flexray communication controller (flexray) RM0029 1598/1740 doc id 15177 rev 8 33.6.9 receive fifos this section provides the functional description of the two receive fifos. overview the two receive fifos implement the queued message buffer concept defined by the flexray communications system protocol specification, version 2.1 rev a. one fifo is assigned to channel a, the other fifo is assigned to channel b. both fifos work completely independent from each other. the message buffer structure of each fifo is described in section , receive fifo . the area in the flexray memory area for each of the two fifos is characterized by: the fifo system memory base address the index of the first fifo entry given by receive fifo start index register (fr_rfsir) the number of fifo entries and the length of each fifo entry as given by receive fifo depth and size register (rfdsr) fifo configuration the fifos can be configured for two different locations of the system memory base address via the fifo address mode bit fam in the module configuration register (fr_mcr) . single system memory base address mode this mode is configured, when the fifo address mode flag fr_mcr[fam] is set to 0. in this mode, the location of the system memory base address for the fifo buffers is system memory base address register (fr_symbadr) . dual system memory base address mode this mode is configured, when the fifo address mode flag fr_mcr[fam] is set to 1. in this mode, the location of the system memory base address for the fifo buffers is receive fifo system memory base address register (fr_rfsymbadr) . the fifo control and configuration data are given in section , receive fifo control and configuration data . the configuration of the fifos consists of two steps. 1. the first step is the allocation of the required amount of memory for the flexray memory area. this includes the allocation of the message buffer header area and the allocation of the message buffer data fields. for more details see section 33.6.4, flexray memory area layout . 2. the second step is the programming of the configuration data register while the pe is in poc:config . RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1599/1740 the following steps configure the layout of the fifo: configure the fifo update and address modes in module configuration register (fr_mcr) configure the fifo system memory base address configure the receive fifo start index register (fr_rfsir) with the first message buffer header index that belongs to the fifo configure the receive fifo depth and size register (rfdsr) with fifo entry size configure the receive fifo depth and size register (rfdsr) with fifo depth configure the fifo filters fifo periodic timer the fifo periodic timer is used to generate an fifo almost-full interrupt at certain point in time, if the almost-full watermark is not reached, but the fifo is not empty. this can be used to prevent frames from get stuck in the fifo for a long time. the fifo periodic timer is configured via the receive fifo periodic timer register (fr_rfptr) . if the periodic timer duration fr_rfptr[ptd] is configured to 0x0000, the periodic timer is continuously expired. if the periodic timer duration fr_rfptr[ptd] is configured to 0x3fff, the periodic timer never expires. if the periodic timer is configured to a value ptd, greater than 0x0000 and smaller 0x3fff, the periodic timer expires and is restarted at the start of every communication cycle, and expires and is restarted after ptd macroticks have been elapsed. fifo reception the fifo reception is a cc internal operation. a message frame reception is directed into the fifo, if no individual message buffer is assigned for transmission or subscribed for reception for the current slot. in this case the fifo filter path shown in figure 974 is activated. if the fifo filter path indicates that the received frame has to be appended to the fifo and the fifo is not full, the cc writes the received frame header into the message buffer header field indicated by the cc internal fifo write index. the frame payload data are written into the corresponding message buffer data field. if the status of the received frame indicates a valid non-null frame, the slot status information is written into the message buffer header field and the cc internal fifo write index is updated by 1 and the fifo fill level fla (flb) in the receive fifo fill level and pop count register (fr_rfflpcr) is incremented.if the status of the received frame indicates an invalid or null frame, the frame is not appended to the fifo. fifo almost-full interrupt generation if the fifo fill level fla (flb) is updated after a frame reception and exceeds the fifo watermark level wm, that is, fla > wm a (flb > wm b ), then the fifo almost-full interrupt flag fr_gifer[fafaif] (fr_gifer[fafbif]) is asserted.if the periodic timer expires, and fifoa (fifob) is not empty, that is, fla > 0 (flb > 0), then the fifo almost-full interrupt flag fr_gifer[fafaif] (fr_gifer[fafbif]) is asserted. fifo overflow error generation if the fifoa (fifob) is full, that is, fla = fifo_depth a (flb = fifo_depth b ) and the conditions for a fifo reception as described in section , fifo reception are fulfilled, then flexray communication controller (flexray) RM0029 1600/1740 doc id 15177 rev 8 the fifo overflow error flag fr_chierfr[fova_ef] (fr_chierfr[fovb_ef]) is asserted. fifo message access the fifoa (fifob) contains valid messages if the fifo fill level fla (flb) is greater than 0. the receive fifo a read index register (fr_rfarir) ( receive fifo b read index register (fr_rfbrir) ) pointing to a message buffer with valid content and the oldest frames stored in the fifo. if the fifo fill level fla (flb) is 0, than the fifoa (fifob) contains no valid messages and the receive fifo a read index register (fr_rfarir) ( receive fifo b read index register (fr_rfbrir) ) pointing to a message buffer with invalid content. in this case the application must not read data from the fifo. to access the oldest message in the fifoa (fifob), the application first reads the read index rdidx out of the receive fifo a read index register (fr_rfarir) ( receive fifo b read index register (fr_rfbrir) ). this read index points to the message buffer header field of the oldest message buffer that contains valid received message data. the application can access the message data as described in section , receive fifo ?. when the application has read the message buffer data and status information, it can update the fifo as described in section , fifo update . fifo update the application updates the fifoa (fifob) by writing a pop count value pc different from 0 to the pca (pcb) field in the receive fifo fill level and pop count register (fr_rfflpcr) . as a result of the this operation, the cc removes the oldest pc entries from fifoa (fifob). if the specified pop count value pc is greater than the current fill level fl provided in fla (fab) field, then only fl entries are removed from the fifoa (fifob), the remaining fl-pc requested pop operations are discarded without any notification. in this case fifoa (fifob) is empty after the update operation. the read index in the receive fifo a read index register (fr_rfarir) ( receive fifo b read index register (fr_rfbrir) ) is incremented by the number of removed items. if the read index reaches the top of the fifo, it wraps around to the fifo start index defined in receive fifo start index register (fr_rfsir) automatically. fifo interrupt flag update th fifo interrupt flag update mode is configured when the fifo update mode flag fr_mcr[fum] is set to ?0?. in this mode fifoa (fifob) will be updated by one entry, when the interrupt flag fr_gifer[fafaif] (fr_gifer[fafbif]) is written with ?1? by the application. if the fifo is empty, the update request is ignored without any notification. the read index in the receive fifo a read index register (fr_rfarir) ( receive fifo b read index register (fr_rfbrir) ) is incremented by 1 if the fifo was not empty. if the read index reaches the top of the fifo, it wraps around to the fifo start index automatically. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1601/1740 fifo filtering the fifo filtering is activated after all enabled individual receive message buffers have been searched without success for a message buffer to receive the current frame. the cc provides three sets of fifo filters. the fifo filters are applied to valid non-null frames only. the fifo will not receive invalid or null-frames. for each fifo filter, the pass criteria is specified in the related section given below. only frames that have passed all filters will be appended to the fifo. the fifo filter path is depicted in figure 974 . flexray communication controller (flexray) RM0029 1602/1740 doc id 15177 rev 8 figure 974. received frame fifo filter path valid frame received ( vrf ) individual null frame frame id value- frame id append to fifo ( vrf ) frame id no frame received fifo full set fifo overflow interrupt flag message buffer found ? no passed passed passed yes (vrf!header!nfindicator = 0 ) ? mask rejection filter ? range rejection filter ? range acceptance filter ? in dynamic segment ? ? store into message buffer ( vrf ) yes no else ignore frame yes else else message id ( vrf!header!ppindicator = 1 ) ? message id yes passed acceptance filter ? no yes no else RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1603/1740 a received frame passes the fifo filtering if it has passed all three type of filter. rx fifo frame id value-mask rejection filter the frame id value-mask rejection filter is a value-mask filter and is defined by the fields in the receive fifo frame id rejection filter value register (fr_rffidrfvr) and the receive fifo frame id rejection filter mask register (fr_rffidrfmr) . each received frame with a frame id fid that does not match the value-mask filter value passes the filter, that is, is not rejected. consequently, a received valid frame with the frame id fid passes the rx fifo frame id value-mask rejection filter if equation 56 is fulfilled. equation 56 the rx fifo frame id value-mask rejection filter can be configured to pass all frames by the following settings. fr_rffidrfvr[fidrfval] = 0x000 and fr_rffidrfmr[fidrfmsk] = 0x7ff using the settings above, only the frame with frame id 0 will be rejected, which is an invalid frame. all other frames will pass. the rx fifo frame id value-mask rejection filter can be configured to reject all frames by the following settings. fr_rffidrfmr[fidrfmsk] = 0x000 using the settings above, equation 56 can never be fulfilled (0 != 0) and thus all frames are rejected; no frame will pass. this is the reset value for the rx fifo. rx fifo frame id range rejection filter each of the four rx fifo frame id range filters can be configured as a rejection filter. the filters are configured by the receive fifo range filter configuration register (fr_rfrfcfr) and controlled by the receive fifo range filter control register (fr_rfrfctr) . the rx fifo frame id range filters apply to all received valid frames. a received frame with the frame id fid passes the rx fifo frame id range rejection filters if either no rejection filter is enabled, or, for all of the enabled rx fifo frame id range rejection filters, that is, fr_rfrfctr [fimd] = 1 and fr_rfrfctr[fien] = 1, equation 57 is fulfilled. equation 57 consequently, all frames with a frame id that fulfills equation 58 for at least one of the enabled rejection filters will be rejected and thus not pass. equation 58 fid & fr_rffidrfmr fidrfmsk [] fr_rffidrfvr fidrfval [] & fr_rffidrfmr fidrfmsk [] fid fr_rfrfcfr sel sid ibd 0 = [] < () or fr_rfrfcfr sel sid ibd 1 = [] fid < () fr_rfrfcfr sel sid ibd 0 = [] fid fr_rfrfcfr sel sid ibd 1 = [] ? flexray communication controller (flexray) RM0029 1604/1740 doc id 15177 rev 8 rx fifo frame id range acceptance filter each of the four rx fifo frame id range filters can be configured as an acceptance filter. the filters are configured by the receive fifo range filter configuration register (fr_rfrfcfr) and controlled by the receive fifo range filter control register (fr_rfrfctr) . the rx fifo frame id range filters apply to all received valid frames. a received frame with the frame id fid passes the rx fifo frame id range acceptance filters if either no acceptance filter is enabled, or, for at least one of the enabled rx fifo frame id range acceptance filters, that is, fr_rfrfctr[fimd] = 0 and fr_rfrfctr[fien] = 1, equation 59 is fulfilled. equation 59 rx fifo message id acceptance filter the rx fifo message id acceptance filter is a value-mask filter and is defined by the receive fifo message id acceptance filter value register (fr_rfmidafvr) and the receive fifo message id acceptance filter mask register (fr_rfmidafmr) . this filter applies only to valid frames received in the dynamic segment with the payload preamble indicator bit ppi set to 1. all other frames will pass this filter. a received valid frame in the dynamic segment with the payload preamble indicator bit ppi set to 1 and with the message id mid (the first two bytes of the payload) will pass the rx fifo message id acceptance filter if equation 60 is fulfilled. equation 60 the rx fifo message id acceptance filter can be configured to accept all frames by setting fr_rfmidafmr[midafmsk] = 0x000 using the settings above, equation 60 is always fulfilled and all frames will pass. 33.6.10 channel device modes this section describes the two flexray channel device modes that are supported by the cc. dual channel device mode in the dual channel device mode, both flexray ports are connected to physical flexray bus lines. the flexray port consisting of fr_a_rx, fr_a_tx, and fr_a_tx_en is connected to the physical bus channel a and the flexray port consisting of fr_b_rx, fr_b_tx, and fr_b_tx_en is connected to the physical bus channel b. the dual channel system is shown in figure 975 . fr_rfrfcfr sel sid ibd 0 = [] fid fr_rfrfcfr sel sid ibd 1 = [] ? [] = fr_rfmidafmr midafval [] & fr_rfmidafmr midafmsk [] = RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1605/1740 figure 975. dual channel device mode single channel device mode the single channel device mode supports devices that have only one flexray port available. this flexray port consists of the signals fr_a_rx, fr_a_tx, and fr_a_tx_en and can be connected to either the physical bus channel a (shown in figure 976 ) or the physical bus channel b (shown in figure 977 ). if the device is configured as a single channel device by setting fr_mcr.scd to 1, only the internal channel a and the flexray port a is used. depending on the setting of fr_mcr.cha and fr_mcr.chb, the internal channel a behaves either as a flexray channel a or flexray channel b. the bit fr_mcr.cha must be set, if the flexray port a is connected to a flexray channel a. the bit fr_mcr.chb must be set if the flexray port a is connected to a flexray channel b. the two flexray channels differ only in the initial value for the frame crc ccrcinit . for a single channel device, the application can access and configure only the registers related to internal channel a. chi pe cfg(a) reg(a) ccrcinit[a] ccrcinit[b] cfg(b) reg(b) channel 0 channel 1 flexray channel a flexray bus driver channel a fr_a_rx fr_a_tx fr_a_tx_en flexray channel b flexray bus driver channel b fr_b_rx fr_b_tx fr_b_tx_en flexray flexray communication controller (flexray) RM0029 1606/1740 doc id 15177 rev 8 figure 976. single channel device mode (channel a) figure 977. single channel device mode (channel b) 33.6.11 external clock synchronization the application of the external rate and offset correction is triggered when the application writes to the eoc_ap and erc_ap fields in the protocol operation control register (fr_pocr) . the pe applies the external correction values in the next even-odd cycle pair as shown in figure 978 and figure 979 . chi pe cfg(a) reg(a) ccrcinit[a] ccrcinit[b] cfg(b) reg(b) channel a channel b flexray channel a flexray bus driver channel a fr_a_rx fr_a_tx fr_a_tx_en fr_b_rx fr_b_tx fr_b_tx_en flexray chi pe cfg(a) reg(a) ccrcinit[b] cfg(b) reg(b) channel a channel b flexray channel b init value for frame crc is ccrcinit[b] ccrcinit[a] flexray bus driver channel a fr_a_rx fr_a_tx fr_a_tx_en fr_b_rx fr_b_tx fr_b_tx_en flexray RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1607/1740 note: the values provided in the eoc_ap and erc_ap fields are the values that were written from the application most recently. if these value were already applied, they will not be applied in the current cycle pair again. if the offset correction applied in the nit of cycle 2n+1 shall be affect by the external offset correction, the eoc_ap field must be written to after the start of cycle 2n and before the end of the static segment of cycle 2n+1. if this field is written to after the end of the static segment of cycle 2n+1, it is not guaranteed that the external correction value is applied in cycle 2n+1. if the value is not applied in cycle 2n+1, then the value will be applied in the cycle 2n+3. refer to figure 978 for timing details. figure 978. external offset correction write and application timing if the rate correction for the cycle pair [2n+2, 2n+3] shall be affect by the external offset correction, the erc_ap field must be written to after the start of cycle 2n and before the end of the static segment start of cycle 2n+1. if this field is written to after the end of the static segment of cycle 2n+1, it is not guaranteed that the external correction value is applied in cycle pair [2n+2, 2n+3]. if the value is not applied for cycle pair [2n+2, 2n+3], then the value will be applied for cycle pair [2n+4, 2n+5]. refer to figure 979 for details. figure 979. external rate correction write and application timing 33.6.12 sync frame id and sync frame deviation tables the flexray protocol requires the provision of a snapshot of the synchronization frame id tables for the even and odd communication cycle for both channels. the cc provides the means to write a copy of these internal tables into the flexray memory area and ensures application access to consistent tables by means of table locking. once the application has locked the table successfully, the cc will not overwrite these tables and the application can read a consistent snapshot. note: only synchronization frames that have passed the synchronization frame filters are considered for clock synchronization and appear in the sync frame tables. sync frame id table content the sync frame id table is a snapshot of the protocol related variables vssyncidlista and vssyncidlistb for each even and odd communication cycle. this table provides a list of the frame ids of the synchronization frames received on the corresponding channel and cycle that are used for the clock synchronization. static segment nit static segment nit eoc_ap write window eoc_ap application cycle 2n cycle 2n+1 static segment nit erc_ap write window erc_ap application cycle 2n static segment nit cycle 2n+1 static segment nit cycle 2n+2 static segment nit cycle 2n+3 flexray communication controller (flexray) RM0029 1608/1740 doc id 15177 rev 8 sync frame deviation table content the sync frame deviation table is a snapshot of the protocol related variable zsdev(id)(oe)(ch)!value. each sync frame deviation table entry provides the deviation value for the sync frame, with the frame id presented in the corresponding entry in the sync frame id table. figure 980. sync table memory layout sync frame id and sync frame deviation table setup the cc writes a copy of the internal synchronization frame id and deviation tables into the flexray memory area if requested by the application. the application must provide the appropriate amount of flexray memory area for the tables. the memory layout of the tables is given in figure 980 . each table occupies 120 16-bit entries. while the protocol is in poc:config state, the application must program the offsets for the tables into the sync frame table offset register (fr_sftor) . sync frame id and sync frame deviation table generation the application controls the generation process of the sync frame id and sync frame deviation tables into the flexray memory area using the sync frame table configuration, control, status register (fr_sftccsr) . a summary of the copy modes is given in ta ble 90 6 . fr_sftor fr_sftor + 180 sync frame id cha 1 sync frame id cha 2 sync frame id cha 3 sync frame id cha 4 sync frame id cha 5 sync frame id cha 6 sync frame id cha 7 sync frame id cha 8 sync frame id cha 9 sync frame id cha 10 sync frame id cha 11 sync frame id cha 12 sync frame id cha 13 sync frame id cha 14 sync frame id cha 15 sync deviation cha 1 sync deviation cha 2 sync deviation cha 3 sync deviation cha 4 sync deviation cha 5 sync deviation cha 6 sync deviation cha 7 sync deviation cha 8 sync deviation cha 9 sync deviation cha 10 sync deviation cha 11 sync deviation cha 12 sync deviation cha 13 sync deviation cha 14 sync deviation cha 15 fr_sftor + 60 fr_sftor +120 sync frame id cha 1 sync frame id cha 2 sync frame id cha 3 sync frame id cha 4 sync frame id cha 5 sync frame id cha 6 sync frame id cha 7 sync frame id cha 8 sync frame id cha 9 sync frame id cha 10 sync frame id cha 11 sync frame id cha 12 sync frame id cha 13 sync frame id cha 14 sync frame id cha 15 sync deviation cha 1 sync deviation cha 2 sync deviation cha 3 sync deviation cha 4 sync deviation cha 5 sync deviation cha 6 sync deviation cha 7 sync deviation cha 8 sync deviation cha 9 sync deviation cha 10 sync deviation cha 11 sync deviation cha 12 sync deviation cha 13 sync deviation cha 14 sync deviation cha 15 offset + $00 offset + $02 offset + $04 offset + $06 offset + $08 offset + $0a offset + $0c offset + $0e offset + $10 offset + $12 offset + $14 offset + $16 offset + $18 offset + $1a offset + $1c sync frame id chb 1 sync frame id chb 2 sync frame id chb 3 sync frame id chb 4 sync frame id chb 5 sync frame id chb 6 sync frame id chb 7 sync frame id chb 8 sync frame id chb 9 sync frame id chb 10 sync frame id chb 11 sync frame id chb 12 sync frame id chb 13 sync frame id chb 14 sync frame id chb 15 sync deviation chb 1 sync deviation chb 2 sync deviation chb 3 sync deviation chb 4 sync deviation chb 5 sync deviation chb 6 sync deviation chb 7 sync deviation chb 8 sync deviation chb 9 sync deviation chb 10 sync deviation chb 11 sync deviation chb 12 sync deviation chb 13 sync deviation chb 14 sync deviation chb 15 sync frame id chb 1 sync frame id chb 2 sync frame id chb 3 sync frame id chb 4 sync frame id chb 5 sync frame id chb 6 sync frame id chb 7 sync frame id chb 8 sync frame id chb 9 sync frame id chb 10 sync frame id chb 11 sync frame id chb 12 sync frame id chb 13 sync frame id chb 14 sync frame id chb 15 sync deviation chb 1 sync deviation chb 2 sync deviation chb 3 sync deviation chb 4 sync deviation chb 5 sync deviation chb 6 sync deviation chb 7 sync deviation chb 8 sync deviation chb 9 sync deviation chb 10 sync deviation chb 11 sync deviation chb 12 sync deviation chb 13 sync deviation chb 14 sync deviation chb 15 offset + $1e offset + $20 offset + $22 offset + $24 offset + $26 offset + $28 offset + $2a offset + $2c offset + $2e offset + $30 offset + $32 offset + $34 offset + $36 offset + $38 offset + $3a fr_sfcntr sfeva sfevb fr_sfcntr sfoda sfodb even odd even odd RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1609/1740 the sync frame table generation process is described in the following for the even cycle. the same sequence applies to the odd cycle. if the application has enabled the sync frame table generation by setting fr_sftccsr[siden] to 1, the cc starts the update of the even cycle related tables after the start of the nit of the next even cycle. the cc checks if the application has locked the tables by reading the fr_sftccsr[elks] lock status bit. if this bit is set, the cc will not update the table in this cycle. if this bit is cleared, the cc locks this table and starts the table update. to indicate that these tables are currently updated and may contain inconsistent data, the cc clears the even table valid status bit fr_sftccsr[eval]. once all table entries related to the even cycle have been transferred into the flexray memory area, the cc sets the even table valid bit fr_sftccsr[eval] and the even cycle table written interrupt flag evt_if in the protocol interrupt flag register 1 (fr_pifr1) . if the interrupt enable flag evt_ie is set, an interrupt request is generated. to read the generated tables, the application must lock the tables to prevent the cc from updating these tables. the locking is initiated by writing a 1 to the even table lock trigger fr_sftccsr[elkt]. when the even table is not currently updated by the cc, the lock is granted and the even table lock status bit fr_sftccsr[elks] is set. this indicates that the application has successfully locked the even sync tables and the corresponding status information fields sfra, sfrb in the sync frame counter register (fr_sfcntr) . the value in the fr_sftccsr[cycnum] field provides the number of the cycle that this table is related to. the number of available table entries per channel is provided in the fr_sfcntr[sfeva] and fr_sfcntr[sfevb] fields. the application can now start to read the sync table data from the locations given in figure 980 . after reading all the data from the locked tables, the application must unlock the table by writing to the even table lock trigger fr_sftccsr[elkt] again. the even table lock status bit fr_sftccsr[elks] is reset immediately. if the sync frame table generation is disabled, the table valid bits fr_sftccsr[eval] and fr_sftccsr[eval] are reset when the counter values in the sync frame counter register (fr_sfcntr) are updated. this is done because the tables stored in the flexray table 906. sync frame table generation modes fr_sftccsr description opt sdven siden 0 0 0 no sync frame table copy 0 0 1 sync frame id tables will be copied continuously 010reserved 011 sync frame id tables and sync frame deviation tables will be copied continuously 1 0 0 no sync frame table copy 1 0 1 sync frame id tables for next even-odd-cycle pair will be copied 110reserved 111 sync frame id tables and sync frame deviation tables for next even-odd-cycle pair will be copied flexray communication controller (flexray) RM0029 1610/1740 doc id 15177 rev 8 memory area are no longer related to the values in the sync frame counter register (fr_sfcntr) . figure 981. sync frame table trigger and generation timing sync frame table access the sync frame tables will be transferred into the flexray memory area during the table write windows shown in figure 981 . during the table write, the application can not lock the table that is currently written. if the application locks the table outside of the table write window, the lock is granted immediately. sync frame table locking and unlocking the application locks the even/odd sync frame table by writing 1 to the lock trigger bit elkt/olkt in the sync frame table configuration, control, status register (fr_sftccsr) . if the affected table is not currently written to the flexray memory area, the lock is granted immediately, and the lock status bit elks/olks is set. if the affected table is currently written to the flexray memory area, the lock is not granted. in this case, the application must issue the lock request again until the lock is granted. the application unlocks the even/odd sync frame table by writing 1 to the lock trigger bit elkt/olkt. the lock status bit elks/olks is cleared immediately. 33.6.13 mts generation the cc provides a flexible means to request the transmission of the media access test symbol mts in the symbol window on channel a or channel b. the application can configure the set of communication cycles in which the mts will be transmitted over the flexray bus by programming the cyccntmsk and cyccntval fields in the mts a configuration register (fr_mtsacfr) and mts b configuration register (mtsbcfr) . the application enables or disables the generation of the mts on either channel by setting or clearing the mte control bit in the mts a configuration register (fr_mtsacfr) or mts b configuration register (mtsbcfr) . if an mts is to be transmitted in a certain communication cycle, the application must set the mte control bit during the static segment of the preceding communication cycle. the mts is transmitted over channel a in the communication cycle with number cyccnt, if equation , equation 63 , and equation 63 are fulfilled. equation 61 equation 62 fr_sftccsr.[opt,siden,sdven] write window even table write static segment nit static segment nit static segment nit cycle 2n-1 cycle 2n cycle 2n+1 odd table write fr_psr0 protstate [] poc:normal active = fr_mtsacrf mte [] 1 = RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1611/1740 equation 63 the mts is transmitted over channel b in the communication cycle with number cyccnt, if equation 62 , equation 64 , and equation 65 are fulfilled. equation 64 equation 65 33.6.14 key slot transmission key slot assignment a key slot is assigned to the cc if the key_slot_id field in the protocol configuration register 18 (fr_pcr18) is configured with a value greater than 0 and less or equal to number_of_static_slots in protocol configuration register 2 (fr_pcr2) , otherwise no key slot is assigned. key slot transmission in poc:startup if a key slot is assigned and the cc is in the poc:startup state, startup null frames will be transmitted as specified by flexray communications system protocol specification, version 2.1 rev a . key slot transmission in poc:normal active if a key slot is assigned and the cc is in poc:normal active , a frame of the type as shown in ta ble 90 7 is transmitted. if a transmit message buffer is configured for the key slot and a valid message is available, a message frame is transmitted (see section , message transmission ). if no transmit message buffer is configured for the key slot or no valid message is available, a null frame is transmitted (see section , null frame transmission ). cyccnt & fr_mtsacfr cyccntmsk [] fr_mtsacfr cyccntval [] & fr_mtsacfr cyccntmsk [] = fr_mtsbcrf mte [] 1 = cyccnt & fr_mtsbcfr cyccntmsk [] fr_mtsbcfr cyccntval [] & fr_mtsbcfr cyccntmsk [] = table 907. key slot frame type fr_pcr11[key_slot_used_for_sync] fr_pcr11[key_slot_used_for_startup] key slot frame type 0 0 normal frame 0 1 normal frame (1) 1 0 sync frame 1 1 startup frame 1. the frame transmitted has an semantically incorrect header and will be detected as an invalid frame at the receiver. flexray communication controller (flexray) RM0029 1612/1740 doc id 15177 rev 8 33.6.15 sync frame filtering each received synchronization frame must pass the sync frame acceptance filter and the sync frame rejection filter before it is considered for clock synchronization. if the synchronization frame filtering is globally disabled, that is, the sffe control bit in the module configuration register (fr_mcr) is cleared, all received synchronization frames are considered for clock synchronization. if a received synchronization frame did not pass at least one of the two filters, this frame is processed as a normal frame and is not considered for clock synchronization. sync frame acceptance filtering the synchronization frame acceptance filter is implemented as a value-mask filter. the value is configured in the sync frame id acceptance filter value register (fr_sfidafvr) and the mask is configured in the sync frame id acceptance filter mask register (fr_sfidafmr) . a received synchronization frame with the frame id fid passes the sync frame acceptance filter, if equation 66 or equation 67 evaluates to true. equation 66 equation 67 note: sync frames are transmitted in the static segment only. thus fid < 1023. sync frame rejection filtering the synchronization frame rejection filter is a comparator. the compare value is defined by the sync frame id rejection filter register (fr_sfidrfr) . a received synchronization frame with the frame id fid passes the sync frame rejection filter if equation 68 or equation 69 evaluates to true. equation 68 equation 69 note: sync frames are transmitted in the static segment only. thus fid < 1023. 33.6.16 strobe signal support the cc provides a number of strobe signals for observing internal protocol timing related signals in the protocol engine. the signals are listed and described in table 794 . strobe signal assignment each of the strobe signals listed in table 794 can be assigned to one of the four strobe ports using the strobe signal control register (fr_stbscr) . to assign multiple strobe signals, the application must write multiple times to the strobe signal control register (fr_stbscr) with appropriate settings. to read out the current settings for a strobe signal with number n, the application must execute the following sequence. fr_mcr sffe [] 0 = fid & fr_sfidafmr fmsk [] fr_sfidafvr fval [] & fr_sfidafmr fmsk [] = fr_mcr sffe [] 0 = fid fr_sfidrfr synfrid [] RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1613/1740 1. write to fr_stbscr with wmd = 1 and sel = n. (updates sel field only) 2. read stbcsr. the sel field provides n and the enb and stbpsel fields provides the settings for signal n. strobe signal timing this section provides detailed timing information of the strobe signals with respect to the protocol engine clock. the strobe signals display internal pe signals. due to the internal architecture of the pe, some signals are generated several pe clock cycles before the actual action is performed on the flexray bus. these signals are listed in table 794 with a negative clock offset. an example waveform is given in figure 982 . figure 982. strobe signal timing (type = pulse, clk_offset = -2) other signals refer to events that occurred on the flexray bus some cycles before the strobe signal is changed. these signals are listed in tab le 7 94 with a positive clock offset. an example waveform is given in figure 983 . figure 983. strobe signal timing (type = pulse, clk_offset = +4) 33.6.17 timer support the cc provides two timers, which run on the flexray time base. each timer generates a maskable interrupt when it reaches a configured point in time. timer t1 is an absolute timer. timer t2 can be configured to be an absolute or a relative timer . both timers can be configured to be repetitive. in the non-repetitive mode, timer stops if it expires. in repetitive mode, timer is restarted when it expires. both timers are active only when the protocol is in poc:normal active or poc:normal passive state. if the protocol is not in one of these modes, the timers are stopped. the application must restart the timers when the protocol has reached the poc:normal active or poc:normal passive state. pe clock strobe signal flexray bus event -2 pe clock strobe signal flexray bus event +4 flexray communication controller (flexray) RM0029 1614/1740 doc id 15177 rev 8 absolute timer t1 the absolute timer t1 has the protocol cycle count and the macrotick count as the time base. the timer 1 interrupt flag ti1_if in the protocol interrupt flag register 0 (fr_pifr0) is set at the macrotick start event, if equation 70 and equation 71 are fulfilled equation 70 equation 71 if the timer 1 interrupt enable bit ti1_ie in the protocol interrupt enable register 0 (fr_pier0) is asserted, an interrupt request is generated. the status bit t1st is set when the timer is triggered, and is cleared when the timer expires and is non-repetitive. if the timer expires but is repetitive, the t1st bit is not cleared and the timer is restarted immediately. the t1st is cleared when the timer is stopped. absolute / relative timer t2 the timer t2 can be configured to be an absolute or relative timer by setting the t2_cfg control bit in the timer configuration and control register (fr_ticcr) . the status bit t2st is set when the timer is triggered, and is cleared when the timer expires and is non- repetitive. if the timer expires but is repetitive, the t2st bit is not cleared and the timer is restarted immediately. the t2st is cleared when the timer is stopped. absolute timer t2 if timer t2 is configured as an absolute timer, it has the same functionality timer t1 but the configuration from timer 2 configuration register 0 (fr_ti2cr0) and timer 2 configuration register 1 (fr_ti2cr1) is used. on expiration of timer t2, the interrupt flag ti2_if in the protocol interrupt flag register 0 (fr_pifr0) is set. if the timer 1 interrupt enable bit ti1_ie in the protocol interrupt enable register 0 (fr_pier0) is asserted, an interrupt request is generated. relative timer t2 if the timer t2 is configured as a relative timer, the interrupt flag ti2_if in the protocol interrupt flag register 0 (fr_pifr0) is set, when the programmed amount of macroticks mt[31:0], defined by timer 2 configuration register 0 (fr_ti2cr0) and timer 2 configuration register 1 (fr_ti2cr1) , has expired since the trigger or restart of timer 2. the relative timer is implemented as a down counter and expires when it has reached 0. at the macrotick start event, the value of mt[31:0] is checked and then decremented. thus, if the timer is started with mt[31:0] == 0, it expires at the next macrotick start. 33.6.18 slot status monitoring the cc provides several means for slot status monitoring. all slot status monitors use the same slot status vector provided by the pe. the pe provides a slot status vector for each static slot, for each dynamic slot, for the symbol window, and for the nit, on a per channel base. the content of the slot status vector is described in ta ble 90 8 . the pe provides the cyctr ctccnt [] & fr_ti1cysr t1_cyc_msk [] fr_ti1cysr t1_cyc_val [] & fr_ti1cysr t1_cyc_msk [] = fr_mtctr mtct [] fr_ti1mtor t1_mtoffset [] = RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1615/1740 slot status vector within the first macrotick after the end of the related slot/window/nit, as shown in figure 984 . figure 984. slot status vector update note: the slot status for the nit of cycle n is provided after the start of cycle n+1. cycle start slot start slot start symbol window mt status(nit) mt status(slot 1) status(slot k) mt status(slot n) mt nit start status(sym.win) mt cycle start status(nit) communication cycle static segment dynamic segment symbol window nit slot 1 mt start flexray communication controller (flexray) RM0029 1616/1740 doc id 15177 rev 8 channel status error counter registers the two channel status error counter registers, channel a status error counter register (fr_casercr) and channel b status error counter register (fr_cbsercr) , incremented by one, if at least one of four slot status error bits, vss!syntaxerror , vss!contenterror , vss!bviolation , or vss!txconflict is set to 1. the status vectors for all slots in the static and dynamic segment, in the symbol window, and in the nit are taken into account. the counters wrap round after they have reached the maximum value. table 908. slot status content slot status content static / dynamic slot slot related status vss!validframe - valid frame received vss!syntaxerror - syntax error occurred while receiving vss!contenterror - content error occurred while receiving vss!bviolation - boundary violation while receiving for slots in which the module transmits: vss!txconflict - reception ongoing while transmission starts for slots in which the module does not transmit: vss!txconflict - reception ongoing while transmission starts first valid - channel that has received the first valid frame received frame related status extracted from a) header of valid frame, if vss!validframe = 1 b) last received header, if vss!validframe = 0 c) set to 0, if nothing was received vrf!header!nfindicator - null frame indicator (0 for null frame) vrf!header!sufindicator - startup frame indicator vrf!header!syfindicator - sync frame indicator symbol window window related status vss!validframe - always 0 vss!contenterror - content error occurred while receiving vss!syntaxerror - syntax error occurred while receiving vss!bviolation - boundary violation while receiving vss!txconflict - reception ongoing while transmission starts received symbol related status vss!validmts - valid media test access symbol received received frame related status see static/dynamic slot nit nit related status vss!validframe - always 0 vss!contenterror - content error occurred while receiving vss!syntaxerror - syntax error occurred while receiving vss!bviolation - boundary violation while receiving vss!txconflict - always 0 received frame related status see static/dynamic slot RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1617/1740 protocol status registers the protocol status register 2 (fr_psr2) provides slot status information about the network idle time nit and the symbol window. the protocol status register 3 (fr_psr3) provides aggregated slot status information. slot status registers the eight slot status registers, slot status registers (fr_ssr0?fr_ssr7) , can be used to observe the status of static slots, dynamic slots, the symbol window, or the nit without individual message buffers. these registers provide all slot status related and received frame / symbol related status information, as given in ta ble 90 8 , except of the first valid indicator for non-transmission slots. slot status counter registers the cc provides four slot status error counter registers, slot status counter registers (fr_sscr0?fr_sscr3) . each of these slot status counter registers is updated with the value of an internal slot status counter at the start of a communication cycle. the internal slot status counter is incremented if its increment condition, defined by the slot status counter condition register (fr_ssccr) , matches the status vector provided by the pe. all static slots, the symbol window, and the nit status are taken into account. dynamic slots are excluded . the internal slot status counting and update timing is shown in figure 985 . figure 985. slot status counting and fr_sscrn update the pe provides the status of the nit in the first slot of the next cycle. due to these facts, the fr_sscrn register reflects, in cycle n, the status of the nit of cycle n-2, and the status of all static slots and the symbol window of cycle n-1. the increment condition for each slot status counter consists of two parts, the frame related condition part and the slot related condition part. the internal slot status counter fr_sscrn_int is incremented if at least one of the conditions is fulfilled: 1. frame related condition: (fr_ssccrn[vfr] | fr_ssccrn[syf] | fr_ssccrn[nuf] | fr_ssccrn[suf]) // count on frame condition = 1; cycle start slot start slot start symbol window mt status(nit) mt status(slot 1) status(slot k) mt status(slot n) mt nit start status(sym.win) mt cycle start status(nit) communication cycle static segment dynamic segment symbol window nit slot 1 mt incr. fr_sscrn_int fr_sscrn = fr_sscrn_int fr_sscrn_int not updated fr_sscrn = fr_sscrn_int on error incr. fr_sscrn_int on error start flexray communication controller (flexray) RM0029 1618/1740 doc id 15177 rev 8 and ((~fr_ssccrn[vfr] | vss!validframe ) & // valid frame restriction (~fr_ssccrn[syf] | vrf!header!syfindicator ) & // sync frame indicator restriction (~fr_ssccrn[nuf] | ~ vrf!header!nfindicator ) & // null frame indicator restriction (~fr_ssccrn[suf] | vrf!header!sufindicator )) // startup frame indicator restriction = 1; note: the indicator bits syf, nuf, and suf are valid only when a valid frame was received. thus it is required to set the vfr always, whenever count on frame condition is used. 2. slot related condition: ((fr_ssccrn[statusmask[3]] & vss!contenterror ) | // increment on content error (fr_ssccrn[statusmask[2]] & vss!syntaxerror ) | // increment on syntax error (fr_ssccrn[statusmask[1]] & vss!bviolation ) | // increment on boundary violation (fr_ssccrn[statusmask[0]] & vss!txconflict )) // increment on transmission conflict = 1; if the slot status counter is in single cycle mode, that is, fr_ssccrn[mcy] = 0, the internal slot status counter fr_sscrn_int is reset at each cycle start. if the slot status counter is in the multicycle mode, that is, fr_ssccrn[mcy] = 1, the counter is not reset and incremented, until the maximum value is reached. message buffer slot status field each individual message buffer and each fifo message buffer provides a slot status field, which provides the information shown in table 908 for the static/dynamic slot. the update conditions for the slot status field depend on the message buffer type. refer to the message buffer update sections in section 33.6.6, individual message buffer functional description . 33.6.19 system bus access this section provides a description of the system bus accesses failures and the related cc behavior. system bus access failures may occur when the cc transfers data to or from the flexray memory area. the system bus access failure types are described in section , system bus access failure types . the behavior of the cc after the occurrence of a system bus access failure is described in section , system bus access failure response . system bus access failure types this section describes the two types of system bus access failures. the behavior of the cc after the occurrence of a system bus failure is defined by the sbff bit in the module configuration register (fr_mcr) . system bus illegal address access if the system bus detects an cc access to an illegal address, the cc receives a notification from the system bus about this event and sets the ilsa_ef flag in the chi error flag register (fr_chierfr) . RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1619/1740 system bus access timeout a system bus access timeout is detected if an access to the flexray memory area is not finished in time. the timeout value is derived from the symator[timeout] setting (see section , configure system memory access time-out register (fr_symator) . if a system bus access timeout is detected, the cc sets the sbcf_ef flag in the chi error flag register (fr_chierfr) . system bus access failure response this section describes the two types of behavior of the cc after the occurrence of a system bus access failure. the actual behavior is defined by the sbff bit in the module configuration register (fr_mcr) . continue after system bus access failure if the sbff bit in the module configuration register (fr_mcr) is 0, the cc will continue its operation after the occurrence of the system bus access failure, but will not generate any system bus accesses until the start of the next communication cycle.since no data are read from or written to the flexray memory area, no messages are received or transmitted. consequently, none of the individual message buffers or receive fifos will be updated until the next communication cycle starts. if a frame is under transmission when the system bus failure occurs, a correct frame is generated with the remaining header and frame data are replaced by all zeros. depending on the point in time this can affect the ppi bit, the header crc, the payload length in case of an dynamic slot, and the payload data. starting from the next slot in the current cycle, no frames will be transmitted and received, except for the key slot, where a sync or startup null- frame is transmitted, if the key slot is assigned. if a frame is received when the system bus failure occurs, the reception is aborted and the related receive message buffer is not updated. normal operation is resumed after the start of next communication cycle. freeze after system bus access failure if the sbff bit in the module configuration register (fr_mcr) is set to 1, the cc will go into the freeze mode immediately after the occurrence of one of the system bus access failures. 33.6.20 interrupt support the cc provides 172 individual interrupt sources and five combined interrupt sources. individual interrupt sources message buffer interrupts the cc provides 128 message buffer interrupt sources. each individual message buffer provides an interrupt flag fr_mbccsrn[mbif] and an interrupt enable bit fr_mbccsrn[mbie]. the cc sets the interrupt flag when the slot status of the message buffer was updated. if the interrupt enable bit is asserted, an interrupt request is generated. flexray communication controller (flexray) RM0029 1620/1740 doc id 15177 rev 8 fifo interrupts the cc provides two fifo interrupt sources. each of the two fifos provides a receive fifo almost full interrupt flag. the cc sets the receive fifo almost full interrupt flags (f r_gifer[fafbif], fr_gifer[fafaif]) in the global interrupt flag and enable register (fr_gifer) if the corresponding receive fifo fill level exceeds the defined watermark. wakeup interrupt the cc provides one interrupt source related to the wakeup. the cc sets the wakeup interrupt flag fr_gifer[wupif] when it has received a wakeup symbol on the flexray bus. the cc generates an interrupt request if the interrupt enable bit fr_gifer[wupie] is asserted. protocol interrupts the cc provides 25 interrupt sources for protocol related events. for details, see protocol interrupt flag register 0 (fr_pifr0) and protocol interrupt flag register 1 (fr_pifr1) . each interrupt source has its own interrupt enable bit. chi interrupts the cc provides 16 interrupt sources for chi related error events. for details, see chi error flag register (fr_chierfr) . there is one common interrupt enable bit fr_gifer[chie] for all chi error interrupt sources. combined interrupt sources each combined interrupt source generates an interrupt request only when at least one of the interrupt sources that is combined generates an interrupt request. receive message buffer interrupt the receive message buffer interrupt request is generated when at least one of the individual receive message buffers generates an interrupt request mbxirq[n] and the interrupt enable bit fr_gifer[rbie] is set. transmit message buffer interrupt the transmit message buffer interrupt request is generated when at least one of the individual transmit message buffers generates an interrupt request mbxirq[n] and the interrupt enable bit fr_gifer[tbie] is asserted. protocol interrupt the protocol interrupt request is generated when at least one of the individual protocol interrupt sources generates an interrupt request and the interrupt enable bit fr_gifer[prie] is set. chi interrupt the chi interrupt request is generated when at least one of the individual chi error interrupt sources generates an interrupt request and the interrupt enable bit fr_gifer[chie] is set. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1621/1740 module interrupt the module interrupt request is generated if at least one of the combined interrupt sources generates an interrupt request and the interrupt enable bit fr_gifer[mie] is set. figure 986. scheme of fr_gifer interrupt signal generation interrupt sources interrupt signals fr_mbccsrn[mbif] n fr_chierfr[15:0] 16 fr_pifr0[15:0] 16 fr_pifr1[9:0] 10 receive message buffer interrupt chi interrupt fr_gifer[fafaif] rx fifo a almost full interrupt fr_gifer[wupif] wakeup interrupt fr_gifer[rbie] fr_mbccsrn[mtd] rxbuf txbuf fr_gifer[prie] fr_gifer[wupie] fr_mbccsrn[mbie] & fr_pier0[15:0] fr_pier1[9:0] or & & & fr_gifer[chie] & & n & or transmit message buffer interrupt fr_gifer[tbie] & n or or & & fr_gifer[fafaie] fr_gifer[fafbif] rx fifo b almost full interrupt & fr_gifer[fafbie] & fr_gifer[rbif] fr_gifer[tbif] fr_gifer[prif] fr_gifer[chif] protocol interrupt fr_gifer n pe or & module interrupt fr_gifer[mif] fr_gifer[mie] rx fifo a rx fifo b protocol interrupt chi interrupt wakeup interrupt rx fifo a almost full interrupt rx fifo b almost full interrupt receive message buffer interrupt transmit message buffer interrupt flexray communication controller (flexray) RM0029 1622/1740 doc id 15177 rev 8 figure 987. scheme of fr_eeifer interrupt signal generation fr_eeifer[lrne_if] lram non-corrected error interrupt & lram ecc interrupt sources interrupt signals fr_eeifer fr_eeifer[lrne_ie] fr_eeifer[lrce_if] & fr_eeifer[lrce_ie] fr_eeifer[drne_if] & fr_eeifer[drne_ie] fr_eeifer[drce_if] & fr_eeifer[drce_ie] dram ecc lram corrected error interrupt dram non-corrected error interrupt dram corrected error interrupt RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1623/1740 figure 988. scheme of fr_cifr flags generation 33.6.21 lower bit rate support the cc supports a number of lower bit rates on the flexray bus channels. the lower bit rates are implemented by modifying the duration of the microtick pdmicrotick , the number of samples per microtick psamplespermicrotick , the number of samples per bit csamplesperbit , and the strobe offset cstrobeoffset. the application configures the flexray channel bit rate by setting the bitrate field in the module configuration register (fr_mcr) . the protocol values are set internally. the available bit rates, the related bitrate field configuration settings and related protocol parameter values are shown in ta ble 90 9 . interrupt sources fr_mbccsrn[mbif] n fr_chierfr[15:0] 16 fr_pifr0[15:0] 16 fr_pifr1[9:0] 10 fr_cifr[fafaif] fr_cifr[wupif] fr_mbccsrn[mtd] rxbuf txbuf or & n & or n or or fr_cifr[fafbif] fr_cifr[rbif] fr_cifr[tbif] fr_cifr[prif] fr_cifr[chif] fr_cifr n pe or fr_cifr[mif] rx fifo a rx fifo b flexray communication controller (flexray) RM0029 1624/1740 doc id 15177 rev 8 note: the bit rate of 8 mbit/s is not defined by the flexray communications system protocol specification, version 2.1 rev a. 33.6.22 pe data memory (pe dram) the pe data memory (pe dram) is 128 word, 16-bit wide memory with byte access, which contains the program data of the pe internal cpu. the pe dram is divided into two banks, 8-bit each. the memory data [7:0] are assigned to bank0, the memory data [15:8] are assigned to bank1. the flexray module provides means to access the pe dram from the application. the pe dram application access is initiated and controlled via pe dram access register (fr_pedrar) and pe dram data register (fr_pedrdr) . this functionality is used to check the memory error detection. pe dram read access a read access from the pe dram can be initiated in any protocol state. the following sequence describes a read access from the pe dram address 0x70. 1. fr_pedrar = 0x00e0; // inst = 0x0; addr = 070 2. wait until fr_pedrar[dad] == 1; // wait for end of pe dram access 3. val = fr_pedrdr[data]; // get read pe dram data the read access is handled by the pe internal cpu with the lowest execution priority. this may cause an response delay with a maximum of 1000 pe clock cycle (25s). table 909. flexray channel bit rate control flexray channel bit rate [mbit/s] fr_mcr.bitrate pdmicrotick [ns] gdsampleclockperiod [ns] psamplespermicrotick csamplesperbit cstrobeoffset 10.0 000 25.0 12.5 2 8 5 8.0 011 25.0 12.5 2 10 6 5.0 001 25.0 25.0 1 8 5 2.5 010 50.0 50.0 1 8 5 table 910. pe dram layout addr bank1 bank0 0x00 byte1 byte0 0x01 byte3 byte2 ... 0x7f byte255 byte254 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1625/1740 pe dram write access a write access into the pe dram can be initiated in any protocol state. the following sequence describes a write access to the pe dram address 0x70. 1. fr_pedrar = 0x30e0; // inst = 0x3; addr = 0x70 2. wait until fr_pedrar[dad] == 1; // wait for end of pe dram access 3. val = fr_pedrdr[data]; // get read back pe dram data the write access is handled by the pe internal cpu with the lowest execution priority. this may causes an response delay with a maximum of 1000 pe clock cycle (25s). if the conditions given in section , pe dram write access limitations are fulfilled, the data provided in pe dram data register (fr_pedrdr) are written into the pe dram, read back in the next clock cycle and stored into the pe dram data register (fr_pedrdr) . otherwise, data are not written into the pe dram and 0x0000 is stored into the pe dram data register (fr_pedrdr) . pe dram write access limitations the pe dram is used by the protocol engine if the module is not in poc:default config state. the only address not used by the protocol engine is 0x70. to prevent the corruption of protocol engine data the following pe dram write access limitations apply for application writes. 1. when the module is in poc:default config state, all pe dram addresses are writable. 2. when the module is not in poc:default config state, only pe dram address 0x70 is writable. 33.6.23 chi lookup-table memory (chi lram) the chi lookup-table memory (chi lram) is an chi internal memory which contains the message buffer configuration data. the configuration data for two message buffers are contained in one memory row. the chi lram is divided into six memory banks. the chi lram is accessed by the application via regular register read and write accesses. 33.6.24 memory content error detection the flexray module provides integrated memory content error detection for both the chi lram and pe dram, and memory content error correction for the pe dram. the memory error detection for the chi lram uses an standard hamming code with a hamming distance of 3 and detects all single-bit and double-bit errors (sedded). the memory error detection and correction for the pe dram uses an enhanced hamming code with a table 911. chi lram layout adr bank5 bank4 bank3 bank2 bank1 bank0 0x00 fr_mbidxr1 fr_mbfidr1 fr_mbccfr1 fr_mbidxr0 fr_mbfidr0 fr_mbccfr0 0x01 fr_mbidxr3 fr_mbfidr3 fr_mbccfr3 fr_mbidxr2 fr_mbfidr2 fr_mbccfr2 ... 0x1f fr_mbidxr127 fr_mbfidr127 fr_mbccfr127 fr_mbidxr126 fr_mbfidr126 fr_mbccfr126 flexray communication controller (flexray) RM0029 1626/1740 doc id 15177 rev 8 hamming distance of 4 and detects and corrects all single-bit errors and detects all double- bit errors (secded). this section describes the reporting of the occurrence of memory content errors, the reaction of the module on the occurrence, and how the application can inject memory errors in order to trigger the report and response behavior. memory error types a memory error is the distortion of one or more bits read out of the memory. the reading of the values of all zeros and all ones is considered as an special case. the flexray module detects and indicates the memory errors as shown in table 912 . the entries on the top have higher priority. each memory read access reads out all banks of the addressed row, and runs error detection on all banks, even in the case that the application has triggered a read from only one bank. this may lead to the reporting of an memory error if at least one bank contains a memory error, even if an error free bank has been read. memory error reporting the memory error reporting is enabled only if the ecc functionality enable bit ecce in the module configuration register (fr_mcr) is set. for each of the two memories exists two sets of internal registers to store the detection of one corrected and one non-corrected memory error. table 912. detected memory error types memory priority memory data indication chi lram 0 (highest) all zero?s no error ? valid data pe dram non-corrected error chi lram all one?s non-corrected error pe dram chi lram 1 (lowest) one bit flipped non-corrected error pe dram corrected error chi lram two bits flipped non-corrected error pe dram chi lram three or more bits flipped one out of {no error, non-corrected error}, defined by coding given in section , chi lram checkbits and section , chi lram checkbits pe dram one out of {no error, corrected error, non-corrected error}, defined by coding given in section , pe dram checkbits and section , pe dram syndrome RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1627/1740 if a memory error is detected, the module checks whether the related error interrupt flag in the ecc error interrupt flag and enable register (fr_eeifer) is set. if the error interrupt flag is set, the related internal error reporting register is not updated and the related error overflow flag is set to 1 to indicate a loss of error condition. if the error interrupt flag is not set, the internal reporting register is updated and the error interrupt flag is set to 1. if two or more memory errors of the same type are detected, the error for the bank with the lower bank number will be reported, and the error overflow flag will be set to 1. if a memory error is detected for at least two banks of one memory, the related error overflow flag is set to 1 to indicate a loss of error condition. pe dram checkbits the coding of the checkbits reported in ecc error report code register (fr_eercr) for pe dram memory errors is shown in table 914 . this table shows the implemented enhanced hamming code. if the error injection was applied to distort the checkbits, then the distorted checkbits are reported. this coding of the checkbit ensures that neither 0x000 nor 0xfff are valid code words and written into the memory pe dram syndrome the coding of the syndrome reported in ecc error report code register (fr_eercr) for pe dram memory errors is shown in table 914 . table 913. pe dram checkbits coding code code data 321076543210 4 (1) xxxxxxxxxxxx 3 (2) ???? x x x x ???? 2 ???? x ??? x x x? 1 ????? x x ? x x ?x 0 ????? x ? x x ? x x 1. the checkbit code[4] is set to 1 if and only if there is a even number of 1?s in columns with x. 2. the checkbits code[3]... code[0] are set to 1 if and onl y if there is a odd number of 1?s in all columns with x. flexray communication controller (flexray) RM0029 1628/1740 doc id 15177 rev 8 chi lram checkbits the coding of the checkbits reported in ecc error report code register (fr_eercr) for chi lram memory errors is shown in table 915 . this table shows the implemented hamming code. if the error injection was applied to distort the checkbits, then the distorted checkbits are reported. ??? table 914. fr_eercr[code] pe dram syndrome coding fr_eercr[code] description [4] [3:0] 0x1 0x0 no error (never appears in error report registers) 0x0 0x0 if data == 0: non-corrected error (dedicated handling of all zero code word) if data != 0: corrected error (parity bit 4) 0x0 0x1 corrected error (parity bit 0) 0x0 0x2 corrected error (parity bit 1) 0x0 0x3 corrected error (data bit 0) 0x0 0x4 corrected error (parity bit 2) 0x0 0x5 corrected error (data bit 1) 0x0 0x6 corrected error (data bit 2) 0x0 0x7 corrected error (data bit 3) 0x0 0x8 corrected error (parity bit 3) 0x0 0x9 corrected error (data bit 4) 0x0 0xa corrected error (data bit 5) 0x0 0xb corrected error (data bit 6) 0x0 0xc corrected error (data bit 7) 0x0 0xd ? 0xf non-corrected error 0x1 0x1 ? 0xf non-corrected error table 915. chi lram checkbits coding code (1) data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 xxxxx ??????????? 3 ????? xxxxxxx???? 2 xx???xxxx???xxx? 1 ??xx?xx??xx?xx?x 0 x?x?x x?x?x?x x?x x 1. the checkbit code[n] is set to 1 if and only if there is a odd number of 1?s in all columns with x. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1629/1740 chi lram syndrome the coding of the syndrome reported in ecc error report code register (fr_eercr) for chi lram memory errors is shown in table 916 . memory error response the memory error response is enabled only when the ecc functionality enable bit ecce in the module configuration register (fr_mcr) is set. in case of the detection of a corrected memory error, the flexray module continues its normal operation using the corrected data word. this section describes the behavior of the flexray module after the detection of a non-corrected memory error. chi lram memory error response after module read the flexray module reads the message buffer configuration buffer data located in the chi lram for each message buffer one time in each slot and in the nit. if a non-corrected memory error is detected during this module read access, the flexray module will consider the affected message buffer as disabled for the current search and will exclude this buffer from the search. the configuration of the affected message buffer is not changed. if the affected message buffer is a tx message buffer, no frame will be transmitted from this message buffer in the next slot. if the affected message buffer is a rx message buffer, no frame will be received to this message buffer in the next slot. chi lram memory error response after application read the application can read the content of the chi lram via reading the fr_mbccfrn, fr_mbfidrn, and fr_mbidxrn registers. if a non-corrected memory error is detected during this kind of read access, the module indicates the detected memory error, delivers the non-corrected data read and continues its normal operation. pe dram error response after module read if the module detects an non-corrected memory error during read of program data which is contained in pe dram, this is considered as an fatal protocol error and the module enters the protocol freeze state immediately. pe dram error response after application read in poc:default config state if the module detects an non-corrected memory error during an application triggered read from any pe dram address and the protocol is in the poc:default config state, this is considered as an fatal protocol error and the module enters the protocol freeze state. this behavior allows for checking the freeze functionality in case of the detection of non- corrected errors. table 916. fr_eercr[code] chi lram syndrome coding fr_eercr[code] description 0x00 no error (never appears in error report registers) 0x01 ? 0x1f non-corrected error flexray communication controller (flexray) RM0029 1630/1740 doc id 15177 rev 8 pe dram error response after application read out of poc:default config if the module detects an non-corrected memory error during an application triggered read from any pe dram address, and the protocol is not in the poc:default config state, this error is not considered as an fatal error and the protocol state is not changed. this prevents any interference of the running protocol by pe dram error injection reads. 33.6.25 memory error injection the error injection functionality is used by the application to inject data errors into the memories to trigger and check the memory error detection functionality. the error injection is enabled only if the ecc functionality enable bit ecce in the module configuration register (fr_mcr) and the error injection enable control bit eie in the ecc error report and injection control register (fr_eericr) are set. the error injection mode is configured by the eim configuration bit in the ecc error report and injection control register (fr_eericr) .when the error injection is enabled, each write access to the configured memory location will be distorted. the injector has the same behavior for flexray module memory writes and application memory writes. chi lram error injection the following sequence describes an error injection sequence for the chi lram. this sequence includes the setup of the error injector followed by an application triggered write access to provoke an distortion of the memory content. when the flexray module is in poc:default config , there are no limitations and impacts of error injection for the application. for error injection out of poc:default config see section 33.7.3, chi lram error injection out of poc:default config . injector setup: 1. fr_mcr[ecce] = 1; enable ecc functionality 2. fr_eerice[eie] = i_mode; configure error injection mode 3. fr_eeiar[mid] = 1; select chi lram for error injection 4. fr_eeiar[bank] = i_bank; define the bank for error injection; i_bank = {0,1,2,3,4,5} 5. fr_eeiar[addr] = i_addr; define the address for error injection; 0 <= i_addr <= 0x1f 6. fr_eeidr[data] = d_dist; define the data distortion pattern 7. fr_eeicr[code] = c_dist; define the checkbit distortion pattern 8. fr_eerice[eie] = 1; enable error injection application write access: RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1631/1740 1. if (i_bank==0) ? fr_mbccfr(2*i_addr) = data; if (i_bank==1) ? fr_mbfidr(2*i_addr) = data; if (i_bank==2) ? fr_mbidxr(2*i_addr) = data; if (i_bank==3) ? fr_mbccfr(2*i_addr+1) = data; if (i_bank==4) ? fr_mbfidr(2*i_addr+1) = data; if (i_bank==5) ? fr_mbidxr(2*i_addr+1) = data; write data to the defined injection bank and injection address pe dram error injection the following sequence describes an error injection sequence for the pe dram. this sequence includes the setup of error injector followed by an application triggered write access to provoke an distortion of the memory content. when the flexray module is in poc:default config , there are no limitations and impacts of error injection for the application. for error injection out of poc:default config see section 33.7.4, pe dram error injection out of poc:default config . injector setup: 1. fr_mcr[ecce] = 1; ? enable ecc functionality 2. fr_eerice[eie] = i_mode; ? configure error injection mode 3. fr_eeiar[mid] = 0; ? select pe dram for error injection 4. fr_eeiar[bank] = i_bank; ? define the bank for error injection; i_bank = {0,1} 5. fr_eeiar[addr] = i_addr; ? define the address for error injection; 0<= i_addr <= 0x7f 6. fr_eeidr[data] = d_dist; ? define the data distortion pattern 7. fr_eeicr[code] = c_dist; ? define the checkbit distortion pattern 8. fr_eerice[eie] = 1; ? enable error injection application write access (i_addr = 0x70): 1. fr_pedrar:= 0x30e0; // inst = 0x3; addr = 0x70 2. wait until fr_pedrar[dad] == 1; // wait for end of pe dram access 3. val = fr_pedrdr[data]; // get read back pe dram data note: the write access to the pe dram triggers a read from pe dram in the next cycle, which triggers the detection of the distorted data. 33.7 application information 33.7.1 module configuration this section describes essential parts of the module configuration. flexray communication controller (flexray) RM0029 1632/1740 doc id 15177 rev 8 configure system memory access time-out register (fr_symator) to ensure reliable operation of the cc, the application has to ensure that the timeout value in system memory access time-out register (fr_symator) and the chi clock frequency f chi in mhz fulfill equation 72 (bk) . equation 72 if the symator[timeout] value and f chi violates equation 72 , the behavior of the cc becomes unreliable and undefined. it may happen that frames are not transmitted at all, including key slot frames. for a given symator[timeout] value f chi can be increased without causing unreliable operation of the cc. the same holds for reducing the symator[timeout] value for a given f chi . some examples for maximum values of the symator[timeout] for a minimum chi frequency are given in table 917 . system bus wait state constraints the symator[timeout] value corresponds directly to a certain acceptable number of wait states on the system bus. for single channel configurations and if the sync frame table generation functionality is not used (fr_sftccsr[sdven,siden] = 0) no timeout will be detected if less than 2*symator[timeout] + 1 wait states will be seen on the system bus for each system bus access. for dual channel configurations, or if the sync frame table generation functionality is used, no timeout will be detected if less than symator[timeout] - 1 wait states will be seen on the system bus for each system bus access. 33.7.2 initialization sequence this section describes the required steps to initialize the cc. the first subsection describes the steps required after a system reset, the second section describes the steps required after preceding shutdown of the cc. bk. see section 33.3, controller host interface clocking for all constraints of minimum chi clock frequency. 0 symator[timeout] 0.45 f chi ? 8 ? ? table 917. maximum symator[timeout] examples f chi symator[timeout] f chi symator[timeout] 18 mhz 0 100 mhz 37 23 mhz 2 120 mhz 46 27 mhz 4 140 mhz 55 32 mhz 6 160 mhz 64 60 mhz 19 180 mhz 73 80 mhz 28 200 mhz 82 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1633/1740 module initialization this section describes the module related initialization steps after a system reset. 1. configure cc. a) configure the control bits in the module configuration register (fr_mcr) b) configure the system memory base address in system memory base address register (fr_symbadr) 2. enable the cc. a) write 1 to the module enable bit men in the module configuration register (fr_mcr) the cc now enters the normal mode. the application can commence with the protocol initialization described in section , protocol initialization . protocol initialization this section describes the protocol related initialization steps. 1. configure the protocol engine. a) issue config command via protocol operation control register (fr_pocr) b) wait for poc:config in protocol status register 0 (fr_psr0) c) configure the fr_pcr0,..., fr_pcr30 registers to set all protocol parameters 2. configure the message buffers and fifos. a) set the number of message buffers used and the message buffer segmentation in the message buffer segment size and utilization register (fr_mbssutr) b) define the message buffer data size in the message buffer data size register (fr_mbdsr) c) configure each message buffer by setting the configuration values in the message buffer configuration, control, status registers (fr_mbccsrn) , message buffer cycle counter filter registers (fr_mbccfrn) , message buffer frame id registers (fr_mbfidrn) , message buffer index registers (fr_mbidxrn) d) configure the fifos e) issue config_complete command via protocol operation control register (fr_pocr) f) wait for poc:ready in protocol status register 0 (fr_psr0) after this sequence, the cc is configured as a flexray node and is ready to integrate into the flexray cluster. chi lram initialization the module will start reading chi lram data if it has entered the start up state, thus, all ecc bits have to set correctly. to fulfill this requirement, the application must write initial values into all message buffer configuration registers fr_mbccfrn, fr_mbfidrn, and fr_mbidxrn during the protocol config state, even if the message buffers are not used. pe dram initialization the pe dram initialization is performed by the module in the poc:default config state. this initialization runs for 4.8 s, and will delay the state transition from poc:default config into poc:config . flexray communication controller (flexray) RM0029 1634/1740 doc id 15177 rev 8 33.7.3 chi lram error injection out of poc:default config when the flexray module is out of the poc:default config state, it reads the configuration data of all utilized message buffers in every slot. if the module reads the chi lram address that was used for error injection, an memory error is detected and the message buffer is not used for transmission or reception. this section describes how to inject errors on the chi lram without disturbing the running application. set injection address to fr_eeidr[addr] = 0x1f ? only the last two message buffers are affected by error injection utilize less than 63 message buffers; fr_mbssutr[last_mb_util] 62 ? the last two message buffers are not used and configuration data are not read by the module 33.7.4 pe dram error injection out of poc:default config when the flexray module is out of the poc:default config state, only the pe dram address 0x70 is writable by the application. this location is not used by the flexray module. 33.7.5 shut down sequence this section describes a secure shut down sequence to stop the cc. the main targets of this sequence are finish all ongoing reception and transmission do not corrupt flexray bus and do not disturb ongoing flexray bus communication for a shutdown the application shall perform the following tasks: 1. disable all enabled message buffers. a) repeatedly write ?1? to fr_mbccsrn[edt] until fr_mbccsrn[eds] == 0. 2. stop protocol engine. a) issue halt command via protocol operation control register (fr_pocr) b) wait for poc:halt in protocol status register 0 (fr_psr0) 33.7.6 number of usable message buffers this section describes the required minimum chi clock frequency for a specified number of utilized message buffers configured in the message buffer segment size and utilization register (fr_mbssutr) , a configured minislot length gdminislot , and a configured nominal macrotick length gdmacrotick (bl) . additional constraints for the minimum chi clock frequency are given in section 33.3, controller host interface clocking . the cc uses a sequential search algorithm to determine the individual message buffer assigned or subscribed to the next slot. this search is started at the start of slot and must be finished before the start of the next slot. the shortest flexray slot is an corrected empty dynamic slot. an corrected empty dynamic slot is a minislot and consists of gdminislot corrected macroticks with a duration of bl. see section 33.3, controller host interface clocking for all constraints of minimum chi clock frequency. RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1635/1740 gdmacrotick . the minimum duration of an corrected macrotick is gdmacrotick min = 39 t. this results in a minimum length of an correct slot equation 73 the message buffer search engine runs on the chi clock and evaluates one individual message buffer per chi clock cycle. for internal status update operations and to account for clock domain crossing jitter, an additional amount of 10 chi clock cycles is required to ensure correct search engine operation. for a given number of utilized message buffers fr_mbssutr[last_mb_util] + 1 and for a given chi clock frequency f chi , this results in a search duration of equation 74 the message buffer search must be finished within one slot which requires that equation 75 must be fulfilled: equation 75 this results in the formula given in equation 76 which determines the required minimum chi frequency for a given number of message buffers that are utilized. equation 76 the required minimum chi clock frequency for a selected set of relevant protocol parameters and for the last_mb_util field in the message buffer segment size and utilization register (fr_mbssutr) set to 127 is given in ta ble 91 8 . 33.7.7 protocol control command execution this section considers the issues of the protocol control command execution. the application issues any of the protocol control commands listed in the poccmd field of ta ble 79 8 by writing the command to the poccmd field of the protocol operation control register (fr_pocr) . as a result the cc sets the bsy bit while the command is transferred slotmin 39 pdmicrotick gdminislot ?? = search 1 f chi -------- - fr_mbssutr[last_mb_util]+10 () ? = search slotmin [] () 39 pdmicrotick gdminislot ?? ------------------------------------------------------------------------------------------------------ table 918. minimum f chi [mhz] examples (128 message buffers) pdmicrotick [ns] gdminislot 234567 25.0 70.77 47.18 35.39 28.31 23.59 20.22 50.0 35.39 23.59 17.70 14.16 11.80 10.11 flexray communication controller (flexray) RM0029 1636/1740 doc id 15177 rev 8 to the pe. when the pe has accepted the command, the bsy flag is cleared. all commands are accepted by the pe. the pe maintains a protocol command vector. for each command that was accepted by the pe, the pe sets the corresponding command bit in the protocol command vector. if a command is issued while the corresponding command bit is set, the command is not queued and is lost. if the command execution block of the pe is idle, it selects the next accepted protocol command with the highest priority from the current protocol command vector according to the protocol control command priorities given in table 919 . if the current protocol state does not allow the execution of this protocol command (see poc state changes in flexray communications system protocol specification, version 2.1 rev a ) the cc asserts the illegal protocol command interrupt flag ipc_if in the protocol interrupt flag register 1 (fr_pifr1) . the protocol command is not executed in this case. some protocol commands may be interrupted by other commands or the detection of a fatal protocol error as indicated by table 919 . if the application issues the freeze or ready command, or if the pe detects a fatal protocol error, some commands already stored in the command vector will be removed from this vector. 33.7.8 message buffer search on simple message buffer configuration this sections describes the message buffer search behavior for a simplified message buffer configuration. the fifo behavior is not considered in this section. simple message buffer configuration a simple message buffer configuration is a configuration that has at most one transmit message buffer and at most one receive message buffer assigned to a slot s . the simple table 919. protocol control command priorities protocol command priority interrupted by cleared and terminated by freeze (highest) 1 none ready 2 config_complete 3 all_slots 4 freeze, ready, config_complete, fatal protocol error freeze, ready, config_complete, fatal protocol error allow_coldstart 5 run 6 freeze, fatal protocol error wakeup 7 freeze, fatal protocol error default_config 8 freeze, fatal protocol error config 9 halt (lowest) 10 freeze, ready, config_complete, fatal protocol error RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1637/1740 configuration used in this section utilizes two message buffers, one single buffered transmit message buffer and one receive message buffer. the transmit message buffer has the message buffer number t and is configured as shown in ta ble 92 0 . the availability of data in the transmit buffer is indicated by the commit bit fr_mbccsrt[cmt] and the lock bit fr_mbccsrt[lcks]. the receive message buffer has the message buffer number r and is configured as shown in ta ble 92 1 . furthermore the assumption is that both message buffers are enabled (fr_mbccsr t [eds] = 1 and fr_mbccsr r [eds] = 1). note: the cycle set {4n+2} = {2,6,10,...} is assigned to the receive buffer only. the cycle set {4n} = {0,4,8,12,...} is assigned to both buffers. table 920. transmit buffer configuration register field value description fr_mbccsr t mcm ? used only for double buffers mbt 0 single transmit buffer mtd 1 transmit buffer fr_mbccfr t mtm 0 event transition mode cha 1 assigned to channel a chb 0 not assigned to channel b ccfe 1 cycle counter filter enabled ccfmsk 000011 cycle set = {4n} = {0,4,8,12,...} ccfval 000000 fr_mbfidr t fid s assigned to slot s table 921. receive buffer configuration register field value description fr_mbccsr r mcm ? n/a mbt ? n/a mtd 0 receive buffer fr_mbccfr r mtm ? n/a cha 1 assigned to channel a chb 0 not assigned to channel b ccfe 1 cycle counter filter enabled ccfmsk 000001 cycle set = {2n} = {0,2,4,6,...} ccfval 000000 fr_mbfidr r fid s subscribed slot flexray communication controller (flexray) RM0029 1638/1740 doc id 15177 rev 8 behavior in static segment in this case, both message buffers are assigned to a slot s in the static segment. the configuration of a transmit buffer for a static slot s assigns this slot to the node as a transmit slot. the flexray protocol requires: when a slot occurs, if the slot is assigned to a node on a channel that node must transmit either a normal frame or a null frame on that channel. specifically, a null frame will be sent if there is no data ready, or if there is no match on a transmit filter (cycle counter filtering, for example). regardless of the availability of data and the cycle counter filter, the node will transmit a frame in the static slot s. in any case, the result of the message buffer search will be the transmit message buffer t. the receive message buffer r will not be found, no reception is possible. behavior in dynamic segment in this case, both message buffers are assigned to a slot s in the dynamic segment. the flexray protocol requires: when a slot occurs, if a slot is assigned to a node on a channel that node only transmits a frame on that channel if there is data ready and there is a match on relevant transmit filters (no null frames are sent). the transmission of a frame in the dynamic segment is determined by the availability of data and the match of the cycle counter filter of the transmit message buffer. transmit data not available if transmit data are not available , that is, the transmit buffer is not committed fr_mbccsr t [cmt] = 0 and/or locked fr_mbccsr t [lcks] = 1, a) for the cycles in the set {4n}, which is assigned to both buffers, the receive buffer will be found and the node can receive data, and b) for the cycles in the set {4n + 2}, which is assigned to the receive buffer only, the receive buffer will be found and the node can receive data. the receive cycles are shown in figure 989 figure 989. transmit data not available transmit data available if transmit data are available , that is, the transmit buffer is committed fr_mbccsr t [cmt] = 1 and not locked fr_mbccsr t [lcks] = 0, a) for the cycles in the set {4n}, which is assigned to both buffers, the transmit buffer will be found and the node transmits data. b) for the cycles in the set {4n + 2}, which is assigned to the receive buffer only, the receive buffer will be found and the node can receive data. 0 rx 1 2 rx 3 4 rx 5 6 rx 7 59 60 rx 61 62 rx 8 rx 63 RM0029 flexray communication controller (flexray) doc id 15177 rev 8 1639/1740 the receive and transmit cycles are shown in figure 989 . figure 990. transmit data not available 0 tx 1 2 rx 3 4 tx 5 6 rx 7 59 60 tx 61 62 rx 8 tx 63 periodic interrupt timer (pit_rti) RM0029 1640/1740 doc id 15177 rev 8 34 periodic interrupt timer (pit_rti) 34.1 information specific to this device this section presents device-specific parameterization and customization information not specifically referenced in the remainder of this chapter. 34.1.1 device-specific features 1 periodic interrupt timer module (pit/rti) ? 32-bit counter ? 4 timer channels ? 1 real time interrupt (rti): timer channel clocked from the crystal oscillator that can be used to wake the part from stop mode. the counter period of a running timer can be modified, by first disabling the timer, setting a new load value and then enabling the timer again (see figure 998 ). in the case of the rti, because of the different clock domains (system clock / oscillator clock), a delay must be respected between setting the new value and re-enabling the rti. (modification to section , timers / rti .). 34.2 introduction figure 991 shows the pit block diagram. RM0029 periodic interrupt timer (pit_rti) doc id 15177 rev 8 1641/1740 figure 991. block diagram of pit_rti 34.2.1 overview this specification describes the function of the periodic interrupt timer block (pit_rti). the pit is an array of timers that can be used to raise interrupts and trigger dma channels. real time interrupt timer (rti) is a dedicated interrupt timer, which runs on a separate clock and can be used for system wakeup. 34.2.2 features the main features of this block are: timers can generate dma trigger pulses timers can generate interrupts all interrupts are maskable independent timeout periods for each timer rti timer n timer 1 . . . pit registers peripheral interrupts timeout load_value peripheral pit . . . triggers independent rti oscillator bus clock bus clock periodic interrupt timer (pit_rti) RM0029 1642/1740 doc id 15177 rev 8 34.3 signal description the pit module has no external pins. 34.4 memory map and register description this section provides a detailed description of all registers accessible in the pit_rti module. 34.4.1 memory map ta ble 92 2 gives an overview of all pit_rti registers. note: register address = base address + address offset, where the base address is defined at the mcu level and the address offset is defined at the module level. note: reserved registers will read as 0, writes will have no effect. 34.4.2 register descriptions this section describes in address order all the pit_rti registers and their individual bits. pit module control register (pitmcr) this register controls whether the timer clocks should be enabled and whether the timers should run in debug mode. table 922. pit_rti memory map address offset use access location 0x000 pit module control register (pitmcr) r/w on page 34-1642 0x004?0x0ec reserved r ? 0x0f0?0x0fc rti channel (1) 1. see table 923 . 0x100?0x10c timer channel 0 1 0x110?0x11c timer channel 1 1 0x120?0x12c timer channel 2 1 0x130?0x13c timer channel 3 1 table 923. timer channel n / rti channel registers address offset use access location channel + 0x00 timer load value register n (ldvaln) r/w on page 34-1643 channel + 0x04 current timer value register n (cvaln) r on page 34-1644 channel + 0x08 timer control register n (tctrln) r/w on page 34-1645 channel + 0x0c timer flag register n (tflgn) r/w on page 34-1646 RM0029 periodic interrupt timer (pit_rti) doc id 15177 rev 8 1643/1740 timer load value register n (ldval n ) these registers select the timeout period for the timer interrupts. in the case of the rti, it will take several cycles until this value is synchronized into the rti clock domain. for all other timers the value change is visible immediately. the synchronization mechanism allows 0 wait states in this case. figure 992. pit module control register (pitmcr) offset 0x000 access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000 0 0 0 0 mdis _rti mdis frz w reset0000000000000000 table 924. pitmcr field descriptions field description mdis_rti module disable?rti section this is used to disable the rti timer. this bit should be enabled before any rti setup is done. 0: clock for rti is enabled (default) 1: clock for rti disabled mdis module disable?pit section this is used to disable the standard timers. the rti timer is not affected by this bit. this bit should be enabled before any other setup is done. 0: clock for pit timers is enabled (default) 1: clock for pit timers is disabled frz freeze allows the timers to be stopped when the device enters debug mode. 0: timers continue to run in debug mode. 1: timers are stopped in debug mode. periodic interrupt timer (pit_rti) RM0029 1644/1740 doc id 15177 rev 8 current timer value register n (cval n ) these registers indicate the current timer position. in the case of the rti, this will show a value which is several cycles old, since it originates from a potentially different clock domain. figure 993. timer load value register (ldval) offset channel_base + 0x00 access: read/write 0123456789101112131415 r tsv31 tsv30 tsv29 tsv28 tsv27 tsv26 tsv25 tsv24 tsv23 tsv22 tsv21 tsv20 tsv19 tsv18 tsv17 tsv16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tsv15 tsv14 tsv13 tsv12 tsv11 tsv10 tsv9 tsv8 tsv7 tsv6 tsv5 tsv4 tsv3 tsv2 tsv1 tsv0 w reset0000000000000000 table 925. ldval field descriptions field description tsv n time start value bits these bits set the timer start value. the timer will count down until it reaches 0, then it will generate an interrupt and load this register value again. writing a new value to this register will not restart the timer, instead the value will be loaded once the timer expires. to abort the current cycle and start a timer period with the new value, the timer must be disabled and enabled again (see figure 998 ). note: for the rti, the timer should not be set to a value lower than 32 cycles, otherwise interrupts may be lost, as it takes several cycles to clear the rti interrupt. for the other timers, this limit does not apply, however there will be practical limits, since the processor will require several cycles to service an interrupt. RM0029 periodic interrupt timer (pit_rti) doc id 15177 rev 8 1645/1740 timer control register n (tctrl n ) these registers contain the control bits for each timer. figure 994. current timer value register (cval) offset channel_base + 0x04 access: read/write 0123456789101112131415 r tvl3 1 tvl3 0 tvl2 9 tvl2 8 tvl2 7 tvl2 6 tvl2 5 tvl2 4 tvl2 3 tvl2 2 tvl2 1 tvl2 0 tvl1 9 tvl1 8 tvl1 7 tvl1 6 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tvl1 5 tvl1 4 tvl1 3 tvl1 2 tvl11 tvl1 0 tvl9 tvl8 tvl7 tvl6 tvl5 tvl4 tvl3 tvl2 tvl1 tvl0 w reset0000000000000000 table 926. cval field descriptions field description tvl n current timer value these bits represent the current timer value. note that the timer uses a downcounter. note: the timer values will be frozen in debug mode if the frz bit is set in the pit module control register (see figure 992 ). figure 995. timer control register (tctrl) offset channel_base + 0x08 access: read/write 0123456789101112131415 r 0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000000000 tie ten w reset0000000000000000 periodic interrupt timer (pit_rti) RM0029 1646/1740 doc id 15177 rev 8 timer flag register n (tflg n ) these registers hold the pit interrupt flags. 34.5 functional description 34.5.1 general this section gives detailed information on the internal operation of the module. each timer can be used to generate trigger pulses as well as to generate interrupts, each interrupt will be available on a separate interrupt line. additionally the rti timer can be used to wakeup the processor. table 927. tctrl field descriptions field description tie timer interrupt enable bit 0: interrupt requests from timer x are disabled 1: interrupt will be requested whenever tif is set when an interrupt is pending (tif set), enabling the interrupt will immediately cause an interrupt event. to avoid this, the associated tif flag must be cleared first. ten timer enable bit 0: timer will be disabled 1: timer will be active figure 996. timer flag register (tflg) offset channel_base + 0x0c access: read/write 0123456789101112131415 r 0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000000 tif w reset0000000000000000 table 928. tflg field descriptions field description tif time interrupt flag tif is set to 1 at the end of the timer period.this flag can be cleared only by writing it with a 1. writing a 0 has no effect. if enabled (tie = 1), tif causes an interrupt request. 0: timeout has not yet occurred 1: timeout has occurred RM0029 periodic interrupt timer (pit_rti) doc id 15177 rev 8 1647/1740 timers / rti the timers generate triggers at periodic intervals, when enabled. they load their start values, as specified in their ldval registers, then count down until they reach 0. then they load their respective start value again. each time a timer reaches 0, it will generate a trigger pulse, and set the interrupt flag. all interrupts can be enabled or masked (by setting the tie bits in the tctrl registers). a new interrupt can be generated only after the previous one is cleared. since in the case of the rti, clearing the interrupt crosses clock domains, a minimum load value of 32 should be maintained. if desired, the current counter value of the timer can be read via the cval registers. the value of the rti counter can be delayed considerably, as it is synchronized to the bus clock from the rti clock domain. the counter period can be restarted, by first disabling, then enabling the timer with the ten bit (see figure 997 ). the counter period of a running timer can be modified, by first disabling the timer, setting a new load value and then enabling the timer again (see figure 998 ). it is also possible to change the counter period without restarting the timer by writing the ldval register with the new load value. this value will then be loaded after the next trigger event (see figure 999 ). figure 997. stopping and starting a timer figure 998. modifying running timer period figure 999. dynamically setting a new load value p1 p1 timer enabled disable timer p1 start value = p1 trigger event p1 re-enable timer p1 timer enabled disable timer, start value = p1 trigger event re-enable timer p1 set new load value p2 p2 p2 p1 p1 timer enabled new start value p2 set p1 p2 start value = p1 p2 trigger event periodic interrupt timer (pit_rti) RM0029 1648/1740 doc id 15177 rev 8 debug mode in debug mode the timers will be frozen?this is intended to aid software development, allowing the developer to halt the processor, investigate the current state of the system (e.g. the timer values) and then continue the operation. 34.5.2 interrupts all of the timers support interrupt generation. the rti is typically used for system wakeup, but can be used for interrupt generation as well. refer to the section ?functional description? in chapter 15: interrupt controller (intc) for related vector addresses and priorities. timer interrupts can be disabled by setting the tie bits to zero. the timer interrupt flags (tif) are set to 1 when a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to that tif bit. the pit_rti generates a real time interrupt when the selected interrupt time period elapses. the rti interrupt is disabled locally by setting the tie bit to zero. the real time interrupt flag (tif) is set to 1 when a timeout occurs, and is cleared by writing a 1 to the tif bit. (the flag will be set regardless of whether the interrupt is enabled.) the rti can be used for periodic wakeup from a low power mode. it can also be used to generate a general purpose interrupt. 34.6 initialization and application information 34.6.1 example configuration in the example configuration the pit clock has a frequency of 50 mhz the rti clock has a frequency of 10 mhz the rti shall be set up to create a wakeup interrupt every 500 ms timer 1 shall create an interrupt every 5.12 ms timer 3 shall create a trigger event every 30 ms first the pit module needs to be activated by writing a 0 to the mdis bit in the pitmcr. the 50 mhz clock frequency equates to a clock period of 20 ns and the 10 mhz frequency equates to a clock period of 100 ns. therefore the rti timer needs to trigger every 500 ms/100 ns = 5000000 cycles. timer 1 needs to trigger every 5.12 ms/20 ns = 256000 cycles and timer 3 every 30 ms/20 ns = 1500000 cycles. the value for the ldval register trigger would be calculated as (period / clock period) ? 1. this means that rti ldval will be written with 0x004c_4b3f, ldval1 with 0x0003_e7ff and ldval3 with 0x0016_e35f. to generate the wakeup interrupt, the interrupt line must be enabled by writing a 1 to the rti tie bit in the tctrl register. to start the rti, the ten bit in the rti tctrl register must also be set. the interrupt for timer 1 is enabled by setting the tie bit in the tctrl1 register. the timer is started by writing a 1 to bit ten in the tctrl1 register. timer 3 shall be used only for triggering. therefore timer 3 is started by writing a 1 to bit ten in the tctrl3 register, bit tie stays at 0. RM0029 periodic interrupt timer (pit_rti) doc id 15177 rev 8 1649/1740 the following example code matches the described setup: // turn on pit pit_ctrl = 0x00; // rti pit_rti_ldval = 0x004c4b3f; // setup rti for 5000000 cycles pit_rti_tctrl = pit_tie; // let rti generate interrupts pit_rti_tctrl |= pit_ten; // start rti // timer 1 pit_ldval1 = 0x0003e7ff; // setup timer 1 for 256000 cycles pit_tctrl1 = tie; // enable timer 1 interrupts pit_tctrl1 |= ten; // start timer 1 // timer 3 pit_ldval3 = 0x0016e35f; // setup timer 3for 1500000 cycles pit_tctrl3 = ten; // start timer 3 power management controller (pmc) RM0029 1650/1740 doc id 15177 rev 8 35 power management controller (pmc) 35.1 introduction internally, spc564a74xx, spc564a80xx devices have four supply voltages, nominally 5 v, 3.3 v, 1.2 v and 1.0 v v stby . externally only a 5 v supply is required. the other voltages are supplied by internal regulators. all supply voltages have voltage monitors and both the v dd regulator and all monitors are adjustable. the pmc controls the internal voltage supplies, with the exception of v stby , which has its own regulator. additionally the pmc controls the low voltage inhibit (lvi) circuits and power-on reset (por) functions. note that although spc564a74xx, spc564a80xx devices have features intended for use in low-power applications, reduced power modes are achieved by clock gating. it is not possible to switch off the power to any on-chip module. reduced power consumption is achieved by turning off the system clock to the modules. see chapter 5: operating modes and clocking for details. the power management controller contains circuitry to generate the internal 3.3 v supply and to control the regulation of 1.2 v supply with external npn ballast transistor. it also contains low voltage inhibit (lvi) and power-on reset (por) circuits for the 1.2 v supply, the 3.3 v supply, the 3.3 v/5 v supply of the closest i/o segment (vddeh1) and the 5 v supply of the regulators (vddreg). there is no requirement for special power up or down sequencing. vddreg can be tied to vss to bypass the 3.3 v and 1.2 v internal regulators. note: although it is possible to bypass the internal regulators by tying the vddreg to ground (vss), doing so also disables most pmc functions, e.g., the user-programmable lvis. regulators and power supply lvi/por control blocks use a precision bandgap voltage reference. a low impedance buffered version of the absolute and curvature corrected bandgap voltage reference is available to be measured using an adc dedicated channel. the pmc block has the following operating modes: normal mode low power ram test vddreg supply grounded (see section 35.4, functional description for details) RM0029 power management controller (pmc) doc id 15177 rev 8 1651/1740 35.1.1 block diagram figure 1000.power management controller diagram vddreg vddreg vddeh vdd33 vdd vdd lvi-vddreg lvi-vddeh lvi-vdd33 lvi-vdd lvi-1p0 vrcctl vddsns vdd33 vssreg vddreg vddeh vdd33 vdd por-vddreg por-vddeh por-vdd33 por-vdd reg1p2ref por-vddreg reg-3p3ref por-vddreg vbgref lvi3p3ref lvi1p2ref lvi1p0ref reg3p3ref reg1p2ref lvi/vreg reference lvi5-vddreg lvi3-vddeh lvi3-vdd33 lvi1.2-vdd lvi1.0-vdd por5-vddreg por3-vddeh por3-vdd33 por1.2-vdd vreg1p2 vreg3p3 digital interface configuration and status registers trimming register por-vddeh, por-vdd33, por_vdd lvi-vddreg, lvi-vddeh, lvi-vdd33, lvi-vdd lvreh, lvre50, lvre33, lvrec lvi from lvrer reset-pin segment por from reset-pin segment por analog kernel vhhgenerator vddreg vdd33 vddeh vhh vhh vhh vssa_lvi vrc3p3sns vssreg vssreg vssreg vssreg vssa_lvi (only for lvi vssreg resistive dividers) power management controller (pmc) RM0029 1652/1740 doc id 15177 rev 8 figure 1001.bandgap reference block diagram 35.2 external signal description ta ble 92 9 provides an overview of the pmc supply signals. 35.2.1 detailed signal descriptions this section provides the descriptions of external signals coming into and going out of the power management control unit. bandgap reference vbg absolute ref vbg buffer vbg trim por-vddreg vbg abs trim vbgref vddreg dvss vbgref vref_buff avss avss avss dvss vddreg vddreg table 929. power management controller external signals (maximum ratings) name type voltage description vddreg supply 4.5 ? 5.5 v power supply for the voltage regulator vddeh1 supply 2.7 ? 5.5 v power supply of the closest i/o segment vrc33 (1) , (2) supply 3.3 ? 3.6 v 3.3 v bypass capacitor or 3.3 v external power supply vdd supply 1.2 ? 1.32 v 1.2 v supply from external ballast transistor vssreg ground ? ground supply for digital core and pmc vrcctl output ? regulator drive for external npn base 1. this table represents the maximum vari ation of the supply when internal regulators are used. for external power supply requirements check the pmc electrical specifications in the ?pmc operating conditions and external regulators voltage? table in the device datasheet. 2. within the pmc block, the signal vdd33 is the output of the internal 3.3 v voltage regulator and the signal vrc33 is used as the feedback of the internal 3.3 v voltage regulator. t hese signals are shorted together on the production package. throughout this document, references to vrc33 and v dd33 refer to the production package signal vrc33. RM0029 power management controller (pmc) doc id 15177 rev 8 1653/1740 vddreg quiet 5 v supply for the voltage regulator and lvi block. it must have an external decoupling capacitor of the order of 4.7 f ? 20 f. regulators and lvi can be turned off by grounding vddreg. in this case external regulation and low voltage control must be supplied. vddeh1 power supply input (5 v or 3.3 v nominal), taken from one of the pad ring i/o segment which is near the voltage regulator. vrc33 when the internal 3.3 v voltage regulator is enabled, this pin must be connected to an external bypass capacitor of 600 nf ? 2 f with low esr (max 50 m ). if the voltage regulator is not powered or the regulator is disabled (pin vddreg to ground or shutdown bit pmc_sr[v33dis] set to ?1?), this pin must be connected to an external 3.3 v supply. vdd this is the 1.2 v supply coming from the emitter of an external npn ballast transistor, whose base current is supplied by vrcctl. if the internal voltage regulator controller is not powered (pin vddreg tied to ground) or the external ballast transistor is not present, the vdd pin must be connected to an external 1.2 v power supply. for maximum transient performance, the recommended bypass capacitor for each pin that supplies the digital core is 2.2 f ? 6 f with very low esr (max 50 m ). a ceramic capacitor is also desirable, with 100 nf capacitance. moreover, a 1 f to 2 f cap might be connected to the base of the external bipolar. vrcctl 1.2 v regulator output that drives the base of the external npn transistor. 35.3 memory map/register definition ta ble 93 0 shows the pmc memory map. the pmc memory map has three registers for configuring, monitoring, and trimming the lvi monitors. note: the pmc base address (pmc_base) is 0xc3fb_c000. register addresses in this chapter are given as offsets to pmc_base. table 930. power management controller memory map address register location pmc_base (0xc3fb_c000) + 0x0000 mcr ? module configuration register on page 35- 1654 pmc_base (0xc3fb_c000) + 0x0004 trimr ? trimming register on page 35- 1656 pmc_base (0xc3fb_c000) + 0x0008 sr ? status register on page 35- 1659 power management controller (pmc) RM0029 1654/1740 doc id 15177 rev 8 35.3.1 module configuration register (mcr) the configuration register contains configuration and reset and interrupt enable bits for the lvi monitors. please note that in the spc564a74xx, spc564a80xx devices the lvi reset is equivalent to a por. after an lvi reset, bit siu_rsr[pors] is set and the pmc_sr is reset?no lvi event information is retained. to enable application to report an lvi event, disable the reset using the appropriate field, i.e., lvrer or lvreh, and enable the interrupt for the lvi using its interrupt enable field, e.g., lvier. you must make sure that the isr will be finished before the voltage sinks below its functional specification and this may require an increase in the lvi level. the software system reset and the por/lvi reset are handled differently by the device. see section 4.5, reset source descriptions for more details. after a software system reset different status flags are set in the siu_rsr register. note: lvi resets and interrupts are only enabled when the voltage regulator is enabled (vddreg = 5 v). if the user grounds vddreg (vddreg = 0 v) and supplies the voltages externally (1.2 v and 3.3 v), it is also necessary to provide the lvi monitoring externally. figure 1002.module confi guration register (mcr) offset: pmc_base + 0x0000 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r lvrer lvreh lvre50 lvre33 lvrec 0 0 0 lvier lvieh lvie50 lvie33 lvic 00 tlk w reset 1001100000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 000000 0 0 00 0000 w reset 0000000000000000 table 931. mcr field descriptions field description 0 lvrer reset-pin-supply lvi (vddeh6) lvi reset enable this bit defines whether an lvi assertion on the vddeh6 supply will generate system reset or not. 0 no reset?lvi assertion on the supply of the i/o segment that contains the reset pin does not cause system reset. 1 reset?lvi assertion on the supply of the i/o segment that contains the reset pin causes system reset. 1 lvreh vddeh1 lvi reset enable this bit defines whether an lvi assertion on the vddeh1 supply will generate system reset or not. 0 no reset?lvi assertion on the vddeh supply does not cause system reset. 1 reset?lvi assertion on the vddeh supply causes system reset. RM0029 power management controller (pmc) doc id 15177 rev 8 1655/1740 2 lvre50 5 v lvi reset enable this bit defines whether an lvi assertion on the 5 v supply of the voltage regulator (vddreg) will generate system reset or not. 0 no reset?lvi assertion on the 5 v supply of the voltage regulator does not cause system reset. 1 reset?lvi assertion on the 5 v supply of the voltage regulator causes system reset. 3 lvre33 3.3 v lvi reset enable this bit defines whether an lvi assertion on the 3.3 v supply will generate system reset or not. 0 no reset?lvi assertion on the 3.3 v supply does not cause system reset. 1 reset?lvi assertion on the 3.3 v supply causes system reset. 4 lvrec 1.2 v lvi reset enable this bit defines whether an lvi assertion on the 1.2 v supply will generate system reset or not. 0 no reset?lvi assertion on the 1.2 v supply does not cause system reset. 1 reset?lvi assertion on the 1.2 v supply causes system reset. 5:7 reserved 8 lvier reset-pin-supply (vddeh6) lvi enable this bit enables the generation of the lvi interrupt request when the vddeh6 lvi falls below the corresponding lvi threshold. the lvi interrupt is independent from lvi reset. if both, interrupt and reset, are enabled, then reset and interrupt will be generated, but reset will then clear the interrupt. 0 disabled?lvi interrupt request is disabled. 1 enabled?lvi interrupt request is enabled. 9 lvieh vddeh1 lvi enable this bit enables the generation of the lvi interrupt request when the vddeh1 supply falls below the corresponding lvi threshold. the lvi interrupt is independent from lvi reset. if both, interrupt and reset, are enabled, then reset and interrupt will be generated, but reset will then clear the interrupt. 0 disabled?lvi interrupt request is disabled. 1 enabled?lvi interrupt request is enabled. 10 lvie50 5 v lvi enable this bit enables the generation of the lvi interrupt request when the 5 v supply of the voltage regulator (vddreg) falls below the corresponding lvi threshold. the lvi interrupt is independent from lvi reset. if both, interrupt and reset, are enabled, then reset and interrupt will be generated, but reset will then clear the interrupt. 0 disabled?lvi interrupt request is disabled. 1 enabled?lvi interrupt request is enabled. 11 lvie33 3.3 v lvi enable this bit enables the generation of the lvi interrupt request when the 3.3 v power supply goes below the corresponding lvi threshold. the lvi interrupt is independent from lvi reset. if both, interrupt and reset, are enabled, then reset and interrupt will be generated, but reset will then clear the interrupt. 0 disabled?lvi interrupt request is disabled. 1 enabled?lvi interrupt request is enabled. 12 lvic 1.2 v lvi enable this bit enables the generation of the lvi interrupt request when the 1.2 v power supply goes below the corresponding lvi threshold. the lvi interrupt is independent from lvi reset. if both, interrupt and reset, are enabled, then reset and interrupt will be generated, but reset will then clear the interrupt. 0 disabled?lvi interrupt request is disabled. 1 enabled?lvi interrupt request is enabled. table 931. mcr field descriptions (continued) field description power management controller (pmc) RM0029 1656/1740 doc id 15177 rev 8 35.3.2 trimming register (trimr) the trimming register enables the user to fine tune the voltage of the regulators and the lvi thresholds. it can only be written when bit pmc_mcr[tlk] is negated. once pmc_mcr[tlk] has been asserted, this register becomes read-only until the next system reset. 13?14 reserved, should be cleared 15 tlk trimming lock this is a set-only bit that comes out of reset negated, and can be asserted one time after reset to lock the trimming register. once asserted, it cannot be negated anymore. when tlk is asserted, the trimming register becomes read-only and cannot be changed until the next reset. 0 trimming register can be written. 1 trimming register is read-only. 16:31 reserved table 931. mcr field descriptions (continued) field description figure 1003.trimming register (trimr) offset: pmc_base + 0x0004 access: user read/write 0123456789101112131415 r 0 000 0 000 0 000 lvdregtrim w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r vdd33trim lvd33trim vddctrim lvdctrim w reset0000000000000000 table 932. trimr field descriptions field description 0?11 reserved, should be cleared RM0029 power management controller (pmc) doc id 15177 rev 8 1657/1740 12?15 lvdregtrim lvi 5 v trimming this field is used to fine tune the voltage threshold of the 5 v rising lvi, which is used to monitor the vddreg supply. nominal configuration: 0111 4.43 v 0110 4.41 v 0101 4.39 v 0100 4.37 v 0011 4.35 v 0010 4.33 v 0001 4.31 v 0000 4.29 v default. 1111 4.27 v 1110 4.25 v 1101 4.23 v 1100 4.21 v 1011 4.19 v 1010 4.17 v 1001 4.15 v 1000 4.13 v 16?19 vdd33trim vreg 3.3 v trimming this field is used to fine tune the voltage of the 3.3 v regulator. nominal configuration: 0111 3.60 v 0110 3.57 v 0101 3.54 v 0100 3.51 v 0011 3.48 v 0010 3.45 v 0001 3.42 v 0000 3.39 v default. 1111 3.36 v 1110 3.33 v 1101 3.30 v 1100 3.27 v 1011 3.24 v 1010 3.21 v 1001 3.18 v 1000 3.15 v table 932. trimr field descriptions (continued) field description power management controller (pmc) RM0029 1658/1740 doc id 15177 rev 8 20?23 lvd33trim lvi 3.3 v trimming this field is used to fine tune the voltage threshold of the 3.3 v rising lvi, which is used to monitor the 3.3 v regulated output and the vddeh supply. nominal configuration: 0111 3.23 v 0110 3.21 v 0101 3.19 v 0100 3.17 v 0011 3.15 v 0010 3.13 v 0001 3.11 v 0000 3.09 v default. 1111 3.07 v 1110 3.05 v 1101 3.03 v 1100 3.01 v 1011 2.99 v 1010 2.97 v 1001 2.95 v 1000 2.93 v the recommended value for the lvd33trim is 0b0011. in the cut 1 device, the register should be written by software. 24?27 vddctrim vreg 1.2 v trimming this field is used to fine tune the voltage of the 1.2 v regulator. nominal configuration: 0111 1.42 v 0110 1.40 v 0101 1.38 v 0100 1.36 v 0011 1.34 v 0010 1.32 v 0001 1.30 v 0000 1.28 v default. 1111 1.26 v 1110 1.24 v 1101 1.22 v 1100 1.20 v 1011 1.18 v 1010 1.16 v 1001 1.14 v 1000 1.12 v table 932. trimr field descriptions (continued) field description RM0029 power management controller (pmc) doc id 15177 rev 8 1659/1740 35.3.3 status register (sr) the status register contains interrupt flag bits for the lvd monitors. 28?31 lvdctrim lvi 1.2 v trimming this field is used to fine tune the voltage threshold of the 1.2 v rising lvi. nominal configuration: 0111 1.30 v 0110 1.28 v 0101 1.26 v 0100 1.24 v 0011 1.22 v 0010 1.20 v 0001 1.18 v 0000 1.16 v default 1111 1.14 v 1110 1.12 v 1101 1.10 v 1100 1.08 v 1011 1.06 v 1010 1.04 v 1001 1.02 v 1000 1.0 v table 932. trimr field descriptions (continued) field description figure 1004.status register (sr) offset: pmc_base + 0x0008 access: user read/write 012345 6 7 89 101112131415 r 0 000 0 lvfvstby bgrdy bgts 0 000 0 00 v33dis w lvfcstby reset000000 0 0 00 0 00 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 lvfr lvfh lvf50 lvf33 lvfc 0 0 0 w lvfcr lvfch lvfc50 lvfc33 lvfcc reset000000 0 0 00 0 00 0 00 power management controller (pmc) RM0029 1660/1740 doc id 15177 rev 8 table 933. sr field descriptions field description 0?4 reserved 5 lvfvstby brown out flag this bit indicates that a brown out condition was detected on the ram standby regulator switch. 0 no brown out detected 1 brown out detected 6 bgrdy bandgap status1 this read-only bit is asserted when the bandgap circuit has finished its startup procedure during power-up. the lvis are disabled (output negated) while bgrdy is negated. 0 bandgap not ready?lvis disabled 1 bandgap ready?lvis enabled 7 bgts bandgap status 2 this read-only bit stores bandgap temperature status information. 0 temperature out of range?above 160 c 1 temperature in range?below 160 c 8:12 reserved 13 lvfcstby standby-ram-supply lvf clear this write-only bit is used to clear the low-voltage flag reported by the ram standby regulator switch. writing 1 to this bit informs the ram standby regulator switch to clear lvfvstby. writing 0 has no effect. reading this bit always returns 0. 0 no effect 1 clears lvfvstby 14 reserved 15 v33dis 3.3 v internal regulator shutdown status bit 0 enabled?vreg3p3 on 1 disabled?vreg3p3 off 16 lvfcr reset-pin-supply (vddeh6) lvi clear this write-only bit is used to clear the lvi interrupt flag associated with the vddeh6 supply. writing 1 to this bit clears the lvfr flag. writing 0 has no effect. reading this bit always return 0. 0 no effect 1 clears the lvfr flag 17 lvfch vddeh1 lvi clear this write-only bit is used to clear the lvi interrupt flag associated with the vddeh1 supply. writing 1 to this bit clears the lvfh flag. writing 0 has no effect. reading this bit always return 0. 0 no effect 1 clears the lvfh flag 18 lvfc50 5 v lvi clear this write-only bit is used to clear the lvi interrupt flag associated with the 5 v voltage regulator supply (vddreg). writing 1 to this bit clears the lvf50 flag. writing 0 has no effect. reading this bit always return 0. 0 no effect 1 clears the lvf50 flag RM0029 power management controller (pmc) doc id 15177 rev 8 1661/1740 19 lvfc33 3.3 v lvi clear this write-only bit is used to clear the lvi interrupt flag associated with the 3.3 v supply. writing 1 to this bit clears the lvf33 flag. writing 0 has no effect. reading this bit always return 0. 0 no effect 1 clears the lvf33 flag 20 lvfcc 1.2 v lvi clear this write-only bit is used to clear the lvi interrupt flag associated with the 1.2 v supply. writing 1 to this bit clears the lvfc flag. writing 0 has no effect. reading this bit always return 0. 0 no effect 1 clears the lvfc flag 21:23 reserved 24 lvfr reset-pin-supply (vddeh6) lvi flag this read-only bit is the lvi interrupt flag associated with the vddeh6 supply. it is asserted when the supply falls below the corresponding lvi threshold, and can be cleared by the cpu by writing 1 to the lvfcr bit. if the lvier bit is also asserted, an lvi interrupt is sent to the cpu. if lvrer is also asserted, a system reset will be generated, which will clear the lvfr flag and negate the interrupt request. 0 no occurrence 1 lvi occurrence detected on the vddeh6 supply 25 lvfh vddeh1 lvi flag this read-only bit is the lvi interrupt flag associated with the vddeh1 supply. it is asserted when the supply falls below the corresponding lvi threshold, and can be cleared by the cpu by writing 1 to the lvfch bit. if the lvieh bit is also asserted, an lvi interrupt is sent to the cpu. if lvreh is also asserted, a system reset will be generated, which will clear the lvfh flag and negate the interrupt request. 0 no occurrence 1 lvi occurrence detected on the vddeh1 supply 26 lvf50 5 v lvi flag this read-only bit is the lvi interrupt flag associated with the 5 v supply of the voltage regulator. it can be cleared by the cpu by writing 1 to the lvfc50 bit. if the lvie50 bit is also asserted, an lvi interrupt is sent to the cpu. if lvre50 is also asserted, a system reset will be generated, which will clear the lvf50 flag and negate the interrupt request. 0 no occurrence 1 lvi occurrence detected on the 5 v supply of the voltage regulator 27 lvf33 3.3 v lvi flag this read-only bit is the lvi interrupt flag associated with the 3.3 v supply. it is asserted when the 3.3 v supply falls below the corresponding lvi threshold, and can be cleared by the cpu by writing 1 to the lvfc33 bit. if the lvie33 bit is also asserted, an lvi interrupt is sent to the cpu. if lvre33 is also asserted, a system reset will be generated, which will clear the lvf33 flag and negate the interrupt request. 0 no occurrence 1 lvi occurrence detected on the 3.3 v supply table 933. sr field descriptions (continued) field description power management controller (pmc) RM0029 1662/1740 doc id 15177 rev 8 35.4 functional description the power management controller provides the base current for an external ballast transistor to generate the 1.2 v supply. it also contains a 3.3 v regulator and several por / lvi voltage monitors for system supervision. a 5 v loose tolerance detection circuit (por 5 v) is used to determine if the supply voltage vddreg is high enough to guarantee the startup of bandgap voltage reference. as a consequence 5 v and 3 v lvis can safely startup with reliable output value. the device is kept in reset until 5 v lvi has been cleared, allowing for correct 3.3 v regulator, 1.2 v regulator and 1.2 v lvi startup. internal 3.3 v and 1.2 v por are included to provide minimum low voltage reset capability. internal 3.3 v and 1.2 v por are included to provide minimum low voltage reset capability. the voltage regulators can be disabled to support the connection of external power supplies to the 3.3 v and 1.2 v pins. it can be done in two ways: 1. grounding vddreg internal regulators are automatically disabled, external bipolar transistor is omitted. in this case, all lvi monitors are also disabled. therefore, when using external power supplies and grounding vddreg, the user has to provide external lvi monitoring. 2. keeping vddreg powered external bipolar transistor is omitted, 3.3 v internal regulator is disabled after startup by setting the v33dis bit in the nvusro register (non volatile user option register in the flash memory. see section 35.4.3, 3.3 v internal voltage regulator for more details.). in this case there is no need of external lvi monitoring. as pors are powered by vhh their value is reliable also when vddreg is grounded, as long as vddeh1 or vdd33 are at the correct voltage. 35.4.1 bandgap the bandgap voltage of the pmc is capable of generating a reference voltage of 1.219 v. it is used as reference to generate all supply voltages, for this reason it is powered directly out of the 5 v domain to avoid startup racing conditions. supply voltage range is from 4.5 v to 5.5 v. the bandgap shall work with decreased performance down to 4.0 v supply. the bandgap is calibrated during factory test?see the ?pmc electrical characteristics? table in the device datasheet for accuracy details. the calibration data is typically stored in 28 lvfc 1.2 v lvi flag this read-only bit is the lvi interrupt flag associated with the 1.2 v supply. it is asserted when the 1.2 v supply falls below the corresponding lvi threshold, and can be cleared by the cpu by writing 1 to the lvfcc bit. if the lvic bit is also asserted, an lvi interrupt is sent to the cpu. if lvrec is also asserted, a system reset will be generated, which will clear the lvfc flag and negate the interrupt request. 0 no occurrence 1 lvi occurrence detected on the 1.2 v supply 29:31 reserved table 933. sr field descriptions (continued) field description RM0029 power management controller (pmc) doc id 15177 rev 8 1663/1740 flash memory and is automatically read from the flash every time the part is initiated through reset. the default lvi thresholds are set to a safe value that accommodates the full uncalibrated bandgap range, so that external voltages can be applied in the specified ranges?see the ?pmc electrical characteristics? table in the device datasheet for details. the bandgap has two monitor signals: bandgap_ok and temperature_ok. the former is low during startup and rises when bandgap reference has settled (uses an internal por on the bandgap supply); the latter is a low accuracy temperature sensor, which goes low when an over temperature condition has occurred, i.e., when local temperature is higher than 160 ? 200 c. both signals and por value are available in the status register (pmc_sr) as bandgap status bits. bandgap is powered by the same supply of the voltage regulator. when voltage regulator supply is removed (to allow for external powering of 3.3 v and 1.2 v domains), bandgap voltage reference will also be disabled. 35.4.2 5 v lvi a programmable low voltage monitor is connected internally to the 5 v supply that feeds the voltage regulator (vddreg). the output of the lvi goes to logical 1 when the monitored voltage rises above the lvi rising trip point. in case the monitored voltage falls below the falling trip point, the lvi output goes to logical 0. the assertion and negation voltages are adjustable via software by writing to field pcm_trimr[lvdregtrim], which selects one of the 16 voltages available. the reset value of the 4-bit register is ?0000?, corresponding to the rising trip point voltage of 4.29 v. this is the typical default value, the real default value may vary from sample to sample according to process, temperature and voltage supply conditions, as detailed in the ?pmc electrical characteristics? table in the device datasheet. 35.4.3 3.3 v internal voltage regulator the 3.3 v internal voltage regulator supplies a total dc current of up to 80 ma or a maximum transient current peak up to 300 ma (if the external decoupling capacitor has the recommended value of 600 nf ? 2 f and esr < 50 m ). the regulator is powered by vddreg and works in the range 4.5 v to 5.5 v, down to 4.0 v with lower current drive capabilities, and uses the bandgap voltage as absolute reference. the 3.3 v regulator output is connected to an i/o pad (vrc33) for external capacitance decoupling, then all blocks (except the flash) that need a 3.3 v supply are connected to the vrc33 pad. the 3.3 v flash power supply is taken at a pad next to the regulator i/o, which is double bonded together with the vrc33 pad. power management controller (pmc) RM0029 1664/1740 doc id 15177 rev 8 figure 1005.vreg 3.3 v power connection the regulator output voltage is adjustable via software by writing to field pcm_trimr[vdd33trim], which selects one of the 16 voltages available. the reset value of the 4-bit register is ?0000?, corresponding to nominal voltage of 3.39 v. this is the typical default value, the real default value may vary from sample to sample according to process, temperature and voltage supply conditions, as detailed in the ?pmc electrical characteristics? table in the device datasheet. the 3.3 v supply is internally connected to a 5 v adc channel such that the actual voltage may be read. moreover, if an external 3.3 v voltage source will be used, the user can disable this regulator by clearing the shutdown bit nvusro[v33dis]. the user might have both internal 3.3 v regulator and external 3.3 v voltage sources at the same time at the cost of additional power consumption on the external voltage source. it is recommended to disable the internal 3.3 v regulator in this case. additional features of this regulator include a current limiter that protects a pmos pass device from overload condition and soft start-up to avoid overshoot during power-on. if an external 3.3 v supply will be used, this regulator can be disabled by setting vdd33shutdown bit to logical 1. the bit resides in the nvusro register in the flash memory shadow row. see figure 1006 and table 934 for details. osc vreg 3.3 vref_3p3 vreg 1.2 internal 3.3v supply vrc33 flash vddreg vddreg vdd33 vrc RM0029 power management controller (pmc) doc id 15177 rev 8 1665/1740 35.4.4 3.3 v lvi the pmc contains two 3.3 v low voltage monitors. one is connected to the internal 3.3 v supply and the other is connected to vddeh1. the output of the lvi goes to logical 1 when the monitored voltage rises above the rising trip point. in case the monitored voltage falls below the falling trip point, the lvi output goes to logical 0. the assertion and negation voltages are adjustable via software by writing to field pcm_trimr[lvd33trim], which selects one of the 16 voltages available. the reset value of the 4-bit register is ?0000?, corresponding to rising trip point voltage of 3.09 v. this is the typical default value, the real default value may vary from sample to sample according to process, temperature and voltage supply conditions, as detailed in the ?pmc electrical characteristics? table in the device datasheet. the lvis can be programmed to trigger power-on reset (enabled by default). if programmed to generate reset, the monitors are able to hold reset from 3.3 v por until greater or equal to lvi threshold. figure 1006.non-volatile user options register (nvusro) - array0 address: 0x00ff_fe10 0 1 2 3 4 5 6 7 8 9 101112131415 resetx x xxxxxxxxxxxxxx 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r v33dis w resetx x xxxxxxxxxxxxx1 = not implemented table 934. non-volatile user options register (nvusro) field description field description 0:30 reserved 31 v33dis vreg33 shutdown bit 1: 3.3 v regulator is enabled. 0: 3.3 v regulator is disabled. the shutdown bit is masked until the 1.2 v achieves it s por trip point, keeping the 3p3 regulator on. after a por the reset value reflects the state of the shadow flash bit at 0x00ff_fe10. power management controller (pmc) RM0029 1666/1740 doc id 15177 rev 8 35.4.5 1.2 v voltage regulator controller a voltage regulator controller is used to source current to the base of an external npn transistor which operates as an emitter follower. the 1.2 v supply is produced at the emitter of this transistor with a maximum dc current of 400 ma (or maximum transient current of 1.2 a). the regulator output voltage is adjustable using software, to permit the device to center the supply for maximum transient margin. this adjustment is achieved by writing to field pcm_trimr[vddctrim], which selects one of the 16 voltages available. the reset value of the 4-bit register is ?0000?, corresponding to a typical default voltage of 1.28 v. the 1.2 v supply can be internally connected internally to a 5 v adc channel such that the actual voltage may be read. 35.4.6 1.2 v lvi a programmable low voltage monitor is connected to the 1.2 v supply. the output of the lvi goes to logical 1 when the monitored voltage rises above the rising trip point. in case the monitored voltage falls below the falling trip point, the lvi output goes to logical 0. the assertion and negation voltages are adjustable via software by writing to field pcm_trimr[lvdctrim], which selects one of the 16 voltages available. the reset value of the 4-bit register is ?0000?, corresponding to a rising trip point voltage of 1.16 v. this is the typical default value, the real default value may vary from sample to sample according to process, temperature and voltage supply conditions, as detailed in the ?pmc electrical characteristics? table in the device datasheet. the lvi 1.2 v can be programmed to trigger power-on reset (enabled by default). if programmed to generate reset, the monitor is able to hold reset from 1.2 v por until greater or equal to lvi threshold. 35.4.7 resets and interrupts power-on reset power-on reset (por) circuits are present at the following power supplies: 3.3 v / 5 v supply of the closest i/o segment (vddeh1); 5 v supply of the pmc block and bandgap (vddreg); 3.3 v regulated supply vdd33; 1.2 v regulated supply. power-on reset will assert when the voltage levels of the por power supplies begin to rise. each por will negate when its power supply rises into the specified range. the behavior for each por during power supply ramping is shown in figure 1007 . the dependence between por and lvi is summarized in figure 1008 . as shown, the lvi will reach a consistent state before the por actually releases the reset, avoiding false startup condition. this is valid for each voltage supply monitored by por/lvi. the pors for each power supply are not intended to indicate that the power supply has dropped below the specified voltage range for the device. the 1.2 v and the 3.3 v supplies are monitored, respectively, by the lvi 1.2 v and lvi 3.3 v circuits for this purpose. RM0029 power management controller (pmc) doc id 15177 rev 8 1667/1740 figure 1007.por rising and falling edges figure 1008.por - lvi relative rising and falling edges the lvi monitors can be configured to generate power-on reset by programming the lvrer, lvreh, lvre50, lvre33 and lvrec bits in the mcr register. por indeterminate por_b asserts por_b negates (ramp up) por_b asserts (ramp down) por indeterminate specified power supply range power supply v supply por asserts lvi asserts por negates lvi negates lvi asserts por asserts lvi indeterminate por indeterminate specified v supply range por & lvi overlap por & lvi overlap power management controller (pmc) RM0029 1668/1740 doc id 15177 rev 8 the combination of por and lvi sources within the pmc generates a single power-on reset output signal which can be distributed throughout the device. the following sections discuss the various modules and functions that use the por. clock control the clock control divides the system clock to generate clkout. because clkout toggles during system reset, one of the sources of reset for the dividers is por. siu the siu uses por in its reset controller state machine, synchronizers and reset filter, siu_rsr, siu_rcsr, siu_ccr and an internal register. reset controller state machine because the reset controller state machine is active during system reset, it is reset with por. synchronizers and reset filter signals affecting the reset controller?s ability to negate system reset need to be synchronized with synchronizers reset by por if they are asynchronous or come from clock domains other than the system clock. a synchronized and filtered assertion of the reset pin will hold the device in system reset. the synchronizers and filter are reset with por so that reset appears to be asserted while por is asserted. synchronizers for the watchdog, nexus, checkstop, and jtag sources of reset use por to reset the synchronizers, but system reset can suffice because those sources are not analyzed until after system reset negates. the loss of clock source synchronizers also are reset with por, but since loss of clock results in loss of lock, which needs and uses por as reset, system reset can suffice for loss of clock. the synchronization of wkpcfg and bootcfg uses por. in the case of wkpcfg, the pin is applied during por. in the case of bootcfg, the pin value is latched before the negation of system reset. changes in bootcfg have no effect after the negation of system reset. siu_rsr because por sets the pors bit of the siu_rsr to indicate that por was the source of reset, the other source indicators, ers, llrs, lcrs, wdrs, crs, and ssrs, are reset with por. the wkpcfg and bootcfg bits are reset with por so that the wkpcfg and bootcfg values can be latched at the negation of system reset. the rgf bit also is reset with por. the serf bit is reset with por, but also is cleared during system reset. system reset can suffice to reset the serf bit. siu_srcr the cre bit of the siu_srcr is reset with por. the ssr and ser bits are reset with por, but system reset can suffice for both of them. siu_ccr the match and disnex bits of the siu_ccr use por. flash memory the flash state machine is reset during por. vflash must be at a high enough voltage to read the shadow row before system reset negates. reset must be asserted when RM0029 power management controller (pmc) doc id 15177 rev 8 1669/1740 vflash is below the minimum specification. since the synchronized and filtered reset appears as asserted during por and then must remain asserted until vflash is within specification, it is used to reset the flash state machine. when the system reset is caused by other sources besides por or reset assertion, the flash state machine uses the system reset indication as an input, but not as a reset, to indicate that the state machine is to read the shadow row. note: the field lvd33trim of the register trimr must be programmed with ?0011? at least, in order to enhance the lvi33 threshold by 60 mv and monitor the vdd33 voltage in all the corners (voltage, process and temperature). this is to ensure that the voltage never becomes lower than 3.0 v in order to guarantee the operations on the flash. fmpll the fmpll analog hard block is held in power down state during por to guarantee that it starts operating only when voltages are high enough to allow its operation. the fmpll programmer?s model registers are reset with por so that the fmpll does not lose lock every time a system reset is asserted. the clock quality monitor (cqm) inside the fmpll uses por to initialize its registers and counters because it operates during system reset to detect when the crystal oscillator has stabilized. npc the npc uses por because it can be configured during system reset. jtagc the assertion of por is equivalent to the negation of the jcomp pin. e200z4 the e200z4 is reset with por or system reset except in some portions of its nexus interface, which only are reset with por. padring the padring 3-states all of the output pins, including clkout, mcko, and rstout when the 1.2 v supply is too low to propagate internal signals, including the por indication. when the por indication can be propagated, the output pins, including clkout, mcko, and rstout , also are 3-stated during por. during por, the actual value of the pin cannot be read. instead, the padring drives an input value. the actual value during por is important for only two pins: wkpcfg and pllref. the values driven during por for all other pins are irrelevant. for those pins, the input value is a 0. wkpcfg during por, the direction of the weak pull is determined by the reset state of the wps bit in the siu_pcrs. for those pins whose wps reset state is determined by the wkpcfg pin, the value of wkpcfg is treated as a 1 during por to be consistent with the default pull up for the wkpcfg pin. therefore, those pins whose wps reset state is determined by wkpcfg will have a pull up during por. power management controller (pmc) RM0029 1670/1740 doc id 15177 rev 8 pllref the pllref pins selects whether crystal or external clock is used as clock source in bypass mode, which is the default mode out of por. furthermore, pllref selects whether the clock reference is monitored or not by the clock quality monitor. if the reference is the crystal oscillator, it is monitored. if the reference is an external clock, it is not monitored. the pllref value during por is kept at logic level 0 to minimize the probability of a clock glitch in the more stringent case when pllref = 0, therefore the cqm will not monitor the reference clock and the internal por will be released as soon as the voltages achieve the lvi thresholds. the clock glitch may occur when the por is released near the external clock falling edge. even if such a glitch happens, it will be still inside the por pulse because all synchronous logic that use por are supposed to synchronize the por negation with a double-register. interrupts the pmc generates one interrupt request signal for each lvi source: reset-pin-supply (vddeh6) lvi, vddeh1 lvi, 5 v lvi, 3.3 v lvi and 1.2 v lvi. the module also generates combined interrupt request signal which is asserted whenever any of the three individual interrupt request signals becomes asserted. 35.4.8 soft-start (for 1.2 v and 3.3 v regulators) a soft-start circuit has been implemented for 1.2 v and 3.3 v regulators. this circuit controls the reference voltage rise time to avoid abrupt ramp-up of these regulators. 35.4.9 adc test mux during pmc functional mode it is possible to perform direct measurements through the adc. pmc internal voltages are routed to the adc. each signal can be measured with adc running at full speed. i table 935. eqadc test mux channel for internal pmc signals eqadc channel adc description 45 adc0/adc1 buffered band gap 128 adc0/adc1 temp sensor 129 adc0/adc1 vssa 144 adc0 buffered band gap 145 adc0 reference voltage for 1.2 v lvd 146 adc0 reference for 1.2 v regulator 147 adc0 reference voltage for 3.3 v lvd 162 adc0 vdda 163 adc0 50% vddeh6 164 adc0 vssa 165 adc0 50% vddeh7 166 adc0 50% vddeh4 RM0029 power management controller (pmc) doc id 15177 rev 8 1671/1740 for any measurements it is strongly recommended to disable all lvi outputs to the logic via software as the multiplexer toggling could induce false detection. 35.5 electrical characteristics for electrical characteristics, please refer to the device datasheet. 167 adc0 vssa 180 adc0 reference voltage for 5.0 v lvd 181 adc0 reference voltage for 3.3 v lvd 182 adc0 reference for 3.3 v regulator 194 adc1 test output from stby pmc 195 adc1 50% vddeh1b 196 adc1 vrc33 197 adc1 vrc33 198 adc1 50% vddeh4 199 adc1 50% vddeh1a table 935. eqadc test mux channel for internal pmc signals (continued) eqadc channel adc description jtag controller (jtagc) RM0029 1672/1740 doc id 15177 rev 8 36 jtag controller (jtagc) 36.1 information specific to this device this section presents device-specific parameterization, customization, and feature availability information not specifically referenced in the remainder of this chapter. 36.1.1 device-specific parameters ta ble 93 6 shows the parameters and associated values for this device. 36.1.2 device identification register parameters ta ble 93 7 shows the fields and values for the device identification register on this device. 36.1.3 auxiliary tap controller instructions ta ble 93 8 lists the auxiliary tap controller instructions (discussed in section 36.5.4, jtagc block instructions ) available on this device. table 936. device-specific parameters parameter value number of jcomp bits used 1 length of the boundary scan chain path for the device 248 number of auxiliary tap controllers that share the tap with the jtagc via an access_aux_tap_x instruction (not including the jtagc) 5 size of the censor_ctrl register (bits) 64 table 937. device identification register parameters field value part revision number (prn) changes in each revision design center code (dc) 0x2b part identification number (pin) 0x202 manufacturer identity code (mic) 0x020 table 938. device-specific auxiliary tap controller instructions instruction code[4:0] instruction summary access_aux_tap_npc 10000 enables access to the npc tap controller access_aux_tap_once 10001 enables access to the e200z4 once tap controller access_aux_tap_etpu 10010 enables access to the etpu nexus tap controller RM0029 jtag controller (jtagc) doc id 15177 rev 8 1673/1740 36.2 introduction figure 1009 is a block diagram of the jtag controller (jtagc) block. figure 1009.jtag stl (ieee 1149.1) block diagram 36.2.1 overview the jtagc block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. testing is performed via a boundary scan technique, as defined in the ieee 1149.1-2001 standard. all data input to and output from the jtagc block is communicated in serial format. 36.2.2 features the jtagc block is compliant with the ieee 1149.1-2001 standard, and supports the following features: ieee 1149.1-2001 test access port (tap) interface ? 4 pins (tdi, tms, tck, and tdo) jcomp input that provides reset control and the ability to share the tap 5-bit instruction register that supports several ieee 1149.1-2001 defined instructions as well as several public and private device-specific instructions (refer to table 942 for a list of supported instructions.) sharing of the tap with other tap controllers via access_aux_tap_x instructions tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry 36.2.3 modes of operation the jtagc block uses jcomp and a power-on reset indication as its primary reset signals. several ieee 1149.1-2001 defined test modes are supported, as well as a bypass mode. reset the jtagc block is placed in reset when either power-on reset is asserted, , or the tms input is held high for enough consecutive rising edges of tck to sequence the tap controller state machine into the test-logic-reset state. holding tms high for five consecutive rising edges of tck guarantees entry into the test-logic-reset state regardless of the current tap controller state. asserting power-on reset or setting jcomp to a value other than the value required to enable the jtagc block results in asynchronous entry into the reset state. while in reset, the following actions occur: the tap controller is forced into the test-logic-reset state, thereby disabling the test logic and allowing normal operation of the on-chip system logic to continue unhindered. the instruction register is loaded with the idcode instruction. ieee 1149.1-2001 defined test modes the jtagc block supports several ieee 1149.1-2001 defined test modes. a test mode is selected by loading the appropriate instruction into the instruction register while the jtagc is enabled. supported test instructions include extest, highz, clamp, sample and sample/preload. each instruction defines the set of data register(s) that may operate jtag controller (jtagc) RM0029 1674/1740 doc id 15177 rev 8 and interact with the on-chip system logic while the instruction is current. only one test data register path is enabled to shift data between tdi and tdo for each instruction. the boundary scan register is enabled for serial access between tdi and tdo when the extest, sample or sample/preload instructions are active. the single-bit bypass register shift stage is enabled for serial access between tdi and tdo when the highz, clamp or reserved instructions are active. the functionality of each test mode is explained in more detail in section 36.5.4, jtagc block instructions . bypass mode when no test operation is required, the bypass instruction can be loaded to place the jtagc block into bypass mode. while in bypass mode, the single-bit bypass shift register is used to provide a minimum-length serial path to shift data between tdi and tdo. 36.3 external signal description 36.3.1 overview the jtagc consists of five signals that connect to off chip development tools and allow access to test support functions. the jtagc signals are outlined in table 939 . 36.3.2 detailed signal descriptions this section describes each of the signals listed in table 939 in more detail. tck?test clock input test clock input (tck) is an input pin used to synchronize the test logic and control register access through the tap. tdi?test data input test data input (tdi) is an input pin that receives serial test instructions and data. tdi is sampled on the rising edge of tck. table 939. jtag signal properties name i/o function reset state pull (1) 1. the pull is not implemented in this block. pu llup/pulldown devices are implemented in the pads. tck input test clock ? down tdi input test data in ? up tdo output test data out high z (2) 2. tdo output buffer enable is negated when the jtagc is not in the shift-ir or shift-dr states. a weak pull may be implemented at the tdo pad for use when jtagc is inactive. ? tms input test mode select ? up jcomp input jtag compliancy ? down RM0029 jtag controller (jtagc) doc id 15177 rev 8 1675/1740 tdo?test data output test data output (tdo) is an output pin that transmits serial output for test instructions and data. tdo is three-stateable and is actively driven only in the shift-ir and shift-dr states of the tap controller state machine, which is described in section 36.5.3, tap controller state machine . the tdo output of this block is clocked on the falling edge of tck and sampled by the development tool on the rising edge of tck. tms?test mode select test mode select (tms) is an input pin used to sequence the ieee 1149.1-2001 test control state machine. tms is sampled on the rising edge of tck. jcomp?jtag compliancy the jcomp signal provides ieee 1149.1-2001 compatibility and provides the ability to share the tap. the jtagc tap controller is enabled when jcomp is set to the jtagc enable encoding, otherwise the jtagc tap controller remains in reset. 36.4 register definition this section provides a detailed description of the jtagc block registers accessible through the tap interface, including data registers and the instruction register. individual bit-level descriptions and reset states of each register are included. these registers are not memory- mapped and can only be accessed through the tap. 36.4.1 register descriptions the jtagc block registers are described in this section. instruction register the jtagc block uses a 5-bit instruction register as shown in table 1010 . the instruction register allows instructions to be loaded into the block to select the test to be performed or the test data register to be accessed or both. instructions are shifted in through tdi while the tap controller is in the shift-ir state, and latched on the falling edge of tck in the update-ir state. the latched instruction value can only be changed in the update-ir and test-logic-reset tap controller states. synchronous entry into the test-logic-reset state results in the idcode instruction being loaded on the falling edge of tck. asynchronous entry into the test-logic-reset state results in asynchronous loading of the idcode instruction. during the capture-ir tap controller state, the instruction shift register is loaded with the value 0b10101, making this value the register?s read value when the tap controller is sequenced into the shift-ir state. figure 1010.5-bit instruction register 43210 r 1 0 1 0 1 w instruction code reset:00001 jtag controller (jtagc) RM0029 1676/1740 doc id 15177 rev 8 bypass register the bypass register is a single-bit shift register path selected for serial data transfer between tdi and tdo when the bypass, clamp, highz or reserve instructions are active. after entry into the capture-dr state, the single-bit shift register is set to a logic 0. therefore, the first bit shifted out after selecting the bypass register is always a logic 0. device identification register the device identification register, shown in figure 1011 , allows the revision number, part number, manufacturer, and design center responsible for the design of the part to be determined through the tap. the device identification register is selected for serial data transfer between tdi and tdo when the idcode instruction is active. entry into the capture-dr state while the device identification register is selected loads the idcode into the shift register to be shifted out on tdo in the shift-dr state. no action occurs in the update-dr state. the part revision number (prn) and part identification number (pin) fields are system plugs, and the manufacturer identity code (mic) is a constant value assigned to the manufacturer by the jedec. the shift register lsb is forced to logic 1 on the rising edge of tck following entry into the capture-dr state. therefore, the first bit to be shifted out after selecting the idcode register is always a logic 1. the remaining 31 bits are forced to the value of the device identification register on the rising edge of tck following entry into the capture-dr state. figure 1011.device identification register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r part revision number design center part identification number w reset prn dc pin 1514131211109876543210 r part identification number manufacturer identity code 1 w reset pin (cont?d) ? (1) ?????????? 1 = reserved 1. see table 937 for value. table 940. device identification register field descriptions field description 31?28 prn part revision number bits [31:28] contain the revision number of the part. 27?22 dc design center bits [27:22] indicate the design center. RM0029 jtag controller (jtagc) doc id 15177 rev 8 1677/1740 censor_ctrl register the censor_ctrl register is a 64-bit shift register path from tdi to tdo selected when the enable_censor_ctrl instruction is active. the default reset value of the censor_ctrl register is 64?b0. the censor_ctrl register transfers its value to a parallel hold register on the rising edge of tck when the tap controller state machine is in the update-dr state. once the enable_censor_ctrl instruction is executed, the register value will remain valid until a jtag reset occurs. figure 1012.censor_ctrl register boundary scan register the boundary scan register is connected between tdi and tdo when the extest, sample or sample/preload instructions are active. it is used to capture input pin data, force fixed values on output pins, and select a logic value and direction for bidirectional pins. each bit of the boundary scan register represents a separate boundary scan register cell, as described in the ieee 1149.1-2001 standard and discussed in section 36.5.5, boundary scan . the size of the boundary scan register and bit ordering is device-dependent. 21?12 pin part identification number bits [21:12] contain the part number of the device. 11?1 mic manufacturer?s identification code bits [11:1] contain the jedec (joint electron device engineering council) manufacturer?s identification code. bit [0] idcode register id bit [0] identifies this register as the device identification register and not the bypass register table 940. device identification register field descriptions (continued) field description * (1) 1. the size of censor_ctrl is 64 bits. ... 2 1 0 r censor_ctrl w reset: * (2) 2. the reset value of censor_ctrl is 64?b0. **** table 941. censor_ctrl register field descriptions field description 63?0 censor_ctrl [63:0] censorship control the censor_ctrl bits are used to control chiptop censorship functions. jtag controller (jtagc) RM0029 1678/1740 doc id 15177 rev 8 36.5 functional description 36.5.1 jtagc reset configuration while in reset, the tap controller is forced into the test-logic-reset state, thus disabling the test logic and allowing normal operation of the on-chip system logic. in addition, the instruction register is loaded with the idcode instruction. 36.5.2 ieee 1149.1-2001 (jtag) test access port the jtagc block uses the ieee 1149.1-2001 tap for accessing registers. this port can be shared with other tap controllers on the mcu. ownership of the port is determined by the value of the jcomp signal and the currently loaded instruction. for more detail on tap sharing via jtagc instructions refer to section , access_aux_tap_x instructions . data is shifted between tdi and tdo through the selected register starting with the least significant bit, as illustrated in figure 1013 . this applies for the instruction register, test data registers, and the bypass register. figure 1013.shifting data through a register 36.5.3 tap controller state machine the tap controller is a synchronous state machine that interprets the sequence of logical values on the tms pin. figure 1014 shows the machine?s states. the value shown next to each state is the value of the tms signal sampled on the rising edge of the tck signal. as figure 1014 shows, holding tms at logic 1 while clocking tck through a sufficient number of rising edges also causes the state machine to enter the test-logic-reset state. selected register msb lsb tdi tdo RM0029 jtag controller (jtagc) doc id 15177 rev 8 1679/1740 figure 1014.ieee 1149.1-2001 tap controller finite state machine test logic reset run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 1 1 1 00 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 note: the value shown adjacent to each state transition in this figure represents the value of tms at the time of a rising edge of tck. jtag controller (jtagc) RM0029 1680/1740 doc id 15177 rev 8 enabling the tap controller the jtagc tap controller is enabled by setting jcomp to the jtagc enable value. the jtagc tap controller is enabled by setting jcomp to a logic 1 value. selecting an ieee 1149.1-2001 register access to the jtagc data registers is achieved by loading the instruction register with any of the jtagc block instructions while the jtagc is enabled. instructions are shifted in via the select-ir-scan path and loaded in the update-ir state. at this point, all data register access is performed via the select-dr-scan path. the select-dr-scan path is used to read or write the register data by shifting in the data (lsb first) during the shift-dr state. when reading a register, the register value is loaded into the ieee 1149.1-2001 shifter during the capture-dr state. when writing a register, the value is loaded from the ieee 1149.1-2001 shifter to the register during the update-dr state. when reading a register, there is no requirement to shift out the entire register contents. shifting may be terminated once the required number of bits have been acquired. 36.5.4 jtagc block instructions the jtagc block implements the ieee 1149.1-2001 defined instructions listed in table 942 . this section gives an overview of each instruction; refer to the ieee 1149.1-2001 standard for more details. all undefined opcodes are reserved. table 942. jtag instructions instruction code[4:0] instruction summary idcode 00001 selects device identification register for shift sample/preload 00010 selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation sample 00011 selects boundary scan register for shifting and sampling without disturbing functional operation extest 00100 selects boundary scan register while applying preloaded values to output pins and asserting functional reset highz 01001 selects bypass register while three-stating all output pins and asserting functional reset clamp 01100 selects bypass register while applying preloaded values to output pins and asserting functional reset access_aux_tap_x 10000? 11110 grants one of the auxiliary tap controllers ownership of the tap as shown in the cells below. the number of auxiliary tap controllers sharing the port is 4. access_aux_tap_npc 10000 enables access to the npc tap controller access_aux_tap_once 10001 enables access to the primary once tap controller (primary cpu) access_aux_tap_etpu 10010 enables access to the etpu nexus tap controller bypass 11111 selects bypass register for data operations factory debug reserved 00101, 00110, 01010, 00111 intended for factory debug only RM0029 jtag controller (jtagc) doc id 15177 rev 8 1681/1740 idcode instruction idcode selects the 32-bit device identification register as the shift path between tdi and tdo. this instruction allows interrogation of the mcu to determine its version number and other part identification data. idcode is the instruction placed into the instruction register when the jtagc block is reset. sample/preload instruction the sample/preload instruction has two functions: first, the sample portion of the instruction obtains a sample of the system data and control signals present at the mcu input pins and just before the boundary scan register cells at the output pins. this sampling occurs on the rising edge of tck in the capture-dr state when the sample/preload instruction is active. the sampled data is viewed by shifting it through the boundary scan register to the tdo output during the shift-dr state. both the data capture and the shift operation are transparent to system operation. secondly, the preload portion of the instruction initializes the boundary scan register cells before selecting the extest or clamp instructions to perform boundary scan tests. this is achieved by shifting in initialization data to the boundary scan register during the shift-dr state. the initialization data is transferred to the parallel outputs of the boundary scan register cells on the falling edge of tck in the update-dr state. the data is applied to the external output pins by the extest or clamp instruction. system operation is not affected. sample instruction the sample instruction obtains a sample of the system data and control signals present at the mcu input pins and just before the boundary scan register cells at the output pins. this sampling occurs on the rising edge of tck in the capture-dr state when the sample instruction is active. the sampled data is viewed by shifting it through the boundary scan register to the tdo output during the shift-dr state. there is no defined action in the update-dr state. both the data capture and the shift operation are transparent to system operation. extest?external test instruction extest selects the boundary scan register as the shift path between tdi and tdo. it allows testing of off-chip circuitry and board-level interconnections by driving preloaded data contained in the boundary scan register onto the system output pins. typically, the preloaded data is loaded into the boundary scan register using the sample/preload instruction before the selection of extest. extest asserts the internal system reset for the mcu to force a predictable internal state while performing external boundary scan operations. reserved (1) all other opcodes decoded to select bypass register 1. the manufacturer reserves the right to change the decoding of reserved instruction codes in the future. table 942. jtag instructions (continued) instruction code[4:0] instruction summary jtag controller (jtagc) RM0029 1682/1740 doc id 15177 rev 8 highz instruction highz selects the bypass register as the shift path between tdi and tdo. while highz is active all output drivers are placed in an inactive drive state (e.g., high impedance). highz also asserts the internal system reset for the mcu to force a predictable internal state. clamp instruction clamp allows the state of signals driven from mcu pins to be determined from the boundary scan register while the bypass register is selected as the serial path between tdi and tdo. clamp enhances test efficiency by reducing the overall shift path to a single bit (the bypass register) while conducting an extest type of instruction through the boundary scan register. clamp also asserts the internal system reset for the mcu to force a predictable internal state. access_aux_tap_x instructions the jtagc is configurable to allow up to fifteen other tap controllers on the device to share the port with it. this is done by providing access_aux_tap_x instructions for each of these tap controllers. when this instruction is loaded, control of the jtag pins are transferred to the selected tap controller. any data input via tdi and tms is passed to the selected tap controller, and any tdo output from the selected tap controller is sent back to the jtagc to be output on the pins. the jtagc regains control of the jtag port during the update-dr state if the pause-dr state was entered. auxiliary tap controllers are held in run-test/idle while they are inactive. instructions not used to access an auxiliary tap controller on a device are treated like the bypass instruction. bypass instruction bypass selects the bypass register, creating a single-bit shift register path between tdi and tdo. bypass enhances test efficiency by reducing the overall shift path when no test operation of the mcu is required. this allows more rapid movement of test data to and from other components on a board that are required to perform test functions. while the bypass instruction is active the system logic operates normally. 36.5.5 boundary scan the boundary scan technique allows signals at component boundaries to be controlled and observed through the shift-register stage associated with each pad. each stage is part of a larger boundary scan register cell, and cells for each pad are interconnected serially to form a shift-register chain around the border of the design. the boundary scan register consists of this shift-register chain, and is connected between tdi and tdo when the extest, sample, or sample/preload instructions are loaded. the shift-register chain contains a serial input and serial output, as well as clock and control signals. 36.6 initialization/application information the test logic is a static logic design, and tck can be stopped in either a high or low state without loss of data. however, the system clock is not synchronized to tck internally. any mixed operation using both the test logic and the system functional logic requires external synchronization. to initialize the jtagc block and enable access to registers, the following sequence is required: RM0029 jtag controller (jtagc) doc id 15177 rev 8 1683/1740 1. set the jcomp signal to the jtagc enable value, thereby enabling the jtagc tap controller. 2. load the appropriate instruction for the test or action to be performed. nexus port controller (npc) RM0029 1684/1740 doc id 15177 rev 8 37 nexus port controller (npc) 37.1 information specific to this device this section presents device-specific parameterization, customization, and feature availability information not specifically referenced in the remainder of this chapter. 37.1.1 device-specific features nexus class 3+ 14-bit full duplex pin interface for high visibility throughput ? reduced port mode (rpm) comprises 4 pins ? auxiliary output port 1 mcko (message clock out) pin 4 mdo (message data out) pins 2 mseo (message start/end out) pins 1 rdy (ready) pin 1 evto (event out) pin ? auxiliary input port 1 evti (event in) pin ? 5-pin jtag port (jcomp, tdi, tdo, tms, and tck) host processor (e200z4) development support ? ieee-isto 5001-2010 standard class 2 compliant ? program trace via branch trace messaging (btm). branch trace messaging displays program flow discontinuities (direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. thus, static code can be traced ? watchpoint messaging (wpm) via the auxiliary port ? watchpoint trigger enable of program trace messaging ? subset of power architecture embedded category software debug facilities with once block (nexus class 1 features) etpu development support ? ieee-isto 5001? - 2003 standard class 1 compliant for the etpu engine ? nexus based breakpoint/watchpoint configuration and single step support ? run-time access to the on-chip memory map via the nexus read/write access protocol. this feature supports accesses for run-time internal visibility, calibration variable acquisition, calibration constant tuning, and external rapid prototyping for powertrain automotive development systems ? all features are independently configurable and controllable via the ieee 1149.1 i/o port ? the nexus block reset is controlled with jcomp, power-on reset, and the tap state machine. all theses sources are independent of system reset ? power-on-reset status indication during reset via mdo[0] in disabled and reset modes RM0029 nexus port controller (npc) doc id 15177 rev 8 1685/1740 as some of the pads used for the nexus interface are multi-voltage pads, the maximum supported interface frequency is limited to 40 mhz in some modes. this corresponds to a mcko clock divider of 1/2 for system clocks up to 80 mhz, and 1/4 for system clocks > 80 mhz. nexus double data rate (ddr) mode is not available in the spc564a74xx, spc564a80xx family of devices. a control bit in the nexus port controller, np_pcr[nexcfg], is used to control whether the added signals for full width trace port are routed to the mdo[4:11] signals, or the cal_mdo[4:11] signals. although the cal_mdo[4:11] signals are only available in the 496 csp package, this control bit still needs to be programmed when the device is assembled in any other package. table 943 shows the maximum trace port frequencies supported in different configurations, as well as the operation of the npc_pcr[fpm] and [nexcfg] control bits. 37.1.2 parameter values table 943. nexus trace port routing and speed package max. trace port mhz port width npc_pcr[fpm] port routing bit npc_pcr[nexcfg] mdo[0:3] usage mdo[4:11] usage cal_mdo[4:11] usage production (176qfp, 208bga, 324bga) 80 4 mdo (narrow, fpm=0) don?t care trace port use i/o use inactive 40 12 mdo (wide, fpm=1) nexcfg = 1 trace port use debug/cal package (496 csp) 80 4 mdo (narrow, fpm=0) don't care i/o use 40 12 mdo (wide, fpm=1) nexcfg = 1 use mdo trace port use trace port use 80 nexcfg = 0 (default setting) use cal_mdo i/o use trace port use table 944. parameter values parameter description value npc parameters rpm_mdo (r) number of mdo pins available in reduced-port mode 4 num_aux (x) number of nexus devices on the device sharing the nexus auxiliary port (not including the npc) 1 num_bkpt (b) number of breakpoint requests coming into the block from nexus and non-nexus sources on the device 1 num_evto (e) number of sources that output an evto 2 nexus port controller (npc) RM0029 1686/1740 doc id 15177 rev 8 37.2 introduction figure 1015 is a block diagram of the nexus port controller (npc) block. num_jcomp (j) number of jcomp bits used. depends on the number of non- nexus blocks sharing the tap 1 dc design code for the design center responsible for the design of the device (tecd) 0x2b part identification number (npc_did_pn_plug[9:0]) part number of the device 0x202 part revision number (npc_did_rev_plug[3:0]) revision number of the device 0x1 npc jcomp plug (npc_jcomp_plug) jcomp value required to grant nexus control of the jtag port 0b1 nsedi parameters part identification number (nex_did_pn_plug[9:0]) part number of the etpu 0x125 part revision number (nex_did_rev_plug[3:0]) revision number of the etpu 0x0 table 944. parameter values (continued) parameter description value RM0029 nexus port controller (npc) doc id 15177 rev 8 1687/1740 figure 1015.nexus port controller block diagram 37.2.1 overview on a system-on-chip device, there are often multiple blocks that require development support. each of these blocks implements a development interface based on the ieee-isto 5001-2001 standard. the blocks share input and output ports that interface with the development tool. the npc controls the usage of the input and output port in a manner that allows all the individual development interface blocks to share the port, and appear to the development tool to be a single block. port arbiter message transmitter mdo/mseo generation jtag tdi tdo tck tms debug mode control register tdo generation reset control jcomp evto control control interface pstat mdo mux mdo mseo_b miscellaneous logic nexus port controller (npc) RM0029 1688/1740 doc id 15177 rev 8 37.2.2 features the npc block performs the following functions: controls arbitration for ownership of the nexus auxiliary output port nexus device identification register and messaging generates mcko enable and frequency division control signals controls sharing of evto generates an mcko clock gating control signal to enable gating of mcko when the auxiliary output port is idle control of the device-wide debug mode generates asynchronous reset signal for nexus blocks based on jcomp input and power-on reset status system clock locked status indication via mdo[0] following power-on reset 37.2.3 modes of operation the npc block uses the jcomp input and an internal power-on reset indication as its primary reset signals. upon exit of reset, the mode of operation is determined by the port configuration register (pcr) settings. reset the npc block is asynchronously placed in reset when either power-on reset is asserted, jcomp is not set for nexus access or the tap controller state machine is in the test-logic- reset state. holding tms high for five consecutive rising edges of tck guarantees entry into the test-logic-reset state regardless of the current tap controller state. following negation of power-on reset, the npc remains in reset until the system clock achieves lock. the npc is unaffected by other sources of reset. while in reset, the following actions occur: the tap controller is forced into the test-logic-reset state the auxiliary output port pins are negated the tdi, tms, and tck tap inputs are ignored (when in power-on reset or jcomp not set for npc operation only) registers default back to their reset values disabled-port mode in disabled-port mode, auxiliary output pin port enable signals are negated, thereby disabling message transmission. any debug feature that generates messages can not be used. the primary features available are class 1 features and read/write access to the registers. class 1 features include the ability to trigger a breakpoint event indication through evto . full-port mode full-port mode (fpm) is entered by asserting the mcko_en and fpm bits in the pcr. all trace features are enabled or can be enabled by writing the configuration registers via the tap. the number of mdo pins available is device-specific. RM0029 nexus port controller (npc) doc id 15177 rev 8 1689/1740 reduced-port mode reduced-port mode (rpm) is entered by asserting the mcko_en bit and negating the fpm bit in the pcr. all trace features are enabled or can be enabled by writing the configuration registers via the tap. the number of mdo pins available is device-specific. 37.3 external signal description 37.3.1 overview the npc pin interface provides for the transmission of messages from nexus blocks to the external development tools and for access to nexus client registers. the npc pin definition is outlined in table 945 . 37.3.2 detailed signal descriptions this section describes each of the signals listed in table 945 in more detail.note that the jtag test clock (tck) input from the pin is not a direct input to the npc. the npc requires two separate input clocks for tck clocked logic, one for posedge (rising edge tck) logic and one for negedge (falling edge tck) logic. both clocks are derived from the pin tck, and generated external to the npc. evto_b ? event out event out (evto ) is an output pin that is asserted upon breakpoint occurrence to provide breakpoint status indication. the evto output of the npc is generated based on the values of the individual evto signals from all nexus blocks that implement the signal. jcomp - jtag compliancy the jcomp signal provides the ability to share the tap. the npc tap controller is enabled when jcomp is set to the npc enable encoding, otherwise the npc tap controller remains in reset. table 945. npc signal properties name port function reset state pull (1) evto_b auxiliary event out pin 0b1 ? jcomp jtag jtag compliancy and tap sharing control ? down mdo auxiliary message data out pins 0 (2) ? mseo auxiliary message start/end out pins 0b11 ? tck jtag test clock input ? down tdi jtag test data input ? up tdo jtag test data output high z (3) ? tms jtag test mode select input ? up 1. the pull is not implemented in this block. pu llup/pulldown devices are implemented in the pads. 2. following a power-on reset, mdo[0] remains asserted until power-on reset is exited and the system clock achieves lock. 3. tdo output buffer enable is negated when the npc is not in the shift-ir or shift-dr states. a weak pull may be implemented on tdo at the soc level. nexus port controller (npc) RM0029 1690/1740 doc id 15177 rev 8 mdo - message data out message data out (mdo) are output pins used for uploading otm, btm, dtm, and other messages to the development tool. the development tool should sample mdo on the rising edge of mcko. the width of the mdo bus used is determined by reset configuration. mseo - message start/end out message start/end out (mseo ) is an output pin that indicates when a message on the mdo pins has started, when a variable length packet has ended, or when the message has ended. the development tool should sample mseo on the rising edge of mcko. tck - test clock input test clock input (tck) pin is used to synchronize the test logic and control register access through the jtag port. tdi - test data input test data input (tdi) pin receives serial test instruction and data. tdi is sampled on the rising edge of tck. tdo - nexus test data output test data output (tdo) pin transmits serial output for instructions and data. tdo is three- stateable and is actively driven in the shift-ir and shift-dr controller states. tdo is updated on the falling edge of tck and sampled by the development tool on the rising edge of tck. tms - test mode select test mode select input (tms) pin is used to sequence the ieee 1149.1-2001 tap controller state machine. tms is sampled on the rising edge of tck. 37.4 register definition this section provides a detailed description of the npc registers accessible to the end user. individual bit-level descriptions and reset states of the registers are included. ta ble 94 6 shows the npc registers by index values. the registers are not memory-mapped and can only be accessed via the tap. the npc block does not implement the client select control register because the value does not matter when accessing the registers. note that the bypass and instruction registers have no index values. these registers are not accessed in the same manner as nexus client registers. refer to the individual register descriptions for more detail. table 946. npc registers index register 0 device id register (did) 127 port configuration register (pcr) RM0029 nexus port controller (npc) doc id 15177 rev 8 1691/1740 37.4.1 register descriptions this section consists of npc register descriptions. bypass register the bypass register is a single-bit shift register path selected for serial data transfer between tdi and tdo when the bypass instruction or any unimplemented instructions are active. after entry into the capture-dr state, the single-bit shift register is set to a logic 0. therefore, the first bit shifted out after selecting the bypass register is always a logic 0. instruction register the npc block uses a 4-bit instruction register as shown in figure 1016 . the instruction register is accessed via the select_ir_scan path of the tap controller state machine, and allows instructions to be loaded into the block to enable the npc for register access (nexus_enable) or select the bypass register as the shift path from tdi to tdo (bypass or unimplemented instructions). instructions are shifted in through tdi while the tap controller is in the shift-ir state, and latched on the falling edge of tck in the update-ir state. the latched instruction value can only be changed in the update-ir and test-logic-reset tap controller states. synchronous entry into the test-logic-reset state results in synchronous loading of the bypass instruction. asynchronous entry into the test-logic-reset state results in asynchronous loading of the bypass instruction. during the capture-ir tap controller state, the instruction register is loaded with the value of the previously executed instruction, making this value the register?s read value when the tap controller is sequenced into the shift-ir state. figure 1016.4-bit instruction register nexus device id register (did) the device identification register, shown in figure 1017 , allows the part revision number, design center, part identification number, and manufacturer identity code of the part to be determined through the auxiliary output port. 3210 r previous instruction opcode w instruction opcode reset: bypass instruction opcode (0xf) nexus port controller (npc) RM0029 1692/1740 doc id 15177 rev 8 figure 1017.nexus device id register port configuration register (pcr) figure 1018.port configuration register (pcr) register index: 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r part revision number design center part identification number w reset: prn dc pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r part identification number manufacturer identity code 1 w reset: pin (cont?d.) 0 0 0 0 0 0 0 1 1 1 0 1 = reserved table 947. did field descriptions bit name description 31:28 prn part revision number these bits contain the revision number of the part. 27:22 dc design center these bits indicate the device design center. 21:12 pin part identification number these bits contain the part number of the device. 11:1 mic manufacturer identity code these bits contain the reduced joint electron device engineering council (jedec) id. 0 bit [0] idcode register id bit [0] identifies this register as the device identification register and not the bypass register. register index: 127 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r fpm mck o_gt mck o_en mcko_div evt_ en 0 nexc fg 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r lp_d bg 0 0 0 0 0 lp2_ syn lp1_ syn 0 0 0 0 0 0 0 psta t_en w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = reserved RM0029 nexus port controller (npc) doc id 15177 rev 8 1693/1740 the pcr, shown in figure 1018 , is used to select the npc mode of operation, enable mcko and select the mcko frequency, and enable or disable mcko gating. this register should be configured as soon as the npc is enabled. the pcr register may be rewritten by the debug tool subsequent to the enabling of the npc for low power debug support. in this case, the debug tool may set and clear the lp_dbg and lpn_syn bits, but must preserve the original state of the remaining bits in the register. note: the mode or clock division must not be modified after mcko has been enabled. changing the mode or clock division while mcko is enabled can produce unpredictable results. table 948. pcr field descriptions bit name description 31 fpm full port mode the value of the fpm bit determines if the auxiliary output port uses the full mdo port or a reduced mdo port to transmit messages. 1 = all mdo pins are used to transmit messages 0 = a subset of mdo pins are used to transmit messages 30 mcko_gt mcko clock gating control this bit is used to enable or disable mcko clock gating. if clock gating is enabled, the mcko clock is gated when the npc is in enabled mode but not actively transmitting messages on the auxiliary output port. when clock gating is disabled, mcko is allowed to run even if no auxiliary output port messages are being transmitted. 1 = mcko gating is enabled 0 = mcko gating is disabled 29 mcko_en mcko enable this bit enables the mcko clock to run. when enabled, the frequency of mcko is determined by the mcko_div field. 1 = mcko clock is enabled 0 = mcko clock is driven to zero 28:26 mcko_div mcko division factor the value of this signal determines the frequency of mcko relative to the system clock frequency when mcko_en is asserted. table 949 shows the meaning of mcko_div values. in this table, sys_clk represents the system clock frequency. 25 evt_en evto/evti enable this bit enables the evto/evti port functions. 1 = evto/evti port enabled 0 = evto/evti port disabled 24 ? reserved 23 nexcfg nexus configuration select generic nexus control bit. function is device-specific. 1 = nexcfg set 0 = nexcfg cleared 22:16 ? reserved nexus port controller (npc) RM0029 1694/1740 doc id 15177 rev 8 15 lp_dbg_en low power debug enable this bit enables debug functionality on exit from low power modes on supported devices. 1 = low power debug enabled 0 = low power debug disabled 14:10 ? reserved 9:8 lpn_syn low power mode n synchronization these bits are used to synchronize the entry into low power modes between the device and debug tool. supported devices set these bits before a pending entry into low power mode. after reading the bit as set, the debug tool then clears the bit to acknowledge to the device that it may enter the low power mode. 1 = low power mode entry pending 0 = low power mode entry acknowledged 7:1 ? reserved 0 pstat_en processor status mode enable (1) this bit enables processor status (pstat) mode. in pstat mode, all auxiliary output port mdo pins are used to transmit processor status information, and nexus messaging is unavailable. 1 = pstat mode enabled 0 = pstat mode disabled 1. pstat mode is intended for factory processor debug only. t he pstat_en bit should be written to disable pstat mode if nexus messaging is desired. no nexus messages are transmitted under any circumstances when pstat mode is enabled. table 948. pcr field descriptions (continued) bit name description table 949. mcko_div values mcko_div[2:0] mcko frequency 0 sys_clk (1) 1. the sys_clk setting for mcko frequency should only be used if this setting does not violate the maximum operating frequency of the auxiliary port pins. 1 sys_clk/2 2 sys_clk/3 3 sys_clk/4 4reserved 5reserved 6reserved 7 sys_clk/8 RM0029 nexus port controller (npc) doc id 15177 rev 8 1695/1740 37.5 functional description 37.5.1 npc reset configuration the npc is placed in disabled mode upon exit of reset. if message transmission via the auxiliary port is desired, a write to the pcr is then required to enable the npc and select the mode of operation. asserting mcko_en places the npc in enabled mode and enables mcko. the frequency of mcko is selected by writing the mcko_div field. asserting or negating the fpm bit selects full-port or reduced-port mode, respectively. ta ble 95 0 describes the npc reset configuration options. 37.5.2 auxiliary output port the auxiliary output port is shared by each of the nexus modules on the device. the npc communicates with each of the nexus modules and arbitrates for access to the port. output message protocol the protocol for transmitting messages via the auxiliary port is accomplished with the mseo functions. the mseo pins are used to signal the end of variable-length packets and the end of messages. they are not required to indicate the end of fixed-length packets. mdo and mseo are sampled on the rising edge of mcko. figure 1019 illustrates the state diagram for mseo transfers. all transitions not included in the figure are reserved, and must not be used. table 950. npc reset configuration options jcomp equal to npc_jcomp_plug? mcko_en bit of the port configuration register fpm bit of the port configuration register configuration no x x reset yes 0 x disabled yes 1 1 full-port mode yes 1 0 reduced-port mode nexus port controller (npc) RM0029 1696/1740 doc id 15177 rev 8 figure 1019.mseo transfers (for 2-bit mseo ) output messages in addition to sending out messages generated in other nexus blocks, the npc can also output the device id message contained in the device id register and the port replacement output message on the mdo pins. the device id message can also be sent out serially through tdo. ta ble 95 1 describes the device id and port replacement output messages that the npc can transmit on the auxiliary port. the tcode is the first packet transmitted. idle start message normal transfer end packet end message mseo = 11 m s e o = 0 1 m s e o = 0 0 mseo = 00 mseo = 00 mseo = 00 mseo = 00 mseo = 11 m s e o = 1 1 mseo = 01 mseo = 01 mseo = 11 m s e o = 1 1 mseo = 01 mseo = 01 mseo = 10 m s e o = 1 0 RM0029 nexus port controller (npc) doc id 15177 rev 8 1697/1740 figure 1020 shows the various message formats that the pin interface formatter has to encounter. note that for variable-length fields, the transmitted size of the field is determined from the range of the least significant bit to the most significant non-zero-valued bit (i.e. most significant zero-valued bits are not transmitted). the double edges in figure 1020 indicate the starts and ends of messages. fields without shaded areas between them are grouped into super-fields and can be transmitted together without end-of-packet indications between them. rules of message a variable-sized field within a message must end on a port boundary. (port boundaries depend on the number of mdo pins active with the current reset configuration.) a variable-sized field may start within a port boundary only when following a fixed- length field. super-fields must end on a port boundary. when a variable-length field is sized such that it does not end on a port boundary, it is necessary to extend and zero fill the remaining bits after the highest order bit so that it can end on a port boundary. multiple fixed-length packets may start and/or end on a single clock. when any packet follows a variable-length packet, it must start on a port boundary. the field containing the tcode number is always transferred out first, followed by subsequent fields of information. within a field, the lowest significant bits are shifted out first. figure 1021 shows the transmission sequence of a message that is made up of a tcode followed by two fields. table 951. npc output messages message name min. packet size (bits) max. packet size (bits) packet type packet name packet description device id message 66fixedtcodevalue = 1 32 32 fixed id did register contents figure 1020.message field sizes message tcode field #1 field #2 field #3 field #4 field #5 min. size (1) (bits) max. size (2) (bits) device id message 1 fixed = 32 na na na na 38 38 1. minimum information size. the actual number of bits transmitted depends on the number of mdo pins 2. maximum information size. the actual number of bits transmitted depends on the number of mdo pins nexus port controller (npc) RM0029 1698/1740 doc id 15177 rev 8 figure 1021.transmission sequence of messages 37.5.3 ieee 1149.1-2001 (jtag) tap the npc block uses the ieee 1149.1-2001 tap for accessing registers. each of the individual nexus blocks on the device implements a tap controller for accessing its registers as well. tap signals include tck, tdi, tms, and tdo. there may also be other blocks on the mcu that use the tap and implement a tap controller. the value of the jcomp input controls ownership of the port between nexus and non-nexus blocks sharing the tap. refer to the ieee 1149.1-2001 specification for further detail on electrical and pin protocol compliance requirements. the npc implements a nexus controller state machine that transitions based on the state of the ieee 1149.1-2001 state machine shown in figure 1023 . the nexus controller state machine is defined by the ieee-isto 5001-2010 standard. it is shown in figure 1024 . the instructions implemented by the npc tap controller are listed in table 952 . the value of the nexus-enable instruction is 0b0000. each unimplemented instruction acts like the bypass instruction. the size of the npc instruction register is 4-bits. data is shifted between tdi and tdo starting with the least significant bit as illustrated in figure 1022 . this applies for the instruction register and all nexus tool-mapped registers. figure 1022.shifting data into register tcode (6 bits) field #1 field #2 12 3 msb lsb msb lsb msb lsb table 952. implemented instructions instruction name private/public opcode description nexus-enable public 0x0 activate nexus controller state machine to read and write npc registers. bypass private 0xf npc bypass instruction. also the value loaded into the npc ir upon exit of reset. selected register msb lsb tdi tdo RM0029 nexus port controller (npc) doc id 15177 rev 8 1699/1740 enabling the npc tap controller assertion of the power-on reset signal or setting jcomp to a value other than the npc enable encoding resets the npc tap controller. when not in power-on reset, the npc tap controller is enabled by driving jcomp with the npc enable value and exiting the test- logic-reset state. loading the nexus-enable instruction then grants access to nexus debug. nexus port controller (npc) RM0029 1700/1740 doc id 15177 rev 8 figure 1023.ieee 1149.1-2001 tap controller state machine test logic reset run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 1 1 1 00 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 note: the value shown adjacent to each state transition in this figure represents the value of tms at the time of a rising edge of tck. RM0029 nexus port controller (npc) doc id 15177 rev 8 1701/1740 retrieving device idcode the nexus tap controller does not implement the idcode instruction. however, the device identification message can be output by the npc through the auxiliary output port or shifted out serially by accessing the nexus device id register through the tap. transmission of the device identification message on the auxiliary output port mdo pins occurs immediately after a write to the pcr, if the npc is enabled. transmission of the device identification message serially via tdo is achieved by performing a read of the register contents as described in section , selecting a nexus client register . loading nexus-enable instruction access to the npc registers is enabled when the tap controller instruction register is loaded with the nexus-enable instruction. this instruction is shifted in via the select- ir-scan path and loaded in the update-ir state. at this point, the nexus controller state machine, shown in figure 1024 , transitions to the reg_select state. the nexus controller has three states: idle, register select, and data access. table 953 illustrates the ieee 1149.1 sequence to load the nexus-enable instruction. figure 1024.nexus controller state machine idle reg_select data_access nexus-enable=0 nexus-enable=1 test-logic-reset=1 update-dr=1 update-dr=1 nexus-enable=1 && update-ir=1 table 953. loading nexus-enable instruction clock tms ieee 1149.1 state nexus state description 0 0 run-test/idle idle ieee 1149.1-2001 tap controller in idle state 1 1 select-dr-scan idle transitional state 2 1 select-ir-scan idle transitional state 3 0 capture-ir idle internal shifter loaded with current instruction 4 0 shift-ir idle tdo becomes active, and the ieee 1149.1-2001 shifter is ready. shift in all but the last bit of the nexus_enable instruction. 3 tcks 12 1 exit1-ir idle last bit of instruction shifted in nexus port controller (npc) RM0029 1702/1740 doc id 15177 rev 8 selecting a nexus client register when the nexus-enable instruction is decoded by the tap controller, the input port allows development tool access to all nexus registers. each register has a 7-bit address index. all register access is performed via the select-dr-scan path. the nexus controller defaults to the reg_select state when enabled. accessing a register requires two passes through the select-dr-scan path: one pass to select the register and the second pass to read/write the register. the first pass through the select-dr-scan path is used to enter an 8-bit nexus command consisting of a read/write control bit in the lsb followed by a 7-bit register address index, as illustrated in figure 1025 . the read/write control bit is set to 1 for writes and 0 for reads. the second pass through the select-dr-scan path is used to read or write the register data by shifting in the data (lsb first) during the shift-dr state. when reading a register, the register value is loaded into the ieee 1149.1-2001 shifter during the capture-dr state. when writing a register, the value is loaded from the ieee 1149.1-2001 shifter to the register during the update-dr state. when reading a register, there is no requirement to shift out the entire register contents. shifting may be terminated once the required number of bits have been acquired. ta ble 95 4 illustrates a sequence which writes a 32-bit value to a register 13 1 update-ir idle nexus-enable loaded into instruction register 14 0 run-test/idle reg_select ready to be read/write nexus registers table 953. loading nexus-enable instruction (continued) clock tms ieee 1149.1 state nexus state description msb lsb 7-bit register index r/w figure 1025.ieee 1149.1 controller command input table 954. write to a 32-bit nexus client register clock tms ieee 1149.1 state nexus state description 0 0 run-test/idle reg_select ieee 1149.1-2001 tap controller in idle state 1 1 select-dr-scan reg_select first pass through select-dr-scan path 2 0 capture-dr reg_select internal shifter loaded with current value of controller command input. 3 0 shift-dr reg_select tdo becomes active, and write bit and 6 bits of register index shifted in. 7 tcks 12 1 exit1-dr reg_select last bit of register index shifted into tdi 13 1 update-dr reg_select controller decodes and selects register 14 1 select-dr-scan data_access second pass through select-dr-scan path RM0029 nexus port controller (npc) doc id 15177 rev 8 1703/1740 37.5.4 nexus jtag port sharing each of the individual nexus blocks on the device implements a tap controller for accessing its registers. when nexus has ownership of the tap, only the block whose nexus-enable instruction is loaded has control of the tap. this allows the interface to all of these individual tap controllers to appear to be a single port from outside the device. if no register is selected as the shift path for a nexus block, that block acts like a single-bit shift register, or bypass register. 37.5.5 mcko and ipg_sync_mcko mcko is an output clock to the development tools used for the timing of mseo and mdo pin functions. mcko is derived from the system clock and its frequency is determined by the value of the mcko_div field in the pcr. possible operating frequencies include system clock, one-half system clock, one-quarter system clock, and one-eighth system clock speed. the npc also generates an mcko clock gating control output signal. this output can be used by the mcko generation logic to gate the transmission of mcko when the auxiliary port is enabled but not transmitting messages. the setting of the mcko_gt bit inside the pcr determines whether or not mcko gating control is active. the mcko_gt bit resets to a logic 0. in this state gating of mcko is disabled. to enable gating of mcko, the mcko_gt bit in the pcr is written to a logic 1. 37.5.6 evto sharing the npc block controls sharing of the evto output between all nexus clients that produce an evto signal. the npc assumes incoming evto signals will be asserted for one system clock period. after receiving a single clock period of asserted evto from any nexus client, the npc latches the result, and drives evto for one mcko period on the following clock. when there is no active mcko, such as in disabled mode, the npc drives evto for two system clock periods. evto sharing is active as long as the npc is not in reset. 37.5.7 nexus reset control the jcomp input that is used as the primary reset signal for the npc is also used by the npc to generate a single-bit reset signal for other nexus blocks. if jcomp is negated, an internal reset is asserted, indicating that all nexus modules should be held in reset. 15 0 capture-dr data_access internal shifter loaded with current value of register 16 0 shift-dr data_access tdo becomes active, and outputs current value of register while new value is shifted in through tdi 31 tcks 48 1 exit1-dr data_access last bit of current value shifted out tdo. last bit of new value shifted in tdi. 49 1 update-dr data_access value written to register 50 0 run-test/idle reg_select controller returned to idle state. it could also return to select-dr-scan to write another register. table 954. write to a 32-bit nexus client register (continued) clock tms ieee 1149.1 state nexus state description nexus port controller (npc) RM0029 1704/1740 doc id 15177 rev 8 37.5.8 system clock locked indication following a power-on reset, mdo[0] can be monitored to provide the lock status of the system clock. mdo[0] is driven to a logic 1 until the system clock achieves lock after exiting power-on reset. once the system clock is locked, mdo[0] is negated and tools may begin nexus configuration. loss of lock conditions that occur subsequent to the exit of power-on reset and the initial lock of the system clock do not cause a nexus reset, and therefore do not result in mdo[0] driven high. 37.6 initialization/application information 37.6.1 accessing npc tool-mapped registers to initialize the tap for nexus register accesses, the following sequence is required: 1. enable the nexus tap controller 2. load the tap controller with the nexus-enable instruction to write control data to npc tool-mapped registers, the following sequence is required: 1. write the 7-bit register index and set the write bit to select the register with a pass through the select-dr-scan path in the tap controller state machine. 2. write the register value with a second pass through the select-dr-scan path. note that the prior value of this register is shifted out during the write. to read status and control data from npc tool-mapped registers, the following sequence is required: 1. write the 7-bit register index and clear the write bit to select register with a pass through select-dr-scan path in the tap controller state machine. 2. read the register value with a second pass through the select-dr-scan path. data shifted in is ignored. see the ieee-isto 5001-2001 standard for more detail. RM0029 development trigger semaphore (dts) doc id 15177 rev 8 1705/1740 38 development trigger semaphore (dts) 38.1 introduction devices in the spc564a74xx, spc564a80xx family (bm) include a system development feature, the development trigger semaphore (dts) module, that enables software to signal an external tool by driving a persistent (affected only by reset or an external tool) signal on an external device pin. there are a variety of ways this module can be used, including as a component of an external real-time data acquisition system (bn) . 38.2 overview the development trigger semaphore (dts) module consists of three registers and a small amount of combinational logic to generate an output signal?dts trigger output (dto ). the registers are as follows. dts_semaphore register?any bit in this 32-bit register, when set to a value of logic ?1?, causes the dts module output signal to be asserted, enabling an external tool to detect up to 32 signals from the application software. in an application, each bit is generally associated with a specific data set. only the processor core and dma module can set bits in this register. the bits can only be cleared by a tool access via nexus read/write access over the jtag port. dts_startup register?this register provides a mechanism for the external tool to notify software running on the cpu that the tool is connected and can provide information about either the type of tool or options that can be used by the software. dts_enable register?this register provides an enable/disable capability for the dts feature. the architecture is shown in figure 1026 . bm.revision 2 and later bn. when used as a component of a tri ggered data acquisition system, nexus read/write access is via the jtag interface of the nexus debug port and is different than the data acquisition protocol defined in the ieee-isto 5001-2003 or ieee-isto 5001-2010 nexus standards , which use the nexus auxiliary port. development trigger semaphore (dts) RM0029 1706/1740 doc id 15177 rev 8 figure 1026.dts block diagram the dts trigger output (dto ) signal is connected to one of the evto inputs of the nexus port controller (npc). the other evto inputs to the npc are connected to the other nexus modules in the device. dto is asserted when any bit in the dts_semaphore register is set. note: when the dts module is enabled (dts_enable[dts_en] = 0b1), the nexus evto function of the evto pin is disabled and evto becomes the dto . unlike the evto function that only asserts for one clock, the dto function remains asserted until the tool reads the dts_semaphore register, clearing the register?s contents. figure 1027 shows the chain of events that begins with setting of any bit in the dts_semaphore register and the clearing of the register caused by a nexus read. figure 1027.dto event sequence dts_en dts_sempaphore 32-bit dts_enable system clock system reset xbar master id peripheral bus (dto ) dts_startup dts trigger output dts trigger output (dto ) evto pin dts_semaphore register cpu writes dts_semaphore to a non-zero value internal dto signal is asserted evto asserted externally initial conditions: ? dts_enable[dts_en] = 0b1 ? dts_semaphore = 0x0000_0000 nexus rwa reads dts_semaphore, which clears register internal dto signal is negated evto negated externally ~ ~ ~ ~ ~ ~ RM0029 development trigger semaphore (dts) doc id 15177 rev 8 1707/1740 38.3 dts device connections the dts module connects to the peripheral bridge (pbridge) for access to the registers. the pbridge is connected to a slave port of the crossbar bus interface (xbar). connected to the xbar master ports are the core (e200z4, with one master port for the instruction and another for the load/store bus), the edma module, the flexray module, and an external bus interface (bo) . the registers have limited access as described in section 38.3.1, dts register access . access is based on the xbar master id of the accessing module. access to the dts_semaphore register is limited to the e200z4 core and the edma module and is restricted to only setting bits. only an access via a nexus read/write access from an external tool through the nexus/jtag port of the device can clear bits in the dts_semaphore register (bp) . similarly, the dts_enable and dts_startup registers can only be written via a nexus read/write access. note: nexus read/write accesses use the load/store bus of the core to perform accesses, but nexus accesses have a different master id than normal core load/stores. figure 1028.dts device connections 38.3.1 dts register access a summary of accesses to all dts registers by bus masters is provided in table 955 . note that only proper 32-bit accesses are valid. the effect of write accesses, that are not 32 bits, is not defined. bo. the external bus interface xbar master port is used for internal test of the device and is not accessible to the user. bp. dts_semaphore bits are cleared automatic ally when read through the nexus/jtag port. edma flexray xbar pbridge xbar slave port xbar master id dts peripheral bus xbar master id e200z4 dts trigger output evto pin (dto ) ebi npc evto inputs development trigger semaphore (dts) RM0029 1708/1740 doc id 15177 rev 8 access to dts module registers is controlled based on the xbar master id of the accessing module. the table below shows the xbar master ids for each of port. note: the xbar master id should not be confused with the master port number of the xbar. see chapter 9: multi-layer ahb crossbar switch (xbar) , for details. tools must access the dts registers (dts_enable, dts_startup, and dts_semaphore) through the nexus read/write access mechanism of the e200z4 core. jtag accesses through either core appear as if the access is via the core and therefore will not have the same level of access as a nexus r/w access. 38.4 memory map ta ble 95 6 shows the memory map of the development trigger semaphore module registers. three 32-bit registers are implemented. the rest of the memory map (0xc3f9_c00c through 0xc3f9_ffff) is reserved. 38.5 register descriptions 38.5.1 dts output enable register (dts_enable) this dts_enable register controls the dts trigger output (dto ) and whether dto is active on the evto output pin of the device. figure 1029 shows the format of the dts_enable register. table 955. dts register access effects register 32-bit read 32-bit write rwa (1) e200z4 edma flexray rwa (1) e200z4 edma flexray dts_enable data data data data data no effect no effect no effect dts_startup data data data data data no effect no effect no effect dts_semaphore data and clear (2) data data data no effect bit or bit or no effect 1. nexus read/write access via an external tool. 2. a read of the dts_semaphore register by either nexus read/write access module is destructive and clears all bits in the register. table 956. dts module address register description size (bits) access dts_base (0xc3f9_c000) dts_enable dts output enable register 32 restricted r/w (1) dts_base + 0x0004 dts_startup dts startup register 32 restricted r/w (1) dts_base + 0x0008 dts_semaphore dts semaphore register 32 restricted r/w (1) dts_base + 0x000c ? dts_base + 0xffff reserved 1. only certain types of accesses are allowed. see separate description. RM0029 development trigger semaphore (dts) doc id 15177 rev 8 1709/1740 note: access to the dts_semaphore and dts_startup registers are unaffected by the state of this register. 38.5.2 dts startup register (dts_startup) the dts_startup register is used for tool detection and startup information exchange between the tool and software running on the microcontroller. figure 1029.dts_enable register address: dts_base+0x0000 access: restricted r/w (1) 0123456789101112131415 r0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000000 dts_en w reset: 0000000000000000 = unimplemented or reserved 1. the dts_enable register can be read by the e200z4 core, but can only be written by a nexus read write access (rwa). table 957. dts_enable field descriptions name description 31 dts_en dts enable controls whether the dto signal is routed to the evto pin. 0: dts output is disabled. 1: dts output is enabled. any bit set in the dts_semaphore register will assert the dts trigger output signal (dto ). the dts enable bit is cleared by a device reset (either the assertion of the external reset or by an internally generated reset). a jtag reset does not change the state of this register. development trigger semaphore (dts) RM0029 1710/1740 doc id 15177 rev 8 38.5.3 dts semaphore register (dts_semaphore) the dts_semaphore register is used by software to assert the dto signal on the device evto pin. a 0b1 in any bit of this register causes the dto signal on the evto pin to be driven low. the intended use of this register is for the dto signal to notify tools that data is available. individual bits are used to identify the specific data. figure 1030.dts_startup register address: dts_base+0x0004 access: restricted r/w (1) 0123456789101112131415 r ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w reset: 0000000000000000 1. the dts_startup register can be read by the e200z4 core, the edma module and nexus but can only be updated by a nexus read write access (rwa). table 958. dts_startup field descriptions name description ad[31:0] application dependent register bits the bits have no defined meaning to the microcontroller. they are used to by an external tool to pass information, e.g., application options and status, to application software running on target microcontroller at startup time. use a nexus rwa 32-bit write access to update the contents of this register. a device reset (either from the reset pin or an internally generated reset) clears all bits in the register. a jtag reset does not change the contents of the register. RM0029 development trigger semaphore (dts) doc id 15177 rev 8 1711/1740 38.6 example application the calibration process of a new engine requires real-time access to calibration tables and the ability to update the tables in real-time (bq) . the dts module enables this capability by enabling software to assert a signal to an external device pin to notify an external tool that data is available. the tool can then retrieve the data. in this type of application the dts_semaphore register and dts trigger output (dto ) signal provide a mechanism to notify the calibration tool that the calibration variable or figure 1031.dts_semaphore register address: dts_base+0x0008 access: restricted r/w (1) 0123456789101112131415 r st31 st30 st29 st28 st27 st26 st25 st24 st23 st22 st21 st20 st19 st18 st17 st16 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r st15 st14 st13 st12 st11 st10 st9 st8 st7 st06 st5 st04 st3 st02 st1 st0 w reset: 0000000000000000 1. the e200z4 core and edma modules can set bits in the dts_ semaphore register but cannot clear them?writes by the core and edma are bitwise ored to the contents of the register. nexus can only read this register but all bits are cleared after the read operation. table 959. dts_semaphore field descriptions name description st[31:0] semaphore trigger when a core or edma writes a logical ?1? to a bit, the bit is set. a write of ?0? by the core or dma does not change the state of the bit. ? all register bits are set to ?1? by a device reset. ? a jtag reset does not change the state of this register. ? the register can be accessed, with restrictions, by any core, dma or any nexus rwa. ? for the core or dma, only 32-bit write or read accesses are valid. ? a core or dma valid read access returns the current value of the register and leaves the register unchanged. 0: no flag 1: flag is set bq. spc564a74xx, spc564a80xx devices also include an mmu modification feature, which enables real-time switching of calibration tables. development trigger semaphore (dts) RM0029 1712/1740 doc id 15177 rev 8 variables (or sets of measurements), up to 32, have been updated with new values and are available for the tool to access. note: it is the user?s responsibility to ensure that the tool has time to retrieve the data prior to that particular trigger being set a second time. it is also permissible to have multiple triggers active at the same time or for a second trigger to be set before a previous trigger has been serviced, as long as it is not the same trigger (unless it is acceptable to the tool to not receive every data set). figure 1032 shows an example dts startup sequence for an external real-time data acquisition system. the startup and synchronization sequence can be as simple or as complicated as the need requires. however, a typical startup sequence is as follows: 1. the dts_startup register is cleared by a power on reset or any cpu reset. 2. the tool writes a non-zero value to the dts_startup register. 3. the cpu (user application software) then reads the value of the dts_startup register. based on this value, different initialization options can be selected. the bits can be used for any application specific definitions. 4. since the dts_semaphore register is cleared when the tool reads the current value. the tool should perform all necessary initialization before reading this register. the application software can then check that the dts_semaphore register was cleared by the tool, to determine that it is safe to start using it for its intended raster trigger semaphore function. 5. an optional hand shake from the cpu can be used to inform the tool that the user software has detected that the tool is attached and the cpu has performed the proper initialization for the tool by writing a predefined value to the dts_semaphore register (the example shown in the figure above uses 0xaaaa_aaaa?all a?s was used since it is unrealistic that 16 channels could be enabled very quickly after start up after a reset). figure 1032.dts startup sequence example !" #$ $ % & '(( ( '''''''' $ % ) * ' % " ( (+ & '(( ( '%,(" -- & '(( ( & . - ( & . - ( & . - ( "" ) * " % "" / ( % RM0029 revision history doc id 15177 rev 8 1713/1740 39 revision history table 960. documenr revision history date revision changes 12-dec-2008 1 initial release 25-jan-2010 2 chapter 2 memory map updated allocated size for the following address locations: ? 0x0100_0000 and 0x1fff_ffff ? 0x2000_0000 and 0x2fff_ffff ? 0x3000_0000 and 0x3fff_ffff added two more reserved spaces 0xc3fd_3800 in place of 0xc3fd_4400 flash shadow row - fl_1 address range changed chapter 3 signal description signal properties table: ? removed signal column ? added function column containing description of all pins ? removed default state after reset ? added pcr pa field column ? added status column with pre-reset and post-reset state and function signal details table: ? signal descriptions updated. chapter 4 resets ? resets detail added ? ?boot configuration (bootcfg[0:1])? section added. ? column of bootcfg values added to ?reset vector location? table ? ps0 bit added to rchw structure. chapter 5 operating modes and clocking ? added flexcan clock divider to list of clock dividers ? added details to flexcan clock support chapter 7 enhanced direct memory access controller (edma) completely rewritten revision history RM0029 1714/1740 doc id 15177 rev 8 25-jan-2010 2 chapter 8 multi-layer ahb crossbar switch (xbar) ? master port functionality and slave port functionality sections deleted ? detail added to sgpcr[park] description ? mpr[mstrx] descriptions updated with port functions ? parking section added ? hlp bit removed from sgpcr register. it has no effect ? register summary removed. ? mprn register reset value is now 0x43020010 removed following bits from xbar_sgpcrn registers (ports controlled by this bits do not exist on this device): ? hpe6 ? hpe5 ? hpe4 ? hpe3 ? hpe1 chapter 10 flash register names changed: ? cr register renamed to mcr ? lml register renamed to lmlr ? hbl register renamed to hlr ? sll register renamed to slmlr ? lms register renamed to lmsr ? hbs register renamed to hsr ? adr register renamed to ar ? pfcr1 register renamed to biucr ? pfapr register renamed to biuapr ? pfcr2 register renamed to biucr2 register field value definitions: ? biuapr[mnap] values table updated with correct master port information ? biucr[mnpfe] values table updated with correct master port information registers added: ? ut0-ut2 ? um0-um4 flash segmentation diagram and memory map updated chapter 11 sram ? note about mudcr register and reference to ecsm chapter adde.d ? added a section on initialization chapter 12 memory protection unit (mpu) ?new chapter table 960. documenr revision history (continued) date revision changes RM0029 revision history doc id 15177 rev 8 1715/1740 25-jan-2010 2 chapter 14 interrupt controller (intc) ? pcr_selx fields removed from intc_psr register maps. ? interrupt vector 307 is sourced by mcm (mcm_ipi_ecc_1bit_int) and is source of both flash and sram single-bit ecc error correction. chapter 15 system integration unit (siu) significant amount of new detail added to pcr register sections register names changed: ? siu_cmpah renamed to siu_carh ? siu_cmpal renamed to siu_carl ? siu_cmpbh renamed to siu_cbrh ? siu_cmpbl renamed to siu_cmrl register field deleted: ? siu_direr[eire6] deleted register field added: siu_osr[ovf6] chapter 17 error correction status module (ecsm) features list updated registers added/memory map updated: ? miscellaneous reset status register (mrsr) ? miscellaneous user-defined control (mudcr) ? ecc error generation register (eegr) ? misc wakeup control register (mwcr) all ecsm register names are now prefixed with ?ecsm_?. register reset values verified/updated ecsm_mudcr[swsr] moved to bit 1 chapter 19 software watchdog timer (swt) swt_cr register renamed to swt_mcr. chapter 20 boot assist module (bam) calibration boot is not supported--ebi boot is supported instead table 960. documenr revision history (continued) date revision changes revision history RM0029 1716/1740 doc id 15177 rev 8 25-jan-2010 2 chapter 21 configurable enhanced modular io subsystem (emios200) register name changes: ? emioss[n] register is now named emios_csr[n] ? gfr register is now named emios_gfr ? mcr register is now named emios_mcr ? oudr register is now named emios_oudr ? ucdis register is now named emios_ucdis ? cadr register is now named emios_cadr ? cbdr register is now named emios_cbdr ? ccntr register is now named emios_ccntr ? ccr register is now named emios_ccr ? altan registers are now named emios_altan all available functions are now available on all channels. formerly, some channel groups had a limited subset of functions. chapter 23 enhanced queued analog-to-digital converter (eqadc) ? reset value for agr1/2 registers changed to 0x4000 ? reset value for aor1/2 registers changed to 0x0000 chapter 24 flash fuse loader (ffl) ?new chapter chapter 27 deserial serial peripheral interface (dspi) dspi frequency support section added. dspi_hcr register deleted. it is not user-configurable. dspi_rser register fields renamed: ? dspi_rser[eoqf_re] renamed to dspi_rser[eoqfre] ? dspi_rser[tfuf_re] renamed to dspi_rser[tfufre] ? dspi_rser[tfff_re] renamed to dspi_rser[tfffre] ? dspi_rser[tfff_dirs] renamed to dspi_rser[tfffdirs] ? dspi_rser[dpef_re] renamed to dspi_rser[dpefre] ? dspi_rser[spef_re] renamed to dspi_rser[spefre] ? dspi_rser[ddif_re] renamed to dspi_rser[ddifre] ? dspi_rser[rfof_re] renamed to dspi_rser[rfofre] ? dspi_rser[rfdf_re] renamed to dspi_rser[rfdfre] ? dspi_rser[rfdf_dirs] renam ed to dspi_rser[rfdfdirs] dspi_dsicr register fields deleted: ?dms ? pes ?pe ?pp spi_dsicr1 register fields deleted: ? dse1 ? dse0 table 960. documenr revision history (continued) date revision changes RM0029 revision history doc id 15177 rev 8 1717/1740 25-jan-2010 2 registers deleted: ? dspi_ssr ? dspi_pisrn ? dspi_dimr ? dspi_dpir chapter 28 enhanced serial communications interface (esci) registers converted to 16- and 32-bit format to match header file: ? fields formerly found in registers scibdh, scibdl, scicr1 and scicr2 are now contained in sci_cr1 ? fields formerly found in registers scicr3 and scicr4 are now contained in sci_cr2 ? registers scidrh and scidrl have been combined into a single register named sci_dr ? fields formerly found in registers scisr1, scirsr2, linstat1 and linstat2 are now contained in sci_sr ? fields formerly found in registers linctrl1, linctrl2 and linctrl3 are now contained in sci_lcr ? the lintx register is now named sci_ltr ? the linrx register is now named sci lrr ? fields formerly found in registers lincrcp1, lincrcp2 and scicr5 are now contained in sci_lpr. field name changes: ? scicr3[berie] is now sci_cr2[ieberr] ? scicr3[brcl] is now sci_cr2[brk13] ? scicr4[besm] is now sci_cr2[besm13] ? scicr4[bestp] is now sci_cr2[sbstp] ? scidrh[rn] is now sci_dr[r8] ? scidrh[tn] is now sci_dr[t8] ? scisr2[ract] is now sci_sr[raf] chapter 29 flexcan module message buffer architecture section added typical can system figure and text added to overview section block diagram replaced message buffer architecture block diagram added register name changes: ? ctrl renamed to cr ? imask2 renamed to imrh ? imask1 renamed to imrl ? iflag2 renamed to ifrh ? iflag1 renamed to ifrl table 960. documenr revision history (continued) date revision changes revision history RM0029 1718/1740 doc id 15177 rev 8 25-jan-2010 2 mcr register fields renamed: ? mcr[not_rdy] renamed to mcr[notrdy] ? mcr[soft_rst] renamed to mcr[softrst] ? mcr[frz_ack] renamed to mcr[frzack] ? mcr[wrn_en] renamed to mcr[wrnen] ? mcr[lpm_ack] renamed to mcr[mdisack] ? mcr[bcc] renamed to mcr[mbfen] cr register fields renamed: ? cr[boff_msk] renamed to cr[boffmsk] ? cr[err_msk] renamed to cr[errmsk] ? cr[clk_src] renamed to cr[clksrc] ? cr[twrn_msk] renamed to cr[twrnmsk] ? cr[rwrn_msk] renamed to cr[rwrnmsk] ? cr[boff_rec] renamed to cr[boffrec] esr register fields renamed: ? esr[twrn_int] renamed to esr[twrnint] ? esr[rwrn_int] renamed to esr[rwrnint] ? esr[bit1_err] renamed to esr[bit1err] ? esr[bit0_err] renamed to esr[bit0err] ? esr[ack_err] renamed to esr[ackerr] ? esr[crc_err] renamed to esr[crcerr] ? esr[frm_err] renamed to esr[frmerr] ? esr[stf_err] renamed to esr[stferr] ? esr[tx_wrn] renamed to esr[txwrn] ? esr[rx_wrn] renamed to esr[rxwrn] ? esr[flt_conf] renamed to esr[fltconf] ? esr[boff_int] renamed to esr[boffint] ? esr[err_int] renamed to esr[errint] ? esr[wak_int] renamed to esr[wakint] chapter 32 power management controller (pmc) ? ?low power ram test? added to list of operating modes. ? in the functional description section, detail added regarding disabling the voltage regulators. ? pmc signals table updated: * vddreg is 4.5-5.5v (was 4.0- 5.5v) * vdd3p3 is 3.3-3.6v (was 3.0-3.6v) * vdd1p1 is 1.2-1.32v (was 1.08-1.32v) ? vddreg requires decoupling capacitor on the order of 4.7 f - 20 f (was 1.0 f - 20 f) ? vdd1p2: bypass capacitor esr max is 50m (was 10m ). ceramic capacitor value is 100nf (was 200nf). deleted sentence stating: ? when switching current load is lower, it is possible to reduce the requirements of the bypass capacitor to 1 f - 5 f and 100 m esr.? ? mcr register reset value is 0x98000000 (was 0x00000000) table 960. documenr revision history (continued) date revision changes RM0029 revision history doc id 15177 rev 8 1719/1740 25-jan-2010 2 ? sr register reset value is ?0x03000000 or 0x06000000 (was 0x02000000 or 0x06000000) ? nvusro register info added--contains bit used to shutdown 3.3v regulator. ? changes to mcr register: * lvre5 field is now lvre50 * lvie5 field is now lvie50 ? changes to trimr register: * lvi50trim is now lvdregtrim * v33trim is now vdd33trim * lvi33trim is now lvd33trim * v12trim is now vddctrim * lvi12trim field is now lvdctrim * updated vdd33trim values * updated vddctrim values * updated lvdctrim values ? changes to sr register: * brw field is now lvfvstby * lvi5c is now lvfc50 * lvi3c is now lvfc33 * lvi1c is now lvfcc * updated vdd33trim values ? in functional description bandgap reference of 2.7v deleted. ? in bandgap section, description of 1.219v reference voltage ?...that varies by 4% before calibration and 1% after calibration over temperature and lifetime? deleted. ? in 5v lvi section, following statement deleted: ? maximum hysteresis value between rising and falling trip points is 90 mv? ? in 5v lvi section, ?in case the monitored voltage falls below the *nominal* trip point, the lvi output goes to logical 0? changed to, ?in case the monitored voltage falls below the *falling* trip point, the lvi output goes to logical 0?. ? in lvi section, description of resistor chain deleted. ? nominal 4.29v trip value noted as being typical and subject to variance. ? in 3.3v internal voltage regulator section, following text deleted: ?tolerance of the 3.3 v supply is -5% / +10% including line and load variation. detail on disabling voltage regulator added. ? in 3.3v lvi section, noted that there are 2 lv monitors. also deleted hysteresis spec. ? in 3.3v lvi section noted 3.09v (was 3.00v) trip value as being typical and subject to variance. ? in 1.2v regulator section, ?tolerance of 10%? on 1.2v supply current deleted. ? in 1.2v regulator section, default voltage is 1.28 v (was 1.270v). ? 1.2v lvi section: hysteresis spec deleted. rising trip point is 1.16 (was 1.08). ? power on reset section: typical values table deleted. ? sections added describing modules affected by pmc. ? adc test mux section added ? electrical characteristics removed. see data sheet. ? replaced pmc block diagram table 960. documenr revision history (continued) date revision changes revision history RM0029 1720/1740 doc id 15177 rev 8 25-jan-2010 2 ? replaced bandgap reference block diagram ? replaced vreg 3.3 v power connection diagram ? vddeh referring to supply of closest i/o segmenet changed to vddeh1. chapter 33 jtag controller device-specific info section added chapter 35 temperature sensor new chapter 07-may-2010 3 chapter 1 introduction updated several instances of text to indicate 8 kb instruction cache (was incorrectly stated as 4 kb) updates to device comparison: ? max clock speed for device is 150 mhz (was 145 mhz) updates to features list: ? core clock speed for device is 150 mhz (was 145 mhz) ? correction: there are 6 reaction channels (noted as 5) ? development trigger semaphore (dts) added to features list and feature details ? flexray now has 128 message buffers and ecc support chapter 2 memory map ? ?allocated size? for reserved area from 0x4003_0000 to 0xbfff_ffff changed to 2 gb - 192 kb. ? range from 0xfff0_0000 to 0xfff0_3fff is no longer reserved?it is allocated to pbridge (aips-lite) registers ? reaction module (reacm) registers added at starting address 0xc403_0000. this space was previously reserved. there is reserved space before and after these registers. chapter 3 signal description in power/ground segmentation table, vdda voltage changed to 5 v (was incorrectly noted as being 1.2 v) power segment vddeh1a renamed to vddeh1 changes to signal properties table (changes apply to revision 2 and later devices: ebi changes: ? we_be[2] (a2) and cal_we_be[2] (a3) signals added to cs[2] (pcr 2) ? we_be[3] (a2) and cal_we_be[3] (a3) signals added to cs[3] (pcr 3) calibration bus changes: ? cal_we[2]/be[2] (a2) signal added to cal_cs[2] (pcr 338) ? cal_we[3]/be[3] (a2) signal added to cal_cs[3] (pcr 339) ? cal_ale (a1) added to cal_addr[15] (pcr 340) table 960. documenr revision history (continued) date revision changes RM0029 revision history doc id 15177 rev 8 1721/1740 07-may-2010 3 chapter 3 signal description (continued) eqadc changes: ? an[8] and an[38] pins swapped. an[8] is now on pins 9 (176-pin), b3 (208-ball) and d6 (324-ball). an[8] was on c5 (324-ball) on previous devices. an[38] is now on c5 (324-ball). an[38] was on pins 9 (176-pin), b3 (208-ball) and d6 (324-ball) on previous devices. ? anz function added to pin an11 reaction channels added to etpu2: ? rch0_a (a3) added to etpu_a[14] (pcr 128) ? rch0_b (a2) added to etpu_a[20] (pcr 134) ? rch0_c (a2) added to etpu_a[21] (pcr 135) ? rch1_a (a2) added to etpu_a[15] (pcr 129) ? rch1_b (a2) added to etpu_a[9] (pcr 123) ? rch1_c (a2) added to etpu_a[10] (pcr 124) ? rch2_a (a2) added to etpu_a[16] (pcr 130) ? rch3_a (a2) added to etpu_a[17] (pcr 131 ? rch4_a (a2) added to etpu_a[18] (pcr 132)) ? rch4_b (a2) added to etpu_a[11] (pcr 125) ? rch4_c (a2) added to etpu_a[12] (pcr 126) ? rch5_a (a2) added to etpu_a[19] (pcr 133) ? rch5_b (a2) added to etpu_a[28] (pcr 142) ? rch5_c (a2) added to etpu_a[29] (pcr 143) reaction channels added to emios: ? rch2_b (a2) added to emios[2] (pcr 181) ? rch2_c (a2) added to emios[4] (pcr 183) ? rch3_b (a2) added to emios[10] (pcr 189) ? rch3_c (a2) added to emios[11] (pcr 190) pad changes: ? etpua16 (pcr 130) has medium (was slow) pad ? etpua17 (pcr 131) has medium (was slow) pad ? etpua18 (pcr 132) has medium (was slow) pad ? etpua19 (pcr 133) has medium (was slow) pad ? etpua25 (pcr 139) has slow+lvds (was medium+lvds) pads signal details table updated: ? added etpu2 reaction channels ? changed irq[0:15] to two ranges, excluding irq6, which does not exist on this device ? changed tcr_a to tcrclka (tcr_a is the pin name, not the signal name) ? changed we_be[0:1] to we_be[0:3] (2 new signals added to rev. 2). also changed notation from ?we_be[n]? to ?we[n]/be[n]? to be consistent. table 960. documenr revision history (continued) date revision changes revision history RM0029 1722/1740 doc id 15177 rev 8 07-may-2010 3 chapter 3 signal description (continued) changes to power/ground segmentation table: ? addr[20:21] removed from vdde2 segment; they are in vdde-eh ? cal_cs1 removed from vdde12 segment (there is no cal_cs1 on this device) ? cal_evto and cal_mcko removed from vdde12 segment. those pins do not exist ? vdde-vddeh renamed to vdde-eh ? emios24 removed from vddeh segment. that pin does not exist. ? etpua[0:9] added to vddeh4 segment ? renamed tcr_a in vddeh4 segment to tcrclka. ? extal and xtal added to vddeh6 segment ? an15-fck added to vddeh7 segment ? gpio98, gpio99, gpio206, gpio207 and gpio219 added to vddeh7 segment. ? mseo1 added to vddeh7 segment chapter 5 operating modes and clocking ? max clock speed is now 150 mhz (was 145 mhz) ? eprediv/idf divider = /7 for 150 mhz clock (was /8 for 145 mhz clock) ? emfd/ndiv loop divider = 60 for 150 mhz clock (was 58 for 145 mhz clock) ? vco clock out = 266.67 mhz for 150 mhz clock (was 290 mhz for 145 mhz clock) ? erfd/odf output divider = /1 for 150 mhz clock (was /2 for 145 mhz clock) ? eprediv/idf divider = /7 for 100 mhz clock (was /4) ? emfd/ndiv loop divider = 80 for 100 mhz clock (was 40) ? erfd/odf output divider = /1 for 100 mhz clock (was /4) chapter 6 performance optimization ?new chapter chapter 7 e200z4 core ? mmu is 24-entry (was 16-entry) ? instruction cache is 8_kb (was incorrectly stated as 4_kb) ? supports wait power-saving mode (previously incorrectly stated doze, nap and sleep modes were also supported) chapter 10 peripheral bridge (pbridge) ? previously there were no control registers for the peripheral bridge. registers added: master privilege registers (mprot), peripheral access control registers (pacr) and off-platform peripheral access control registers (opacr). chapter 11 flash memory ? added utn registers to memory map chapter 12 sram ? detail on standby sram power sources added to standby mode section table 960. documenr revision history (continued) date revision changes RM0029 revision history doc id 15177 rev 8 1723/1740 07-may-2010 3 chapter 13 memory protection unit (mpu) changes to mpu rgd alternate access control n (mpu_rgdaacn) ? four new fields added; m7re, m7we, m6re and m6we ? three fields deleted: m1pe, m1sm, m1um and m0pe chapter 15 interrupt controller (intc) interrupts added: ? dspi_bsr[spef] ? dspi_bsr[dpef] ? dspi_bsr[ddif] ? dspi_csr[spef] ? dspi_csr[dpef] ? dspi_csr[ddif] ? dspi_dsr[spef] ? dspi_dsr[dpef] ? dspi_dsr[ddif]gifer[lrne] ? gifer[drne] ? gifer[lrce] ? gifer[drce] ? reacm_ge ? reacm[0] ? reacm[1] ? reacm[2] ? reacm[3] chapter 16 system integration unit (siu) changes to siu_pcr2: ? two new functions added: we[2]/be[2] and cal_we[2]/be[2] ? pa field expanded to 4 bits changes to siu_pcr3: ? two new functions added: we[3]/be[3] and cal_we[3]/be[3] ? pa field expanded to 4 bits changes to siu_pcr123: ? new function added: rch1_b changes to siu_pcr124: ? new function added: rch1_c changes to siu_pcr125: ? new function added: rch4_b changes to siu_pcr126: ? new function added: rch4_c ? pa field expanded to 3 bits changes to siu_pcr128: ? new function added: rch0_a ? pa field expanded to 4 bits table 960. documenr revision history (continued) date revision changes revision history RM0029 1724/1740 doc id 15177 rev 8 07-may-2010 3 chapter 16 system integration unit (siu) (continued) changes to siu_pcr129: ? new function added: rch1_a ? pa field expanded to 3 bits changes to siu_pcr130: ? new function added: rch2_a ? pa field expanded to 3 bits changes to siu_pcr131: ? new function added: rch3_a ? pa field expanded to 3 bits changes to siu_pcr132: ? new function added: rch4_a ? pa field expanded to 3 bits changes to siu_pcr133: ? new function added: rch5_a ? pa field expanded to 3 bits changes to siu_pcr134: ? new function added: rch0_b changes to siu_pcr135: new function added: rch0_c changes to siu_pcr142: ? new function added: rch5_b ? pa field expanded to 3 bits changes to siu_pcr143: ? new function added: rch5_c ? pa field expanded to 3 bits changes to siu_pcr181: ? new function added: rch2_b ? pa field expanded to 3 bits changes to siu_pcr183: ? new function added: rch2_c ? pa field expanded to 3 bits changes to siu_pcr189: ? new function added: rch3_b ? pa field expanded to 3 bits changes to siu_pcr190: ? new function added: rch3_c ? pa field expanded to 3 bits changes to siu_pcr219: ? this pin is not used to select gpio[219]. instead, it is used to control the electrica characteristics of the mcko pin. table 960. documenr revision history (continued) date revision changes RM0029 revision history doc id 15177 rev 8 1725/1740 07-may-2010 3 chapter 16 system integration unit (siu) (continued) new siu_pcr registers added (control the electrical characteristics of mdo[0:3] pins): ? siu_pcr[220] ? siu_pcr[221] ? siu_pcr[222] ? siu_pcr[223] new siu_pcr registers added (control the electrical characteristics of mseo[0:1] pins): ? siu_pcr[224] ? siu_pcr[225] new siu_pcr registers added (control the electrical characteristics of evto and tdo pins respectively: ? siu_pcr[227] ? siu_pcr[228] new siu_pcr registers added (control the electrical characteristics of rstout, evti and emios5 (output only) pins respectively: ? siu_pcr[230] ? siu_pcr[231] ? siu_pcr[232] new siu_pcr registers added (control the electrical characteristics of txdc and rxdc pins respectively: ? siu_pcr[244] ? siu_pcr[245] new siu_pcr registers added (control the electric characteristics of some calibration bus pins): ? siu_pcr336 ? siu_pcr338 ? siu_pcr339 ? siu_pcr340 ? siu_pcr341 ? siu_pcr342 ? siu_pcr343 ? siu_pcr345 added clarification to eqadc trigger input select register (siu_etisr) section. new register added: core mmu pid control register (siu_empcr0). provides capability of real-time modification of mmu entries. chapter 17 frequency-modulated phase locked loop (fmpll) ? esyncr1 register reset value updated ? esyncr2 register reset value updated table 960. documenr revision history (continued) date revision changes revision history RM0029 1726/1740 doc id 15177 rev 8 07-may-2010 3 chapter 21 boot assist module (bam) added/updated register values in calibration bus/ebi register settings table: ? ebi_mcr and ebi_br0 values updated ? values added for siu_pcr0, siu_pcr[8:11], siu_pcr[12:27], siu_pcr[28:43], siu_pcr64 and siu_pcr[68:69]. added new section: enabling debug of a censored device chapter 23 enhanced time processing unit (etpu2) changes to register reset values: ? etpu_tbcr register reset value is 0x2000_0000 ? etpu_redcr register reset value is 0x0000_0200 chapter 24 reaction module new chapter chapter 25 enhanced queued analog-to-digital converter (eqadc) ? note added to ?50% x vref? in ?non-multiplexed channel assignments? and ?multiplexed channel assignments? tables explaning that value is accurate only before calibration and should not be used for calibration of the adc. ? new section added: ?adc sampling delay after power-up? chapter 27 temperature sensor location of tsc3 changed; register field descriptions updated chapter 28 flash fuse loader (ffl) ? moved location of third temperature sensor calibration constant ? added device serial number location chapter 32 flexcan register field name changes ? ecr[rx_err_counter] is now ecr[rxecnt] ? ecr[tx_err_counter] is now ecr[txecnt] table 960. documenr revision history (continued) date revision changes RM0029 revision history doc id 15177 rev 8 1727/1740 07-may-2010 3 chapter 34 flexray module ecc has been added to the pe dram memory ? single-bit error detection and correction ? multi-bit error detection ecc has been added to the chi lram memory ? single-bit error detection ? multi-bit error detection module now has 128 message buffers (was 64) new sections added: ? ?controller host interface clocking? ? ?system bus access? ? ?pe data memory (pe dram)? ? ?chi lookup-table memory (chi lram)? ? ?memory content error detection? memory management content added to application information section. new registers added: ? fr_pedrar ? fr_pedrdr ? fr_eeifer ? fr_eericr ? fr_eerar ? fr_eerdr ? fr_eercr ? fr_eeiar ? fr_eeidr fr_eeicr chapter 38 development trigger semaphore (dts) new chapter table 960. documenr revision history (continued) date revision changes revision history RM0029 1728/1740 doc id 15177 rev 8 18-oct-2010 4 throughout document ? most occurrences of ?powerpc? have been replaced with either ?power architecture? or ?power isa (instruction set architecture)? ? editorial and formatting changes chapter 1 introduction ? nexus development interface (ndi) is compliantieee-isto 5001-2003 and 2010 standards updates to device comparison table: ? correction to package offerings: device is offered in lqfp176 (lqfp100 package was incorrectly listed twice) ? interrupt controller has 486 channels ? 199 interrupt vectors are reserved (was 197) adc conversion times updated: ? 12-bit conversion time: 938 ns (1m sample/sec) ? 10-bit conversion time: 813 ns (1.2m sample/second) ? 8-bit conversion time: 688 ns (1.4m sample/second chapter 2 memory map dts module registers mapping changed: 0xc3f9_c000 - 0xc3f9_ffff chapter 3 signal description change in signal name notation for dspi signals: ? pcs_x[n] is now dspi_x_pcs[n] ? sout_x is now dspi_x_sout ? sin_x is now dspi_x_sin ? sck_x is now dspi_x_sck change in signal name notation for can signals: cntxx is now can_x_tx cnrxx is now can_x_rx change in signal name notation for sci signals: rxdx is now sci_x_rx txdx is now sci_x_tx pin 96 added to list of vss pins for 176-pin package gpio[219] and mcko pins are both controlled by siu_pcr219, which does not have a pa field. both are single-function pins. see siu_pcr219 section in siu chapter for details. table 960. documenr revision history (continued) date revision changes RM0029 revision history doc id 15177 rev 8 1729/1740 18-oct-2010 4 (cont?d) chapter 3 signal description (cont) clarification: following signals are active low: ? (ebi) cs [0:3] ? (ebi) bdip ? (ebi) oe ? (ebi) ta ? (ebi) ts ? (ebi) rd_wr ? (ebi) we [0:1]/be [0:1] ? (nexus) mseo [0:1] ? (nexus) rdy ?irq [0:15] ? (flexray) fr_a_tx_en ? (flexray) fr_b_tx_en note added to multiv pads: multivoltage pads are automatically configured in low swing mode when a jtag or nexus function is selected, otherwise they are high swing. note added to vddeh7 voltage on an12-an15: for pins an12-an15, if the analog features are used the vddeh7 input pins should be tied to vdda because that segment must meet the vdda specification to support analog input function. added vrl, vrh, and refbypc functions after reset. clarification: ?10? on bootcfg[0:1] causes boot from external memory using ebi changes to pad types table: ? multiv high swing mode range changed. ? footnote added: veedeh7 supply cannot be below 4.5 v when in low-swing mode. power segment for etpua[10:20] changed from vddeh2 to vddeh1. we[n], be[n] and cal_cs[n] signals are active low. ball w4 on bga324 package is v ss t21 added to vss list on 324 ball bga package. footnote added to vrc33: do not use vrc33 to drive external circuits chapter 4 resets chapter content replaced. the most significant changes are: ? watchdog timeout table updated ? rchw location table updated ? bootcfg options table updated chapter 5 operating modes and clocking fmpll_esyncr1[pllcfg] field is no w called fmpll_esyncr1[clkcfg] added explanation of how sysdiv programming depends on values of fields bypass and sysclkdiv in siu_sysdiv register chapter 8 enhanced direct memory access controller (edma) notation change: register bitfield naming changed from module_register.field to module_register[field] table 960. documenr revision history (continued) date revision changes revision history RM0029 1730/1740 doc id 15177 rev 8 18-oct-2010 4 (cont?d) chapter 10 peripheral bridge (pbridge) renamed master privilege register (mprot) to master privilege control register (mpcr) correction: offset 0x0044, bits 20?23 are opac13 (was opacr3) chapter 11 flash memory added block size column to flash memory map memory map updates: ? corrected flash_x_ut0 register addresses ? added umisrn registers footnote added warning that flash configuration registers must not be written by software executing from flash memory. all references to stop mode removed. chapter 13 memory protection unit (mpu) warning added to application information section discussing errors caused by application code that crosses mpu region boundaries. chapter 14 external bus interface (ebi dbm bit added to ebi_mcr register chapter 15 interrupt controller (intc) ? interrupt 307 source updated ? largest addressable irq vector number is now 485 ? the total number of interrupts available is 486 ? there are 279 peripheral irqs ? there are 199 reserved irqs. chapter 16 system integration unit (siu) ? ?memory map and register descriptions? section: changed signal name notation for dspi: - pcsxn or dspi_x_cs[n] is now dspi_x_pcs[n] - soutx is now dspi_x_sout - sinx is now dspi_x_sin - sckx is now dspi_x_sck siu address map: added page index ?location? column removed ?pin? column from pcr pa values tables (including table in sample pcr map) pad configuration register (siu_pcr12): replaced ?data[0]? with ?data[16]? in footnotes siu_pcr113 pa values: change name tcr_a to tcrclka siu_pcr138 to siu_pcr143 pa values tables: added footnote explaining that the etpu function controlled by these registers has an additional dependency on the siu_isel8 register settings siu_pcr143 pa values: corrected pa value for alt2?was 0b0100; is 0b100 updated ?pad configuration register 219 (siu_pcr219)? section siu_pcr228 pa values: changed pa value for tdo?was ???; is ?01? table 960. documenr revision history (continued) date revision changes RM0029 revision history doc id 15177 rev 8 1731/1740 18-oct-2010 4 (cont?d) chapter 16 system integration unit (siu) (cont) siu_pcr232 pa values: changed pin and associated content from ?emios[5] output only? to ?tdi? added details to siu_pcr219 section. this pcr is unusual in that it controls configuration for two pins: gpio[219] and mcko, but not all fields apply to both pins. siu_sysdiv field description: added note to sysclkdiv field description to explain that clock divider selection depends on bypass field value added section 16.7.24, ?imux select register 10 (siu_isel10 or siu_decfil1) eqadc advance trigger selection: changed input for values 00000 and 00111 to ?reserved? reacmstp field added to siu_hlt register reacmack field added to siy_hltack register nsetiack field added to siu_hltack register flash removed from list of modules affected by siu_hlt_cpustp] chapter 17 frequency-modulated phase locked loop (fmpll) bypass mode with crystal reference mode can be entered after reset by programming fmpll_esyncr1[clkcfg] (previously pointed to pllcfg field). chapter 19 system timer module (stm) stm memory map: ? added location page index column ? changed name of stm_cnt (was stm counter value; is stm count register) ? removed 32-bit size and r/w access from ?reserved? rows chapter 20 software watchdog timer (swt) ? deleted device-specific information section ? updated reset value of swt_mcr register ? updated reset value of swt_to register ? updated reset value of swt_co register chapter 21 boot assist module (bam) ebi register settings table updates: ? siu_pcr3xx registers deleted ? ebi_mcr and ebi_br0 comments updated update to ?booting from the external bus interface (ebi) section: ? deleted statement that the rchw[ps0] bit has to be programmed to ?1?, since the ebi does not support a 32-bit port size. ? deleted statement that the bam program first checks that the device is in the csp package ? correction: bootcfg0 pin must be driven high for serial boot (was bootcfg) updates to bam program operation section: ? boot modes table updated bam program flow chart updated table 960. documenr revision history (continued) date revision changes revision history RM0029 1732/1740 doc id 15177 rev 8 18-oct-2010 4 (cont?d) chapter 22 configurable enhanced modular io subsystem (emios200) added ?device-specific features? section (includes notation that doze mode is not supported) ?stac client submodule? section: removed content referencing two etpu engines chapter 23 enhanced time processing unit (etpu2) ? detailed memory map: added page index location column; updated register names ? removed content referencing block guides ? etpu_ecr field description: modified description of bit stf to reflect single engine implementation ? added note in device specific features: tcrclk and channel 0 are connected together internally on the 176-pin lqfp package. ? siu_isel8 cross reference added to device specific features list ? siu_isel8 cross reference added to channel configuration and control registers section chapter 24 reaction module reacm channel n configuration register (reacm_cr) renamed to reacm_chcrn reacm channel n status register (reacm_sr) renamed to reacm_chsrn reacm channel n router register (reacm_rr) renamed to reacm_chrrn updates to ?threshold bank and comparator? section: ? changed formula for second comparison to: ?comp = adc_data >= threshold_value[threspt + 1]? (was ?>=? instead ? RM0029 revision history doc id 15177 rev 8 1733/1740 18-oct-2010 4 (cont?d) chapter 24 reaction module (cont) new subsection added to adc interface section: input buffer overrun deleted ?no modulation mode? section added information in debug mode description deleted threshold bank section dma support section added correction: there are 3 shared timers implemented (was 16) memory map updated chapter 26 decimation filter reformatted register information chapter 28 system information module and trim (sim) renamed chapter (formerly flash fuse loader (ffl)) added description of unique device id chapter 35 power management controller (pmc) updated voltage regulator external circuit diagram and recommended transistor data. updated adc channels table register changes: ? bit values for sr[v33dis] changed ? nvusro[v33dis] is r/w and has a reset value of 1 ? nvusro register address is 0xc3f8_802c ? bit values for nvusro[v33dis] changed; note on reset behavior added chapter 36 jtag controller (jtagc) number of auxiliary tap controllers sharing the port is 4. chapter 37 nexus port controller (npc) ddr section deleted?spc564a74xx, spc564a80xx devices do not support ddr. parameter values table updated. process core is compliant to ieee-isto 5001-2010 standard 28-jul-2011 5 cover page updated the title preface replaced all instances of powerpc book e with power architecture. chapter 1 introduction ? conditionalized note 6 of table ?andorra 4m device comparison? as fsl_specific. ? added a column for spc564a70 features and hence changed title of table1 and section 1.2 to ?spc564a80, spc563m64 and spc564a70 comparison?. table 960. documenr revision history (continued) date revision changes revision history RM0029 1734/1740 doc id 15177 rev 8 28-jul-2011 5 chapter 2 memory map ? in table ?spc564a80 memory map?, deleted the ?used size? entry for ?start address? of 0xc3fb_c000. ? in the table ?singnal properties?: added a sub-row ?input for external 3.3 v supply? in the row ?vrc33?. ? added the column ?name? in the table ?pad types?. chapter 4 resets unconditionalized the mention of e200z4 reference manual. chapter 5 operating modes and clocking figure 6 ?system clock diagram? updated. chapter 6 device performance optimization ? unconditionalized the mention of e200z4 core reference manual. ? corrected description of ?g? field in the table?mas2 field descriptions?. chapter enhanced direct memory access controller (edma) in the table ?dma request summary for edma?: ? removed the mention of etpub in the rm. ? changed the ?description? and ?source? for the channels 32, 33 and 52 - 63. chapter 11 flash memory ? changed biucr reset and biuapr reset bits to 0x0000ff00 and 0x000000ff, respectively. ? added section ?utest mode?. ? previous errata err001433 (e6878253pdm) integrated into the reference manual, added the following in table ?umisrn field descriptions?: ?after running the user-test-mode margin read...? ? added a new row ?0x00f0_0000 reserved? in the table ?flash memory map?. ? extracted a new table 79 ?flash shadow block mapping? from already existing table 78 ?flash memory?. ? replaced umx with umisrx, throughout. chapter 12 general-purpose static ram (sram) added text ?vstby pad needs an external rc ...? chapter 16 system integration unit (siu) conditionalized a cross-reference as fsl-specific in ?partnum [0?15]? description row of the table ?siu_midr field description?. chapter 17 frequency-modulated phase locked loop (fmpll) added a footnote to ?vsspll? stating ?this signal is internally bonded to vss", in table ?signal properties?. chapter 21 boot assist module (bam) updated table 445. ?watchdog timeouts? to match the values in table 12. ?watchdog timeout periods?. chapter 22 configurable enhanced modular io subsystem (emios200) corrected the table ?stac client submodule server slot assignment?. chapter 23 enhanced time processing unit (etpu2) removed register etpuwdsr. table 960. documenr revision history (continued) date revision changes RM0029 revision history doc id 15177 rev 8 1735/1740 28-jul-2011 5 (cont?d) chapter 25 enhanced queued analog-to-digital converter (eqadc) ? in the figure: ?on-chip adc control scheme? renamed block ?result format? to ?result format and calibration sub-block?. ? previous errata err002449 (e12982697pdm) integrated into the reference manual: added note ?both adc0 and adc1 of an eqadc module...? ? previous errata err000652 (e6877374pdm) integrated into the reference manual: updated table ?non-multiplexed channel assignments?and the note ?50% x vref = 50% ref = (vrh / vrl)/2, but...? ? previous errata err001741 (e6860916pdm) integrated into the reference manual: added paragraph ?for accurate calibration ... command message (lst = 0b10 or 0b11)? in section 25.7.6 ?adc result calibration?. chapter 30 deserial serial peripheral interface (dspi) ? removed figure from section 30.10.18.1 ?stop mode (external stop mode)?, as per monaco. ? dse[1:0] bits added in figure 727 ?dspi dsi configuration register 1 (dspi_dsicr1)? (bits 14 and15) and table 739 ?dspi_dsicr1 field description?per mamba manual. chapter 32 flexcan module ? previous errata err002360 (e6871272pdm) integrated into the reference manual: added section 32.5.7.1 ?precautions when using global mask and individual mask registers?. ? in section 32.2.3 ?modes of operation? under bullet ?module disable mode?replaced the text with ?this low power mode...sub-modules?. in section 35.5.9.2 ?module disable mode? replaced the text with ?this low power mode...and negates the frz_ack bit?. ? in section 32.5.2 ?transmit process? deleted text and added ?the deactivated message ... code field?. added note ?an abort request to a txmb ... can bus arbitration? in section 32.5.6.1 ?transmission abort mechanism?. chapter 33 periodic interrupt timer (pit_rti) section 33.3.1, overview: rephrased ?the rti is a dedicated real time interrupt timer (rti)? to ?real time interrupt timer (rti) is a dedicated interrupt timer?. chapter 34 flexray communication controller (flexray) ? updated table 834: ?channel assignment description?:previous errata err002423 (e6858715pdm) integrated into the reference manual: removed the text in the first row and added ?reserved? instead. ? updated sections 34.6.6.2.3.1 and 34.6.6.3.3.1, previous errata err002421 (e6853852pdm) integrated into the reference manual: added paragraph: ?if the communication controller is started as a non-coldstart node...? ? previous errata err001369 (e6949905pdm) integrated into the reference manual: added footnote ?the flexray controller should be stopped?. ? previous errata err001364 (e6886033pdm) integrated into the reference manual: added note ?slot status information of ... is set? in section 34.5.2.46 ?slot status selection register (fr_sssr)?. ? previous errata err001322 (e6859837pdm) integrated into the reference manual: added note ?when the ecc functionality ... should not be set to 1?. chapter 36 jtag controller (jtagc) corrected the description for ?mic? field in table 978. table 960. documenr revision history (continued) date revision changes revision history RM0029 1736/1740 doc id 15177 rev 8 01-mar-2012 6 chapter introduction ? removed references of ?mpc5634m and spc563m64? from section 1.2: spc564a80 and spc564a70 device comparison . ?in table 1: spc564a80 and spc564a70 comparison for column ?spc564a70? done the following changes: ?for row ?packages? conditionalized ?324? of ?pbga 324?as ?st specific? and removed text ?known good die(kgd)?. ?for row ?external bus? added value 4 128-bit. ?for row ?calibration bus? changed the value to ?none?. chapter signal description ? changed table 1 (spc564a80 signal properties) . ?in row ?reset? column ?status/during reset? changed the value from ?reset / up? to ?? / up?. ?in row ?rstout? column ?status/during reset? changed the value from ?rstout /down? to ?rstout / low?. ?in row ?rstout? column ?status/after reset? changed the value from ?rstout/down? to ?rstout /high?. ?in row ?pllref? column ?status/during reset? changed the value from ?? /up? to ?pllref/up? and column ?status/after reset? changed from ?pllref/up? to ?? /up?. ?in row ?bootcfg[0]? column ?status/during reset? changed the value from ?? /down? to ?bootcfg[0]/down? and column ?status/after reset? changed from ?bootcfg[0]/down? to ?? /down?. ?in row ?bootcfg[1]? column ?status/during reset? changed the value from ?? /down? to ?bootcfg[1]/down? and column ?status/after reset? changed from ?bootcfg[1]/ down? to ?? /down?. ?in row ?wkpcfg? column ?status/during reset? changed from ?? /up? to ?wkpcfg/up? and column ?status/after reset? changed from ?wkpcfg/up? to ?? /up?. ? updated table 2 (pad types) by hiding the ?name? column. chapter operating modes and clocking ? updated text of section 5.3.3.1: support for 150 mhz system clock generation to ?a possible pll configuration is shown below: ? input clock (crystal frequency): 40 mhz ? eprediv/idf divider = /8 (1?15 range supported) ? emfd/ndiv loop divider = 60 (32?96 supported) ? vco clock out = 300 mhz (256?512 mhz range supported) ? erfd/odf output divider = /2 (/2, /4, /8, /16 supported)?. ? updated the following texts of section 5.3.3.2: support for 100 mhz system clock generation to ? eprediv/idf divider = /8 (1?15 range supported) ? erfd/odf output divider = /4 (/2, /4, /8, /16 supported). changed the note of section 5.3.4.6.2: external bus clock (clkout) from ?the clkout pin is only available in the 208- and 324-pin packages? to ?the clkout pin is only available in the 324-pin package?. table 960. documenr revision history (continued) date revision changes RM0029 revision history doc id 15177 rev 8 1737/1740 01-mar-2012 6 (cont?d) chapter device performance optimization ? changed bit 27 in figure 14 (l1 cache control and status register 1 (l1csr1)) from ?0? to ?icorg?. ? added description for ?icorg? bit. ? removed instance of z7 from section 6.3.4.2: recommended configuration chapter enhanced direct memory access controller in table 41 (dma request summary for edma) for ?channels? 32,33,58-63 the change done is as follows: ? changed ?dma request? from ?reserved? to ?no request? ? changed ?source? and ?description? from ?reserved? to ???. ? updated section 8.5.8: dynamic programming chapter multi-layer ahb crossbar switch in figure 50 (slave general purpose control register (xbar_sgpcrn)) updated ? bit ?14? from ?0? to ?hpe1? and access to read/write. ? bit ?13? from ?hpe2? to ?0? and access to ?read only zero? ? bit ?11? from ?0? to ?hpe4? and access to read/write. ? bit ?9? from ?0? to ?hpe6? and access to read/write. chapter system integration unit ? table 287 (siu_pcr215 pa values) changed the ?i/o? value from ?i/o? to ?o? ? table 333 (siu_eccr field description) bit ?engdicv? changed the equation from to ? updated table 315 (siu_pcr350 ? siu_pcr381 dspi muxing) as follows: ?removed column ?dspi deserialize destination?. ?updated column ?pa value? by changing ?0b01? to ?0b001? ?0b11? to ?0b100? ?0b10? to ?0b010? ?0b00? to ?0b000?. ? updated table 316 (siu_pcr382 ? siu_pcr389 dspi muxing) as follows: ?removed column ?dspi deserialize destination?. ?updated column ?pa value? by changing ?0b011? to ?0b100? ? updated table 317 (siu_pcr390 ? siu_pcr413 dspi muxing) as follows: ?removed column ?dspi deserialize destination?. ?updated column ?pa value? by changing ?0b01? to ?0b001? ?0b11? to ?0b100? ?0b10? to ?0b010? ?0b00? to ?0b000?. table 960. documenr revision history (continued) date revision changes engclk systemclockfrequency engdivx2 ----------------------------------------------------------------------- - = engclk systemclockorcrystaloscillator engdivx2 ------------------------------------------------------------------------------------------------- = revision history RM0029 1738/1740 doc id 15177 rev 8 01-mar-2012 6 (cont?d) chapter system integration unit (continued) ? change done in section 16.6.24: imux select register 10 (siu_isel10) is as follows:. change from: the imux select register 10 (siu_isel10 or siu_decfil1) register contains bit fields that specifywhich etpu output is used to trigger the decimation filter result output buffer for decimation filters a andb. change to: the imux select register 10 (siu_isel10 or siu_decfil1) register contains bit fields that specify which etpu output is connected to the decimation filter integrator halt signal (hselx) and integrator reset signal (zselx).for more details refer to section 26.3.3: integrator halt signal and section 26.3.4: integrator reset signal . modified the note in section 16.6.15.48: pad configuration registers 75?82 (siu_pcr75?siu_pcr82) . chapter frequency-modulated phase locked loop ? added note in section 17.5.2: clock configuration ?maximum system clock frequency is 150 mhz and max/min vco frequency is 256 mhz to 512 mhz?. ? replaced instances of f ref with f fbk throughout the chapter. chapter reaction module in section 23.1.1: features added a note ?dma is not supported in spc564a80 devices?. chapter enhanced queued analog-to-digital converter (eqadc) in section 25.2.2: block diagram : ? added foot note ?decimation filters a and b and reaction module?. ? added information about decimation filters a and b and about reaction module. ?in section 25.6.5.2: distributing result data into rfifos added information about decimation filters a and b and about reaction module. chapter decimation filter ?in section 26.4.2.3: decimation filter module extended configuration register (decfilter_mxcr) / table 648 added two notes: for bits szrosel[1:0], srqsel[2:0] and sensel[1:0] the note is: ?the hardware input signals are zsela for decimation filter a and zselb fractionation filter b for bit shltsel[1:0] the note added is: ?the hardware input signals are hsela for decimation filter a and hseb for decimation filter b. ? updated section 26.5.10: soft-reset command description chapter deserial serial peripheral interface ?in section 30.8.2.11: dspi dsi configuration register (dspi_dsicr) added dms,pes,pe,pp bits in dspi_dsicr register. ? added the following registers ?dspi hardware configuration register (dspi_hcr) ?dspi dsi serialization source select register (dspi_ssr) ?dspi dsi parallel input select register 0 (dpsi_pisr0) ?dspi dsi parallel input select register 1 (dpsi_pisr1) ?dspi dsi parallel input select register 2 (dpsi_pisr2) ?dspi dsi parallel input select register 3 (dpsi_pisr3) ?dspi dsi deserialized data interrupt mask register (dspi_dimr) ?dspi dsi deserialized data polarity interrupt register (dspi_dpir) table 960. documenr revision history (continued) date revision changes RM0029 revision history doc id 15177 rev 8 1739/1740 01-mar-2012 6 (cont?d) chapter deserial serial peripheral interface ?in section 30.8.2.11: dspi dsi configuration register (dspi_dsicr) added dms,pes,pe,pp bits in dspi_dsicr register. ? added the following registers ?dspi hardware configuration register (dspi_hcr) ?dspi dsi serialization source select register (dspi_ssr) ?dspi dsi parallel input select register 0 (dpsi_pisr0) ?dspi dsi parallel input select register 1 (dpsi_pisr1) ?dspi dsi parallel input select register 2 (dpsi_pisr2) ?dspi dsi parallel input select register 3 (dpsi_pisr3) ?dspi dsi deserialized data interrupt mask register (dspi_dimr) ?dspi dsi deserialized data polarity interrupt register (dspi_dpir) chapter enhanced serial communication interface ? updated figure 767 (control register 2 (esci_cr2)) by changing bit ?brk13? to ?brcl? ?besm13? to ?besm? ?sbstp? to ?bestp?. ? updated figure 768 (sci data register (esci_dr)) by changing bit ?r8? to ?rn? ?r? to ?rd[11:8]?. ? updated section 31.4.5.3.4: single wire mode by removing the text ?the txdir bit (esci_cr2[1]) determines whether the txd pin is going to be used as an input (txdir= 0) or an output (txdir = 1) in this mode of operation?. ? updated the entire section 31.3: memory map and register definition . ?in section 31.3.2.2: control register 1 (esci_cr1) changed the access of bits 16- 31 to read/write. ?in section 31.3.2.2: control register 1 (esci_cr1) changed the access of bits 21 to read only. chapter flexcan module ? table 780 (esr register field descriptions) updated the ?description? for ?field? txwrn to ?tx error warning? rxwrn to ?rx error warning?. ? section 32.4.5.8: error and status register (esr) . changed the text from ?the cpu read action clears bits 16?23? to ?the cpu read action clears bits 16?21?. chapter jtag controller section 36.4.1.1: instruction register / figure 992 (5-bit instruction register) changed the reset value 00001. chapter nexus port controller in table 950 (nexus trace port routing and speed) , row ?debug/cal package? changes done are as follows: ?in column ?port routing bit npc_pcr[nexcfg]? changed the value to ?don?t care?. ?in column ?cal_mdo[4:11] usage changed the value to ?trace port use?. 03-oct-2012 7 updated rpns in the title. 24-sep-2013 8 updated disclaimer. table 960. documenr revision history (continued) date revision changes RM0029 1740/1740 doc id 15177 rev 8 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? 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